diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v new file mode 100644 index 0000000..13dd715 --- /dev/null +++ b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v @@ -0,0 +1,100362 @@ +// +// +// +// +// +// +module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_103 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1347 ( .A ( ropt_net_114 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_106 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_103 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_104 ) , + .X ( ropt_net_114 ) ) ; +endmodule + + +module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_2__1__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module cby_2__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_2__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_113 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ccff_head[0] ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_98 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_101 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1345 ( .A ( ropt_net_111 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( ropt_net_112 ) , + .X ( ropt_net_113 ) ) ; +endmodule + + +module cby_2__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module cby_2__1__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cby_2__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_2__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_194 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_295 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591232 ( .A ( ctsbuf_net_194 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641237 ( .A ( ctsbuf_net_295 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( mem_out[3] ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module cby_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_130 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( copt_net_123 ) , + .X ( ropt_net_131 ) ) ; +endmodule + + +module cby_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module cby_1__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_1__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign Test_en_S_in = Test_en_E_in ; +assign Test_en_W_in = Test_en_E_in ; +assign Reset_S_in = Reset_E_in ; +assign Reset_W_in = Reset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_N_in = prog_clk_2_S_in ; +assign prog_clk_3_S_in = prog_clk_3_N_in ; +assign clk_2_N_in = clk_2_S_in ; +assign clk_3_S_in = clk_3_N_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_78 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_78 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_78 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , + .X ( copt_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) , + .X ( copt_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , + .X ( copt_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_70 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_71 ) , + .X ( copt_net_72 ) ) ; +endmodule + + +module cby_0__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cby_0__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; + +wire ropt_net_134 ; +wire ropt_net_128 ; +wire ropt_net_129 ; +wire ropt_net_133 ; +wire ropt_net_127 ; +wire ropt_net_122 ; +wire ropt_net_124 ; +wire ropt_net_132 ; +wire ropt_net_123 ; +wire ropt_net_120 ; +wire ropt_net_138 ; +wire ropt_net_125 ; +wire ropt_net_137 ; +wire ropt_net_121 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_120 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[14] ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_108 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module cbx_1__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module cbx_1__2__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_107 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_101 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1327 ( .A ( ccff_head[0] ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1329 ( .A ( copt_net_102 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1333 ( .A ( copt_net_103 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_106 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_104 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_105 ) , + .X ( copt_net_107 ) ) ; +endmodule + + +module cbx_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module cbx_1__1__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module cbx_1__1__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; + +wire ropt_net_130 ; +wire ropt_net_121 ; +wire ropt_net_132 ; +wire ropt_net_124 ; +wire ropt_net_125 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_W_in = prog_clk_1_E_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_W_in = prog_clk_3_E_in ; +assign clk_1_W_in = clk_1_E_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_W_in = clk_3_E_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_96 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_96 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_94 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_94 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_108 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_198 ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( ZBUF_39_0 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1345 ( .A ( ZBUF_39_0 ) , + .X ( clk_3_W_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531232 ( .A ( ctsbuf_net_198 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( ropt_net_133 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1356 ( .A ( copt_net_108 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_110 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( ropt_net_135 ) , + .X ( copt_net_113 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_125 ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1377 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1379 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1380 ( .A ( copt_net_113 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1381 ( .A ( copt_net_112 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1382 ( .A ( ropt_net_134 ) , + .X ( ropt_net_135 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_113 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_898_f_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_898_f_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_208_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_208_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_96 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_217_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_217_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_95 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_91 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) , + .X ( ropt_net_124 ) ) ; +endmodule + + +module cbx_1__0__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module cbx_1__0__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , + .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , + .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_2__2__const1_51 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1_51 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_50 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1_50 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_49 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__2__const1_49 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_172 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_172 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_172 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__const1_48 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_48 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_47 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_150 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_150 ) ) ; +endmodule + + +module sb_2__2__const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_2__2__const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_2__2__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_2__2__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; +endmodule + + +module sb_2__2__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_146 ) ) ; +endmodule + + +module sb_2__2__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__2__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__2__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_2__2__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_2__2__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_104 ) ) ; +endmodule + + +module sb_2__2__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_102 ) ) ; +endmodule + + +module sb_2__2__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_2__2__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_2__2__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_2__2__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_2__2__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_2__2__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_2__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module sb_2__2__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module sb_2__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module sb_2__2__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +endmodule + + +module sb_2__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_2__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_207 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_166 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( ccff_head[0] ) , + .X ( copt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_161 ) , + .X ( copt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_162 ) , + .X ( copt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_163 ) , + .X ( copt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_164 ) , + .X ( copt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1378 ( .A ( copt_net_165 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_205 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( ropt_net_203 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_204 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1382 ( .A ( ropt_net_206 ) , + .X ( ropt_net_207 ) ) ; +endmodule + + +module sb_2__2__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_144 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_144 ) ) ; +endmodule + + +module sb_2__2__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +endmodule + + +module sb_2__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__2__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_68 ) ) ; +endmodule + + +module sb_2__2__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_2__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_2__2__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; + +wire ropt_net_182 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_124 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_125 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_126 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[29] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_47 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_2__1__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_2__1__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_2__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_2__1__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_2__1__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_2__1__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__1__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_2__1__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_2__1__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_2__1__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__1__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_2__1__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_2__1__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_2__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_2__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_2__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_2__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_2__1__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module sb_2__1__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_166 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) , + .X ( copt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) , + .X ( copt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , + .X ( copt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_168 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1337 ( .A ( copt_net_150 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( copt_net_158 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1339 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) ) ; +endmodule + + +module sb_2__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_93 ) ) ; +endmodule + + +module sb_2__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_2__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_164 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_164 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_142 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_51 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_51 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_148 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_50 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_50 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_49 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_49 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__0__const1_48 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_48 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__0__const1_47 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_2__0__const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_140 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__0__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_138 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_136 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_146 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_2__0__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_2__0__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_132 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_128 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_126 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_124 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__0__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_156 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_158 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( ccff_head[0] ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( ropt_net_192 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_157 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1393 ( .A ( ropt_net_196 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1394 ( .A ( copt_net_159 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_194 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1397 ( .A ( ropt_net_195 ) , + .X ( ropt_net_196 ) ) ; +endmodule + + +module sb_2__0__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_122 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +endmodule + + +module sb_2__0__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__0__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_70 ) ) ; +endmodule + + +module sb_2__0__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_68 ) ) ; +endmodule + + +module sb_2__0__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_2__0__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_144 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_2__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire ropt_net_174 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( pReset_W_in ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1337 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[29] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_135 ) ) ; +endmodule + + +module sb_1__2__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__2__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_1__2__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_1__2__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__2__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_1__2__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__2__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__2__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__2__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_1__2__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_1__2__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_1__2__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_1__2__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_1__2__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__2__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_1__2__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_104 ) ) ; +endmodule + + +module sb_1__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) ) ; +endmodule + + +module sb_1__2__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_1__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_1__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_147 ) , + .X ( copt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_150 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_148 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_149 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_151 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_182 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_183 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_184 ) , + .X ( ropt_net_185 ) ) ; +endmodule + + +module sb_1__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_1__2__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__2__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; + +wire ropt_net_167 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , + chanx_right_out[17] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_139 ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( net_net_139 ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1349 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[29] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_149 ) ) ; +endmodule + + +module sb_1__1__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_147 ) ) ; +endmodule + + +module sb_1__1__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__1__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__1__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_155 ) ) ; +endmodule + + +module sb_1__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__1__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__1__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_1__1__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_1__1__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_1__1__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__1__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_153 ) ) ; +endmodule + + +module sb_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_172 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ropt_net_179 ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_173 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , + .X ( copt_net_176 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ccff_head[0] ) , + .X ( ropt_net_179 ) ) ; +endmodule + + +module sb_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__1__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_E_in ; +assign prog_clk_2_S_out = prog_clk_2_E_in ; +assign prog_clk_2_N_out = prog_clk_2_E_in ; +assign prog_clk_2_E_out = prog_clk_2_E_in ; +assign prog_clk_3_E_out = prog_clk_3_E_in ; +assign prog_clk_3_W_out = prog_clk_3_E_in ; +assign prog_clk_3_N_out = prog_clk_3_E_in ; +assign prog_clk_3_S_out = prog_clk_3_E_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_E_in ; +assign clk_2_S_out = clk_2_E_in ; +assign clk_2_N_out = clk_2_E_in ; +assign clk_2_E_out = clk_2_E_in ; +assign clk_3_E_out = clk_3_E_in ; +assign clk_3_W_out = clk_3_E_in ; +assign clk_3_N_out = clk_3_E_in ; +assign clk_3_S_out = clk_3_E_in ; +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_N_in = prog_clk_1_S_in ; +assign prog_clk_2_N_in = prog_clk_2_E_in ; +assign prog_clk_2_S_in = prog_clk_2_E_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_W_in = prog_clk_3_E_in ; +assign prog_clk_3_S_in = prog_clk_3_E_in ; +assign prog_clk_3_N_in = prog_clk_3_E_in ; +assign clk_1_N_in = clk_1_S_in ; +assign clk_2_N_in = clk_2_E_in ; +assign clk_2_S_in = clk_2_E_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_W_in = clk_3_E_in ; +assign clk_3_S_in = clk_3_E_in ; +assign clk_3_N_in = clk_3_E_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( { ropt_net_180 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( { copt_net_170 } ) , + .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__buf_8 copt_h_inst_1358 ( .A ( copt_net_170 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__0__const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__0__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_1__0__const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__0__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__0__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__0__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__0__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_1__0__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_1__0__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__0__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_1__0__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; +endmodule + + +module sb_1__0__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module sb_1__0__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_1__0__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_1__0__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_1__0__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_1__0__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_1__0__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_1__0__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_1__0__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_1__0__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_1__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_1__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_1__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_1__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__0__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__0__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_1__0__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_155 ) , + .X ( copt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_157 ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_152 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( ccff_head[0] ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_153 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( copt_net_154 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_156 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_184 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_182 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_183 ) , + .X ( ropt_net_185 ) ) ; +endmodule + + +module sb_1__0__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__0__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__0__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; + +wire ropt_net_170 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , + .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( Test_en_S_in ) , .Y ( BUF_net_133 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( Reset_S_in ) , .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_139 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_170 ) , + .X ( SC_OUT_TOP ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__2__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__2__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_102 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_101 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_103 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module sb_0__2__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__2__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_0__2__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module sb_0__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; +endmodule + + +module sb_0__2__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_73 ) ) ; +endmodule + + +module sb_0__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__2__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_0__2__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; +endmodule + + +module sb_0__2__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_99 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_95 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +endmodule + + +module sb_0__2__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_0__2__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_0__2__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__2__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_129 ; +wire ropt_net_127 ; +wire ropt_net_137 ; +wire ropt_net_128 ; +wire ropt_net_134 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[20] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_0__1__const1_48 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_48 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_47 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_47 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_146 ) ) ; +endmodule + + +module sb_0__1__const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_143 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__1__const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_164 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_164 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_137 ) ) ; +endmodule + + +module sb_0__1__const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_135 ) ) ; +endmodule + + +module sb_0__1__const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_0__1__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_0__1__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__1__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_0__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_0__1__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_0__1__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_0__1__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) ) ; +endmodule + + +module sb_0__1__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_0__1__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_0__1__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_0__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_0__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_0__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_0__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sb_0__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( ccff_head[0] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1347 ( .A ( copt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1348 ( .A ( ropt_net_177 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1349 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1350 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +endmodule + + +module sb_0__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_0__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_0__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_0__1__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_168 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , ropt_net_168 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + ropt_net_168 } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1340 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[23] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_0__0__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_0__0__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_0__0__const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_0__0__const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__0__const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_116 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( mem_out[1] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_114 ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_115 ) , + .X ( copt_net_116 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_194 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( ccff_head[0] ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_112 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_110 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_109 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( copt_net_111 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_192 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1358 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) ) ; +endmodule + + +module sb_0__0__const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_0__0__const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__0__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_0__0__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +endmodule + + +module sb_0__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__0__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_0__0__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; +endmodule + + +module sb_0__0__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_0__0__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_71 ) ) ; +endmodule + + +module sb_0__0__const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_0__0__const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_67 ) ) ; +endmodule + + +module sb_0__0__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module sb_0__0__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_63 ) ) ; +endmodule + + +module sb_0__0__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_61 ) ) ; +endmodule + + +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; + +wire ropt_net_139 ; +wire ropt_net_140 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1614 ( .A ( copt_net_198 ) , + .X ( copt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1615 ( .A ( copt_net_195 ) , + .X ( copt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1616 ( .A ( copt_net_199 ) , + .X ( copt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1617 ( .A ( copt_net_197 ) , + .X ( copt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1618 ( .A ( mem_out[1] ) , + .X ( copt_net_199 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_46 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_45 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_44 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_46 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_46 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_46 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_45 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_45 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_45 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_521_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module grid_clb_const1_44 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_44 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_44 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_520_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_520_ ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +output p_abuf0 ; +output p_abuf1 ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_43 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_42 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_43 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_43 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_43 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_42 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_42 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_42 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb22 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_43 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf2 , p_abuf3 , p0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_45 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_46 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( p_abuf1 ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , + .p0 ( p1 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_41 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_40 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_39 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_38 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_41 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_41 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_41 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_40 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_40 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_39 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_39 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_39 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_518_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module grid_clb_const1_38 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_38 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_517_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_37 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_36 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_37 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_37 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_36 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_36 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_36 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb19 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p3 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_37 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p1 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p1 ) ) ; +grid_clb_mux_tree_size2_40 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_39 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_40 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_41 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; +input p3 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_35 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_35 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_35 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_34 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_34 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_33 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_33 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_516_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module grid_clb_const1_32 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_32 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_32 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_31 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_31 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_31 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_30 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb16 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p3 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_31 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_32 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_33 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_34 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_35 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p3 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_28 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_27 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_27 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module grid_clb_const1_26 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_26 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_513_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_25 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_25 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_24 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_24 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb13 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p0 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p0 ; +input p2 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_25 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p2 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p2 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) , .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_27 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_28 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_29 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p2 ; +input p3 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_23 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_23 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_21 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_512_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module grid_clb_const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p_abuf0 , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_104 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb10 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_19 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_20 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_21 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_22 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_23 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p2 ( p2 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module grid_clb_const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p_abuf0 , + p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb7 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p2 ; +input p4 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_13 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p1 , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p2 ; +input p4 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) , .p4 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_14 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_17 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_15 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_16 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_17 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p2 ; +input p4 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p1 ( p1 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module grid_clb_const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb4 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_7 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_9 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_11 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p1 ( p1 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_4 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module grid_clb_const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb1 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1607 ( .A ( ccff_head[0] ) , + .X ( copt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1608 ( .A ( copt_net_191 ) , + .X ( copt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1609 ( .A ( copt_net_192 ) , + .X ( copt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1610 ( .A ( copt_net_190 ) , + .X ( copt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1611 ( .A ( copt_net_188 ) , + .X ( copt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1612 ( .A ( copt_net_189 ) , + .X ( copt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1619 ( .A ( copt_net_193 ) , + .X ( ropt_net_200 ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p1 ; +input p4 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_1 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p4 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) , .p4 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_2 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_5 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_3 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_4 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_5 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p4 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p1 ( p1 ) , .p4 ( p4 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_clb_ ( pReset , prog_clk , Test_en , + clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , + clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , + clb_I7 , clb_I7i , clb_reg_in , clb_sc_in , clb_cin , clb_reset , + clb_clk , ccff_head , clb_O , clb_reg_out , clb_sc_out , clb_cout , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , + p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , + p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , p4 , p5 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:1] clb_I0 ; +input [0:1] clb_I0i ; +input [0:1] clb_I1 ; +input [0:1] clb_I1i ; +input [0:1] clb_I2 ; +input [0:1] clb_I2i ; +input [0:1] clb_I3 ; +input [0:1] clb_I3i ; +input [0:1] clb_I4 ; +input [0:1] clb_I4i ; +input [0:1] clb_I5 ; +input [0:1] clb_I5i ; +input [0:1] clb_I6 ; +input [0:1] clb_I6i ; +input [0:1] clb_I7 ; +input [0:1] clb_I7i ; +input [0:0] clb_reg_in ; +input [0:0] clb_sc_in ; +input [0:0] clb_cin ; +input [0:0] clb_reset ; +input [0:0] clb_clk ; +input [0:0] ccff_head ; +output [0:15] clb_O ; +output [0:0] clb_reg_out ; +output [0:0] clb_sc_out ; +output [0:0] clb_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; +output p_abuf7 ; +output p_abuf8 ; +output p_abuf9 ; +output p_abuf10 ; +output p_abuf11 ; +output p_abuf12 ; +output p_abuf13 ; +output p_abuf14 ; +output p_abuf15 ; +output p_abuf16 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; +input p4 ; +input p5 ; + +wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_86_out ; +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; + +grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) , + .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( ccff_head ) , + .fle_out ( { clb_O[1] , clb_O[0] } ) , + .fle_reg_out ( direct_interc_32_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , + .fle_reg_in ( direct_interc_32_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , + .fle_reg_out ( direct_interc_41_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , + .fle_reg_in ( direct_interc_41_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .fle_out ( { clb_O[5] , clb_O[4] } ) , + .fle_reg_out ( direct_interc_50_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) , + .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , + .fle_reg_in ( direct_interc_50_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { clb_O[7] , clb_O[6] } ) , + .fle_reg_out ( direct_interc_59_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , + .fle_reg_in ( direct_interc_59_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .fle_out ( { clb_O[9] , clb_O[8] } ) , + .fle_reg_out ( direct_interc_68_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , + .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , + .fle_reg_in ( direct_interc_68_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .fle_out ( { clb_O[11] , clb_O[10] } ) , + .fle_reg_out ( direct_interc_77_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , + .fle_reg_in ( direct_interc_77_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .fle_out ( { clb_O[13] , clb_O[12] } ) , + .fle_reg_out ( direct_interc_86_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , + .fle_reg_in ( direct_interc_86_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , + .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p1 ( p1 ) ) ; +endmodule + + +module grid_clb ( pReset , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , + top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , + top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , + top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , + top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , top_width_0_height_0__pin_34_ , + right_width_0_height_0__pin_16_ , right_width_0_height_0__pin_17_ , + right_width_0_height_0__pin_18_ , right_width_0_height_0__pin_19_ , + right_width_0_height_0__pin_20_ , right_width_0_height_0__pin_21_ , + right_width_0_height_0__pin_22_ , right_width_0_height_0__pin_23_ , + right_width_0_height_0__pin_24_ , right_width_0_height_0__pin_25_ , + right_width_0_height_0__pin_26_ , right_width_0_height_0__pin_27_ , + right_width_0_height_0__pin_28_ , right_width_0_height_0__pin_29_ , + right_width_0_height_0__pin_30_ , right_width_0_height_0__pin_31_ , + Reset , ccff_head , top_width_0_height_0__pin_36_upper , + top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , + top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , + top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , + top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , + top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , + top_width_0_height_0__pin_41_lower , top_width_0_height_0__pin_42_upper , + top_width_0_height_0__pin_42_lower , top_width_0_height_0__pin_43_upper , + top_width_0_height_0__pin_43_lower , + right_width_0_height_0__pin_44_upper , + right_width_0_height_0__pin_44_lower , + right_width_0_height_0__pin_45_upper , + right_width_0_height_0__pin_45_lower , + right_width_0_height_0__pin_46_upper , + right_width_0_height_0__pin_46_lower , + right_width_0_height_0__pin_47_upper , + right_width_0_height_0__pin_47_lower , + right_width_0_height_0__pin_48_upper , + right_width_0_height_0__pin_48_lower , + right_width_0_height_0__pin_49_upper , + right_width_0_height_0__pin_49_lower , + right_width_0_height_0__pin_50_upper , + right_width_0_height_0__pin_50_lower , + right_width_0_height_0__pin_51_upper , + right_width_0_height_0__pin_51_lower , bottom_width_0_height_0__pin_52_ , + bottom_width_0_height_0__pin_53_ , bottom_width_0_height_0__pin_54_ , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + Test_en_E_in , Test_en_W_in , Test_en_W_out , Test_en_E_out , + pReset_N_in , Reset_E_in , Reset_W_in , Reset_W_out , Reset_E_out , + prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out , prog_clk_0_E_out , + prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in ) ; +input [0:0] pReset ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_1_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_3_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_5_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_7_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_9_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_11_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_13_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_15_ ; +input [0:0] top_width_0_height_0__pin_32_ ; +input [0:0] top_width_0_height_0__pin_33_ ; +input [0:0] top_width_0_height_0__pin_34_ ; +input [0:0] right_width_0_height_0__pin_16_ ; +input [0:0] right_width_0_height_0__pin_17_ ; +input [0:0] right_width_0_height_0__pin_18_ ; +input [0:0] right_width_0_height_0__pin_19_ ; +input [0:0] right_width_0_height_0__pin_20_ ; +input [0:0] right_width_0_height_0__pin_21_ ; +input [0:0] right_width_0_height_0__pin_22_ ; +input [0:0] right_width_0_height_0__pin_23_ ; +input [0:0] right_width_0_height_0__pin_24_ ; +input [0:0] right_width_0_height_0__pin_25_ ; +input [0:0] right_width_0_height_0__pin_26_ ; +input [0:0] right_width_0_height_0__pin_27_ ; +input [0:0] right_width_0_height_0__pin_28_ ; +input [0:0] right_width_0_height_0__pin_29_ ; +input [0:0] right_width_0_height_0__pin_30_ ; +input [0:0] right_width_0_height_0__pin_31_ ; +input [0:0] Reset ; +input [0:0] ccff_head ; +output [0:0] top_width_0_height_0__pin_36_upper ; +output [0:0] top_width_0_height_0__pin_36_lower ; +output [0:0] top_width_0_height_0__pin_37_upper ; +output [0:0] top_width_0_height_0__pin_37_lower ; +output [0:0] top_width_0_height_0__pin_38_upper ; +output [0:0] top_width_0_height_0__pin_38_lower ; +output [0:0] top_width_0_height_0__pin_39_upper ; +output [0:0] top_width_0_height_0__pin_39_lower ; +output [0:0] top_width_0_height_0__pin_40_upper ; +output [0:0] top_width_0_height_0__pin_40_lower ; +output [0:0] top_width_0_height_0__pin_41_upper ; +output [0:0] top_width_0_height_0__pin_41_lower ; +output [0:0] top_width_0_height_0__pin_42_upper ; +output [0:0] top_width_0_height_0__pin_42_lower ; +output [0:0] top_width_0_height_0__pin_43_upper ; +output [0:0] top_width_0_height_0__pin_43_lower ; +output [0:0] right_width_0_height_0__pin_44_upper ; +output [0:0] right_width_0_height_0__pin_44_lower ; +output [0:0] right_width_0_height_0__pin_45_upper ; +output [0:0] right_width_0_height_0__pin_45_lower ; +output [0:0] right_width_0_height_0__pin_46_upper ; +output [0:0] right_width_0_height_0__pin_46_lower ; +output [0:0] right_width_0_height_0__pin_47_upper ; +output [0:0] right_width_0_height_0__pin_47_lower ; +output [0:0] right_width_0_height_0__pin_48_upper ; +output [0:0] right_width_0_height_0__pin_48_lower ; +output [0:0] right_width_0_height_0__pin_49_upper ; +output [0:0] right_width_0_height_0__pin_49_lower ; +output [0:0] right_width_0_height_0__pin_50_upper ; +output [0:0] right_width_0_height_0__pin_50_lower ; +output [0:0] right_width_0_height_0__pin_51_upper ; +output [0:0] right_width_0_height_0__pin_51_lower ; +output [0:0] bottom_width_0_height_0__pin_52_ ; +output [0:0] bottom_width_0_height_0__pin_53_ ; +output [0:0] bottom_width_0_height_0__pin_54_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_N_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_N_in ; +input prog_clk_0_S_in ; +output prog_clk_0_S_out ; +output prog_clk_0_E_out ; +output prog_clk_0_W_out ; +output prog_clk_0_N_out ; +input clk_0_N_in ; +input clk_0_S_in ; + +wire p_abuf12 ; +wire p_abuf11 ; +wire p_abuf16 ; +wire prog_clk_0 ; +wire [0:0] prog_clk ; +wire [0:0] clk ; +wire clk_0 ; +wire [0:0] Test_en ; + +assign SC_IN_TOP = SC_IN_BOT ; +assign Test_en_E_in = Test_en_W_in ; +assign Reset_E_in = Reset_W_in ; +assign prog_clk[0] = prog_clk_0 ; +assign prog_clk_0_N_in = prog_clk_0_S_in ; +assign clk_0 = clk[0] ; +assign clk_0_N_in = clk_0_S_in ; + +grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .pReset ( pReset ) , + .prog_clk ( { prog_clk_0 } ) , + .Test_en ( Test_en ) , + .clb_I0 ( { top_width_0_height_0__pin_0_[0] , + top_width_0_height_0__pin_1_[0] } ) , + .clb_I0i ( { top_width_0_height_0__pin_2_[0] , + top_width_0_height_0__pin_3_[0] } ) , + .clb_I1 ( { top_width_0_height_0__pin_4_[0] , + top_width_0_height_0__pin_5_[0] } ) , + .clb_I1i ( { top_width_0_height_0__pin_6_[0] , + top_width_0_height_0__pin_7_[0] } ) , + .clb_I2 ( { top_width_0_height_0__pin_8_[0] , + top_width_0_height_0__pin_9_[0] } ) , + .clb_I2i ( { top_width_0_height_0__pin_10_[0] , + top_width_0_height_0__pin_11_[0] } ) , + .clb_I3 ( { top_width_0_height_0__pin_12_[0] , + top_width_0_height_0__pin_13_[0] } ) , + .clb_I3i ( { top_width_0_height_0__pin_14_[0] , + top_width_0_height_0__pin_15_[0] } ) , + .clb_I4 ( { right_width_0_height_0__pin_16_[0] , + right_width_0_height_0__pin_17_[0] } ) , + .clb_I4i ( { right_width_0_height_0__pin_18_[0] , + right_width_0_height_0__pin_19_[0] } ) , + .clb_I5 ( { right_width_0_height_0__pin_20_[0] , + right_width_0_height_0__pin_21_[0] } ) , + .clb_I5i ( { right_width_0_height_0__pin_22_[0] , + right_width_0_height_0__pin_23_[0] } ) , + .clb_I6 ( { right_width_0_height_0__pin_24_[0] , + right_width_0_height_0__pin_25_[0] } ) , + .clb_I6i ( { right_width_0_height_0__pin_26_[0] , + right_width_0_height_0__pin_27_[0] } ) , + .clb_I7 ( { right_width_0_height_0__pin_28_[0] , + right_width_0_height_0__pin_29_[0] } ) , + .clb_I7i ( { right_width_0_height_0__pin_30_[0] , + right_width_0_height_0__pin_31_[0] } ) , + .clb_reg_in ( top_width_0_height_0__pin_32_ ) , + .clb_sc_in ( { SC_IN_BOT } ) , + .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_522_ , aps_rename_523_ , aps_rename_524_ , + aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , + aps_rename_528_ , aps_rename_529_ , aps_rename_530_ , + aps_rename_531_ , right_width_0_height_0__pin_46_lower[0] , + right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , + aps_rename_535_ , right_width_0_height_0__pin_50_lower[0] , + aps_rename_537_ } ) , + .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , + .clb_sc_out ( { aps_rename_538_ } ) , + .clb_cout ( bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) , + .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , + .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , + .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , + .p_abuf4 ( top_width_0_height_0__pin_38_lower[0] ) , + .p_abuf5 ( top_width_0_height_0__pin_41_lower[0] ) , + .p_abuf6 ( top_width_0_height_0__pin_40_lower[0] ) , + .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) , + .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) , + .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) , + .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) , + .p_abuf11 ( p_abuf11 ) , .p_abuf12 ( p_abuf12 ) , + .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , + .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , + .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_178 ) , .p1 ( optlc_net_179 ) , + .p2 ( optlc_net_180 ) , .p3 ( optlc_net_181 ) , .p4 ( optlc_net_182 ) , + .p5 ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , + .X ( Test_en[0] ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_539_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_540_ ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_541_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_542_ ) ) ; +sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk_0 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1184 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2185 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3186 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_4187 ) ) ; +sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , + .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_523_ ) , + .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_524_ ) , + .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_525_ ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_526_ ) , + .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_527_ ) , + .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_528_ ) , + .X ( top_width_0_height_0__pin_42_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_529_ ) , + .X ( top_width_0_height_0__pin_43_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_530_ ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_531_ ) , + .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , + .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_534_ ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_535_ ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) , + .X ( right_width_0_height_0__pin_50_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , + .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , + .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_539_ ) , + .Y ( BUF_net_133 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , + .Y ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_542_ ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3981324 ( .A ( ctsbuf_net_1184 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_4031329 ( .A ( ctsbuf_net_2185 ) , + .X ( prog_clk_0_E_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_4081334 ( .A ( ctsbuf_net_3186 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_4131339 ( .A ( ctsbuf_net_4187 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + +module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head , + sc_tail , h_incr0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] IO_ISOL_N ; +input [0:0] clk ; +input [0:0] Reset ; +input [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +input sc_head ; +output sc_tail ; +input h_incr0 ; + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:29] cbx_1__0__0_chanx_left_out ; +wire [0:29] cbx_1__0__0_chanx_right_out ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__10_ccff_tail ; +wire [0:29] cbx_1__0__10_chanx_left_out ; +wire [0:29] cbx_1__0__10_chanx_right_out ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__11_ccff_tail ; +wire [0:29] cbx_1__0__11_chanx_left_out ; +wire [0:29] cbx_1__0__11_chanx_right_out ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:29] cbx_1__0__1_chanx_left_out ; +wire [0:29] cbx_1__0__1_chanx_right_out ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__2_ccff_tail ; +wire [0:29] cbx_1__0__2_chanx_left_out ; +wire [0:29] cbx_1__0__2_chanx_right_out ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__3_ccff_tail ; +wire [0:29] cbx_1__0__3_chanx_left_out ; +wire [0:29] cbx_1__0__3_chanx_right_out ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__4_ccff_tail ; +wire [0:29] cbx_1__0__4_chanx_left_out ; +wire [0:29] cbx_1__0__4_chanx_right_out ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__5_ccff_tail ; +wire [0:29] cbx_1__0__5_chanx_left_out ; +wire [0:29] cbx_1__0__5_chanx_right_out ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__6_ccff_tail ; +wire [0:29] cbx_1__0__6_chanx_left_out ; +wire [0:29] cbx_1__0__6_chanx_right_out ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__7_ccff_tail ; +wire [0:29] cbx_1__0__7_chanx_left_out ; +wire [0:29] cbx_1__0__7_chanx_right_out ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__8_ccff_tail ; +wire [0:29] cbx_1__0__8_chanx_left_out ; +wire [0:29] cbx_1__0__8_chanx_right_out ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__9_ccff_tail ; +wire [0:29] cbx_1__0__9_chanx_left_out ; +wire [0:29] cbx_1__0__9_chanx_right_out ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__0_ccff_tail ; +wire [0:29] cbx_1__12__0_chanx_left_out ; +wire [0:29] cbx_1__12__0_chanx_right_out ; +wire [0:0] cbx_1__12__0_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__10_ccff_tail ; +wire [0:29] cbx_1__12__10_chanx_left_out ; +wire [0:29] cbx_1__12__10_chanx_right_out ; +wire [0:0] cbx_1__12__10_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__11_ccff_tail ; +wire [0:29] cbx_1__12__11_chanx_left_out ; +wire [0:29] cbx_1__12__11_chanx_right_out ; +wire [0:0] cbx_1__12__11_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__1_ccff_tail ; +wire [0:29] cbx_1__12__1_chanx_left_out ; +wire [0:29] cbx_1__12__1_chanx_right_out ; +wire [0:0] cbx_1__12__1_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__2_ccff_tail ; +wire [0:29] cbx_1__12__2_chanx_left_out ; +wire [0:29] cbx_1__12__2_chanx_right_out ; +wire [0:0] cbx_1__12__2_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__3_ccff_tail ; +wire [0:29] cbx_1__12__3_chanx_left_out ; +wire [0:29] cbx_1__12__3_chanx_right_out ; +wire [0:0] cbx_1__12__3_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__4_ccff_tail ; +wire [0:29] cbx_1__12__4_chanx_left_out ; +wire [0:29] cbx_1__12__4_chanx_right_out ; +wire [0:0] cbx_1__12__4_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__5_ccff_tail ; +wire [0:29] cbx_1__12__5_chanx_left_out ; +wire [0:29] cbx_1__12__5_chanx_right_out ; +wire [0:0] cbx_1__12__5_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__6_ccff_tail ; +wire [0:29] cbx_1__12__6_chanx_left_out ; +wire [0:29] cbx_1__12__6_chanx_right_out ; +wire [0:0] cbx_1__12__6_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__7_ccff_tail ; +wire [0:29] cbx_1__12__7_chanx_left_out ; +wire [0:29] cbx_1__12__7_chanx_right_out ; +wire [0:0] cbx_1__12__7_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__8_ccff_tail ; +wire [0:29] cbx_1__12__8_chanx_left_out ; +wire [0:29] cbx_1__12__8_chanx_right_out ; +wire [0:0] cbx_1__12__8_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__9_ccff_tail ; +wire [0:29] cbx_1__12__9_chanx_left_out ; +wire [0:29] cbx_1__12__9_chanx_right_out ; +wire [0:0] cbx_1__12__9_top_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__0_ccff_tail ; +wire [0:29] cbx_1__1__0_chanx_left_out ; +wire [0:29] cbx_1__1__0_chanx_right_out ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__100_ccff_tail ; +wire [0:29] cbx_1__1__100_chanx_left_out ; +wire [0:29] cbx_1__1__100_chanx_right_out ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__101_ccff_tail ; +wire [0:29] cbx_1__1__101_chanx_left_out ; +wire [0:29] cbx_1__1__101_chanx_right_out ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__102_ccff_tail ; +wire [0:29] cbx_1__1__102_chanx_left_out ; +wire [0:29] cbx_1__1__102_chanx_right_out ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__103_ccff_tail ; +wire [0:29] cbx_1__1__103_chanx_left_out ; +wire [0:29] cbx_1__1__103_chanx_right_out ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__104_ccff_tail ; +wire [0:29] cbx_1__1__104_chanx_left_out ; +wire [0:29] cbx_1__1__104_chanx_right_out ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__105_ccff_tail ; +wire [0:29] cbx_1__1__105_chanx_left_out ; +wire [0:29] cbx_1__1__105_chanx_right_out ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__106_ccff_tail ; +wire [0:29] cbx_1__1__106_chanx_left_out ; +wire [0:29] cbx_1__1__106_chanx_right_out ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__107_ccff_tail ; +wire [0:29] cbx_1__1__107_chanx_left_out ; +wire [0:29] cbx_1__1__107_chanx_right_out ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__108_ccff_tail ; +wire [0:29] cbx_1__1__108_chanx_left_out ; +wire [0:29] cbx_1__1__108_chanx_right_out ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__109_ccff_tail ; +wire [0:29] cbx_1__1__109_chanx_left_out ; +wire [0:29] cbx_1__1__109_chanx_right_out ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__10_ccff_tail ; +wire [0:29] cbx_1__1__10_chanx_left_out ; +wire [0:29] cbx_1__1__10_chanx_right_out ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__110_ccff_tail ; +wire [0:29] cbx_1__1__110_chanx_left_out ; +wire [0:29] cbx_1__1__110_chanx_right_out ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__111_ccff_tail ; +wire [0:29] cbx_1__1__111_chanx_left_out ; +wire [0:29] cbx_1__1__111_chanx_right_out ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__112_ccff_tail ; +wire [0:29] cbx_1__1__112_chanx_left_out ; +wire [0:29] cbx_1__1__112_chanx_right_out ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__113_ccff_tail ; +wire [0:29] cbx_1__1__113_chanx_left_out ; +wire [0:29] cbx_1__1__113_chanx_right_out ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__114_ccff_tail ; +wire [0:29] cbx_1__1__114_chanx_left_out ; +wire [0:29] cbx_1__1__114_chanx_right_out ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__115_ccff_tail ; +wire [0:29] cbx_1__1__115_chanx_left_out ; +wire [0:29] cbx_1__1__115_chanx_right_out ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__116_ccff_tail ; +wire [0:29] cbx_1__1__116_chanx_left_out ; +wire [0:29] cbx_1__1__116_chanx_right_out ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__117_ccff_tail ; +wire [0:29] cbx_1__1__117_chanx_left_out ; +wire [0:29] cbx_1__1__117_chanx_right_out ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__118_ccff_tail ; +wire [0:29] cbx_1__1__118_chanx_left_out ; +wire [0:29] cbx_1__1__118_chanx_right_out ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__119_ccff_tail ; +wire [0:29] cbx_1__1__119_chanx_left_out ; +wire [0:29] cbx_1__1__119_chanx_right_out ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__11_ccff_tail ; +wire [0:29] cbx_1__1__11_chanx_left_out ; +wire [0:29] cbx_1__1__11_chanx_right_out ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__120_ccff_tail ; +wire [0:29] cbx_1__1__120_chanx_left_out ; +wire [0:29] cbx_1__1__120_chanx_right_out ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__121_ccff_tail ; +wire [0:29] cbx_1__1__121_chanx_left_out ; +wire [0:29] cbx_1__1__121_chanx_right_out ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__122_ccff_tail ; +wire [0:29] cbx_1__1__122_chanx_left_out ; +wire [0:29] cbx_1__1__122_chanx_right_out ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__123_ccff_tail ; +wire [0:29] cbx_1__1__123_chanx_left_out ; +wire [0:29] cbx_1__1__123_chanx_right_out ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__124_ccff_tail ; +wire [0:29] cbx_1__1__124_chanx_left_out ; +wire [0:29] cbx_1__1__124_chanx_right_out ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__125_ccff_tail ; +wire [0:29] cbx_1__1__125_chanx_left_out ; +wire [0:29] cbx_1__1__125_chanx_right_out ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__126_ccff_tail ; +wire [0:29] cbx_1__1__126_chanx_left_out ; +wire [0:29] cbx_1__1__126_chanx_right_out ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__127_ccff_tail ; +wire [0:29] cbx_1__1__127_chanx_left_out ; +wire [0:29] cbx_1__1__127_chanx_right_out ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__128_ccff_tail ; +wire [0:29] cbx_1__1__128_chanx_left_out ; +wire [0:29] cbx_1__1__128_chanx_right_out ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__129_ccff_tail ; +wire [0:29] cbx_1__1__129_chanx_left_out ; +wire [0:29] cbx_1__1__129_chanx_right_out ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__12_ccff_tail ; +wire [0:29] cbx_1__1__12_chanx_left_out ; +wire [0:29] cbx_1__1__12_chanx_right_out ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__130_ccff_tail ; +wire [0:29] cbx_1__1__130_chanx_left_out ; +wire [0:29] cbx_1__1__130_chanx_right_out ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__131_ccff_tail ; +wire [0:29] cbx_1__1__131_chanx_left_out ; +wire [0:29] cbx_1__1__131_chanx_right_out ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__13_ccff_tail ; +wire [0:29] cbx_1__1__13_chanx_left_out ; +wire [0:29] cbx_1__1__13_chanx_right_out ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__14_ccff_tail ; +wire [0:29] cbx_1__1__14_chanx_left_out ; +wire [0:29] cbx_1__1__14_chanx_right_out ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__15_ccff_tail ; +wire [0:29] cbx_1__1__15_chanx_left_out ; +wire [0:29] cbx_1__1__15_chanx_right_out ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__16_ccff_tail ; +wire [0:29] cbx_1__1__16_chanx_left_out ; +wire [0:29] cbx_1__1__16_chanx_right_out ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__17_ccff_tail ; +wire [0:29] cbx_1__1__17_chanx_left_out ; +wire [0:29] cbx_1__1__17_chanx_right_out ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__18_ccff_tail ; +wire [0:29] cbx_1__1__18_chanx_left_out ; +wire [0:29] cbx_1__1__18_chanx_right_out ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__19_ccff_tail ; +wire [0:29] cbx_1__1__19_chanx_left_out ; +wire [0:29] cbx_1__1__19_chanx_right_out ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__1_ccff_tail ; +wire [0:29] cbx_1__1__1_chanx_left_out ; +wire [0:29] cbx_1__1__1_chanx_right_out ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__20_ccff_tail ; +wire [0:29] cbx_1__1__20_chanx_left_out ; +wire [0:29] cbx_1__1__20_chanx_right_out ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__21_ccff_tail ; +wire [0:29] cbx_1__1__21_chanx_left_out ; +wire [0:29] cbx_1__1__21_chanx_right_out ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__22_ccff_tail ; +wire [0:29] cbx_1__1__22_chanx_left_out ; +wire [0:29] cbx_1__1__22_chanx_right_out ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__23_ccff_tail ; +wire [0:29] cbx_1__1__23_chanx_left_out ; +wire [0:29] cbx_1__1__23_chanx_right_out ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__24_ccff_tail ; +wire [0:29] cbx_1__1__24_chanx_left_out ; +wire [0:29] cbx_1__1__24_chanx_right_out ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__25_ccff_tail ; +wire [0:29] cbx_1__1__25_chanx_left_out ; +wire [0:29] cbx_1__1__25_chanx_right_out ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__26_ccff_tail ; +wire [0:29] cbx_1__1__26_chanx_left_out ; +wire [0:29] cbx_1__1__26_chanx_right_out ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__27_ccff_tail ; +wire [0:29] cbx_1__1__27_chanx_left_out ; +wire [0:29] cbx_1__1__27_chanx_right_out ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__28_ccff_tail ; +wire [0:29] cbx_1__1__28_chanx_left_out ; +wire [0:29] cbx_1__1__28_chanx_right_out ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__29_ccff_tail ; +wire [0:29] cbx_1__1__29_chanx_left_out ; +wire [0:29] cbx_1__1__29_chanx_right_out ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__2_ccff_tail ; +wire [0:29] cbx_1__1__2_chanx_left_out ; +wire [0:29] cbx_1__1__2_chanx_right_out ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__30_ccff_tail ; +wire [0:29] cbx_1__1__30_chanx_left_out ; +wire [0:29] cbx_1__1__30_chanx_right_out ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__31_ccff_tail ; +wire [0:29] cbx_1__1__31_chanx_left_out ; +wire [0:29] cbx_1__1__31_chanx_right_out ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__32_ccff_tail ; +wire [0:29] cbx_1__1__32_chanx_left_out ; +wire [0:29] cbx_1__1__32_chanx_right_out ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__33_ccff_tail ; +wire [0:29] cbx_1__1__33_chanx_left_out ; +wire [0:29] cbx_1__1__33_chanx_right_out ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__34_ccff_tail ; +wire [0:29] cbx_1__1__34_chanx_left_out ; +wire [0:29] cbx_1__1__34_chanx_right_out ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__35_ccff_tail ; +wire [0:29] cbx_1__1__35_chanx_left_out ; +wire [0:29] cbx_1__1__35_chanx_right_out ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__36_ccff_tail ; +wire [0:29] cbx_1__1__36_chanx_left_out ; +wire [0:29] cbx_1__1__36_chanx_right_out ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__37_ccff_tail ; +wire [0:29] cbx_1__1__37_chanx_left_out ; +wire [0:29] cbx_1__1__37_chanx_right_out ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__38_ccff_tail ; +wire [0:29] cbx_1__1__38_chanx_left_out ; +wire [0:29] cbx_1__1__38_chanx_right_out ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__39_ccff_tail ; +wire [0:29] cbx_1__1__39_chanx_left_out ; +wire [0:29] cbx_1__1__39_chanx_right_out ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__3_ccff_tail ; +wire [0:29] cbx_1__1__3_chanx_left_out ; +wire [0:29] cbx_1__1__3_chanx_right_out ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__40_ccff_tail ; +wire [0:29] cbx_1__1__40_chanx_left_out ; +wire [0:29] cbx_1__1__40_chanx_right_out ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__41_ccff_tail ; +wire [0:29] cbx_1__1__41_chanx_left_out ; +wire [0:29] cbx_1__1__41_chanx_right_out ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__42_ccff_tail ; +wire [0:29] cbx_1__1__42_chanx_left_out ; +wire [0:29] cbx_1__1__42_chanx_right_out ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__43_ccff_tail ; +wire [0:29] cbx_1__1__43_chanx_left_out ; +wire [0:29] cbx_1__1__43_chanx_right_out ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__44_ccff_tail ; +wire [0:29] cbx_1__1__44_chanx_left_out ; +wire [0:29] cbx_1__1__44_chanx_right_out ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__45_ccff_tail ; +wire [0:29] cbx_1__1__45_chanx_left_out ; +wire [0:29] cbx_1__1__45_chanx_right_out ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__46_ccff_tail ; +wire [0:29] cbx_1__1__46_chanx_left_out ; +wire [0:29] cbx_1__1__46_chanx_right_out ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__47_ccff_tail ; +wire [0:29] cbx_1__1__47_chanx_left_out ; +wire [0:29] cbx_1__1__47_chanx_right_out ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__48_ccff_tail ; +wire [0:29] cbx_1__1__48_chanx_left_out ; +wire [0:29] cbx_1__1__48_chanx_right_out ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__49_ccff_tail ; +wire [0:29] cbx_1__1__49_chanx_left_out ; +wire [0:29] cbx_1__1__49_chanx_right_out ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__4_ccff_tail ; +wire [0:29] cbx_1__1__4_chanx_left_out ; +wire [0:29] cbx_1__1__4_chanx_right_out ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__50_ccff_tail ; +wire [0:29] cbx_1__1__50_chanx_left_out ; +wire [0:29] cbx_1__1__50_chanx_right_out ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__51_ccff_tail ; +wire [0:29] cbx_1__1__51_chanx_left_out ; +wire [0:29] cbx_1__1__51_chanx_right_out ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__52_ccff_tail ; +wire [0:29] cbx_1__1__52_chanx_left_out ; +wire [0:29] cbx_1__1__52_chanx_right_out ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__53_ccff_tail ; +wire [0:29] cbx_1__1__53_chanx_left_out ; +wire [0:29] cbx_1__1__53_chanx_right_out ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__54_ccff_tail ; +wire [0:29] cbx_1__1__54_chanx_left_out ; +wire [0:29] cbx_1__1__54_chanx_right_out ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__55_ccff_tail ; +wire [0:29] cbx_1__1__55_chanx_left_out ; +wire [0:29] cbx_1__1__55_chanx_right_out ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__56_ccff_tail ; +wire [0:29] cbx_1__1__56_chanx_left_out ; +wire [0:29] cbx_1__1__56_chanx_right_out ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__57_ccff_tail ; +wire [0:29] cbx_1__1__57_chanx_left_out ; +wire [0:29] cbx_1__1__57_chanx_right_out ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__58_ccff_tail ; +wire [0:29] cbx_1__1__58_chanx_left_out ; +wire [0:29] cbx_1__1__58_chanx_right_out ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__59_ccff_tail ; +wire [0:29] cbx_1__1__59_chanx_left_out ; +wire [0:29] cbx_1__1__59_chanx_right_out ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__5_ccff_tail ; +wire [0:29] cbx_1__1__5_chanx_left_out ; +wire [0:29] cbx_1__1__5_chanx_right_out ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__60_ccff_tail ; +wire [0:29] cbx_1__1__60_chanx_left_out ; +wire [0:29] cbx_1__1__60_chanx_right_out ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__61_ccff_tail ; +wire [0:29] cbx_1__1__61_chanx_left_out ; +wire [0:29] cbx_1__1__61_chanx_right_out ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__62_ccff_tail ; +wire [0:29] cbx_1__1__62_chanx_left_out ; +wire [0:29] cbx_1__1__62_chanx_right_out ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__63_ccff_tail ; +wire [0:29] cbx_1__1__63_chanx_left_out ; +wire [0:29] cbx_1__1__63_chanx_right_out ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__64_ccff_tail ; +wire [0:29] cbx_1__1__64_chanx_left_out ; +wire [0:29] cbx_1__1__64_chanx_right_out ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__65_ccff_tail ; +wire [0:29] cbx_1__1__65_chanx_left_out ; +wire [0:29] cbx_1__1__65_chanx_right_out ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__66_ccff_tail ; +wire [0:29] cbx_1__1__66_chanx_left_out ; +wire [0:29] cbx_1__1__66_chanx_right_out ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__67_ccff_tail ; +wire [0:29] cbx_1__1__67_chanx_left_out ; +wire [0:29] cbx_1__1__67_chanx_right_out ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__68_ccff_tail ; +wire [0:29] cbx_1__1__68_chanx_left_out ; +wire [0:29] cbx_1__1__68_chanx_right_out ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__69_ccff_tail ; +wire [0:29] cbx_1__1__69_chanx_left_out ; +wire [0:29] cbx_1__1__69_chanx_right_out ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__6_ccff_tail ; +wire [0:29] cbx_1__1__6_chanx_left_out ; +wire [0:29] cbx_1__1__6_chanx_right_out ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__70_ccff_tail ; +wire [0:29] cbx_1__1__70_chanx_left_out ; +wire [0:29] cbx_1__1__70_chanx_right_out ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__71_ccff_tail ; +wire [0:29] cbx_1__1__71_chanx_left_out ; +wire [0:29] cbx_1__1__71_chanx_right_out ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__72_ccff_tail ; +wire [0:29] cbx_1__1__72_chanx_left_out ; +wire [0:29] cbx_1__1__72_chanx_right_out ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__73_ccff_tail ; +wire [0:29] cbx_1__1__73_chanx_left_out ; +wire [0:29] cbx_1__1__73_chanx_right_out ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__74_ccff_tail ; +wire [0:29] cbx_1__1__74_chanx_left_out ; +wire [0:29] cbx_1__1__74_chanx_right_out ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__75_ccff_tail ; +wire [0:29] cbx_1__1__75_chanx_left_out ; +wire [0:29] cbx_1__1__75_chanx_right_out ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__76_ccff_tail ; +wire [0:29] cbx_1__1__76_chanx_left_out ; +wire [0:29] cbx_1__1__76_chanx_right_out ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__77_ccff_tail ; +wire [0:29] cbx_1__1__77_chanx_left_out ; +wire [0:29] cbx_1__1__77_chanx_right_out ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__78_ccff_tail ; +wire [0:29] cbx_1__1__78_chanx_left_out ; +wire [0:29] cbx_1__1__78_chanx_right_out ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__79_ccff_tail ; +wire [0:29] cbx_1__1__79_chanx_left_out ; +wire [0:29] cbx_1__1__79_chanx_right_out ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__7_ccff_tail ; +wire [0:29] cbx_1__1__7_chanx_left_out ; +wire [0:29] cbx_1__1__7_chanx_right_out ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__80_ccff_tail ; +wire [0:29] cbx_1__1__80_chanx_left_out ; +wire [0:29] cbx_1__1__80_chanx_right_out ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__81_ccff_tail ; +wire [0:29] cbx_1__1__81_chanx_left_out ; +wire [0:29] cbx_1__1__81_chanx_right_out ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__82_ccff_tail ; +wire [0:29] cbx_1__1__82_chanx_left_out ; +wire [0:29] cbx_1__1__82_chanx_right_out ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__83_ccff_tail ; +wire [0:29] cbx_1__1__83_chanx_left_out ; +wire [0:29] cbx_1__1__83_chanx_right_out ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__84_ccff_tail ; +wire [0:29] cbx_1__1__84_chanx_left_out ; +wire [0:29] cbx_1__1__84_chanx_right_out ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__85_ccff_tail ; +wire [0:29] cbx_1__1__85_chanx_left_out ; +wire [0:29] cbx_1__1__85_chanx_right_out ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__86_ccff_tail ; +wire [0:29] cbx_1__1__86_chanx_left_out ; +wire [0:29] cbx_1__1__86_chanx_right_out ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__87_ccff_tail ; +wire [0:29] cbx_1__1__87_chanx_left_out ; +wire [0:29] cbx_1__1__87_chanx_right_out ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__88_ccff_tail ; +wire [0:29] cbx_1__1__88_chanx_left_out ; +wire [0:29] cbx_1__1__88_chanx_right_out ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__89_ccff_tail ; +wire [0:29] cbx_1__1__89_chanx_left_out ; +wire [0:29] cbx_1__1__89_chanx_right_out ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__8_ccff_tail ; +wire [0:29] cbx_1__1__8_chanx_left_out ; +wire [0:29] cbx_1__1__8_chanx_right_out ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__90_ccff_tail ; +wire [0:29] cbx_1__1__90_chanx_left_out ; +wire [0:29] cbx_1__1__90_chanx_right_out ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__91_ccff_tail ; +wire [0:29] cbx_1__1__91_chanx_left_out ; +wire [0:29] cbx_1__1__91_chanx_right_out ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__92_ccff_tail ; +wire [0:29] cbx_1__1__92_chanx_left_out ; +wire [0:29] cbx_1__1__92_chanx_right_out ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__93_ccff_tail ; +wire [0:29] cbx_1__1__93_chanx_left_out ; +wire [0:29] cbx_1__1__93_chanx_right_out ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__94_ccff_tail ; +wire [0:29] cbx_1__1__94_chanx_left_out ; +wire [0:29] cbx_1__1__94_chanx_right_out ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__95_ccff_tail ; +wire [0:29] cbx_1__1__95_chanx_left_out ; +wire [0:29] cbx_1__1__95_chanx_right_out ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__96_ccff_tail ; +wire [0:29] cbx_1__1__96_chanx_left_out ; +wire [0:29] cbx_1__1__96_chanx_right_out ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__97_ccff_tail ; +wire [0:29] cbx_1__1__97_chanx_left_out ; +wire [0:29] cbx_1__1__97_chanx_right_out ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__98_ccff_tail ; +wire [0:29] cbx_1__1__98_chanx_left_out ; +wire [0:29] cbx_1__1__98_chanx_right_out ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__99_ccff_tail ; +wire [0:29] cbx_1__1__99_chanx_left_out ; +wire [0:29] cbx_1__1__99_chanx_right_out ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__9_ccff_tail ; +wire [0:29] cbx_1__1__9_chanx_left_out ; +wire [0:29] cbx_1__1__9_chanx_right_out ; +wire [0:0] cby_0__1__0_ccff_tail ; +wire [0:29] cby_0__1__0_chany_bottom_out ; +wire [0:29] cby_0__1__0_chany_top_out ; +wire [0:0] cby_0__1__0_left_grid_pin_0_ ; +wire [0:0] cby_0__1__10_ccff_tail ; +wire [0:29] cby_0__1__10_chany_bottom_out ; +wire [0:29] cby_0__1__10_chany_top_out ; +wire [0:0] cby_0__1__10_left_grid_pin_0_ ; +wire [0:0] cby_0__1__11_ccff_tail ; +wire [0:29] cby_0__1__11_chany_bottom_out ; +wire [0:29] cby_0__1__11_chany_top_out ; +wire [0:0] cby_0__1__11_left_grid_pin_0_ ; +wire [0:0] cby_0__1__1_ccff_tail ; +wire [0:29] cby_0__1__1_chany_bottom_out ; +wire [0:29] cby_0__1__1_chany_top_out ; +wire [0:0] cby_0__1__1_left_grid_pin_0_ ; +wire [0:0] cby_0__1__2_ccff_tail ; +wire [0:29] cby_0__1__2_chany_bottom_out ; +wire [0:29] cby_0__1__2_chany_top_out ; +wire [0:0] cby_0__1__2_left_grid_pin_0_ ; +wire [0:0] cby_0__1__3_ccff_tail ; +wire [0:29] cby_0__1__3_chany_bottom_out ; +wire [0:29] cby_0__1__3_chany_top_out ; +wire [0:0] cby_0__1__3_left_grid_pin_0_ ; +wire [0:0] cby_0__1__4_ccff_tail ; +wire [0:29] cby_0__1__4_chany_bottom_out ; +wire [0:29] cby_0__1__4_chany_top_out ; +wire [0:0] cby_0__1__4_left_grid_pin_0_ ; +wire [0:0] cby_0__1__5_ccff_tail ; +wire [0:29] cby_0__1__5_chany_bottom_out ; +wire [0:29] cby_0__1__5_chany_top_out ; +wire [0:0] cby_0__1__5_left_grid_pin_0_ ; +wire [0:0] cby_0__1__6_ccff_tail ; +wire [0:29] cby_0__1__6_chany_bottom_out ; +wire [0:29] cby_0__1__6_chany_top_out ; +wire [0:0] cby_0__1__6_left_grid_pin_0_ ; +wire [0:0] cby_0__1__7_ccff_tail ; +wire [0:29] cby_0__1__7_chany_bottom_out ; +wire [0:29] cby_0__1__7_chany_top_out ; +wire [0:0] cby_0__1__7_left_grid_pin_0_ ; +wire [0:0] cby_0__1__8_ccff_tail ; +wire [0:29] cby_0__1__8_chany_bottom_out ; +wire [0:29] cby_0__1__8_chany_top_out ; +wire [0:0] cby_0__1__8_left_grid_pin_0_ ; +wire [0:0] cby_0__1__9_ccff_tail ; +wire [0:29] cby_0__1__9_chany_bottom_out ; +wire [0:29] cby_0__1__9_chany_top_out ; +wire [0:0] cby_0__1__9_left_grid_pin_0_ ; +wire [0:0] cby_12__1__0_ccff_tail ; +wire [0:29] cby_12__1__0_chany_bottom_out ; +wire [0:29] cby_12__1__0_chany_top_out ; +wire [0:0] cby_12__1__0_left_grid_pin_16_ ; +wire [0:0] cby_12__1__0_left_grid_pin_17_ ; +wire [0:0] cby_12__1__0_left_grid_pin_18_ ; +wire [0:0] cby_12__1__0_left_grid_pin_19_ ; +wire [0:0] cby_12__1__0_left_grid_pin_20_ ; +wire [0:0] cby_12__1__0_left_grid_pin_21_ ; +wire [0:0] cby_12__1__0_left_grid_pin_22_ ; +wire [0:0] cby_12__1__0_left_grid_pin_23_ ; +wire [0:0] cby_12__1__0_left_grid_pin_24_ ; +wire [0:0] cby_12__1__0_left_grid_pin_25_ ; +wire [0:0] cby_12__1__0_left_grid_pin_26_ ; +wire [0:0] cby_12__1__0_left_grid_pin_27_ ; +wire [0:0] cby_12__1__0_left_grid_pin_28_ ; +wire [0:0] cby_12__1__0_left_grid_pin_29_ ; +wire [0:0] cby_12__1__0_left_grid_pin_30_ ; +wire [0:0] cby_12__1__0_left_grid_pin_31_ ; +wire [0:0] cby_12__1__0_right_grid_pin_0_ ; +wire [0:0] cby_12__1__10_ccff_tail ; +wire [0:29] cby_12__1__10_chany_bottom_out ; +wire [0:29] cby_12__1__10_chany_top_out ; +wire [0:0] cby_12__1__10_left_grid_pin_16_ ; +wire [0:0] cby_12__1__10_left_grid_pin_17_ ; +wire [0:0] cby_12__1__10_left_grid_pin_18_ ; +wire [0:0] cby_12__1__10_left_grid_pin_19_ ; +wire [0:0] cby_12__1__10_left_grid_pin_20_ ; +wire [0:0] cby_12__1__10_left_grid_pin_21_ ; +wire [0:0] cby_12__1__10_left_grid_pin_22_ ; +wire [0:0] cby_12__1__10_left_grid_pin_23_ ; +wire [0:0] cby_12__1__10_left_grid_pin_24_ ; +wire [0:0] cby_12__1__10_left_grid_pin_25_ ; +wire [0:0] cby_12__1__10_left_grid_pin_26_ ; +wire [0:0] cby_12__1__10_left_grid_pin_27_ ; +wire [0:0] cby_12__1__10_left_grid_pin_28_ ; +wire [0:0] cby_12__1__10_left_grid_pin_29_ ; +wire [0:0] cby_12__1__10_left_grid_pin_30_ ; +wire [0:0] cby_12__1__10_left_grid_pin_31_ ; +wire [0:0] cby_12__1__10_right_grid_pin_0_ ; +wire [0:0] cby_12__1__11_ccff_tail ; +wire [0:29] cby_12__1__11_chany_bottom_out ; +wire [0:29] cby_12__1__11_chany_top_out ; +wire [0:0] cby_12__1__11_left_grid_pin_16_ ; +wire [0:0] cby_12__1__11_left_grid_pin_17_ ; +wire [0:0] cby_12__1__11_left_grid_pin_18_ ; +wire [0:0] cby_12__1__11_left_grid_pin_19_ ; +wire [0:0] cby_12__1__11_left_grid_pin_20_ ; +wire [0:0] cby_12__1__11_left_grid_pin_21_ ; +wire [0:0] cby_12__1__11_left_grid_pin_22_ ; +wire [0:0] cby_12__1__11_left_grid_pin_23_ ; +wire [0:0] cby_12__1__11_left_grid_pin_24_ ; +wire [0:0] cby_12__1__11_left_grid_pin_25_ ; +wire [0:0] cby_12__1__11_left_grid_pin_26_ ; +wire [0:0] cby_12__1__11_left_grid_pin_27_ ; +wire [0:0] cby_12__1__11_left_grid_pin_28_ ; +wire [0:0] cby_12__1__11_left_grid_pin_29_ ; +wire [0:0] cby_12__1__11_left_grid_pin_30_ ; +wire [0:0] cby_12__1__11_left_grid_pin_31_ ; +wire [0:0] cby_12__1__11_right_grid_pin_0_ ; +wire [0:0] cby_12__1__1_ccff_tail ; +wire [0:29] cby_12__1__1_chany_bottom_out ; +wire [0:29] cby_12__1__1_chany_top_out ; +wire [0:0] cby_12__1__1_left_grid_pin_16_ ; +wire [0:0] cby_12__1__1_left_grid_pin_17_ ; +wire [0:0] cby_12__1__1_left_grid_pin_18_ ; +wire [0:0] cby_12__1__1_left_grid_pin_19_ ; +wire [0:0] cby_12__1__1_left_grid_pin_20_ ; +wire [0:0] cby_12__1__1_left_grid_pin_21_ ; +wire [0:0] cby_12__1__1_left_grid_pin_22_ ; +wire [0:0] cby_12__1__1_left_grid_pin_23_ ; +wire [0:0] cby_12__1__1_left_grid_pin_24_ ; +wire [0:0] cby_12__1__1_left_grid_pin_25_ ; +wire [0:0] cby_12__1__1_left_grid_pin_26_ ; +wire [0:0] cby_12__1__1_left_grid_pin_27_ ; +wire [0:0] cby_12__1__1_left_grid_pin_28_ ; +wire [0:0] cby_12__1__1_left_grid_pin_29_ ; +wire [0:0] cby_12__1__1_left_grid_pin_30_ ; +wire [0:0] cby_12__1__1_left_grid_pin_31_ ; +wire [0:0] cby_12__1__1_right_grid_pin_0_ ; +wire [0:0] cby_12__1__2_ccff_tail ; +wire [0:29] cby_12__1__2_chany_bottom_out ; +wire [0:29] cby_12__1__2_chany_top_out ; +wire [0:0] cby_12__1__2_left_grid_pin_16_ ; +wire [0:0] cby_12__1__2_left_grid_pin_17_ ; +wire [0:0] cby_12__1__2_left_grid_pin_18_ ; +wire [0:0] cby_12__1__2_left_grid_pin_19_ ; +wire [0:0] cby_12__1__2_left_grid_pin_20_ ; +wire [0:0] cby_12__1__2_left_grid_pin_21_ ; +wire [0:0] cby_12__1__2_left_grid_pin_22_ ; +wire [0:0] cby_12__1__2_left_grid_pin_23_ ; +wire [0:0] cby_12__1__2_left_grid_pin_24_ ; +wire [0:0] cby_12__1__2_left_grid_pin_25_ ; +wire [0:0] cby_12__1__2_left_grid_pin_26_ ; +wire [0:0] cby_12__1__2_left_grid_pin_27_ ; +wire [0:0] cby_12__1__2_left_grid_pin_28_ ; +wire [0:0] cby_12__1__2_left_grid_pin_29_ ; +wire [0:0] cby_12__1__2_left_grid_pin_30_ ; +wire [0:0] cby_12__1__2_left_grid_pin_31_ ; +wire [0:0] cby_12__1__2_right_grid_pin_0_ ; +wire [0:0] cby_12__1__3_ccff_tail ; +wire [0:29] cby_12__1__3_chany_bottom_out ; +wire [0:29] cby_12__1__3_chany_top_out ; +wire [0:0] cby_12__1__3_left_grid_pin_16_ ; +wire [0:0] cby_12__1__3_left_grid_pin_17_ ; +wire [0:0] cby_12__1__3_left_grid_pin_18_ ; +wire [0:0] cby_12__1__3_left_grid_pin_19_ ; +wire [0:0] cby_12__1__3_left_grid_pin_20_ ; +wire [0:0] cby_12__1__3_left_grid_pin_21_ ; +wire [0:0] cby_12__1__3_left_grid_pin_22_ ; +wire [0:0] cby_12__1__3_left_grid_pin_23_ ; +wire [0:0] cby_12__1__3_left_grid_pin_24_ ; +wire [0:0] cby_12__1__3_left_grid_pin_25_ ; +wire [0:0] cby_12__1__3_left_grid_pin_26_ ; +wire [0:0] cby_12__1__3_left_grid_pin_27_ ; +wire [0:0] cby_12__1__3_left_grid_pin_28_ ; +wire [0:0] cby_12__1__3_left_grid_pin_29_ ; +wire [0:0] cby_12__1__3_left_grid_pin_30_ ; +wire [0:0] cby_12__1__3_left_grid_pin_31_ ; +wire [0:0] cby_12__1__3_right_grid_pin_0_ ; +wire [0:0] cby_12__1__4_ccff_tail ; +wire [0:29] cby_12__1__4_chany_bottom_out ; +wire [0:29] cby_12__1__4_chany_top_out ; +wire [0:0] cby_12__1__4_left_grid_pin_16_ ; +wire [0:0] cby_12__1__4_left_grid_pin_17_ ; +wire [0:0] cby_12__1__4_left_grid_pin_18_ ; +wire [0:0] cby_12__1__4_left_grid_pin_19_ ; +wire [0:0] cby_12__1__4_left_grid_pin_20_ ; +wire [0:0] cby_12__1__4_left_grid_pin_21_ ; +wire [0:0] cby_12__1__4_left_grid_pin_22_ ; +wire [0:0] cby_12__1__4_left_grid_pin_23_ ; +wire [0:0] cby_12__1__4_left_grid_pin_24_ ; +wire [0:0] cby_12__1__4_left_grid_pin_25_ ; +wire [0:0] cby_12__1__4_left_grid_pin_26_ ; +wire [0:0] cby_12__1__4_left_grid_pin_27_ ; +wire [0:0] cby_12__1__4_left_grid_pin_28_ ; +wire [0:0] cby_12__1__4_left_grid_pin_29_ ; +wire [0:0] cby_12__1__4_left_grid_pin_30_ ; +wire [0:0] cby_12__1__4_left_grid_pin_31_ ; +wire [0:0] cby_12__1__4_right_grid_pin_0_ ; +wire [0:0] cby_12__1__5_ccff_tail ; +wire [0:29] cby_12__1__5_chany_bottom_out ; +wire [0:29] cby_12__1__5_chany_top_out ; +wire [0:0] cby_12__1__5_left_grid_pin_16_ ; +wire [0:0] cby_12__1__5_left_grid_pin_17_ ; +wire [0:0] cby_12__1__5_left_grid_pin_18_ ; +wire [0:0] cby_12__1__5_left_grid_pin_19_ ; +wire [0:0] cby_12__1__5_left_grid_pin_20_ ; +wire [0:0] cby_12__1__5_left_grid_pin_21_ ; +wire [0:0] cby_12__1__5_left_grid_pin_22_ ; +wire [0:0] cby_12__1__5_left_grid_pin_23_ ; +wire [0:0] cby_12__1__5_left_grid_pin_24_ ; +wire [0:0] cby_12__1__5_left_grid_pin_25_ ; +wire [0:0] cby_12__1__5_left_grid_pin_26_ ; +wire [0:0] cby_12__1__5_left_grid_pin_27_ ; +wire [0:0] cby_12__1__5_left_grid_pin_28_ ; +wire [0:0] cby_12__1__5_left_grid_pin_29_ ; +wire [0:0] cby_12__1__5_left_grid_pin_30_ ; +wire [0:0] cby_12__1__5_left_grid_pin_31_ ; +wire [0:0] cby_12__1__5_right_grid_pin_0_ ; +wire [0:0] cby_12__1__6_ccff_tail ; +wire [0:29] cby_12__1__6_chany_bottom_out ; +wire [0:29] cby_12__1__6_chany_top_out ; +wire [0:0] cby_12__1__6_left_grid_pin_16_ ; +wire [0:0] cby_12__1__6_left_grid_pin_17_ ; +wire [0:0] cby_12__1__6_left_grid_pin_18_ ; +wire [0:0] cby_12__1__6_left_grid_pin_19_ ; +wire [0:0] cby_12__1__6_left_grid_pin_20_ ; +wire [0:0] cby_12__1__6_left_grid_pin_21_ ; +wire [0:0] cby_12__1__6_left_grid_pin_22_ ; +wire [0:0] cby_12__1__6_left_grid_pin_23_ ; +wire [0:0] cby_12__1__6_left_grid_pin_24_ ; +wire [0:0] cby_12__1__6_left_grid_pin_25_ ; +wire [0:0] cby_12__1__6_left_grid_pin_26_ ; +wire [0:0] cby_12__1__6_left_grid_pin_27_ ; +wire [0:0] cby_12__1__6_left_grid_pin_28_ ; +wire [0:0] cby_12__1__6_left_grid_pin_29_ ; +wire [0:0] cby_12__1__6_left_grid_pin_30_ ; +wire [0:0] cby_12__1__6_left_grid_pin_31_ ; +wire [0:0] cby_12__1__6_right_grid_pin_0_ ; +wire [0:0] cby_12__1__7_ccff_tail ; +wire [0:29] cby_12__1__7_chany_bottom_out ; +wire [0:29] cby_12__1__7_chany_top_out ; +wire [0:0] cby_12__1__7_left_grid_pin_16_ ; +wire [0:0] cby_12__1__7_left_grid_pin_17_ ; +wire [0:0] cby_12__1__7_left_grid_pin_18_ ; +wire [0:0] cby_12__1__7_left_grid_pin_19_ ; +wire [0:0] cby_12__1__7_left_grid_pin_20_ ; +wire [0:0] cby_12__1__7_left_grid_pin_21_ ; +wire [0:0] cby_12__1__7_left_grid_pin_22_ ; +wire [0:0] cby_12__1__7_left_grid_pin_23_ ; +wire [0:0] cby_12__1__7_left_grid_pin_24_ ; +wire [0:0] cby_12__1__7_left_grid_pin_25_ ; +wire [0:0] cby_12__1__7_left_grid_pin_26_ ; +wire [0:0] cby_12__1__7_left_grid_pin_27_ ; +wire [0:0] cby_12__1__7_left_grid_pin_28_ ; +wire [0:0] cby_12__1__7_left_grid_pin_29_ ; +wire [0:0] cby_12__1__7_left_grid_pin_30_ ; +wire [0:0] cby_12__1__7_left_grid_pin_31_ ; +wire [0:0] cby_12__1__7_right_grid_pin_0_ ; +wire [0:0] cby_12__1__8_ccff_tail ; +wire [0:29] cby_12__1__8_chany_bottom_out ; +wire [0:29] cby_12__1__8_chany_top_out ; +wire [0:0] cby_12__1__8_left_grid_pin_16_ ; +wire [0:0] cby_12__1__8_left_grid_pin_17_ ; +wire [0:0] cby_12__1__8_left_grid_pin_18_ ; +wire [0:0] cby_12__1__8_left_grid_pin_19_ ; +wire [0:0] cby_12__1__8_left_grid_pin_20_ ; +wire [0:0] cby_12__1__8_left_grid_pin_21_ ; +wire [0:0] cby_12__1__8_left_grid_pin_22_ ; +wire [0:0] cby_12__1__8_left_grid_pin_23_ ; +wire [0:0] cby_12__1__8_left_grid_pin_24_ ; +wire [0:0] cby_12__1__8_left_grid_pin_25_ ; +wire [0:0] cby_12__1__8_left_grid_pin_26_ ; +wire [0:0] cby_12__1__8_left_grid_pin_27_ ; +wire [0:0] cby_12__1__8_left_grid_pin_28_ ; +wire [0:0] cby_12__1__8_left_grid_pin_29_ ; +wire [0:0] cby_12__1__8_left_grid_pin_30_ ; +wire [0:0] cby_12__1__8_left_grid_pin_31_ ; +wire [0:0] cby_12__1__8_right_grid_pin_0_ ; +wire [0:0] cby_12__1__9_ccff_tail ; +wire [0:29] cby_12__1__9_chany_bottom_out ; +wire [0:29] cby_12__1__9_chany_top_out ; +wire [0:0] cby_12__1__9_left_grid_pin_16_ ; +wire [0:0] cby_12__1__9_left_grid_pin_17_ ; +wire [0:0] cby_12__1__9_left_grid_pin_18_ ; +wire [0:0] cby_12__1__9_left_grid_pin_19_ ; +wire [0:0] cby_12__1__9_left_grid_pin_20_ ; +wire [0:0] cby_12__1__9_left_grid_pin_21_ ; +wire [0:0] cby_12__1__9_left_grid_pin_22_ ; +wire [0:0] cby_12__1__9_left_grid_pin_23_ ; +wire [0:0] cby_12__1__9_left_grid_pin_24_ ; +wire [0:0] cby_12__1__9_left_grid_pin_25_ ; +wire [0:0] cby_12__1__9_left_grid_pin_26_ ; +wire [0:0] cby_12__1__9_left_grid_pin_27_ ; +wire [0:0] cby_12__1__9_left_grid_pin_28_ ; +wire [0:0] cby_12__1__9_left_grid_pin_29_ ; +wire [0:0] cby_12__1__9_left_grid_pin_30_ ; +wire [0:0] cby_12__1__9_left_grid_pin_31_ ; +wire [0:0] cby_12__1__9_right_grid_pin_0_ ; +wire [0:0] cby_1__1__0_ccff_tail ; +wire [0:29] cby_1__1__0_chany_bottom_out ; +wire [0:29] cby_1__1__0_chany_top_out ; +wire [0:0] cby_1__1__0_left_grid_pin_16_ ; +wire [0:0] cby_1__1__0_left_grid_pin_17_ ; +wire [0:0] cby_1__1__0_left_grid_pin_18_ ; +wire [0:0] cby_1__1__0_left_grid_pin_19_ ; +wire [0:0] cby_1__1__0_left_grid_pin_20_ ; +wire [0:0] cby_1__1__0_left_grid_pin_21_ ; +wire [0:0] cby_1__1__0_left_grid_pin_22_ ; +wire [0:0] cby_1__1__0_left_grid_pin_23_ ; +wire [0:0] cby_1__1__0_left_grid_pin_24_ ; +wire [0:0] cby_1__1__0_left_grid_pin_25_ ; +wire [0:0] cby_1__1__0_left_grid_pin_26_ ; +wire [0:0] cby_1__1__0_left_grid_pin_27_ ; +wire [0:0] cby_1__1__0_left_grid_pin_28_ ; +wire [0:0] cby_1__1__0_left_grid_pin_29_ ; +wire [0:0] cby_1__1__0_left_grid_pin_30_ ; +wire [0:0] cby_1__1__0_left_grid_pin_31_ ; +wire [0:0] cby_1__1__100_ccff_tail ; +wire [0:29] cby_1__1__100_chany_bottom_out ; +wire [0:29] cby_1__1__100_chany_top_out ; +wire [0:0] cby_1__1__100_left_grid_pin_16_ ; +wire [0:0] cby_1__1__100_left_grid_pin_17_ ; +wire [0:0] cby_1__1__100_left_grid_pin_18_ ; +wire [0:0] cby_1__1__100_left_grid_pin_19_ ; +wire [0:0] cby_1__1__100_left_grid_pin_20_ ; +wire [0:0] cby_1__1__100_left_grid_pin_21_ ; +wire [0:0] cby_1__1__100_left_grid_pin_22_ ; +wire [0:0] cby_1__1__100_left_grid_pin_23_ ; +wire [0:0] cby_1__1__100_left_grid_pin_24_ ; +wire [0:0] cby_1__1__100_left_grid_pin_25_ ; +wire [0:0] cby_1__1__100_left_grid_pin_26_ ; +wire [0:0] cby_1__1__100_left_grid_pin_27_ ; +wire [0:0] cby_1__1__100_left_grid_pin_28_ ; +wire [0:0] cby_1__1__100_left_grid_pin_29_ ; +wire [0:0] cby_1__1__100_left_grid_pin_30_ ; +wire [0:0] cby_1__1__100_left_grid_pin_31_ ; +wire [0:0] cby_1__1__101_ccff_tail ; +wire [0:29] cby_1__1__101_chany_bottom_out ; +wire [0:29] cby_1__1__101_chany_top_out ; +wire [0:0] cby_1__1__101_left_grid_pin_16_ ; +wire [0:0] cby_1__1__101_left_grid_pin_17_ ; +wire [0:0] cby_1__1__101_left_grid_pin_18_ ; +wire [0:0] cby_1__1__101_left_grid_pin_19_ ; +wire [0:0] cby_1__1__101_left_grid_pin_20_ ; +wire [0:0] cby_1__1__101_left_grid_pin_21_ ; +wire [0:0] cby_1__1__101_left_grid_pin_22_ ; +wire [0:0] cby_1__1__101_left_grid_pin_23_ ; +wire [0:0] cby_1__1__101_left_grid_pin_24_ ; +wire [0:0] cby_1__1__101_left_grid_pin_25_ ; +wire [0:0] cby_1__1__101_left_grid_pin_26_ ; +wire [0:0] cby_1__1__101_left_grid_pin_27_ ; +wire [0:0] cby_1__1__101_left_grid_pin_28_ ; +wire [0:0] cby_1__1__101_left_grid_pin_29_ ; +wire [0:0] cby_1__1__101_left_grid_pin_30_ ; +wire [0:0] cby_1__1__101_left_grid_pin_31_ ; +wire [0:0] cby_1__1__102_ccff_tail ; +wire [0:29] cby_1__1__102_chany_bottom_out ; +wire [0:29] cby_1__1__102_chany_top_out ; +wire [0:0] cby_1__1__102_left_grid_pin_16_ ; +wire [0:0] cby_1__1__102_left_grid_pin_17_ ; +wire [0:0] cby_1__1__102_left_grid_pin_18_ ; +wire [0:0] cby_1__1__102_left_grid_pin_19_ ; +wire [0:0] cby_1__1__102_left_grid_pin_20_ ; +wire [0:0] cby_1__1__102_left_grid_pin_21_ ; +wire [0:0] cby_1__1__102_left_grid_pin_22_ ; +wire [0:0] cby_1__1__102_left_grid_pin_23_ ; +wire [0:0] cby_1__1__102_left_grid_pin_24_ ; +wire [0:0] cby_1__1__102_left_grid_pin_25_ ; +wire [0:0] cby_1__1__102_left_grid_pin_26_ ; +wire [0:0] cby_1__1__102_left_grid_pin_27_ ; +wire [0:0] cby_1__1__102_left_grid_pin_28_ ; +wire [0:0] cby_1__1__102_left_grid_pin_29_ ; +wire [0:0] cby_1__1__102_left_grid_pin_30_ ; +wire [0:0] cby_1__1__102_left_grid_pin_31_ ; +wire [0:0] cby_1__1__103_ccff_tail ; +wire [0:29] cby_1__1__103_chany_bottom_out ; +wire [0:29] cby_1__1__103_chany_top_out ; +wire [0:0] cby_1__1__103_left_grid_pin_16_ ; +wire [0:0] cby_1__1__103_left_grid_pin_17_ ; +wire [0:0] cby_1__1__103_left_grid_pin_18_ ; +wire [0:0] cby_1__1__103_left_grid_pin_19_ ; +wire [0:0] cby_1__1__103_left_grid_pin_20_ ; +wire [0:0] cby_1__1__103_left_grid_pin_21_ ; +wire [0:0] cby_1__1__103_left_grid_pin_22_ ; +wire [0:0] cby_1__1__103_left_grid_pin_23_ ; +wire [0:0] cby_1__1__103_left_grid_pin_24_ ; +wire [0:0] cby_1__1__103_left_grid_pin_25_ ; +wire [0:0] cby_1__1__103_left_grid_pin_26_ ; +wire [0:0] cby_1__1__103_left_grid_pin_27_ ; +wire [0:0] cby_1__1__103_left_grid_pin_28_ ; +wire [0:0] cby_1__1__103_left_grid_pin_29_ ; +wire [0:0] cby_1__1__103_left_grid_pin_30_ ; +wire [0:0] cby_1__1__103_left_grid_pin_31_ ; +wire [0:0] cby_1__1__104_ccff_tail ; +wire [0:29] cby_1__1__104_chany_bottom_out ; +wire [0:29] cby_1__1__104_chany_top_out ; +wire [0:0] cby_1__1__104_left_grid_pin_16_ ; +wire [0:0] cby_1__1__104_left_grid_pin_17_ ; +wire [0:0] cby_1__1__104_left_grid_pin_18_ ; +wire [0:0] cby_1__1__104_left_grid_pin_19_ ; +wire [0:0] cby_1__1__104_left_grid_pin_20_ ; +wire [0:0] cby_1__1__104_left_grid_pin_21_ ; +wire [0:0] cby_1__1__104_left_grid_pin_22_ ; +wire [0:0] cby_1__1__104_left_grid_pin_23_ ; +wire [0:0] cby_1__1__104_left_grid_pin_24_ ; +wire [0:0] cby_1__1__104_left_grid_pin_25_ ; +wire [0:0] cby_1__1__104_left_grid_pin_26_ ; +wire [0:0] cby_1__1__104_left_grid_pin_27_ ; +wire [0:0] cby_1__1__104_left_grid_pin_28_ ; +wire [0:0] cby_1__1__104_left_grid_pin_29_ ; +wire [0:0] cby_1__1__104_left_grid_pin_30_ ; +wire [0:0] cby_1__1__104_left_grid_pin_31_ ; +wire [0:0] cby_1__1__105_ccff_tail ; +wire [0:29] cby_1__1__105_chany_bottom_out ; +wire [0:29] cby_1__1__105_chany_top_out ; +wire [0:0] cby_1__1__105_left_grid_pin_16_ ; +wire [0:0] cby_1__1__105_left_grid_pin_17_ ; +wire [0:0] cby_1__1__105_left_grid_pin_18_ ; +wire [0:0] cby_1__1__105_left_grid_pin_19_ ; +wire [0:0] cby_1__1__105_left_grid_pin_20_ ; +wire [0:0] cby_1__1__105_left_grid_pin_21_ ; +wire [0:0] cby_1__1__105_left_grid_pin_22_ ; +wire [0:0] cby_1__1__105_left_grid_pin_23_ ; +wire [0:0] cby_1__1__105_left_grid_pin_24_ ; +wire [0:0] cby_1__1__105_left_grid_pin_25_ ; +wire [0:0] cby_1__1__105_left_grid_pin_26_ ; +wire [0:0] cby_1__1__105_left_grid_pin_27_ ; +wire [0:0] cby_1__1__105_left_grid_pin_28_ ; +wire [0:0] cby_1__1__105_left_grid_pin_29_ ; +wire [0:0] cby_1__1__105_left_grid_pin_30_ ; +wire [0:0] cby_1__1__105_left_grid_pin_31_ ; +wire [0:0] cby_1__1__106_ccff_tail ; +wire [0:29] cby_1__1__106_chany_bottom_out ; +wire [0:29] cby_1__1__106_chany_top_out ; +wire [0:0] cby_1__1__106_left_grid_pin_16_ ; +wire [0:0] cby_1__1__106_left_grid_pin_17_ ; +wire [0:0] cby_1__1__106_left_grid_pin_18_ ; +wire [0:0] cby_1__1__106_left_grid_pin_19_ ; +wire [0:0] cby_1__1__106_left_grid_pin_20_ ; +wire [0:0] cby_1__1__106_left_grid_pin_21_ ; +wire [0:0] cby_1__1__106_left_grid_pin_22_ ; +wire [0:0] cby_1__1__106_left_grid_pin_23_ ; +wire [0:0] cby_1__1__106_left_grid_pin_24_ ; +wire [0:0] cby_1__1__106_left_grid_pin_25_ ; +wire [0:0] cby_1__1__106_left_grid_pin_26_ ; +wire [0:0] cby_1__1__106_left_grid_pin_27_ ; +wire [0:0] cby_1__1__106_left_grid_pin_28_ ; +wire [0:0] cby_1__1__106_left_grid_pin_29_ ; +wire [0:0] cby_1__1__106_left_grid_pin_30_ ; +wire [0:0] cby_1__1__106_left_grid_pin_31_ ; +wire [0:0] cby_1__1__107_ccff_tail ; +wire [0:29] cby_1__1__107_chany_bottom_out ; +wire [0:29] cby_1__1__107_chany_top_out ; +wire [0:0] cby_1__1__107_left_grid_pin_16_ ; +wire [0:0] cby_1__1__107_left_grid_pin_17_ ; +wire [0:0] cby_1__1__107_left_grid_pin_18_ ; +wire [0:0] cby_1__1__107_left_grid_pin_19_ ; +wire [0:0] cby_1__1__107_left_grid_pin_20_ ; +wire [0:0] cby_1__1__107_left_grid_pin_21_ ; +wire [0:0] cby_1__1__107_left_grid_pin_22_ ; +wire [0:0] cby_1__1__107_left_grid_pin_23_ ; +wire [0:0] cby_1__1__107_left_grid_pin_24_ ; +wire [0:0] cby_1__1__107_left_grid_pin_25_ ; +wire [0:0] cby_1__1__107_left_grid_pin_26_ ; +wire [0:0] cby_1__1__107_left_grid_pin_27_ ; +wire [0:0] cby_1__1__107_left_grid_pin_28_ ; +wire [0:0] cby_1__1__107_left_grid_pin_29_ ; +wire [0:0] cby_1__1__107_left_grid_pin_30_ ; +wire [0:0] cby_1__1__107_left_grid_pin_31_ ; +wire [0:0] cby_1__1__108_ccff_tail ; +wire [0:29] cby_1__1__108_chany_bottom_out ; +wire [0:29] cby_1__1__108_chany_top_out ; +wire [0:0] cby_1__1__108_left_grid_pin_16_ ; +wire [0:0] cby_1__1__108_left_grid_pin_17_ ; +wire [0:0] cby_1__1__108_left_grid_pin_18_ ; +wire [0:0] cby_1__1__108_left_grid_pin_19_ ; +wire [0:0] cby_1__1__108_left_grid_pin_20_ ; +wire [0:0] cby_1__1__108_left_grid_pin_21_ ; +wire [0:0] cby_1__1__108_left_grid_pin_22_ ; +wire [0:0] cby_1__1__108_left_grid_pin_23_ ; +wire [0:0] cby_1__1__108_left_grid_pin_24_ ; +wire [0:0] cby_1__1__108_left_grid_pin_25_ ; +wire [0:0] cby_1__1__108_left_grid_pin_26_ ; +wire [0:0] cby_1__1__108_left_grid_pin_27_ ; +wire [0:0] cby_1__1__108_left_grid_pin_28_ ; +wire [0:0] cby_1__1__108_left_grid_pin_29_ ; +wire [0:0] cby_1__1__108_left_grid_pin_30_ ; +wire [0:0] cby_1__1__108_left_grid_pin_31_ ; +wire [0:0] cby_1__1__109_ccff_tail ; +wire [0:29] cby_1__1__109_chany_bottom_out ; +wire [0:29] cby_1__1__109_chany_top_out ; +wire [0:0] cby_1__1__109_left_grid_pin_16_ ; +wire [0:0] cby_1__1__109_left_grid_pin_17_ ; +wire [0:0] cby_1__1__109_left_grid_pin_18_ ; +wire [0:0] cby_1__1__109_left_grid_pin_19_ ; +wire [0:0] cby_1__1__109_left_grid_pin_20_ ; +wire [0:0] cby_1__1__109_left_grid_pin_21_ ; +wire [0:0] cby_1__1__109_left_grid_pin_22_ ; +wire [0:0] cby_1__1__109_left_grid_pin_23_ ; +wire [0:0] cby_1__1__109_left_grid_pin_24_ ; +wire [0:0] cby_1__1__109_left_grid_pin_25_ ; +wire [0:0] cby_1__1__109_left_grid_pin_26_ ; +wire [0:0] cby_1__1__109_left_grid_pin_27_ ; +wire [0:0] cby_1__1__109_left_grid_pin_28_ ; +wire [0:0] cby_1__1__109_left_grid_pin_29_ ; +wire [0:0] cby_1__1__109_left_grid_pin_30_ ; +wire [0:0] cby_1__1__109_left_grid_pin_31_ ; +wire [0:0] cby_1__1__10_ccff_tail ; +wire [0:29] cby_1__1__10_chany_bottom_out ; +wire [0:29] cby_1__1__10_chany_top_out ; +wire [0:0] cby_1__1__10_left_grid_pin_16_ ; +wire [0:0] cby_1__1__10_left_grid_pin_17_ ; +wire [0:0] cby_1__1__10_left_grid_pin_18_ ; +wire [0:0] cby_1__1__10_left_grid_pin_19_ ; +wire [0:0] cby_1__1__10_left_grid_pin_20_ ; +wire [0:0] cby_1__1__10_left_grid_pin_21_ ; +wire [0:0] cby_1__1__10_left_grid_pin_22_ ; +wire [0:0] cby_1__1__10_left_grid_pin_23_ ; +wire [0:0] cby_1__1__10_left_grid_pin_24_ ; +wire [0:0] cby_1__1__10_left_grid_pin_25_ ; +wire [0:0] cby_1__1__10_left_grid_pin_26_ ; +wire [0:0] cby_1__1__10_left_grid_pin_27_ ; +wire [0:0] cby_1__1__10_left_grid_pin_28_ ; +wire [0:0] cby_1__1__10_left_grid_pin_29_ ; +wire [0:0] cby_1__1__10_left_grid_pin_30_ ; +wire [0:0] cby_1__1__10_left_grid_pin_31_ ; +wire [0:0] cby_1__1__110_ccff_tail ; +wire [0:29] cby_1__1__110_chany_bottom_out ; +wire [0:29] cby_1__1__110_chany_top_out ; +wire [0:0] cby_1__1__110_left_grid_pin_16_ ; +wire [0:0] cby_1__1__110_left_grid_pin_17_ ; +wire [0:0] cby_1__1__110_left_grid_pin_18_ ; +wire [0:0] cby_1__1__110_left_grid_pin_19_ ; +wire [0:0] cby_1__1__110_left_grid_pin_20_ ; +wire [0:0] cby_1__1__110_left_grid_pin_21_ ; +wire [0:0] cby_1__1__110_left_grid_pin_22_ ; +wire [0:0] cby_1__1__110_left_grid_pin_23_ ; +wire [0:0] cby_1__1__110_left_grid_pin_24_ ; +wire [0:0] cby_1__1__110_left_grid_pin_25_ ; +wire [0:0] cby_1__1__110_left_grid_pin_26_ ; +wire [0:0] cby_1__1__110_left_grid_pin_27_ ; +wire [0:0] cby_1__1__110_left_grid_pin_28_ ; +wire [0:0] cby_1__1__110_left_grid_pin_29_ ; +wire [0:0] cby_1__1__110_left_grid_pin_30_ ; +wire [0:0] cby_1__1__110_left_grid_pin_31_ ; +wire [0:0] cby_1__1__111_ccff_tail ; +wire [0:29] cby_1__1__111_chany_bottom_out ; +wire [0:29] cby_1__1__111_chany_top_out ; +wire [0:0] cby_1__1__111_left_grid_pin_16_ ; +wire [0:0] cby_1__1__111_left_grid_pin_17_ ; +wire [0:0] cby_1__1__111_left_grid_pin_18_ ; +wire [0:0] cby_1__1__111_left_grid_pin_19_ ; +wire [0:0] cby_1__1__111_left_grid_pin_20_ ; +wire [0:0] cby_1__1__111_left_grid_pin_21_ ; +wire [0:0] cby_1__1__111_left_grid_pin_22_ ; +wire [0:0] cby_1__1__111_left_grid_pin_23_ ; +wire [0:0] cby_1__1__111_left_grid_pin_24_ ; +wire [0:0] cby_1__1__111_left_grid_pin_25_ ; +wire [0:0] cby_1__1__111_left_grid_pin_26_ ; +wire [0:0] cby_1__1__111_left_grid_pin_27_ ; +wire [0:0] cby_1__1__111_left_grid_pin_28_ ; +wire [0:0] cby_1__1__111_left_grid_pin_29_ ; +wire [0:0] cby_1__1__111_left_grid_pin_30_ ; +wire [0:0] cby_1__1__111_left_grid_pin_31_ ; +wire [0:0] cby_1__1__112_ccff_tail ; +wire [0:29] cby_1__1__112_chany_bottom_out ; +wire [0:29] cby_1__1__112_chany_top_out ; +wire [0:0] cby_1__1__112_left_grid_pin_16_ ; +wire [0:0] cby_1__1__112_left_grid_pin_17_ ; +wire [0:0] cby_1__1__112_left_grid_pin_18_ ; +wire [0:0] cby_1__1__112_left_grid_pin_19_ ; +wire [0:0] cby_1__1__112_left_grid_pin_20_ ; +wire [0:0] cby_1__1__112_left_grid_pin_21_ ; +wire [0:0] cby_1__1__112_left_grid_pin_22_ ; +wire [0:0] cby_1__1__112_left_grid_pin_23_ ; +wire [0:0] cby_1__1__112_left_grid_pin_24_ ; +wire [0:0] cby_1__1__112_left_grid_pin_25_ ; +wire [0:0] cby_1__1__112_left_grid_pin_26_ ; +wire [0:0] cby_1__1__112_left_grid_pin_27_ ; +wire [0:0] cby_1__1__112_left_grid_pin_28_ ; +wire [0:0] cby_1__1__112_left_grid_pin_29_ ; +wire [0:0] cby_1__1__112_left_grid_pin_30_ ; +wire [0:0] cby_1__1__112_left_grid_pin_31_ ; +wire [0:0] cby_1__1__113_ccff_tail ; +wire [0:29] cby_1__1__113_chany_bottom_out ; +wire [0:29] cby_1__1__113_chany_top_out ; +wire [0:0] cby_1__1__113_left_grid_pin_16_ ; +wire [0:0] cby_1__1__113_left_grid_pin_17_ ; +wire [0:0] cby_1__1__113_left_grid_pin_18_ ; +wire [0:0] cby_1__1__113_left_grid_pin_19_ ; +wire [0:0] cby_1__1__113_left_grid_pin_20_ ; +wire [0:0] cby_1__1__113_left_grid_pin_21_ ; +wire [0:0] cby_1__1__113_left_grid_pin_22_ ; +wire [0:0] cby_1__1__113_left_grid_pin_23_ ; +wire [0:0] cby_1__1__113_left_grid_pin_24_ ; +wire [0:0] cby_1__1__113_left_grid_pin_25_ ; +wire [0:0] cby_1__1__113_left_grid_pin_26_ ; +wire [0:0] cby_1__1__113_left_grid_pin_27_ ; +wire [0:0] cby_1__1__113_left_grid_pin_28_ ; +wire [0:0] cby_1__1__113_left_grid_pin_29_ ; +wire [0:0] cby_1__1__113_left_grid_pin_30_ ; +wire [0:0] cby_1__1__113_left_grid_pin_31_ ; +wire [0:0] cby_1__1__114_ccff_tail ; +wire [0:29] cby_1__1__114_chany_bottom_out ; +wire [0:29] cby_1__1__114_chany_top_out ; +wire [0:0] cby_1__1__114_left_grid_pin_16_ ; +wire [0:0] cby_1__1__114_left_grid_pin_17_ ; +wire [0:0] cby_1__1__114_left_grid_pin_18_ ; +wire [0:0] cby_1__1__114_left_grid_pin_19_ ; +wire [0:0] cby_1__1__114_left_grid_pin_20_ ; +wire [0:0] cby_1__1__114_left_grid_pin_21_ ; +wire [0:0] cby_1__1__114_left_grid_pin_22_ ; +wire [0:0] cby_1__1__114_left_grid_pin_23_ ; +wire [0:0] cby_1__1__114_left_grid_pin_24_ ; +wire [0:0] cby_1__1__114_left_grid_pin_25_ ; +wire [0:0] cby_1__1__114_left_grid_pin_26_ ; +wire [0:0] cby_1__1__114_left_grid_pin_27_ ; +wire [0:0] cby_1__1__114_left_grid_pin_28_ ; +wire [0:0] cby_1__1__114_left_grid_pin_29_ ; +wire [0:0] cby_1__1__114_left_grid_pin_30_ ; +wire [0:0] cby_1__1__114_left_grid_pin_31_ ; +wire [0:0] cby_1__1__115_ccff_tail ; +wire [0:29] cby_1__1__115_chany_bottom_out ; +wire [0:29] cby_1__1__115_chany_top_out ; +wire [0:0] cby_1__1__115_left_grid_pin_16_ ; +wire [0:0] cby_1__1__115_left_grid_pin_17_ ; +wire [0:0] cby_1__1__115_left_grid_pin_18_ ; +wire [0:0] cby_1__1__115_left_grid_pin_19_ ; +wire [0:0] cby_1__1__115_left_grid_pin_20_ ; +wire [0:0] cby_1__1__115_left_grid_pin_21_ ; +wire [0:0] cby_1__1__115_left_grid_pin_22_ ; +wire [0:0] cby_1__1__115_left_grid_pin_23_ ; +wire [0:0] cby_1__1__115_left_grid_pin_24_ ; +wire [0:0] cby_1__1__115_left_grid_pin_25_ ; +wire [0:0] cby_1__1__115_left_grid_pin_26_ ; +wire [0:0] cby_1__1__115_left_grid_pin_27_ ; +wire [0:0] cby_1__1__115_left_grid_pin_28_ ; +wire [0:0] cby_1__1__115_left_grid_pin_29_ ; +wire [0:0] cby_1__1__115_left_grid_pin_30_ ; +wire [0:0] cby_1__1__115_left_grid_pin_31_ ; +wire [0:0] cby_1__1__116_ccff_tail ; +wire [0:29] cby_1__1__116_chany_bottom_out ; +wire [0:29] cby_1__1__116_chany_top_out ; +wire [0:0] cby_1__1__116_left_grid_pin_16_ ; +wire [0:0] cby_1__1__116_left_grid_pin_17_ ; +wire [0:0] cby_1__1__116_left_grid_pin_18_ ; +wire [0:0] cby_1__1__116_left_grid_pin_19_ ; +wire [0:0] cby_1__1__116_left_grid_pin_20_ ; +wire [0:0] cby_1__1__116_left_grid_pin_21_ ; +wire [0:0] cby_1__1__116_left_grid_pin_22_ ; +wire [0:0] cby_1__1__116_left_grid_pin_23_ ; +wire [0:0] cby_1__1__116_left_grid_pin_24_ ; +wire [0:0] cby_1__1__116_left_grid_pin_25_ ; +wire [0:0] cby_1__1__116_left_grid_pin_26_ ; +wire [0:0] cby_1__1__116_left_grid_pin_27_ ; +wire [0:0] cby_1__1__116_left_grid_pin_28_ ; +wire [0:0] cby_1__1__116_left_grid_pin_29_ ; +wire [0:0] cby_1__1__116_left_grid_pin_30_ ; +wire [0:0] cby_1__1__116_left_grid_pin_31_ ; +wire [0:0] cby_1__1__117_ccff_tail ; +wire [0:29] cby_1__1__117_chany_bottom_out ; +wire [0:29] cby_1__1__117_chany_top_out ; +wire [0:0] cby_1__1__117_left_grid_pin_16_ ; +wire [0:0] cby_1__1__117_left_grid_pin_17_ ; +wire [0:0] cby_1__1__117_left_grid_pin_18_ ; +wire [0:0] cby_1__1__117_left_grid_pin_19_ ; +wire [0:0] cby_1__1__117_left_grid_pin_20_ ; +wire [0:0] cby_1__1__117_left_grid_pin_21_ ; +wire [0:0] cby_1__1__117_left_grid_pin_22_ ; +wire [0:0] cby_1__1__117_left_grid_pin_23_ ; +wire [0:0] cby_1__1__117_left_grid_pin_24_ ; +wire [0:0] cby_1__1__117_left_grid_pin_25_ ; +wire [0:0] cby_1__1__117_left_grid_pin_26_ ; +wire [0:0] cby_1__1__117_left_grid_pin_27_ ; +wire [0:0] cby_1__1__117_left_grid_pin_28_ ; +wire [0:0] cby_1__1__117_left_grid_pin_29_ ; +wire [0:0] cby_1__1__117_left_grid_pin_30_ ; +wire [0:0] cby_1__1__117_left_grid_pin_31_ ; +wire [0:0] cby_1__1__118_ccff_tail ; +wire [0:29] cby_1__1__118_chany_bottom_out ; +wire [0:29] cby_1__1__118_chany_top_out ; +wire [0:0] cby_1__1__118_left_grid_pin_16_ ; +wire [0:0] cby_1__1__118_left_grid_pin_17_ ; +wire [0:0] cby_1__1__118_left_grid_pin_18_ ; +wire [0:0] cby_1__1__118_left_grid_pin_19_ ; +wire [0:0] cby_1__1__118_left_grid_pin_20_ ; +wire [0:0] cby_1__1__118_left_grid_pin_21_ ; +wire [0:0] cby_1__1__118_left_grid_pin_22_ ; +wire [0:0] cby_1__1__118_left_grid_pin_23_ ; +wire [0:0] cby_1__1__118_left_grid_pin_24_ ; +wire [0:0] cby_1__1__118_left_grid_pin_25_ ; +wire [0:0] cby_1__1__118_left_grid_pin_26_ ; +wire [0:0] cby_1__1__118_left_grid_pin_27_ ; +wire [0:0] cby_1__1__118_left_grid_pin_28_ ; +wire [0:0] cby_1__1__118_left_grid_pin_29_ ; +wire [0:0] cby_1__1__118_left_grid_pin_30_ ; +wire [0:0] cby_1__1__118_left_grid_pin_31_ ; +wire [0:0] cby_1__1__119_ccff_tail ; +wire [0:29] cby_1__1__119_chany_bottom_out ; +wire [0:29] cby_1__1__119_chany_top_out ; +wire [0:0] cby_1__1__119_left_grid_pin_16_ ; +wire [0:0] cby_1__1__119_left_grid_pin_17_ ; +wire [0:0] cby_1__1__119_left_grid_pin_18_ ; +wire [0:0] cby_1__1__119_left_grid_pin_19_ ; +wire [0:0] cby_1__1__119_left_grid_pin_20_ ; +wire [0:0] cby_1__1__119_left_grid_pin_21_ ; +wire [0:0] cby_1__1__119_left_grid_pin_22_ ; +wire [0:0] cby_1__1__119_left_grid_pin_23_ ; +wire [0:0] cby_1__1__119_left_grid_pin_24_ ; +wire [0:0] cby_1__1__119_left_grid_pin_25_ ; +wire [0:0] cby_1__1__119_left_grid_pin_26_ ; +wire [0:0] cby_1__1__119_left_grid_pin_27_ ; +wire [0:0] cby_1__1__119_left_grid_pin_28_ ; +wire [0:0] cby_1__1__119_left_grid_pin_29_ ; +wire [0:0] cby_1__1__119_left_grid_pin_30_ ; +wire [0:0] cby_1__1__119_left_grid_pin_31_ ; +wire [0:0] cby_1__1__11_ccff_tail ; +wire [0:29] cby_1__1__11_chany_bottom_out ; +wire [0:29] cby_1__1__11_chany_top_out ; +wire [0:0] cby_1__1__11_left_grid_pin_16_ ; +wire [0:0] cby_1__1__11_left_grid_pin_17_ ; +wire [0:0] cby_1__1__11_left_grid_pin_18_ ; +wire [0:0] cby_1__1__11_left_grid_pin_19_ ; +wire [0:0] cby_1__1__11_left_grid_pin_20_ ; +wire [0:0] cby_1__1__11_left_grid_pin_21_ ; +wire [0:0] cby_1__1__11_left_grid_pin_22_ ; +wire [0:0] cby_1__1__11_left_grid_pin_23_ ; +wire [0:0] cby_1__1__11_left_grid_pin_24_ ; +wire [0:0] cby_1__1__11_left_grid_pin_25_ ; +wire [0:0] cby_1__1__11_left_grid_pin_26_ ; +wire [0:0] cby_1__1__11_left_grid_pin_27_ ; +wire [0:0] cby_1__1__11_left_grid_pin_28_ ; +wire [0:0] cby_1__1__11_left_grid_pin_29_ ; +wire [0:0] cby_1__1__11_left_grid_pin_30_ ; +wire [0:0] cby_1__1__11_left_grid_pin_31_ ; +wire [0:0] cby_1__1__120_ccff_tail ; +wire [0:29] cby_1__1__120_chany_bottom_out ; +wire [0:29] cby_1__1__120_chany_top_out ; +wire [0:0] cby_1__1__120_left_grid_pin_16_ ; +wire [0:0] cby_1__1__120_left_grid_pin_17_ ; +wire [0:0] cby_1__1__120_left_grid_pin_18_ ; +wire [0:0] cby_1__1__120_left_grid_pin_19_ ; +wire [0:0] cby_1__1__120_left_grid_pin_20_ ; +wire [0:0] cby_1__1__120_left_grid_pin_21_ ; +wire [0:0] cby_1__1__120_left_grid_pin_22_ ; +wire [0:0] cby_1__1__120_left_grid_pin_23_ ; +wire [0:0] cby_1__1__120_left_grid_pin_24_ ; +wire [0:0] cby_1__1__120_left_grid_pin_25_ ; +wire [0:0] cby_1__1__120_left_grid_pin_26_ ; +wire [0:0] cby_1__1__120_left_grid_pin_27_ ; +wire [0:0] cby_1__1__120_left_grid_pin_28_ ; +wire [0:0] cby_1__1__120_left_grid_pin_29_ ; +wire [0:0] cby_1__1__120_left_grid_pin_30_ ; +wire [0:0] cby_1__1__120_left_grid_pin_31_ ; +wire [0:0] cby_1__1__121_ccff_tail ; +wire [0:29] cby_1__1__121_chany_bottom_out ; +wire [0:29] cby_1__1__121_chany_top_out ; +wire [0:0] cby_1__1__121_left_grid_pin_16_ ; +wire [0:0] cby_1__1__121_left_grid_pin_17_ ; +wire [0:0] cby_1__1__121_left_grid_pin_18_ ; +wire [0:0] cby_1__1__121_left_grid_pin_19_ ; +wire [0:0] cby_1__1__121_left_grid_pin_20_ ; +wire [0:0] cby_1__1__121_left_grid_pin_21_ ; +wire [0:0] cby_1__1__121_left_grid_pin_22_ ; +wire [0:0] cby_1__1__121_left_grid_pin_23_ ; +wire [0:0] cby_1__1__121_left_grid_pin_24_ ; +wire [0:0] cby_1__1__121_left_grid_pin_25_ ; +wire [0:0] cby_1__1__121_left_grid_pin_26_ ; +wire [0:0] cby_1__1__121_left_grid_pin_27_ ; +wire [0:0] cby_1__1__121_left_grid_pin_28_ ; +wire [0:0] cby_1__1__121_left_grid_pin_29_ ; +wire [0:0] cby_1__1__121_left_grid_pin_30_ ; +wire [0:0] cby_1__1__121_left_grid_pin_31_ ; +wire [0:0] cby_1__1__122_ccff_tail ; +wire [0:29] cby_1__1__122_chany_bottom_out ; +wire [0:29] cby_1__1__122_chany_top_out ; +wire [0:0] cby_1__1__122_left_grid_pin_16_ ; +wire [0:0] cby_1__1__122_left_grid_pin_17_ ; +wire [0:0] cby_1__1__122_left_grid_pin_18_ ; +wire [0:0] cby_1__1__122_left_grid_pin_19_ ; +wire [0:0] cby_1__1__122_left_grid_pin_20_ ; +wire [0:0] cby_1__1__122_left_grid_pin_21_ ; +wire [0:0] cby_1__1__122_left_grid_pin_22_ ; +wire [0:0] cby_1__1__122_left_grid_pin_23_ ; +wire [0:0] cby_1__1__122_left_grid_pin_24_ ; +wire [0:0] cby_1__1__122_left_grid_pin_25_ ; +wire [0:0] cby_1__1__122_left_grid_pin_26_ ; +wire [0:0] cby_1__1__122_left_grid_pin_27_ ; +wire [0:0] cby_1__1__122_left_grid_pin_28_ ; +wire [0:0] cby_1__1__122_left_grid_pin_29_ ; +wire [0:0] cby_1__1__122_left_grid_pin_30_ ; +wire [0:0] cby_1__1__122_left_grid_pin_31_ ; +wire [0:0] cby_1__1__123_ccff_tail ; +wire [0:29] cby_1__1__123_chany_bottom_out ; +wire [0:29] cby_1__1__123_chany_top_out ; +wire [0:0] cby_1__1__123_left_grid_pin_16_ ; +wire [0:0] cby_1__1__123_left_grid_pin_17_ ; +wire [0:0] cby_1__1__123_left_grid_pin_18_ ; +wire [0:0] cby_1__1__123_left_grid_pin_19_ ; +wire [0:0] cby_1__1__123_left_grid_pin_20_ ; +wire [0:0] cby_1__1__123_left_grid_pin_21_ ; +wire [0:0] cby_1__1__123_left_grid_pin_22_ ; +wire [0:0] cby_1__1__123_left_grid_pin_23_ ; +wire [0:0] cby_1__1__123_left_grid_pin_24_ ; +wire [0:0] cby_1__1__123_left_grid_pin_25_ ; +wire [0:0] cby_1__1__123_left_grid_pin_26_ ; +wire [0:0] cby_1__1__123_left_grid_pin_27_ ; +wire [0:0] cby_1__1__123_left_grid_pin_28_ ; +wire [0:0] cby_1__1__123_left_grid_pin_29_ ; +wire [0:0] cby_1__1__123_left_grid_pin_30_ ; +wire [0:0] cby_1__1__123_left_grid_pin_31_ ; +wire [0:0] cby_1__1__124_ccff_tail ; +wire [0:29] cby_1__1__124_chany_bottom_out ; +wire [0:29] cby_1__1__124_chany_top_out ; +wire [0:0] cby_1__1__124_left_grid_pin_16_ ; +wire [0:0] cby_1__1__124_left_grid_pin_17_ ; +wire [0:0] cby_1__1__124_left_grid_pin_18_ ; +wire [0:0] cby_1__1__124_left_grid_pin_19_ ; +wire [0:0] cby_1__1__124_left_grid_pin_20_ ; +wire [0:0] cby_1__1__124_left_grid_pin_21_ ; +wire [0:0] cby_1__1__124_left_grid_pin_22_ ; +wire [0:0] cby_1__1__124_left_grid_pin_23_ ; +wire [0:0] cby_1__1__124_left_grid_pin_24_ ; +wire [0:0] cby_1__1__124_left_grid_pin_25_ ; +wire [0:0] cby_1__1__124_left_grid_pin_26_ ; +wire [0:0] cby_1__1__124_left_grid_pin_27_ ; +wire [0:0] cby_1__1__124_left_grid_pin_28_ ; +wire [0:0] cby_1__1__124_left_grid_pin_29_ ; +wire [0:0] cby_1__1__124_left_grid_pin_30_ ; +wire [0:0] cby_1__1__124_left_grid_pin_31_ ; +wire [0:0] cby_1__1__125_ccff_tail ; +wire [0:29] cby_1__1__125_chany_bottom_out ; +wire [0:29] cby_1__1__125_chany_top_out ; +wire [0:0] cby_1__1__125_left_grid_pin_16_ ; +wire [0:0] cby_1__1__125_left_grid_pin_17_ ; +wire [0:0] cby_1__1__125_left_grid_pin_18_ ; +wire [0:0] cby_1__1__125_left_grid_pin_19_ ; +wire [0:0] cby_1__1__125_left_grid_pin_20_ ; +wire [0:0] cby_1__1__125_left_grid_pin_21_ ; +wire [0:0] cby_1__1__125_left_grid_pin_22_ ; +wire [0:0] cby_1__1__125_left_grid_pin_23_ ; +wire [0:0] cby_1__1__125_left_grid_pin_24_ ; +wire [0:0] cby_1__1__125_left_grid_pin_25_ ; +wire [0:0] cby_1__1__125_left_grid_pin_26_ ; +wire [0:0] cby_1__1__125_left_grid_pin_27_ ; +wire [0:0] cby_1__1__125_left_grid_pin_28_ ; +wire [0:0] cby_1__1__125_left_grid_pin_29_ ; +wire [0:0] cby_1__1__125_left_grid_pin_30_ ; +wire [0:0] cby_1__1__125_left_grid_pin_31_ ; +wire [0:0] cby_1__1__126_ccff_tail ; +wire [0:29] cby_1__1__126_chany_bottom_out ; +wire [0:29] cby_1__1__126_chany_top_out ; +wire [0:0] cby_1__1__126_left_grid_pin_16_ ; +wire [0:0] cby_1__1__126_left_grid_pin_17_ ; +wire [0:0] cby_1__1__126_left_grid_pin_18_ ; +wire [0:0] cby_1__1__126_left_grid_pin_19_ ; +wire [0:0] cby_1__1__126_left_grid_pin_20_ ; +wire [0:0] cby_1__1__126_left_grid_pin_21_ ; +wire [0:0] cby_1__1__126_left_grid_pin_22_ ; +wire [0:0] cby_1__1__126_left_grid_pin_23_ ; +wire [0:0] cby_1__1__126_left_grid_pin_24_ ; +wire [0:0] cby_1__1__126_left_grid_pin_25_ ; +wire [0:0] cby_1__1__126_left_grid_pin_26_ ; +wire [0:0] cby_1__1__126_left_grid_pin_27_ ; +wire [0:0] cby_1__1__126_left_grid_pin_28_ ; +wire [0:0] cby_1__1__126_left_grid_pin_29_ ; +wire [0:0] cby_1__1__126_left_grid_pin_30_ ; +wire [0:0] cby_1__1__126_left_grid_pin_31_ ; +wire [0:0] cby_1__1__127_ccff_tail ; +wire [0:29] cby_1__1__127_chany_bottom_out ; +wire [0:29] cby_1__1__127_chany_top_out ; +wire [0:0] cby_1__1__127_left_grid_pin_16_ ; +wire [0:0] cby_1__1__127_left_grid_pin_17_ ; +wire [0:0] cby_1__1__127_left_grid_pin_18_ ; +wire [0:0] cby_1__1__127_left_grid_pin_19_ ; +wire [0:0] cby_1__1__127_left_grid_pin_20_ ; +wire [0:0] cby_1__1__127_left_grid_pin_21_ ; +wire [0:0] cby_1__1__127_left_grid_pin_22_ ; +wire [0:0] cby_1__1__127_left_grid_pin_23_ ; +wire [0:0] cby_1__1__127_left_grid_pin_24_ ; +wire [0:0] cby_1__1__127_left_grid_pin_25_ ; +wire [0:0] cby_1__1__127_left_grid_pin_26_ ; +wire [0:0] cby_1__1__127_left_grid_pin_27_ ; +wire [0:0] cby_1__1__127_left_grid_pin_28_ ; +wire [0:0] cby_1__1__127_left_grid_pin_29_ ; +wire [0:0] cby_1__1__127_left_grid_pin_30_ ; +wire [0:0] cby_1__1__127_left_grid_pin_31_ ; +wire [0:0] cby_1__1__128_ccff_tail ; +wire [0:29] cby_1__1__128_chany_bottom_out ; +wire [0:29] cby_1__1__128_chany_top_out ; +wire [0:0] cby_1__1__128_left_grid_pin_16_ ; +wire [0:0] cby_1__1__128_left_grid_pin_17_ ; +wire [0:0] cby_1__1__128_left_grid_pin_18_ ; +wire [0:0] cby_1__1__128_left_grid_pin_19_ ; +wire [0:0] cby_1__1__128_left_grid_pin_20_ ; +wire [0:0] cby_1__1__128_left_grid_pin_21_ ; +wire [0:0] cby_1__1__128_left_grid_pin_22_ ; +wire [0:0] cby_1__1__128_left_grid_pin_23_ ; +wire [0:0] cby_1__1__128_left_grid_pin_24_ ; +wire [0:0] cby_1__1__128_left_grid_pin_25_ ; +wire [0:0] cby_1__1__128_left_grid_pin_26_ ; +wire [0:0] cby_1__1__128_left_grid_pin_27_ ; +wire [0:0] cby_1__1__128_left_grid_pin_28_ ; +wire [0:0] cby_1__1__128_left_grid_pin_29_ ; +wire [0:0] cby_1__1__128_left_grid_pin_30_ ; +wire [0:0] cby_1__1__128_left_grid_pin_31_ ; +wire [0:0] cby_1__1__129_ccff_tail ; +wire [0:29] cby_1__1__129_chany_bottom_out ; +wire [0:29] cby_1__1__129_chany_top_out ; +wire [0:0] cby_1__1__129_left_grid_pin_16_ ; +wire [0:0] cby_1__1__129_left_grid_pin_17_ ; +wire [0:0] cby_1__1__129_left_grid_pin_18_ ; +wire [0:0] cby_1__1__129_left_grid_pin_19_ ; +wire [0:0] cby_1__1__129_left_grid_pin_20_ ; +wire [0:0] cby_1__1__129_left_grid_pin_21_ ; +wire [0:0] cby_1__1__129_left_grid_pin_22_ ; +wire [0:0] cby_1__1__129_left_grid_pin_23_ ; +wire [0:0] cby_1__1__129_left_grid_pin_24_ ; +wire [0:0] cby_1__1__129_left_grid_pin_25_ ; +wire [0:0] cby_1__1__129_left_grid_pin_26_ ; +wire [0:0] cby_1__1__129_left_grid_pin_27_ ; +wire [0:0] cby_1__1__129_left_grid_pin_28_ ; +wire [0:0] cby_1__1__129_left_grid_pin_29_ ; +wire [0:0] cby_1__1__129_left_grid_pin_30_ ; +wire [0:0] cby_1__1__129_left_grid_pin_31_ ; +wire [0:0] cby_1__1__12_ccff_tail ; +wire [0:29] cby_1__1__12_chany_bottom_out ; +wire [0:29] cby_1__1__12_chany_top_out ; +wire [0:0] cby_1__1__12_left_grid_pin_16_ ; +wire [0:0] cby_1__1__12_left_grid_pin_17_ ; +wire [0:0] cby_1__1__12_left_grid_pin_18_ ; +wire [0:0] cby_1__1__12_left_grid_pin_19_ ; +wire [0:0] cby_1__1__12_left_grid_pin_20_ ; +wire [0:0] cby_1__1__12_left_grid_pin_21_ ; +wire [0:0] cby_1__1__12_left_grid_pin_22_ ; +wire [0:0] cby_1__1__12_left_grid_pin_23_ ; +wire [0:0] cby_1__1__12_left_grid_pin_24_ ; +wire [0:0] cby_1__1__12_left_grid_pin_25_ ; +wire [0:0] cby_1__1__12_left_grid_pin_26_ ; +wire [0:0] cby_1__1__12_left_grid_pin_27_ ; +wire [0:0] cby_1__1__12_left_grid_pin_28_ ; +wire [0:0] cby_1__1__12_left_grid_pin_29_ ; +wire [0:0] cby_1__1__12_left_grid_pin_30_ ; +wire [0:0] cby_1__1__12_left_grid_pin_31_ ; +wire [0:0] cby_1__1__130_ccff_tail ; +wire [0:29] cby_1__1__130_chany_bottom_out ; +wire [0:29] cby_1__1__130_chany_top_out ; +wire [0:0] cby_1__1__130_left_grid_pin_16_ ; +wire [0:0] cby_1__1__130_left_grid_pin_17_ ; +wire [0:0] cby_1__1__130_left_grid_pin_18_ ; +wire [0:0] cby_1__1__130_left_grid_pin_19_ ; +wire [0:0] cby_1__1__130_left_grid_pin_20_ ; +wire [0:0] cby_1__1__130_left_grid_pin_21_ ; +wire [0:0] cby_1__1__130_left_grid_pin_22_ ; +wire [0:0] cby_1__1__130_left_grid_pin_23_ ; +wire [0:0] cby_1__1__130_left_grid_pin_24_ ; +wire [0:0] cby_1__1__130_left_grid_pin_25_ ; +wire [0:0] cby_1__1__130_left_grid_pin_26_ ; +wire [0:0] cby_1__1__130_left_grid_pin_27_ ; +wire [0:0] cby_1__1__130_left_grid_pin_28_ ; +wire [0:0] cby_1__1__130_left_grid_pin_29_ ; +wire [0:0] cby_1__1__130_left_grid_pin_30_ ; +wire [0:0] cby_1__1__130_left_grid_pin_31_ ; +wire [0:0] cby_1__1__131_ccff_tail ; +wire [0:29] cby_1__1__131_chany_bottom_out ; +wire [0:29] cby_1__1__131_chany_top_out ; +wire [0:0] cby_1__1__131_left_grid_pin_16_ ; +wire [0:0] cby_1__1__131_left_grid_pin_17_ ; +wire [0:0] cby_1__1__131_left_grid_pin_18_ ; +wire [0:0] cby_1__1__131_left_grid_pin_19_ ; +wire [0:0] cby_1__1__131_left_grid_pin_20_ ; +wire [0:0] cby_1__1__131_left_grid_pin_21_ ; +wire [0:0] cby_1__1__131_left_grid_pin_22_ ; +wire [0:0] cby_1__1__131_left_grid_pin_23_ ; +wire [0:0] cby_1__1__131_left_grid_pin_24_ ; +wire [0:0] cby_1__1__131_left_grid_pin_25_ ; +wire [0:0] cby_1__1__131_left_grid_pin_26_ ; +wire [0:0] cby_1__1__131_left_grid_pin_27_ ; +wire [0:0] cby_1__1__131_left_grid_pin_28_ ; +wire [0:0] cby_1__1__131_left_grid_pin_29_ ; +wire [0:0] cby_1__1__131_left_grid_pin_30_ ; +wire [0:0] cby_1__1__131_left_grid_pin_31_ ; +wire [0:0] cby_1__1__13_ccff_tail ; +wire [0:29] cby_1__1__13_chany_bottom_out ; +wire [0:29] cby_1__1__13_chany_top_out ; +wire [0:0] cby_1__1__13_left_grid_pin_16_ ; +wire [0:0] cby_1__1__13_left_grid_pin_17_ ; +wire [0:0] cby_1__1__13_left_grid_pin_18_ ; +wire [0:0] cby_1__1__13_left_grid_pin_19_ ; +wire [0:0] cby_1__1__13_left_grid_pin_20_ ; +wire [0:0] cby_1__1__13_left_grid_pin_21_ ; +wire [0:0] cby_1__1__13_left_grid_pin_22_ ; +wire [0:0] cby_1__1__13_left_grid_pin_23_ ; +wire [0:0] cby_1__1__13_left_grid_pin_24_ ; +wire [0:0] cby_1__1__13_left_grid_pin_25_ ; +wire [0:0] cby_1__1__13_left_grid_pin_26_ ; +wire [0:0] cby_1__1__13_left_grid_pin_27_ ; +wire [0:0] cby_1__1__13_left_grid_pin_28_ ; +wire [0:0] cby_1__1__13_left_grid_pin_29_ ; +wire [0:0] cby_1__1__13_left_grid_pin_30_ ; +wire [0:0] cby_1__1__13_left_grid_pin_31_ ; +wire [0:0] cby_1__1__14_ccff_tail ; +wire [0:29] cby_1__1__14_chany_bottom_out ; +wire [0:29] cby_1__1__14_chany_top_out ; +wire [0:0] cby_1__1__14_left_grid_pin_16_ ; +wire [0:0] cby_1__1__14_left_grid_pin_17_ ; +wire [0:0] cby_1__1__14_left_grid_pin_18_ ; +wire [0:0] cby_1__1__14_left_grid_pin_19_ ; +wire [0:0] cby_1__1__14_left_grid_pin_20_ ; +wire [0:0] cby_1__1__14_left_grid_pin_21_ ; +wire [0:0] cby_1__1__14_left_grid_pin_22_ ; +wire [0:0] cby_1__1__14_left_grid_pin_23_ ; +wire [0:0] cby_1__1__14_left_grid_pin_24_ ; +wire [0:0] cby_1__1__14_left_grid_pin_25_ ; +wire [0:0] cby_1__1__14_left_grid_pin_26_ ; +wire [0:0] cby_1__1__14_left_grid_pin_27_ ; +wire [0:0] cby_1__1__14_left_grid_pin_28_ ; +wire [0:0] cby_1__1__14_left_grid_pin_29_ ; +wire [0:0] cby_1__1__14_left_grid_pin_30_ ; +wire [0:0] cby_1__1__14_left_grid_pin_31_ ; +wire [0:0] cby_1__1__15_ccff_tail ; +wire [0:29] cby_1__1__15_chany_bottom_out ; +wire [0:29] cby_1__1__15_chany_top_out ; +wire [0:0] cby_1__1__15_left_grid_pin_16_ ; +wire [0:0] cby_1__1__15_left_grid_pin_17_ ; +wire [0:0] cby_1__1__15_left_grid_pin_18_ ; +wire [0:0] cby_1__1__15_left_grid_pin_19_ ; +wire [0:0] cby_1__1__15_left_grid_pin_20_ ; +wire [0:0] cby_1__1__15_left_grid_pin_21_ ; +wire [0:0] cby_1__1__15_left_grid_pin_22_ ; +wire [0:0] cby_1__1__15_left_grid_pin_23_ ; +wire [0:0] cby_1__1__15_left_grid_pin_24_ ; +wire [0:0] cby_1__1__15_left_grid_pin_25_ ; +wire [0:0] cby_1__1__15_left_grid_pin_26_ ; +wire [0:0] cby_1__1__15_left_grid_pin_27_ ; +wire [0:0] cby_1__1__15_left_grid_pin_28_ ; +wire [0:0] cby_1__1__15_left_grid_pin_29_ ; +wire [0:0] cby_1__1__15_left_grid_pin_30_ ; +wire [0:0] cby_1__1__15_left_grid_pin_31_ ; +wire [0:0] cby_1__1__16_ccff_tail ; +wire [0:29] cby_1__1__16_chany_bottom_out ; +wire [0:29] cby_1__1__16_chany_top_out ; +wire [0:0] cby_1__1__16_left_grid_pin_16_ ; +wire [0:0] cby_1__1__16_left_grid_pin_17_ ; +wire [0:0] cby_1__1__16_left_grid_pin_18_ ; +wire [0:0] cby_1__1__16_left_grid_pin_19_ ; +wire [0:0] cby_1__1__16_left_grid_pin_20_ ; +wire [0:0] cby_1__1__16_left_grid_pin_21_ ; +wire [0:0] cby_1__1__16_left_grid_pin_22_ ; +wire [0:0] cby_1__1__16_left_grid_pin_23_ ; +wire [0:0] cby_1__1__16_left_grid_pin_24_ ; +wire [0:0] cby_1__1__16_left_grid_pin_25_ ; +wire [0:0] cby_1__1__16_left_grid_pin_26_ ; +wire [0:0] cby_1__1__16_left_grid_pin_27_ ; +wire [0:0] cby_1__1__16_left_grid_pin_28_ ; +wire [0:0] cby_1__1__16_left_grid_pin_29_ ; +wire [0:0] cby_1__1__16_left_grid_pin_30_ ; +wire [0:0] cby_1__1__16_left_grid_pin_31_ ; +wire [0:0] cby_1__1__17_ccff_tail ; +wire [0:29] cby_1__1__17_chany_bottom_out ; +wire [0:29] cby_1__1__17_chany_top_out ; +wire [0:0] cby_1__1__17_left_grid_pin_16_ ; +wire [0:0] cby_1__1__17_left_grid_pin_17_ ; +wire [0:0] cby_1__1__17_left_grid_pin_18_ ; +wire [0:0] cby_1__1__17_left_grid_pin_19_ ; +wire [0:0] cby_1__1__17_left_grid_pin_20_ ; +wire [0:0] cby_1__1__17_left_grid_pin_21_ ; +wire [0:0] cby_1__1__17_left_grid_pin_22_ ; +wire [0:0] cby_1__1__17_left_grid_pin_23_ ; +wire [0:0] cby_1__1__17_left_grid_pin_24_ ; +wire [0:0] cby_1__1__17_left_grid_pin_25_ ; +wire [0:0] cby_1__1__17_left_grid_pin_26_ ; +wire [0:0] cby_1__1__17_left_grid_pin_27_ ; +wire [0:0] cby_1__1__17_left_grid_pin_28_ ; +wire [0:0] cby_1__1__17_left_grid_pin_29_ ; +wire [0:0] cby_1__1__17_left_grid_pin_30_ ; +wire [0:0] cby_1__1__17_left_grid_pin_31_ ; +wire [0:0] cby_1__1__18_ccff_tail ; +wire [0:29] cby_1__1__18_chany_bottom_out ; +wire [0:29] cby_1__1__18_chany_top_out ; +wire [0:0] cby_1__1__18_left_grid_pin_16_ ; +wire [0:0] cby_1__1__18_left_grid_pin_17_ ; +wire [0:0] cby_1__1__18_left_grid_pin_18_ ; +wire [0:0] cby_1__1__18_left_grid_pin_19_ ; +wire [0:0] cby_1__1__18_left_grid_pin_20_ ; +wire [0:0] cby_1__1__18_left_grid_pin_21_ ; +wire [0:0] cby_1__1__18_left_grid_pin_22_ ; +wire [0:0] cby_1__1__18_left_grid_pin_23_ ; +wire [0:0] cby_1__1__18_left_grid_pin_24_ ; +wire [0:0] cby_1__1__18_left_grid_pin_25_ ; +wire [0:0] cby_1__1__18_left_grid_pin_26_ ; +wire [0:0] cby_1__1__18_left_grid_pin_27_ ; +wire [0:0] cby_1__1__18_left_grid_pin_28_ ; +wire [0:0] cby_1__1__18_left_grid_pin_29_ ; +wire [0:0] cby_1__1__18_left_grid_pin_30_ ; +wire [0:0] cby_1__1__18_left_grid_pin_31_ ; +wire [0:0] cby_1__1__19_ccff_tail ; +wire [0:29] cby_1__1__19_chany_bottom_out ; +wire [0:29] cby_1__1__19_chany_top_out ; +wire [0:0] cby_1__1__19_left_grid_pin_16_ ; +wire [0:0] cby_1__1__19_left_grid_pin_17_ ; +wire [0:0] cby_1__1__19_left_grid_pin_18_ ; +wire [0:0] cby_1__1__19_left_grid_pin_19_ ; +wire [0:0] cby_1__1__19_left_grid_pin_20_ ; +wire [0:0] cby_1__1__19_left_grid_pin_21_ ; +wire [0:0] cby_1__1__19_left_grid_pin_22_ ; +wire [0:0] cby_1__1__19_left_grid_pin_23_ ; +wire [0:0] cby_1__1__19_left_grid_pin_24_ ; +wire [0:0] cby_1__1__19_left_grid_pin_25_ ; +wire [0:0] cby_1__1__19_left_grid_pin_26_ ; +wire [0:0] cby_1__1__19_left_grid_pin_27_ ; +wire [0:0] cby_1__1__19_left_grid_pin_28_ ; +wire [0:0] cby_1__1__19_left_grid_pin_29_ ; +wire [0:0] cby_1__1__19_left_grid_pin_30_ ; +wire [0:0] cby_1__1__19_left_grid_pin_31_ ; +wire [0:0] cby_1__1__1_ccff_tail ; +wire [0:29] cby_1__1__1_chany_bottom_out ; +wire [0:29] cby_1__1__1_chany_top_out ; +wire [0:0] cby_1__1__1_left_grid_pin_16_ ; +wire [0:0] cby_1__1__1_left_grid_pin_17_ ; +wire [0:0] cby_1__1__1_left_grid_pin_18_ ; +wire [0:0] cby_1__1__1_left_grid_pin_19_ ; +wire [0:0] cby_1__1__1_left_grid_pin_20_ ; +wire [0:0] cby_1__1__1_left_grid_pin_21_ ; +wire [0:0] cby_1__1__1_left_grid_pin_22_ ; +wire [0:0] cby_1__1__1_left_grid_pin_23_ ; +wire [0:0] cby_1__1__1_left_grid_pin_24_ ; +wire [0:0] cby_1__1__1_left_grid_pin_25_ ; +wire [0:0] cby_1__1__1_left_grid_pin_26_ ; +wire [0:0] cby_1__1__1_left_grid_pin_27_ ; +wire [0:0] cby_1__1__1_left_grid_pin_28_ ; +wire [0:0] cby_1__1__1_left_grid_pin_29_ ; +wire [0:0] cby_1__1__1_left_grid_pin_30_ ; +wire [0:0] cby_1__1__1_left_grid_pin_31_ ; +wire [0:0] cby_1__1__20_ccff_tail ; +wire [0:29] cby_1__1__20_chany_bottom_out ; +wire [0:29] cby_1__1__20_chany_top_out ; +wire [0:0] cby_1__1__20_left_grid_pin_16_ ; +wire [0:0] cby_1__1__20_left_grid_pin_17_ ; +wire [0:0] cby_1__1__20_left_grid_pin_18_ ; +wire [0:0] cby_1__1__20_left_grid_pin_19_ ; +wire [0:0] cby_1__1__20_left_grid_pin_20_ ; +wire [0:0] cby_1__1__20_left_grid_pin_21_ ; +wire [0:0] cby_1__1__20_left_grid_pin_22_ ; +wire [0:0] cby_1__1__20_left_grid_pin_23_ ; +wire [0:0] cby_1__1__20_left_grid_pin_24_ ; +wire [0:0] cby_1__1__20_left_grid_pin_25_ ; +wire [0:0] cby_1__1__20_left_grid_pin_26_ ; +wire [0:0] cby_1__1__20_left_grid_pin_27_ ; +wire [0:0] cby_1__1__20_left_grid_pin_28_ ; +wire [0:0] cby_1__1__20_left_grid_pin_29_ ; +wire [0:0] cby_1__1__20_left_grid_pin_30_ ; +wire [0:0] cby_1__1__20_left_grid_pin_31_ ; +wire [0:0] cby_1__1__21_ccff_tail ; +wire [0:29] cby_1__1__21_chany_bottom_out ; +wire [0:29] cby_1__1__21_chany_top_out ; +wire [0:0] cby_1__1__21_left_grid_pin_16_ ; +wire [0:0] cby_1__1__21_left_grid_pin_17_ ; +wire [0:0] cby_1__1__21_left_grid_pin_18_ ; +wire [0:0] cby_1__1__21_left_grid_pin_19_ ; +wire [0:0] cby_1__1__21_left_grid_pin_20_ ; +wire [0:0] cby_1__1__21_left_grid_pin_21_ ; +wire [0:0] cby_1__1__21_left_grid_pin_22_ ; +wire [0:0] cby_1__1__21_left_grid_pin_23_ ; +wire [0:0] cby_1__1__21_left_grid_pin_24_ ; +wire [0:0] cby_1__1__21_left_grid_pin_25_ ; +wire [0:0] cby_1__1__21_left_grid_pin_26_ ; +wire [0:0] cby_1__1__21_left_grid_pin_27_ ; +wire [0:0] cby_1__1__21_left_grid_pin_28_ ; +wire [0:0] cby_1__1__21_left_grid_pin_29_ ; +wire [0:0] cby_1__1__21_left_grid_pin_30_ ; +wire [0:0] cby_1__1__21_left_grid_pin_31_ ; +wire [0:0] cby_1__1__22_ccff_tail ; +wire [0:29] cby_1__1__22_chany_bottom_out ; +wire [0:29] cby_1__1__22_chany_top_out ; +wire [0:0] cby_1__1__22_left_grid_pin_16_ ; +wire [0:0] cby_1__1__22_left_grid_pin_17_ ; +wire [0:0] cby_1__1__22_left_grid_pin_18_ ; +wire [0:0] cby_1__1__22_left_grid_pin_19_ ; +wire [0:0] cby_1__1__22_left_grid_pin_20_ ; +wire [0:0] cby_1__1__22_left_grid_pin_21_ ; +wire [0:0] cby_1__1__22_left_grid_pin_22_ ; +wire [0:0] cby_1__1__22_left_grid_pin_23_ ; +wire [0:0] cby_1__1__22_left_grid_pin_24_ ; +wire [0:0] cby_1__1__22_left_grid_pin_25_ ; +wire [0:0] cby_1__1__22_left_grid_pin_26_ ; +wire [0:0] cby_1__1__22_left_grid_pin_27_ ; +wire [0:0] cby_1__1__22_left_grid_pin_28_ ; +wire [0:0] cby_1__1__22_left_grid_pin_29_ ; +wire [0:0] cby_1__1__22_left_grid_pin_30_ ; +wire [0:0] cby_1__1__22_left_grid_pin_31_ ; +wire [0:0] cby_1__1__23_ccff_tail ; +wire [0:29] cby_1__1__23_chany_bottom_out ; +wire [0:29] cby_1__1__23_chany_top_out ; +wire [0:0] cby_1__1__23_left_grid_pin_16_ ; +wire [0:0] cby_1__1__23_left_grid_pin_17_ ; +wire [0:0] cby_1__1__23_left_grid_pin_18_ ; +wire [0:0] cby_1__1__23_left_grid_pin_19_ ; +wire [0:0] cby_1__1__23_left_grid_pin_20_ ; +wire [0:0] cby_1__1__23_left_grid_pin_21_ ; +wire [0:0] cby_1__1__23_left_grid_pin_22_ ; +wire [0:0] cby_1__1__23_left_grid_pin_23_ ; +wire [0:0] cby_1__1__23_left_grid_pin_24_ ; +wire [0:0] cby_1__1__23_left_grid_pin_25_ ; +wire [0:0] cby_1__1__23_left_grid_pin_26_ ; +wire [0:0] cby_1__1__23_left_grid_pin_27_ ; +wire [0:0] cby_1__1__23_left_grid_pin_28_ ; +wire [0:0] cby_1__1__23_left_grid_pin_29_ ; +wire [0:0] cby_1__1__23_left_grid_pin_30_ ; +wire [0:0] cby_1__1__23_left_grid_pin_31_ ; +wire [0:0] cby_1__1__24_ccff_tail ; +wire [0:29] cby_1__1__24_chany_bottom_out ; +wire [0:29] cby_1__1__24_chany_top_out ; +wire [0:0] cby_1__1__24_left_grid_pin_16_ ; +wire [0:0] cby_1__1__24_left_grid_pin_17_ ; +wire [0:0] cby_1__1__24_left_grid_pin_18_ ; +wire [0:0] cby_1__1__24_left_grid_pin_19_ ; +wire [0:0] cby_1__1__24_left_grid_pin_20_ ; +wire [0:0] cby_1__1__24_left_grid_pin_21_ ; +wire [0:0] cby_1__1__24_left_grid_pin_22_ ; +wire [0:0] cby_1__1__24_left_grid_pin_23_ ; +wire [0:0] cby_1__1__24_left_grid_pin_24_ ; +wire [0:0] cby_1__1__24_left_grid_pin_25_ ; +wire [0:0] cby_1__1__24_left_grid_pin_26_ ; +wire [0:0] cby_1__1__24_left_grid_pin_27_ ; +wire [0:0] cby_1__1__24_left_grid_pin_28_ ; +wire [0:0] cby_1__1__24_left_grid_pin_29_ ; +wire [0:0] cby_1__1__24_left_grid_pin_30_ ; +wire [0:0] cby_1__1__24_left_grid_pin_31_ ; +wire [0:0] cby_1__1__25_ccff_tail ; +wire [0:29] cby_1__1__25_chany_bottom_out ; +wire [0:29] cby_1__1__25_chany_top_out ; +wire [0:0] cby_1__1__25_left_grid_pin_16_ ; +wire [0:0] cby_1__1__25_left_grid_pin_17_ ; +wire [0:0] cby_1__1__25_left_grid_pin_18_ ; +wire [0:0] cby_1__1__25_left_grid_pin_19_ ; +wire [0:0] cby_1__1__25_left_grid_pin_20_ ; +wire [0:0] cby_1__1__25_left_grid_pin_21_ ; +wire [0:0] cby_1__1__25_left_grid_pin_22_ ; +wire [0:0] cby_1__1__25_left_grid_pin_23_ ; +wire [0:0] cby_1__1__25_left_grid_pin_24_ ; +wire [0:0] cby_1__1__25_left_grid_pin_25_ ; +wire [0:0] cby_1__1__25_left_grid_pin_26_ ; +wire [0:0] cby_1__1__25_left_grid_pin_27_ ; +wire [0:0] cby_1__1__25_left_grid_pin_28_ ; +wire [0:0] cby_1__1__25_left_grid_pin_29_ ; +wire [0:0] cby_1__1__25_left_grid_pin_30_ ; +wire [0:0] cby_1__1__25_left_grid_pin_31_ ; +wire [0:0] cby_1__1__26_ccff_tail ; +wire [0:29] cby_1__1__26_chany_bottom_out ; +wire [0:29] cby_1__1__26_chany_top_out ; +wire [0:0] cby_1__1__26_left_grid_pin_16_ ; +wire [0:0] cby_1__1__26_left_grid_pin_17_ ; +wire [0:0] cby_1__1__26_left_grid_pin_18_ ; +wire [0:0] cby_1__1__26_left_grid_pin_19_ ; +wire [0:0] cby_1__1__26_left_grid_pin_20_ ; +wire [0:0] cby_1__1__26_left_grid_pin_21_ ; +wire [0:0] cby_1__1__26_left_grid_pin_22_ ; +wire [0:0] cby_1__1__26_left_grid_pin_23_ ; +wire [0:0] cby_1__1__26_left_grid_pin_24_ ; +wire [0:0] cby_1__1__26_left_grid_pin_25_ ; +wire [0:0] cby_1__1__26_left_grid_pin_26_ ; +wire [0:0] cby_1__1__26_left_grid_pin_27_ ; +wire [0:0] cby_1__1__26_left_grid_pin_28_ ; +wire [0:0] cby_1__1__26_left_grid_pin_29_ ; +wire [0:0] cby_1__1__26_left_grid_pin_30_ ; +wire [0:0] cby_1__1__26_left_grid_pin_31_ ; +wire [0:0] cby_1__1__27_ccff_tail ; +wire [0:29] cby_1__1__27_chany_bottom_out ; +wire [0:29] cby_1__1__27_chany_top_out ; +wire [0:0] cby_1__1__27_left_grid_pin_16_ ; +wire [0:0] cby_1__1__27_left_grid_pin_17_ ; +wire [0:0] cby_1__1__27_left_grid_pin_18_ ; +wire [0:0] cby_1__1__27_left_grid_pin_19_ ; +wire [0:0] cby_1__1__27_left_grid_pin_20_ ; +wire [0:0] cby_1__1__27_left_grid_pin_21_ ; +wire [0:0] cby_1__1__27_left_grid_pin_22_ ; +wire [0:0] cby_1__1__27_left_grid_pin_23_ ; +wire [0:0] cby_1__1__27_left_grid_pin_24_ ; +wire [0:0] cby_1__1__27_left_grid_pin_25_ ; +wire [0:0] cby_1__1__27_left_grid_pin_26_ ; +wire [0:0] cby_1__1__27_left_grid_pin_27_ ; +wire [0:0] cby_1__1__27_left_grid_pin_28_ ; +wire [0:0] cby_1__1__27_left_grid_pin_29_ ; +wire [0:0] cby_1__1__27_left_grid_pin_30_ ; +wire [0:0] cby_1__1__27_left_grid_pin_31_ ; +wire [0:0] cby_1__1__28_ccff_tail ; +wire [0:29] cby_1__1__28_chany_bottom_out ; +wire [0:29] cby_1__1__28_chany_top_out ; +wire [0:0] cby_1__1__28_left_grid_pin_16_ ; +wire [0:0] cby_1__1__28_left_grid_pin_17_ ; +wire [0:0] cby_1__1__28_left_grid_pin_18_ ; +wire [0:0] cby_1__1__28_left_grid_pin_19_ ; +wire [0:0] cby_1__1__28_left_grid_pin_20_ ; +wire [0:0] cby_1__1__28_left_grid_pin_21_ ; +wire [0:0] cby_1__1__28_left_grid_pin_22_ ; +wire [0:0] cby_1__1__28_left_grid_pin_23_ ; +wire [0:0] cby_1__1__28_left_grid_pin_24_ ; +wire [0:0] cby_1__1__28_left_grid_pin_25_ ; +wire [0:0] cby_1__1__28_left_grid_pin_26_ ; +wire [0:0] cby_1__1__28_left_grid_pin_27_ ; +wire [0:0] cby_1__1__28_left_grid_pin_28_ ; +wire [0:0] cby_1__1__28_left_grid_pin_29_ ; +wire [0:0] cby_1__1__28_left_grid_pin_30_ ; +wire [0:0] cby_1__1__28_left_grid_pin_31_ ; +wire [0:0] cby_1__1__29_ccff_tail ; +wire [0:29] cby_1__1__29_chany_bottom_out ; +wire [0:29] cby_1__1__29_chany_top_out ; +wire [0:0] cby_1__1__29_left_grid_pin_16_ ; +wire [0:0] cby_1__1__29_left_grid_pin_17_ ; +wire [0:0] cby_1__1__29_left_grid_pin_18_ ; +wire [0:0] cby_1__1__29_left_grid_pin_19_ ; +wire [0:0] cby_1__1__29_left_grid_pin_20_ ; +wire [0:0] cby_1__1__29_left_grid_pin_21_ ; +wire [0:0] cby_1__1__29_left_grid_pin_22_ ; +wire [0:0] cby_1__1__29_left_grid_pin_23_ ; +wire [0:0] cby_1__1__29_left_grid_pin_24_ ; +wire [0:0] cby_1__1__29_left_grid_pin_25_ ; +wire [0:0] cby_1__1__29_left_grid_pin_26_ ; +wire [0:0] cby_1__1__29_left_grid_pin_27_ ; +wire [0:0] cby_1__1__29_left_grid_pin_28_ ; +wire [0:0] cby_1__1__29_left_grid_pin_29_ ; +wire [0:0] cby_1__1__29_left_grid_pin_30_ ; +wire [0:0] cby_1__1__29_left_grid_pin_31_ ; +wire [0:0] cby_1__1__2_ccff_tail ; +wire [0:29] cby_1__1__2_chany_bottom_out ; +wire [0:29] cby_1__1__2_chany_top_out ; +wire [0:0] cby_1__1__2_left_grid_pin_16_ ; +wire [0:0] cby_1__1__2_left_grid_pin_17_ ; +wire [0:0] cby_1__1__2_left_grid_pin_18_ ; +wire [0:0] cby_1__1__2_left_grid_pin_19_ ; +wire [0:0] cby_1__1__2_left_grid_pin_20_ ; +wire [0:0] cby_1__1__2_left_grid_pin_21_ ; +wire [0:0] cby_1__1__2_left_grid_pin_22_ ; +wire [0:0] cby_1__1__2_left_grid_pin_23_ ; +wire [0:0] cby_1__1__2_left_grid_pin_24_ ; +wire [0:0] cby_1__1__2_left_grid_pin_25_ ; +wire [0:0] cby_1__1__2_left_grid_pin_26_ ; +wire [0:0] cby_1__1__2_left_grid_pin_27_ ; +wire [0:0] cby_1__1__2_left_grid_pin_28_ ; +wire [0:0] cby_1__1__2_left_grid_pin_29_ ; +wire [0:0] cby_1__1__2_left_grid_pin_30_ ; +wire [0:0] cby_1__1__2_left_grid_pin_31_ ; +wire [0:0] cby_1__1__30_ccff_tail ; +wire [0:29] cby_1__1__30_chany_bottom_out ; +wire [0:29] cby_1__1__30_chany_top_out ; +wire [0:0] cby_1__1__30_left_grid_pin_16_ ; +wire [0:0] cby_1__1__30_left_grid_pin_17_ ; +wire [0:0] cby_1__1__30_left_grid_pin_18_ ; +wire [0:0] cby_1__1__30_left_grid_pin_19_ ; +wire [0:0] cby_1__1__30_left_grid_pin_20_ ; +wire [0:0] cby_1__1__30_left_grid_pin_21_ ; +wire [0:0] cby_1__1__30_left_grid_pin_22_ ; +wire [0:0] cby_1__1__30_left_grid_pin_23_ ; +wire [0:0] cby_1__1__30_left_grid_pin_24_ ; +wire [0:0] cby_1__1__30_left_grid_pin_25_ ; +wire [0:0] cby_1__1__30_left_grid_pin_26_ ; +wire [0:0] cby_1__1__30_left_grid_pin_27_ ; +wire [0:0] cby_1__1__30_left_grid_pin_28_ ; +wire [0:0] cby_1__1__30_left_grid_pin_29_ ; +wire [0:0] cby_1__1__30_left_grid_pin_30_ ; +wire [0:0] cby_1__1__30_left_grid_pin_31_ ; +wire [0:0] cby_1__1__31_ccff_tail ; +wire [0:29] cby_1__1__31_chany_bottom_out ; +wire [0:29] cby_1__1__31_chany_top_out ; +wire [0:0] cby_1__1__31_left_grid_pin_16_ ; +wire [0:0] cby_1__1__31_left_grid_pin_17_ ; +wire [0:0] cby_1__1__31_left_grid_pin_18_ ; +wire [0:0] cby_1__1__31_left_grid_pin_19_ ; +wire [0:0] cby_1__1__31_left_grid_pin_20_ ; +wire [0:0] cby_1__1__31_left_grid_pin_21_ ; +wire [0:0] cby_1__1__31_left_grid_pin_22_ ; +wire [0:0] cby_1__1__31_left_grid_pin_23_ ; +wire [0:0] cby_1__1__31_left_grid_pin_24_ ; +wire [0:0] cby_1__1__31_left_grid_pin_25_ ; +wire [0:0] cby_1__1__31_left_grid_pin_26_ ; +wire [0:0] cby_1__1__31_left_grid_pin_27_ ; +wire [0:0] cby_1__1__31_left_grid_pin_28_ ; +wire [0:0] cby_1__1__31_left_grid_pin_29_ ; +wire [0:0] cby_1__1__31_left_grid_pin_30_ ; +wire [0:0] cby_1__1__31_left_grid_pin_31_ ; +wire [0:0] cby_1__1__32_ccff_tail ; +wire [0:29] cby_1__1__32_chany_bottom_out ; +wire [0:29] cby_1__1__32_chany_top_out ; +wire [0:0] cby_1__1__32_left_grid_pin_16_ ; +wire [0:0] cby_1__1__32_left_grid_pin_17_ ; +wire [0:0] cby_1__1__32_left_grid_pin_18_ ; +wire [0:0] cby_1__1__32_left_grid_pin_19_ ; +wire [0:0] cby_1__1__32_left_grid_pin_20_ ; +wire [0:0] cby_1__1__32_left_grid_pin_21_ ; +wire [0:0] cby_1__1__32_left_grid_pin_22_ ; +wire [0:0] cby_1__1__32_left_grid_pin_23_ ; +wire [0:0] cby_1__1__32_left_grid_pin_24_ ; +wire [0:0] cby_1__1__32_left_grid_pin_25_ ; +wire [0:0] cby_1__1__32_left_grid_pin_26_ ; +wire [0:0] cby_1__1__32_left_grid_pin_27_ ; +wire [0:0] cby_1__1__32_left_grid_pin_28_ ; +wire [0:0] cby_1__1__32_left_grid_pin_29_ ; +wire [0:0] cby_1__1__32_left_grid_pin_30_ ; +wire [0:0] cby_1__1__32_left_grid_pin_31_ ; +wire [0:0] cby_1__1__33_ccff_tail ; +wire [0:29] cby_1__1__33_chany_bottom_out ; +wire [0:29] cby_1__1__33_chany_top_out ; +wire [0:0] cby_1__1__33_left_grid_pin_16_ ; +wire [0:0] cby_1__1__33_left_grid_pin_17_ ; +wire [0:0] cby_1__1__33_left_grid_pin_18_ ; +wire [0:0] cby_1__1__33_left_grid_pin_19_ ; +wire [0:0] cby_1__1__33_left_grid_pin_20_ ; +wire [0:0] cby_1__1__33_left_grid_pin_21_ ; +wire [0:0] cby_1__1__33_left_grid_pin_22_ ; +wire [0:0] cby_1__1__33_left_grid_pin_23_ ; +wire [0:0] cby_1__1__33_left_grid_pin_24_ ; +wire [0:0] cby_1__1__33_left_grid_pin_25_ ; +wire [0:0] cby_1__1__33_left_grid_pin_26_ ; +wire [0:0] cby_1__1__33_left_grid_pin_27_ ; +wire [0:0] cby_1__1__33_left_grid_pin_28_ ; +wire [0:0] cby_1__1__33_left_grid_pin_29_ ; +wire [0:0] cby_1__1__33_left_grid_pin_30_ ; +wire [0:0] cby_1__1__33_left_grid_pin_31_ ; +wire [0:0] cby_1__1__34_ccff_tail ; +wire [0:29] cby_1__1__34_chany_bottom_out ; +wire [0:29] cby_1__1__34_chany_top_out ; +wire [0:0] cby_1__1__34_left_grid_pin_16_ ; +wire [0:0] cby_1__1__34_left_grid_pin_17_ ; +wire [0:0] cby_1__1__34_left_grid_pin_18_ ; +wire [0:0] cby_1__1__34_left_grid_pin_19_ ; +wire [0:0] cby_1__1__34_left_grid_pin_20_ ; +wire [0:0] cby_1__1__34_left_grid_pin_21_ ; +wire [0:0] cby_1__1__34_left_grid_pin_22_ ; +wire [0:0] cby_1__1__34_left_grid_pin_23_ ; +wire [0:0] cby_1__1__34_left_grid_pin_24_ ; +wire [0:0] cby_1__1__34_left_grid_pin_25_ ; +wire [0:0] cby_1__1__34_left_grid_pin_26_ ; +wire [0:0] cby_1__1__34_left_grid_pin_27_ ; +wire [0:0] cby_1__1__34_left_grid_pin_28_ ; +wire [0:0] cby_1__1__34_left_grid_pin_29_ ; +wire [0:0] cby_1__1__34_left_grid_pin_30_ ; +wire [0:0] cby_1__1__34_left_grid_pin_31_ ; +wire [0:0] cby_1__1__35_ccff_tail ; +wire [0:29] cby_1__1__35_chany_bottom_out ; +wire [0:29] cby_1__1__35_chany_top_out ; +wire [0:0] cby_1__1__35_left_grid_pin_16_ ; +wire [0:0] cby_1__1__35_left_grid_pin_17_ ; +wire [0:0] cby_1__1__35_left_grid_pin_18_ ; +wire [0:0] cby_1__1__35_left_grid_pin_19_ ; +wire [0:0] cby_1__1__35_left_grid_pin_20_ ; +wire [0:0] cby_1__1__35_left_grid_pin_21_ ; +wire [0:0] cby_1__1__35_left_grid_pin_22_ ; +wire [0:0] cby_1__1__35_left_grid_pin_23_ ; +wire [0:0] cby_1__1__35_left_grid_pin_24_ ; +wire [0:0] cby_1__1__35_left_grid_pin_25_ ; +wire [0:0] cby_1__1__35_left_grid_pin_26_ ; +wire [0:0] cby_1__1__35_left_grid_pin_27_ ; +wire [0:0] cby_1__1__35_left_grid_pin_28_ ; +wire [0:0] cby_1__1__35_left_grid_pin_29_ ; +wire [0:0] cby_1__1__35_left_grid_pin_30_ ; +wire [0:0] cby_1__1__35_left_grid_pin_31_ ; +wire [0:0] cby_1__1__36_ccff_tail ; +wire [0:29] cby_1__1__36_chany_bottom_out ; +wire [0:29] cby_1__1__36_chany_top_out ; +wire [0:0] cby_1__1__36_left_grid_pin_16_ ; +wire [0:0] cby_1__1__36_left_grid_pin_17_ ; +wire [0:0] cby_1__1__36_left_grid_pin_18_ ; +wire [0:0] cby_1__1__36_left_grid_pin_19_ ; +wire [0:0] cby_1__1__36_left_grid_pin_20_ ; +wire [0:0] cby_1__1__36_left_grid_pin_21_ ; +wire [0:0] cby_1__1__36_left_grid_pin_22_ ; +wire [0:0] cby_1__1__36_left_grid_pin_23_ ; +wire [0:0] cby_1__1__36_left_grid_pin_24_ ; +wire [0:0] cby_1__1__36_left_grid_pin_25_ ; +wire [0:0] cby_1__1__36_left_grid_pin_26_ ; +wire [0:0] cby_1__1__36_left_grid_pin_27_ ; +wire [0:0] cby_1__1__36_left_grid_pin_28_ ; +wire [0:0] cby_1__1__36_left_grid_pin_29_ ; +wire [0:0] cby_1__1__36_left_grid_pin_30_ ; +wire [0:0] cby_1__1__36_left_grid_pin_31_ ; +wire [0:0] cby_1__1__37_ccff_tail ; +wire [0:29] cby_1__1__37_chany_bottom_out ; +wire [0:29] cby_1__1__37_chany_top_out ; +wire [0:0] cby_1__1__37_left_grid_pin_16_ ; +wire [0:0] cby_1__1__37_left_grid_pin_17_ ; +wire [0:0] cby_1__1__37_left_grid_pin_18_ ; +wire [0:0] cby_1__1__37_left_grid_pin_19_ ; +wire [0:0] cby_1__1__37_left_grid_pin_20_ ; +wire [0:0] cby_1__1__37_left_grid_pin_21_ ; +wire [0:0] cby_1__1__37_left_grid_pin_22_ ; +wire [0:0] cby_1__1__37_left_grid_pin_23_ ; +wire [0:0] cby_1__1__37_left_grid_pin_24_ ; +wire [0:0] cby_1__1__37_left_grid_pin_25_ ; +wire [0:0] cby_1__1__37_left_grid_pin_26_ ; +wire [0:0] cby_1__1__37_left_grid_pin_27_ ; +wire [0:0] cby_1__1__37_left_grid_pin_28_ ; +wire [0:0] cby_1__1__37_left_grid_pin_29_ ; +wire [0:0] cby_1__1__37_left_grid_pin_30_ ; +wire [0:0] cby_1__1__37_left_grid_pin_31_ ; +wire [0:0] cby_1__1__38_ccff_tail ; +wire [0:29] cby_1__1__38_chany_bottom_out ; +wire [0:29] cby_1__1__38_chany_top_out ; +wire [0:0] cby_1__1__38_left_grid_pin_16_ ; +wire [0:0] cby_1__1__38_left_grid_pin_17_ ; +wire [0:0] cby_1__1__38_left_grid_pin_18_ ; +wire [0:0] cby_1__1__38_left_grid_pin_19_ ; +wire [0:0] cby_1__1__38_left_grid_pin_20_ ; +wire [0:0] cby_1__1__38_left_grid_pin_21_ ; +wire [0:0] cby_1__1__38_left_grid_pin_22_ ; +wire [0:0] cby_1__1__38_left_grid_pin_23_ ; +wire [0:0] cby_1__1__38_left_grid_pin_24_ ; +wire [0:0] cby_1__1__38_left_grid_pin_25_ ; +wire [0:0] cby_1__1__38_left_grid_pin_26_ ; +wire [0:0] cby_1__1__38_left_grid_pin_27_ ; +wire [0:0] cby_1__1__38_left_grid_pin_28_ ; +wire [0:0] cby_1__1__38_left_grid_pin_29_ ; +wire [0:0] cby_1__1__38_left_grid_pin_30_ ; +wire [0:0] cby_1__1__38_left_grid_pin_31_ ; +wire [0:0] cby_1__1__39_ccff_tail ; +wire [0:29] cby_1__1__39_chany_bottom_out ; +wire [0:29] cby_1__1__39_chany_top_out ; +wire [0:0] cby_1__1__39_left_grid_pin_16_ ; +wire [0:0] cby_1__1__39_left_grid_pin_17_ ; +wire [0:0] cby_1__1__39_left_grid_pin_18_ ; +wire [0:0] cby_1__1__39_left_grid_pin_19_ ; +wire [0:0] cby_1__1__39_left_grid_pin_20_ ; +wire [0:0] cby_1__1__39_left_grid_pin_21_ ; +wire [0:0] cby_1__1__39_left_grid_pin_22_ ; +wire [0:0] cby_1__1__39_left_grid_pin_23_ ; +wire [0:0] cby_1__1__39_left_grid_pin_24_ ; +wire [0:0] cby_1__1__39_left_grid_pin_25_ ; +wire [0:0] cby_1__1__39_left_grid_pin_26_ ; +wire [0:0] cby_1__1__39_left_grid_pin_27_ ; +wire [0:0] cby_1__1__39_left_grid_pin_28_ ; +wire [0:0] cby_1__1__39_left_grid_pin_29_ ; +wire [0:0] cby_1__1__39_left_grid_pin_30_ ; +wire [0:0] cby_1__1__39_left_grid_pin_31_ ; +wire [0:0] cby_1__1__3_ccff_tail ; +wire [0:29] cby_1__1__3_chany_bottom_out ; +wire [0:29] cby_1__1__3_chany_top_out ; +wire [0:0] cby_1__1__3_left_grid_pin_16_ ; +wire [0:0] cby_1__1__3_left_grid_pin_17_ ; +wire [0:0] cby_1__1__3_left_grid_pin_18_ ; +wire [0:0] cby_1__1__3_left_grid_pin_19_ ; +wire [0:0] cby_1__1__3_left_grid_pin_20_ ; +wire [0:0] cby_1__1__3_left_grid_pin_21_ ; +wire [0:0] cby_1__1__3_left_grid_pin_22_ ; +wire [0:0] cby_1__1__3_left_grid_pin_23_ ; +wire [0:0] cby_1__1__3_left_grid_pin_24_ ; +wire [0:0] cby_1__1__3_left_grid_pin_25_ ; +wire [0:0] cby_1__1__3_left_grid_pin_26_ ; +wire [0:0] cby_1__1__3_left_grid_pin_27_ ; +wire [0:0] cby_1__1__3_left_grid_pin_28_ ; +wire [0:0] cby_1__1__3_left_grid_pin_29_ ; +wire [0:0] cby_1__1__3_left_grid_pin_30_ ; +wire [0:0] cby_1__1__3_left_grid_pin_31_ ; +wire [0:0] cby_1__1__40_ccff_tail ; +wire [0:29] cby_1__1__40_chany_bottom_out ; +wire [0:29] cby_1__1__40_chany_top_out ; +wire [0:0] cby_1__1__40_left_grid_pin_16_ ; +wire [0:0] cby_1__1__40_left_grid_pin_17_ ; +wire [0:0] cby_1__1__40_left_grid_pin_18_ ; +wire [0:0] cby_1__1__40_left_grid_pin_19_ ; +wire [0:0] cby_1__1__40_left_grid_pin_20_ ; +wire [0:0] cby_1__1__40_left_grid_pin_21_ ; +wire [0:0] cby_1__1__40_left_grid_pin_22_ ; +wire [0:0] cby_1__1__40_left_grid_pin_23_ ; +wire [0:0] cby_1__1__40_left_grid_pin_24_ ; +wire [0:0] cby_1__1__40_left_grid_pin_25_ ; +wire [0:0] cby_1__1__40_left_grid_pin_26_ ; +wire [0:0] cby_1__1__40_left_grid_pin_27_ ; +wire [0:0] cby_1__1__40_left_grid_pin_28_ ; +wire [0:0] cby_1__1__40_left_grid_pin_29_ ; +wire [0:0] cby_1__1__40_left_grid_pin_30_ ; +wire [0:0] cby_1__1__40_left_grid_pin_31_ ; +wire [0:0] cby_1__1__41_ccff_tail ; +wire [0:29] cby_1__1__41_chany_bottom_out ; +wire [0:29] cby_1__1__41_chany_top_out ; +wire [0:0] cby_1__1__41_left_grid_pin_16_ ; +wire [0:0] cby_1__1__41_left_grid_pin_17_ ; +wire [0:0] cby_1__1__41_left_grid_pin_18_ ; +wire [0:0] cby_1__1__41_left_grid_pin_19_ ; +wire [0:0] cby_1__1__41_left_grid_pin_20_ ; +wire [0:0] cby_1__1__41_left_grid_pin_21_ ; +wire [0:0] cby_1__1__41_left_grid_pin_22_ ; +wire [0:0] cby_1__1__41_left_grid_pin_23_ ; +wire [0:0] cby_1__1__41_left_grid_pin_24_ ; +wire [0:0] cby_1__1__41_left_grid_pin_25_ ; +wire [0:0] cby_1__1__41_left_grid_pin_26_ ; +wire [0:0] cby_1__1__41_left_grid_pin_27_ ; +wire [0:0] cby_1__1__41_left_grid_pin_28_ ; +wire [0:0] cby_1__1__41_left_grid_pin_29_ ; +wire [0:0] cby_1__1__41_left_grid_pin_30_ ; +wire [0:0] cby_1__1__41_left_grid_pin_31_ ; +wire [0:0] cby_1__1__42_ccff_tail ; +wire [0:29] cby_1__1__42_chany_bottom_out ; +wire [0:29] cby_1__1__42_chany_top_out ; +wire [0:0] cby_1__1__42_left_grid_pin_16_ ; +wire [0:0] cby_1__1__42_left_grid_pin_17_ ; +wire [0:0] cby_1__1__42_left_grid_pin_18_ ; +wire [0:0] cby_1__1__42_left_grid_pin_19_ ; +wire [0:0] cby_1__1__42_left_grid_pin_20_ ; +wire [0:0] cby_1__1__42_left_grid_pin_21_ ; +wire [0:0] cby_1__1__42_left_grid_pin_22_ ; +wire [0:0] cby_1__1__42_left_grid_pin_23_ ; +wire [0:0] cby_1__1__42_left_grid_pin_24_ ; +wire [0:0] cby_1__1__42_left_grid_pin_25_ ; +wire [0:0] cby_1__1__42_left_grid_pin_26_ ; +wire [0:0] cby_1__1__42_left_grid_pin_27_ ; +wire [0:0] cby_1__1__42_left_grid_pin_28_ ; +wire [0:0] cby_1__1__42_left_grid_pin_29_ ; +wire [0:0] cby_1__1__42_left_grid_pin_30_ ; +wire [0:0] cby_1__1__42_left_grid_pin_31_ ; +wire [0:0] cby_1__1__43_ccff_tail ; +wire [0:29] cby_1__1__43_chany_bottom_out ; +wire [0:29] cby_1__1__43_chany_top_out ; +wire [0:0] cby_1__1__43_left_grid_pin_16_ ; +wire [0:0] cby_1__1__43_left_grid_pin_17_ ; +wire [0:0] cby_1__1__43_left_grid_pin_18_ ; +wire [0:0] cby_1__1__43_left_grid_pin_19_ ; +wire [0:0] cby_1__1__43_left_grid_pin_20_ ; +wire [0:0] cby_1__1__43_left_grid_pin_21_ ; +wire [0:0] cby_1__1__43_left_grid_pin_22_ ; +wire [0:0] cby_1__1__43_left_grid_pin_23_ ; +wire [0:0] cby_1__1__43_left_grid_pin_24_ ; +wire [0:0] cby_1__1__43_left_grid_pin_25_ ; +wire [0:0] cby_1__1__43_left_grid_pin_26_ ; +wire [0:0] cby_1__1__43_left_grid_pin_27_ ; +wire [0:0] cby_1__1__43_left_grid_pin_28_ ; +wire [0:0] cby_1__1__43_left_grid_pin_29_ ; +wire [0:0] cby_1__1__43_left_grid_pin_30_ ; +wire [0:0] cby_1__1__43_left_grid_pin_31_ ; +wire [0:0] cby_1__1__44_ccff_tail ; +wire [0:29] cby_1__1__44_chany_bottom_out ; +wire [0:29] cby_1__1__44_chany_top_out ; +wire [0:0] cby_1__1__44_left_grid_pin_16_ ; +wire [0:0] cby_1__1__44_left_grid_pin_17_ ; +wire [0:0] cby_1__1__44_left_grid_pin_18_ ; +wire [0:0] cby_1__1__44_left_grid_pin_19_ ; +wire [0:0] cby_1__1__44_left_grid_pin_20_ ; +wire [0:0] cby_1__1__44_left_grid_pin_21_ ; +wire [0:0] cby_1__1__44_left_grid_pin_22_ ; +wire [0:0] cby_1__1__44_left_grid_pin_23_ ; +wire [0:0] cby_1__1__44_left_grid_pin_24_ ; +wire [0:0] cby_1__1__44_left_grid_pin_25_ ; +wire [0:0] cby_1__1__44_left_grid_pin_26_ ; +wire [0:0] cby_1__1__44_left_grid_pin_27_ ; +wire [0:0] cby_1__1__44_left_grid_pin_28_ ; +wire [0:0] cby_1__1__44_left_grid_pin_29_ ; +wire [0:0] cby_1__1__44_left_grid_pin_30_ ; +wire [0:0] cby_1__1__44_left_grid_pin_31_ ; +wire [0:0] cby_1__1__45_ccff_tail ; +wire [0:29] cby_1__1__45_chany_bottom_out ; +wire [0:29] cby_1__1__45_chany_top_out ; +wire [0:0] cby_1__1__45_left_grid_pin_16_ ; +wire [0:0] cby_1__1__45_left_grid_pin_17_ ; +wire [0:0] cby_1__1__45_left_grid_pin_18_ ; +wire [0:0] cby_1__1__45_left_grid_pin_19_ ; +wire [0:0] cby_1__1__45_left_grid_pin_20_ ; +wire [0:0] cby_1__1__45_left_grid_pin_21_ ; +wire [0:0] cby_1__1__45_left_grid_pin_22_ ; +wire [0:0] cby_1__1__45_left_grid_pin_23_ ; +wire [0:0] cby_1__1__45_left_grid_pin_24_ ; +wire [0:0] cby_1__1__45_left_grid_pin_25_ ; +wire [0:0] cby_1__1__45_left_grid_pin_26_ ; +wire [0:0] cby_1__1__45_left_grid_pin_27_ ; +wire [0:0] cby_1__1__45_left_grid_pin_28_ ; +wire [0:0] cby_1__1__45_left_grid_pin_29_ ; +wire [0:0] cby_1__1__45_left_grid_pin_30_ ; +wire [0:0] cby_1__1__45_left_grid_pin_31_ ; +wire [0:0] cby_1__1__46_ccff_tail ; +wire [0:29] cby_1__1__46_chany_bottom_out ; +wire [0:29] cby_1__1__46_chany_top_out ; +wire [0:0] cby_1__1__46_left_grid_pin_16_ ; +wire [0:0] cby_1__1__46_left_grid_pin_17_ ; +wire [0:0] cby_1__1__46_left_grid_pin_18_ ; +wire [0:0] cby_1__1__46_left_grid_pin_19_ ; +wire [0:0] cby_1__1__46_left_grid_pin_20_ ; +wire [0:0] cby_1__1__46_left_grid_pin_21_ ; +wire [0:0] cby_1__1__46_left_grid_pin_22_ ; +wire [0:0] cby_1__1__46_left_grid_pin_23_ ; +wire [0:0] cby_1__1__46_left_grid_pin_24_ ; +wire [0:0] cby_1__1__46_left_grid_pin_25_ ; +wire [0:0] cby_1__1__46_left_grid_pin_26_ ; +wire [0:0] cby_1__1__46_left_grid_pin_27_ ; +wire [0:0] cby_1__1__46_left_grid_pin_28_ ; +wire [0:0] cby_1__1__46_left_grid_pin_29_ ; +wire [0:0] cby_1__1__46_left_grid_pin_30_ ; +wire [0:0] cby_1__1__46_left_grid_pin_31_ ; +wire [0:0] cby_1__1__47_ccff_tail ; +wire [0:29] cby_1__1__47_chany_bottom_out ; +wire [0:29] cby_1__1__47_chany_top_out ; +wire [0:0] cby_1__1__47_left_grid_pin_16_ ; +wire [0:0] cby_1__1__47_left_grid_pin_17_ ; +wire [0:0] cby_1__1__47_left_grid_pin_18_ ; +wire [0:0] cby_1__1__47_left_grid_pin_19_ ; +wire [0:0] cby_1__1__47_left_grid_pin_20_ ; +wire [0:0] cby_1__1__47_left_grid_pin_21_ ; +wire [0:0] cby_1__1__47_left_grid_pin_22_ ; +wire [0:0] cby_1__1__47_left_grid_pin_23_ ; +wire [0:0] cby_1__1__47_left_grid_pin_24_ ; +wire [0:0] cby_1__1__47_left_grid_pin_25_ ; +wire [0:0] cby_1__1__47_left_grid_pin_26_ ; +wire [0:0] cby_1__1__47_left_grid_pin_27_ ; +wire [0:0] cby_1__1__47_left_grid_pin_28_ ; +wire [0:0] cby_1__1__47_left_grid_pin_29_ ; +wire [0:0] cby_1__1__47_left_grid_pin_30_ ; +wire [0:0] cby_1__1__47_left_grid_pin_31_ ; +wire [0:0] cby_1__1__48_ccff_tail ; +wire [0:29] cby_1__1__48_chany_bottom_out ; +wire [0:29] cby_1__1__48_chany_top_out ; +wire [0:0] cby_1__1__48_left_grid_pin_16_ ; +wire [0:0] cby_1__1__48_left_grid_pin_17_ ; +wire [0:0] cby_1__1__48_left_grid_pin_18_ ; +wire [0:0] cby_1__1__48_left_grid_pin_19_ ; +wire [0:0] cby_1__1__48_left_grid_pin_20_ ; +wire [0:0] cby_1__1__48_left_grid_pin_21_ ; +wire [0:0] cby_1__1__48_left_grid_pin_22_ ; +wire [0:0] cby_1__1__48_left_grid_pin_23_ ; +wire [0:0] cby_1__1__48_left_grid_pin_24_ ; +wire [0:0] cby_1__1__48_left_grid_pin_25_ ; +wire [0:0] cby_1__1__48_left_grid_pin_26_ ; +wire [0:0] cby_1__1__48_left_grid_pin_27_ ; +wire [0:0] cby_1__1__48_left_grid_pin_28_ ; +wire [0:0] cby_1__1__48_left_grid_pin_29_ ; +wire [0:0] cby_1__1__48_left_grid_pin_30_ ; +wire [0:0] cby_1__1__48_left_grid_pin_31_ ; +wire [0:0] cby_1__1__49_ccff_tail ; +wire [0:29] cby_1__1__49_chany_bottom_out ; +wire [0:29] cby_1__1__49_chany_top_out ; +wire [0:0] cby_1__1__49_left_grid_pin_16_ ; +wire [0:0] cby_1__1__49_left_grid_pin_17_ ; +wire [0:0] cby_1__1__49_left_grid_pin_18_ ; +wire [0:0] cby_1__1__49_left_grid_pin_19_ ; +wire [0:0] cby_1__1__49_left_grid_pin_20_ ; +wire [0:0] cby_1__1__49_left_grid_pin_21_ ; +wire [0:0] cby_1__1__49_left_grid_pin_22_ ; +wire [0:0] cby_1__1__49_left_grid_pin_23_ ; +wire [0:0] cby_1__1__49_left_grid_pin_24_ ; +wire [0:0] cby_1__1__49_left_grid_pin_25_ ; +wire [0:0] cby_1__1__49_left_grid_pin_26_ ; +wire [0:0] cby_1__1__49_left_grid_pin_27_ ; +wire [0:0] cby_1__1__49_left_grid_pin_28_ ; +wire [0:0] cby_1__1__49_left_grid_pin_29_ ; +wire [0:0] cby_1__1__49_left_grid_pin_30_ ; +wire [0:0] cby_1__1__49_left_grid_pin_31_ ; +wire [0:0] cby_1__1__4_ccff_tail ; +wire [0:29] cby_1__1__4_chany_bottom_out ; +wire [0:29] cby_1__1__4_chany_top_out ; +wire [0:0] cby_1__1__4_left_grid_pin_16_ ; +wire [0:0] cby_1__1__4_left_grid_pin_17_ ; +wire [0:0] cby_1__1__4_left_grid_pin_18_ ; +wire [0:0] cby_1__1__4_left_grid_pin_19_ ; +wire [0:0] cby_1__1__4_left_grid_pin_20_ ; +wire [0:0] cby_1__1__4_left_grid_pin_21_ ; +wire [0:0] cby_1__1__4_left_grid_pin_22_ ; +wire [0:0] cby_1__1__4_left_grid_pin_23_ ; +wire [0:0] cby_1__1__4_left_grid_pin_24_ ; +wire [0:0] cby_1__1__4_left_grid_pin_25_ ; +wire [0:0] cby_1__1__4_left_grid_pin_26_ ; +wire [0:0] cby_1__1__4_left_grid_pin_27_ ; +wire [0:0] cby_1__1__4_left_grid_pin_28_ ; +wire [0:0] cby_1__1__4_left_grid_pin_29_ ; +wire [0:0] cby_1__1__4_left_grid_pin_30_ ; +wire [0:0] cby_1__1__4_left_grid_pin_31_ ; +wire [0:0] cby_1__1__50_ccff_tail ; +wire [0:29] cby_1__1__50_chany_bottom_out ; +wire [0:29] cby_1__1__50_chany_top_out ; +wire [0:0] cby_1__1__50_left_grid_pin_16_ ; +wire [0:0] cby_1__1__50_left_grid_pin_17_ ; +wire [0:0] cby_1__1__50_left_grid_pin_18_ ; +wire [0:0] cby_1__1__50_left_grid_pin_19_ ; +wire [0:0] cby_1__1__50_left_grid_pin_20_ ; +wire [0:0] cby_1__1__50_left_grid_pin_21_ ; +wire [0:0] cby_1__1__50_left_grid_pin_22_ ; +wire [0:0] cby_1__1__50_left_grid_pin_23_ ; +wire [0:0] cby_1__1__50_left_grid_pin_24_ ; +wire [0:0] cby_1__1__50_left_grid_pin_25_ ; +wire [0:0] cby_1__1__50_left_grid_pin_26_ ; +wire [0:0] cby_1__1__50_left_grid_pin_27_ ; +wire [0:0] cby_1__1__50_left_grid_pin_28_ ; +wire [0:0] cby_1__1__50_left_grid_pin_29_ ; +wire [0:0] cby_1__1__50_left_grid_pin_30_ ; +wire [0:0] cby_1__1__50_left_grid_pin_31_ ; +wire [0:0] cby_1__1__51_ccff_tail ; +wire [0:29] cby_1__1__51_chany_bottom_out ; +wire [0:29] cby_1__1__51_chany_top_out ; +wire [0:0] cby_1__1__51_left_grid_pin_16_ ; +wire [0:0] cby_1__1__51_left_grid_pin_17_ ; +wire [0:0] cby_1__1__51_left_grid_pin_18_ ; +wire [0:0] cby_1__1__51_left_grid_pin_19_ ; +wire [0:0] cby_1__1__51_left_grid_pin_20_ ; +wire [0:0] cby_1__1__51_left_grid_pin_21_ ; +wire [0:0] cby_1__1__51_left_grid_pin_22_ ; +wire [0:0] cby_1__1__51_left_grid_pin_23_ ; +wire [0:0] cby_1__1__51_left_grid_pin_24_ ; +wire [0:0] cby_1__1__51_left_grid_pin_25_ ; +wire [0:0] cby_1__1__51_left_grid_pin_26_ ; +wire [0:0] cby_1__1__51_left_grid_pin_27_ ; +wire [0:0] cby_1__1__51_left_grid_pin_28_ ; +wire [0:0] cby_1__1__51_left_grid_pin_29_ ; +wire [0:0] cby_1__1__51_left_grid_pin_30_ ; +wire [0:0] cby_1__1__51_left_grid_pin_31_ ; +wire [0:0] cby_1__1__52_ccff_tail ; +wire [0:29] cby_1__1__52_chany_bottom_out ; +wire [0:29] cby_1__1__52_chany_top_out ; +wire [0:0] cby_1__1__52_left_grid_pin_16_ ; +wire [0:0] cby_1__1__52_left_grid_pin_17_ ; +wire [0:0] cby_1__1__52_left_grid_pin_18_ ; +wire [0:0] cby_1__1__52_left_grid_pin_19_ ; +wire [0:0] cby_1__1__52_left_grid_pin_20_ ; +wire [0:0] cby_1__1__52_left_grid_pin_21_ ; +wire [0:0] cby_1__1__52_left_grid_pin_22_ ; +wire [0:0] cby_1__1__52_left_grid_pin_23_ ; +wire [0:0] cby_1__1__52_left_grid_pin_24_ ; +wire [0:0] cby_1__1__52_left_grid_pin_25_ ; +wire [0:0] cby_1__1__52_left_grid_pin_26_ ; +wire [0:0] cby_1__1__52_left_grid_pin_27_ ; +wire [0:0] cby_1__1__52_left_grid_pin_28_ ; +wire [0:0] cby_1__1__52_left_grid_pin_29_ ; +wire [0:0] cby_1__1__52_left_grid_pin_30_ ; +wire [0:0] cby_1__1__52_left_grid_pin_31_ ; +wire [0:0] cby_1__1__53_ccff_tail ; +wire [0:29] cby_1__1__53_chany_bottom_out ; +wire [0:29] cby_1__1__53_chany_top_out ; +wire [0:0] cby_1__1__53_left_grid_pin_16_ ; +wire [0:0] cby_1__1__53_left_grid_pin_17_ ; +wire [0:0] cby_1__1__53_left_grid_pin_18_ ; +wire [0:0] cby_1__1__53_left_grid_pin_19_ ; +wire [0:0] cby_1__1__53_left_grid_pin_20_ ; +wire [0:0] cby_1__1__53_left_grid_pin_21_ ; +wire [0:0] cby_1__1__53_left_grid_pin_22_ ; +wire [0:0] cby_1__1__53_left_grid_pin_23_ ; +wire [0:0] cby_1__1__53_left_grid_pin_24_ ; +wire [0:0] cby_1__1__53_left_grid_pin_25_ ; +wire [0:0] cby_1__1__53_left_grid_pin_26_ ; +wire [0:0] cby_1__1__53_left_grid_pin_27_ ; +wire [0:0] cby_1__1__53_left_grid_pin_28_ ; +wire [0:0] cby_1__1__53_left_grid_pin_29_ ; +wire [0:0] cby_1__1__53_left_grid_pin_30_ ; +wire [0:0] cby_1__1__53_left_grid_pin_31_ ; +wire [0:0] cby_1__1__54_ccff_tail ; +wire [0:29] cby_1__1__54_chany_bottom_out ; +wire [0:29] cby_1__1__54_chany_top_out ; +wire [0:0] cby_1__1__54_left_grid_pin_16_ ; +wire [0:0] cby_1__1__54_left_grid_pin_17_ ; +wire [0:0] cby_1__1__54_left_grid_pin_18_ ; +wire [0:0] cby_1__1__54_left_grid_pin_19_ ; +wire [0:0] cby_1__1__54_left_grid_pin_20_ ; +wire [0:0] cby_1__1__54_left_grid_pin_21_ ; +wire [0:0] cby_1__1__54_left_grid_pin_22_ ; +wire [0:0] cby_1__1__54_left_grid_pin_23_ ; +wire [0:0] cby_1__1__54_left_grid_pin_24_ ; +wire [0:0] cby_1__1__54_left_grid_pin_25_ ; +wire [0:0] cby_1__1__54_left_grid_pin_26_ ; +wire [0:0] cby_1__1__54_left_grid_pin_27_ ; +wire [0:0] cby_1__1__54_left_grid_pin_28_ ; +wire [0:0] cby_1__1__54_left_grid_pin_29_ ; +wire [0:0] cby_1__1__54_left_grid_pin_30_ ; +wire [0:0] cby_1__1__54_left_grid_pin_31_ ; +wire [0:0] cby_1__1__55_ccff_tail ; +wire [0:29] cby_1__1__55_chany_bottom_out ; +wire [0:29] cby_1__1__55_chany_top_out ; +wire [0:0] cby_1__1__55_left_grid_pin_16_ ; +wire [0:0] cby_1__1__55_left_grid_pin_17_ ; +wire [0:0] cby_1__1__55_left_grid_pin_18_ ; +wire [0:0] cby_1__1__55_left_grid_pin_19_ ; +wire [0:0] cby_1__1__55_left_grid_pin_20_ ; +wire [0:0] cby_1__1__55_left_grid_pin_21_ ; +wire [0:0] cby_1__1__55_left_grid_pin_22_ ; +wire [0:0] cby_1__1__55_left_grid_pin_23_ ; +wire [0:0] cby_1__1__55_left_grid_pin_24_ ; +wire [0:0] cby_1__1__55_left_grid_pin_25_ ; +wire [0:0] cby_1__1__55_left_grid_pin_26_ ; +wire [0:0] cby_1__1__55_left_grid_pin_27_ ; +wire [0:0] cby_1__1__55_left_grid_pin_28_ ; +wire [0:0] cby_1__1__55_left_grid_pin_29_ ; +wire [0:0] cby_1__1__55_left_grid_pin_30_ ; +wire [0:0] cby_1__1__55_left_grid_pin_31_ ; +wire [0:0] cby_1__1__56_ccff_tail ; +wire [0:29] cby_1__1__56_chany_bottom_out ; +wire [0:29] cby_1__1__56_chany_top_out ; +wire [0:0] cby_1__1__56_left_grid_pin_16_ ; +wire [0:0] cby_1__1__56_left_grid_pin_17_ ; +wire [0:0] cby_1__1__56_left_grid_pin_18_ ; +wire [0:0] cby_1__1__56_left_grid_pin_19_ ; +wire [0:0] cby_1__1__56_left_grid_pin_20_ ; +wire [0:0] cby_1__1__56_left_grid_pin_21_ ; +wire [0:0] cby_1__1__56_left_grid_pin_22_ ; +wire [0:0] cby_1__1__56_left_grid_pin_23_ ; +wire [0:0] cby_1__1__56_left_grid_pin_24_ ; +wire [0:0] cby_1__1__56_left_grid_pin_25_ ; +wire [0:0] cby_1__1__56_left_grid_pin_26_ ; +wire [0:0] cby_1__1__56_left_grid_pin_27_ ; +wire [0:0] cby_1__1__56_left_grid_pin_28_ ; +wire [0:0] cby_1__1__56_left_grid_pin_29_ ; +wire [0:0] cby_1__1__56_left_grid_pin_30_ ; +wire [0:0] cby_1__1__56_left_grid_pin_31_ ; +wire [0:0] cby_1__1__57_ccff_tail ; +wire [0:29] cby_1__1__57_chany_bottom_out ; +wire [0:29] cby_1__1__57_chany_top_out ; +wire [0:0] cby_1__1__57_left_grid_pin_16_ ; +wire [0:0] cby_1__1__57_left_grid_pin_17_ ; +wire [0:0] cby_1__1__57_left_grid_pin_18_ ; +wire [0:0] cby_1__1__57_left_grid_pin_19_ ; +wire [0:0] cby_1__1__57_left_grid_pin_20_ ; +wire [0:0] cby_1__1__57_left_grid_pin_21_ ; +wire [0:0] cby_1__1__57_left_grid_pin_22_ ; +wire [0:0] cby_1__1__57_left_grid_pin_23_ ; +wire [0:0] cby_1__1__57_left_grid_pin_24_ ; +wire [0:0] cby_1__1__57_left_grid_pin_25_ ; +wire [0:0] cby_1__1__57_left_grid_pin_26_ ; +wire [0:0] cby_1__1__57_left_grid_pin_27_ ; +wire [0:0] cby_1__1__57_left_grid_pin_28_ ; +wire [0:0] cby_1__1__57_left_grid_pin_29_ ; +wire [0:0] cby_1__1__57_left_grid_pin_30_ ; +wire [0:0] cby_1__1__57_left_grid_pin_31_ ; +wire [0:0] cby_1__1__58_ccff_tail ; +wire [0:29] cby_1__1__58_chany_bottom_out ; +wire [0:29] cby_1__1__58_chany_top_out ; +wire [0:0] cby_1__1__58_left_grid_pin_16_ ; +wire [0:0] cby_1__1__58_left_grid_pin_17_ ; +wire [0:0] cby_1__1__58_left_grid_pin_18_ ; +wire [0:0] cby_1__1__58_left_grid_pin_19_ ; +wire [0:0] cby_1__1__58_left_grid_pin_20_ ; +wire [0:0] cby_1__1__58_left_grid_pin_21_ ; +wire [0:0] cby_1__1__58_left_grid_pin_22_ ; +wire [0:0] cby_1__1__58_left_grid_pin_23_ ; +wire [0:0] cby_1__1__58_left_grid_pin_24_ ; +wire [0:0] cby_1__1__58_left_grid_pin_25_ ; +wire [0:0] cby_1__1__58_left_grid_pin_26_ ; +wire [0:0] cby_1__1__58_left_grid_pin_27_ ; +wire [0:0] cby_1__1__58_left_grid_pin_28_ ; +wire [0:0] cby_1__1__58_left_grid_pin_29_ ; +wire [0:0] cby_1__1__58_left_grid_pin_30_ ; +wire [0:0] cby_1__1__58_left_grid_pin_31_ ; +wire [0:0] cby_1__1__59_ccff_tail ; +wire [0:29] cby_1__1__59_chany_bottom_out ; +wire [0:29] cby_1__1__59_chany_top_out ; +wire [0:0] cby_1__1__59_left_grid_pin_16_ ; +wire [0:0] cby_1__1__59_left_grid_pin_17_ ; +wire [0:0] cby_1__1__59_left_grid_pin_18_ ; +wire [0:0] cby_1__1__59_left_grid_pin_19_ ; +wire [0:0] cby_1__1__59_left_grid_pin_20_ ; +wire [0:0] cby_1__1__59_left_grid_pin_21_ ; +wire [0:0] cby_1__1__59_left_grid_pin_22_ ; +wire [0:0] cby_1__1__59_left_grid_pin_23_ ; +wire [0:0] cby_1__1__59_left_grid_pin_24_ ; +wire [0:0] cby_1__1__59_left_grid_pin_25_ ; +wire [0:0] cby_1__1__59_left_grid_pin_26_ ; +wire [0:0] cby_1__1__59_left_grid_pin_27_ ; +wire [0:0] cby_1__1__59_left_grid_pin_28_ ; +wire [0:0] cby_1__1__59_left_grid_pin_29_ ; +wire [0:0] cby_1__1__59_left_grid_pin_30_ ; +wire [0:0] cby_1__1__59_left_grid_pin_31_ ; +wire [0:0] cby_1__1__5_ccff_tail ; +wire [0:29] cby_1__1__5_chany_bottom_out ; +wire [0:29] cby_1__1__5_chany_top_out ; +wire [0:0] cby_1__1__5_left_grid_pin_16_ ; +wire [0:0] cby_1__1__5_left_grid_pin_17_ ; +wire [0:0] cby_1__1__5_left_grid_pin_18_ ; +wire [0:0] cby_1__1__5_left_grid_pin_19_ ; +wire [0:0] cby_1__1__5_left_grid_pin_20_ ; +wire [0:0] cby_1__1__5_left_grid_pin_21_ ; +wire [0:0] cby_1__1__5_left_grid_pin_22_ ; +wire [0:0] cby_1__1__5_left_grid_pin_23_ ; +wire [0:0] cby_1__1__5_left_grid_pin_24_ ; +wire [0:0] cby_1__1__5_left_grid_pin_25_ ; +wire [0:0] cby_1__1__5_left_grid_pin_26_ ; +wire [0:0] cby_1__1__5_left_grid_pin_27_ ; +wire [0:0] cby_1__1__5_left_grid_pin_28_ ; +wire [0:0] cby_1__1__5_left_grid_pin_29_ ; +wire [0:0] cby_1__1__5_left_grid_pin_30_ ; +wire [0:0] cby_1__1__5_left_grid_pin_31_ ; +wire [0:0] cby_1__1__60_ccff_tail ; +wire [0:29] cby_1__1__60_chany_bottom_out ; +wire [0:29] cby_1__1__60_chany_top_out ; +wire [0:0] cby_1__1__60_left_grid_pin_16_ ; +wire [0:0] cby_1__1__60_left_grid_pin_17_ ; +wire [0:0] cby_1__1__60_left_grid_pin_18_ ; +wire [0:0] cby_1__1__60_left_grid_pin_19_ ; +wire [0:0] cby_1__1__60_left_grid_pin_20_ ; +wire [0:0] cby_1__1__60_left_grid_pin_21_ ; +wire [0:0] cby_1__1__60_left_grid_pin_22_ ; +wire [0:0] cby_1__1__60_left_grid_pin_23_ ; +wire [0:0] cby_1__1__60_left_grid_pin_24_ ; +wire [0:0] cby_1__1__60_left_grid_pin_25_ ; +wire [0:0] cby_1__1__60_left_grid_pin_26_ ; +wire [0:0] cby_1__1__60_left_grid_pin_27_ ; +wire [0:0] cby_1__1__60_left_grid_pin_28_ ; +wire [0:0] cby_1__1__60_left_grid_pin_29_ ; +wire [0:0] cby_1__1__60_left_grid_pin_30_ ; +wire [0:0] cby_1__1__60_left_grid_pin_31_ ; +wire [0:0] cby_1__1__61_ccff_tail ; +wire [0:29] cby_1__1__61_chany_bottom_out ; +wire [0:29] cby_1__1__61_chany_top_out ; +wire [0:0] cby_1__1__61_left_grid_pin_16_ ; +wire [0:0] cby_1__1__61_left_grid_pin_17_ ; +wire [0:0] cby_1__1__61_left_grid_pin_18_ ; +wire [0:0] cby_1__1__61_left_grid_pin_19_ ; +wire [0:0] cby_1__1__61_left_grid_pin_20_ ; +wire [0:0] cby_1__1__61_left_grid_pin_21_ ; +wire [0:0] cby_1__1__61_left_grid_pin_22_ ; +wire [0:0] cby_1__1__61_left_grid_pin_23_ ; +wire [0:0] cby_1__1__61_left_grid_pin_24_ ; +wire [0:0] cby_1__1__61_left_grid_pin_25_ ; +wire [0:0] cby_1__1__61_left_grid_pin_26_ ; +wire [0:0] cby_1__1__61_left_grid_pin_27_ ; +wire [0:0] cby_1__1__61_left_grid_pin_28_ ; +wire [0:0] cby_1__1__61_left_grid_pin_29_ ; +wire [0:0] cby_1__1__61_left_grid_pin_30_ ; +wire [0:0] cby_1__1__61_left_grid_pin_31_ ; +wire [0:0] cby_1__1__62_ccff_tail ; +wire [0:29] cby_1__1__62_chany_bottom_out ; +wire [0:29] cby_1__1__62_chany_top_out ; +wire [0:0] cby_1__1__62_left_grid_pin_16_ ; +wire [0:0] cby_1__1__62_left_grid_pin_17_ ; +wire [0:0] cby_1__1__62_left_grid_pin_18_ ; +wire [0:0] cby_1__1__62_left_grid_pin_19_ ; +wire [0:0] cby_1__1__62_left_grid_pin_20_ ; +wire [0:0] cby_1__1__62_left_grid_pin_21_ ; +wire [0:0] cby_1__1__62_left_grid_pin_22_ ; +wire [0:0] cby_1__1__62_left_grid_pin_23_ ; +wire [0:0] cby_1__1__62_left_grid_pin_24_ ; +wire [0:0] cby_1__1__62_left_grid_pin_25_ ; +wire [0:0] cby_1__1__62_left_grid_pin_26_ ; +wire [0:0] cby_1__1__62_left_grid_pin_27_ ; +wire [0:0] cby_1__1__62_left_grid_pin_28_ ; +wire [0:0] cby_1__1__62_left_grid_pin_29_ ; +wire [0:0] cby_1__1__62_left_grid_pin_30_ ; +wire [0:0] cby_1__1__62_left_grid_pin_31_ ; +wire [0:0] cby_1__1__63_ccff_tail ; +wire [0:29] cby_1__1__63_chany_bottom_out ; +wire [0:29] cby_1__1__63_chany_top_out ; +wire [0:0] cby_1__1__63_left_grid_pin_16_ ; +wire [0:0] cby_1__1__63_left_grid_pin_17_ ; +wire [0:0] cby_1__1__63_left_grid_pin_18_ ; +wire [0:0] cby_1__1__63_left_grid_pin_19_ ; +wire [0:0] cby_1__1__63_left_grid_pin_20_ ; +wire [0:0] cby_1__1__63_left_grid_pin_21_ ; +wire [0:0] cby_1__1__63_left_grid_pin_22_ ; +wire [0:0] cby_1__1__63_left_grid_pin_23_ ; +wire [0:0] cby_1__1__63_left_grid_pin_24_ ; +wire [0:0] cby_1__1__63_left_grid_pin_25_ ; +wire [0:0] cby_1__1__63_left_grid_pin_26_ ; +wire [0:0] cby_1__1__63_left_grid_pin_27_ ; +wire [0:0] cby_1__1__63_left_grid_pin_28_ ; +wire [0:0] cby_1__1__63_left_grid_pin_29_ ; +wire [0:0] cby_1__1__63_left_grid_pin_30_ ; +wire [0:0] cby_1__1__63_left_grid_pin_31_ ; +wire [0:0] cby_1__1__64_ccff_tail ; +wire [0:29] cby_1__1__64_chany_bottom_out ; +wire [0:29] cby_1__1__64_chany_top_out ; +wire [0:0] cby_1__1__64_left_grid_pin_16_ ; +wire [0:0] cby_1__1__64_left_grid_pin_17_ ; +wire [0:0] cby_1__1__64_left_grid_pin_18_ ; +wire [0:0] cby_1__1__64_left_grid_pin_19_ ; +wire [0:0] cby_1__1__64_left_grid_pin_20_ ; +wire [0:0] cby_1__1__64_left_grid_pin_21_ ; +wire [0:0] cby_1__1__64_left_grid_pin_22_ ; +wire [0:0] cby_1__1__64_left_grid_pin_23_ ; +wire [0:0] cby_1__1__64_left_grid_pin_24_ ; +wire [0:0] cby_1__1__64_left_grid_pin_25_ ; +wire [0:0] cby_1__1__64_left_grid_pin_26_ ; +wire [0:0] cby_1__1__64_left_grid_pin_27_ ; +wire [0:0] cby_1__1__64_left_grid_pin_28_ ; +wire [0:0] cby_1__1__64_left_grid_pin_29_ ; +wire [0:0] cby_1__1__64_left_grid_pin_30_ ; +wire [0:0] cby_1__1__64_left_grid_pin_31_ ; +wire [0:0] cby_1__1__65_ccff_tail ; +wire [0:29] cby_1__1__65_chany_bottom_out ; +wire [0:29] cby_1__1__65_chany_top_out ; +wire [0:0] cby_1__1__65_left_grid_pin_16_ ; +wire [0:0] cby_1__1__65_left_grid_pin_17_ ; +wire [0:0] cby_1__1__65_left_grid_pin_18_ ; +wire [0:0] cby_1__1__65_left_grid_pin_19_ ; +wire [0:0] cby_1__1__65_left_grid_pin_20_ ; +wire [0:0] cby_1__1__65_left_grid_pin_21_ ; +wire [0:0] cby_1__1__65_left_grid_pin_22_ ; +wire [0:0] cby_1__1__65_left_grid_pin_23_ ; +wire [0:0] cby_1__1__65_left_grid_pin_24_ ; +wire [0:0] cby_1__1__65_left_grid_pin_25_ ; +wire [0:0] cby_1__1__65_left_grid_pin_26_ ; +wire [0:0] cby_1__1__65_left_grid_pin_27_ ; +wire [0:0] cby_1__1__65_left_grid_pin_28_ ; +wire [0:0] cby_1__1__65_left_grid_pin_29_ ; +wire [0:0] cby_1__1__65_left_grid_pin_30_ ; +wire [0:0] cby_1__1__65_left_grid_pin_31_ ; +wire [0:0] cby_1__1__66_ccff_tail ; +wire [0:29] cby_1__1__66_chany_bottom_out ; +wire [0:29] cby_1__1__66_chany_top_out ; +wire [0:0] cby_1__1__66_left_grid_pin_16_ ; +wire [0:0] cby_1__1__66_left_grid_pin_17_ ; +wire [0:0] cby_1__1__66_left_grid_pin_18_ ; +wire [0:0] cby_1__1__66_left_grid_pin_19_ ; +wire [0:0] cby_1__1__66_left_grid_pin_20_ ; +wire [0:0] cby_1__1__66_left_grid_pin_21_ ; +wire [0:0] cby_1__1__66_left_grid_pin_22_ ; +wire [0:0] cby_1__1__66_left_grid_pin_23_ ; +wire [0:0] cby_1__1__66_left_grid_pin_24_ ; +wire [0:0] cby_1__1__66_left_grid_pin_25_ ; +wire [0:0] cby_1__1__66_left_grid_pin_26_ ; +wire [0:0] cby_1__1__66_left_grid_pin_27_ ; +wire [0:0] cby_1__1__66_left_grid_pin_28_ ; +wire [0:0] cby_1__1__66_left_grid_pin_29_ ; +wire [0:0] cby_1__1__66_left_grid_pin_30_ ; +wire [0:0] cby_1__1__66_left_grid_pin_31_ ; +wire [0:0] cby_1__1__67_ccff_tail ; +wire [0:29] cby_1__1__67_chany_bottom_out ; +wire [0:29] cby_1__1__67_chany_top_out ; +wire [0:0] cby_1__1__67_left_grid_pin_16_ ; +wire [0:0] cby_1__1__67_left_grid_pin_17_ ; +wire [0:0] cby_1__1__67_left_grid_pin_18_ ; +wire [0:0] cby_1__1__67_left_grid_pin_19_ ; +wire [0:0] cby_1__1__67_left_grid_pin_20_ ; +wire [0:0] cby_1__1__67_left_grid_pin_21_ ; +wire [0:0] cby_1__1__67_left_grid_pin_22_ ; +wire [0:0] cby_1__1__67_left_grid_pin_23_ ; +wire [0:0] cby_1__1__67_left_grid_pin_24_ ; +wire [0:0] cby_1__1__67_left_grid_pin_25_ ; +wire [0:0] cby_1__1__67_left_grid_pin_26_ ; +wire [0:0] cby_1__1__67_left_grid_pin_27_ ; +wire [0:0] cby_1__1__67_left_grid_pin_28_ ; +wire [0:0] cby_1__1__67_left_grid_pin_29_ ; +wire [0:0] cby_1__1__67_left_grid_pin_30_ ; +wire [0:0] cby_1__1__67_left_grid_pin_31_ ; +wire [0:0] cby_1__1__68_ccff_tail ; +wire [0:29] cby_1__1__68_chany_bottom_out ; +wire [0:29] cby_1__1__68_chany_top_out ; +wire [0:0] cby_1__1__68_left_grid_pin_16_ ; +wire [0:0] cby_1__1__68_left_grid_pin_17_ ; +wire [0:0] cby_1__1__68_left_grid_pin_18_ ; +wire [0:0] cby_1__1__68_left_grid_pin_19_ ; +wire [0:0] cby_1__1__68_left_grid_pin_20_ ; +wire [0:0] cby_1__1__68_left_grid_pin_21_ ; +wire [0:0] cby_1__1__68_left_grid_pin_22_ ; +wire [0:0] cby_1__1__68_left_grid_pin_23_ ; +wire [0:0] cby_1__1__68_left_grid_pin_24_ ; +wire [0:0] cby_1__1__68_left_grid_pin_25_ ; +wire [0:0] cby_1__1__68_left_grid_pin_26_ ; +wire [0:0] cby_1__1__68_left_grid_pin_27_ ; +wire [0:0] cby_1__1__68_left_grid_pin_28_ ; +wire [0:0] cby_1__1__68_left_grid_pin_29_ ; +wire [0:0] cby_1__1__68_left_grid_pin_30_ ; +wire [0:0] cby_1__1__68_left_grid_pin_31_ ; +wire [0:0] cby_1__1__69_ccff_tail ; +wire [0:29] cby_1__1__69_chany_bottom_out ; +wire [0:29] cby_1__1__69_chany_top_out ; +wire [0:0] cby_1__1__69_left_grid_pin_16_ ; +wire [0:0] cby_1__1__69_left_grid_pin_17_ ; +wire [0:0] cby_1__1__69_left_grid_pin_18_ ; +wire [0:0] cby_1__1__69_left_grid_pin_19_ ; +wire [0:0] cby_1__1__69_left_grid_pin_20_ ; +wire [0:0] cby_1__1__69_left_grid_pin_21_ ; +wire [0:0] cby_1__1__69_left_grid_pin_22_ ; +wire [0:0] cby_1__1__69_left_grid_pin_23_ ; +wire [0:0] cby_1__1__69_left_grid_pin_24_ ; +wire [0:0] cby_1__1__69_left_grid_pin_25_ ; +wire [0:0] cby_1__1__69_left_grid_pin_26_ ; +wire [0:0] cby_1__1__69_left_grid_pin_27_ ; +wire [0:0] cby_1__1__69_left_grid_pin_28_ ; +wire [0:0] cby_1__1__69_left_grid_pin_29_ ; +wire [0:0] cby_1__1__69_left_grid_pin_30_ ; +wire [0:0] cby_1__1__69_left_grid_pin_31_ ; +wire [0:0] cby_1__1__6_ccff_tail ; +wire [0:29] cby_1__1__6_chany_bottom_out ; +wire [0:29] cby_1__1__6_chany_top_out ; +wire [0:0] cby_1__1__6_left_grid_pin_16_ ; +wire [0:0] cby_1__1__6_left_grid_pin_17_ ; +wire [0:0] cby_1__1__6_left_grid_pin_18_ ; +wire [0:0] cby_1__1__6_left_grid_pin_19_ ; +wire [0:0] cby_1__1__6_left_grid_pin_20_ ; +wire [0:0] cby_1__1__6_left_grid_pin_21_ ; +wire [0:0] cby_1__1__6_left_grid_pin_22_ ; +wire [0:0] cby_1__1__6_left_grid_pin_23_ ; +wire [0:0] cby_1__1__6_left_grid_pin_24_ ; +wire [0:0] cby_1__1__6_left_grid_pin_25_ ; +wire [0:0] cby_1__1__6_left_grid_pin_26_ ; +wire [0:0] cby_1__1__6_left_grid_pin_27_ ; +wire [0:0] cby_1__1__6_left_grid_pin_28_ ; +wire [0:0] cby_1__1__6_left_grid_pin_29_ ; +wire [0:0] cby_1__1__6_left_grid_pin_30_ ; +wire [0:0] cby_1__1__6_left_grid_pin_31_ ; +wire [0:0] cby_1__1__70_ccff_tail ; +wire [0:29] cby_1__1__70_chany_bottom_out ; +wire [0:29] cby_1__1__70_chany_top_out ; +wire [0:0] cby_1__1__70_left_grid_pin_16_ ; +wire [0:0] cby_1__1__70_left_grid_pin_17_ ; +wire [0:0] cby_1__1__70_left_grid_pin_18_ ; +wire [0:0] cby_1__1__70_left_grid_pin_19_ ; +wire [0:0] cby_1__1__70_left_grid_pin_20_ ; +wire [0:0] cby_1__1__70_left_grid_pin_21_ ; +wire [0:0] cby_1__1__70_left_grid_pin_22_ ; +wire [0:0] cby_1__1__70_left_grid_pin_23_ ; +wire [0:0] cby_1__1__70_left_grid_pin_24_ ; +wire [0:0] cby_1__1__70_left_grid_pin_25_ ; +wire [0:0] cby_1__1__70_left_grid_pin_26_ ; +wire [0:0] cby_1__1__70_left_grid_pin_27_ ; +wire [0:0] cby_1__1__70_left_grid_pin_28_ ; +wire [0:0] cby_1__1__70_left_grid_pin_29_ ; +wire [0:0] cby_1__1__70_left_grid_pin_30_ ; +wire [0:0] cby_1__1__70_left_grid_pin_31_ ; +wire [0:0] cby_1__1__71_ccff_tail ; +wire [0:29] cby_1__1__71_chany_bottom_out ; +wire [0:29] cby_1__1__71_chany_top_out ; +wire [0:0] cby_1__1__71_left_grid_pin_16_ ; +wire [0:0] cby_1__1__71_left_grid_pin_17_ ; +wire [0:0] cby_1__1__71_left_grid_pin_18_ ; +wire [0:0] cby_1__1__71_left_grid_pin_19_ ; +wire [0:0] cby_1__1__71_left_grid_pin_20_ ; +wire [0:0] cby_1__1__71_left_grid_pin_21_ ; +wire [0:0] cby_1__1__71_left_grid_pin_22_ ; +wire [0:0] cby_1__1__71_left_grid_pin_23_ ; +wire [0:0] cby_1__1__71_left_grid_pin_24_ ; +wire [0:0] cby_1__1__71_left_grid_pin_25_ ; +wire [0:0] cby_1__1__71_left_grid_pin_26_ ; +wire [0:0] cby_1__1__71_left_grid_pin_27_ ; +wire [0:0] cby_1__1__71_left_grid_pin_28_ ; +wire [0:0] cby_1__1__71_left_grid_pin_29_ ; +wire [0:0] cby_1__1__71_left_grid_pin_30_ ; +wire [0:0] cby_1__1__71_left_grid_pin_31_ ; +wire [0:0] cby_1__1__72_ccff_tail ; +wire [0:29] cby_1__1__72_chany_bottom_out ; +wire [0:29] cby_1__1__72_chany_top_out ; +wire [0:0] cby_1__1__72_left_grid_pin_16_ ; +wire [0:0] cby_1__1__72_left_grid_pin_17_ ; +wire [0:0] cby_1__1__72_left_grid_pin_18_ ; +wire [0:0] cby_1__1__72_left_grid_pin_19_ ; +wire [0:0] cby_1__1__72_left_grid_pin_20_ ; +wire [0:0] cby_1__1__72_left_grid_pin_21_ ; +wire [0:0] cby_1__1__72_left_grid_pin_22_ ; +wire [0:0] cby_1__1__72_left_grid_pin_23_ ; +wire [0:0] cby_1__1__72_left_grid_pin_24_ ; +wire [0:0] cby_1__1__72_left_grid_pin_25_ ; +wire [0:0] cby_1__1__72_left_grid_pin_26_ ; +wire [0:0] cby_1__1__72_left_grid_pin_27_ ; +wire [0:0] cby_1__1__72_left_grid_pin_28_ ; +wire [0:0] cby_1__1__72_left_grid_pin_29_ ; +wire [0:0] cby_1__1__72_left_grid_pin_30_ ; +wire [0:0] cby_1__1__72_left_grid_pin_31_ ; +wire [0:0] cby_1__1__73_ccff_tail ; +wire [0:29] cby_1__1__73_chany_bottom_out ; +wire [0:29] cby_1__1__73_chany_top_out ; +wire [0:0] cby_1__1__73_left_grid_pin_16_ ; +wire [0:0] cby_1__1__73_left_grid_pin_17_ ; +wire [0:0] cby_1__1__73_left_grid_pin_18_ ; +wire [0:0] cby_1__1__73_left_grid_pin_19_ ; +wire [0:0] cby_1__1__73_left_grid_pin_20_ ; +wire [0:0] cby_1__1__73_left_grid_pin_21_ ; +wire [0:0] cby_1__1__73_left_grid_pin_22_ ; +wire [0:0] cby_1__1__73_left_grid_pin_23_ ; +wire [0:0] cby_1__1__73_left_grid_pin_24_ ; +wire [0:0] cby_1__1__73_left_grid_pin_25_ ; +wire [0:0] cby_1__1__73_left_grid_pin_26_ ; +wire [0:0] cby_1__1__73_left_grid_pin_27_ ; +wire [0:0] cby_1__1__73_left_grid_pin_28_ ; +wire [0:0] cby_1__1__73_left_grid_pin_29_ ; +wire [0:0] cby_1__1__73_left_grid_pin_30_ ; +wire [0:0] cby_1__1__73_left_grid_pin_31_ ; +wire [0:0] cby_1__1__74_ccff_tail ; +wire [0:29] cby_1__1__74_chany_bottom_out ; +wire [0:29] cby_1__1__74_chany_top_out ; +wire [0:0] cby_1__1__74_left_grid_pin_16_ ; +wire [0:0] cby_1__1__74_left_grid_pin_17_ ; +wire [0:0] cby_1__1__74_left_grid_pin_18_ ; +wire [0:0] cby_1__1__74_left_grid_pin_19_ ; +wire [0:0] cby_1__1__74_left_grid_pin_20_ ; +wire [0:0] cby_1__1__74_left_grid_pin_21_ ; +wire [0:0] cby_1__1__74_left_grid_pin_22_ ; +wire [0:0] cby_1__1__74_left_grid_pin_23_ ; +wire [0:0] cby_1__1__74_left_grid_pin_24_ ; +wire [0:0] cby_1__1__74_left_grid_pin_25_ ; +wire [0:0] cby_1__1__74_left_grid_pin_26_ ; +wire [0:0] cby_1__1__74_left_grid_pin_27_ ; +wire [0:0] cby_1__1__74_left_grid_pin_28_ ; +wire [0:0] cby_1__1__74_left_grid_pin_29_ ; +wire [0:0] cby_1__1__74_left_grid_pin_30_ ; +wire [0:0] cby_1__1__74_left_grid_pin_31_ ; +wire [0:0] cby_1__1__75_ccff_tail ; +wire [0:29] cby_1__1__75_chany_bottom_out ; +wire [0:29] cby_1__1__75_chany_top_out ; +wire [0:0] cby_1__1__75_left_grid_pin_16_ ; +wire [0:0] cby_1__1__75_left_grid_pin_17_ ; +wire [0:0] cby_1__1__75_left_grid_pin_18_ ; +wire [0:0] cby_1__1__75_left_grid_pin_19_ ; +wire [0:0] cby_1__1__75_left_grid_pin_20_ ; +wire [0:0] cby_1__1__75_left_grid_pin_21_ ; +wire [0:0] cby_1__1__75_left_grid_pin_22_ ; +wire [0:0] cby_1__1__75_left_grid_pin_23_ ; +wire [0:0] cby_1__1__75_left_grid_pin_24_ ; +wire [0:0] cby_1__1__75_left_grid_pin_25_ ; +wire [0:0] cby_1__1__75_left_grid_pin_26_ ; +wire [0:0] cby_1__1__75_left_grid_pin_27_ ; +wire [0:0] cby_1__1__75_left_grid_pin_28_ ; +wire [0:0] cby_1__1__75_left_grid_pin_29_ ; +wire [0:0] cby_1__1__75_left_grid_pin_30_ ; +wire [0:0] cby_1__1__75_left_grid_pin_31_ ; +wire [0:0] cby_1__1__76_ccff_tail ; +wire [0:29] cby_1__1__76_chany_bottom_out ; +wire [0:29] cby_1__1__76_chany_top_out ; +wire [0:0] cby_1__1__76_left_grid_pin_16_ ; +wire [0:0] cby_1__1__76_left_grid_pin_17_ ; +wire [0:0] cby_1__1__76_left_grid_pin_18_ ; +wire [0:0] cby_1__1__76_left_grid_pin_19_ ; +wire [0:0] cby_1__1__76_left_grid_pin_20_ ; +wire [0:0] cby_1__1__76_left_grid_pin_21_ ; +wire [0:0] cby_1__1__76_left_grid_pin_22_ ; +wire [0:0] cby_1__1__76_left_grid_pin_23_ ; +wire [0:0] cby_1__1__76_left_grid_pin_24_ ; +wire [0:0] cby_1__1__76_left_grid_pin_25_ ; +wire [0:0] cby_1__1__76_left_grid_pin_26_ ; +wire [0:0] cby_1__1__76_left_grid_pin_27_ ; +wire [0:0] cby_1__1__76_left_grid_pin_28_ ; +wire [0:0] cby_1__1__76_left_grid_pin_29_ ; +wire [0:0] cby_1__1__76_left_grid_pin_30_ ; +wire [0:0] cby_1__1__76_left_grid_pin_31_ ; +wire [0:0] cby_1__1__77_ccff_tail ; +wire [0:29] cby_1__1__77_chany_bottom_out ; +wire [0:29] cby_1__1__77_chany_top_out ; +wire [0:0] cby_1__1__77_left_grid_pin_16_ ; +wire [0:0] cby_1__1__77_left_grid_pin_17_ ; +wire [0:0] cby_1__1__77_left_grid_pin_18_ ; +wire [0:0] cby_1__1__77_left_grid_pin_19_ ; +wire [0:0] cby_1__1__77_left_grid_pin_20_ ; +wire [0:0] cby_1__1__77_left_grid_pin_21_ ; +wire [0:0] cby_1__1__77_left_grid_pin_22_ ; +wire [0:0] cby_1__1__77_left_grid_pin_23_ ; +wire [0:0] cby_1__1__77_left_grid_pin_24_ ; +wire [0:0] cby_1__1__77_left_grid_pin_25_ ; +wire [0:0] cby_1__1__77_left_grid_pin_26_ ; +wire [0:0] cby_1__1__77_left_grid_pin_27_ ; +wire [0:0] cby_1__1__77_left_grid_pin_28_ ; +wire [0:0] cby_1__1__77_left_grid_pin_29_ ; +wire [0:0] cby_1__1__77_left_grid_pin_30_ ; +wire [0:0] cby_1__1__77_left_grid_pin_31_ ; +wire [0:0] cby_1__1__78_ccff_tail ; +wire [0:29] cby_1__1__78_chany_bottom_out ; +wire [0:29] cby_1__1__78_chany_top_out ; +wire [0:0] cby_1__1__78_left_grid_pin_16_ ; +wire [0:0] cby_1__1__78_left_grid_pin_17_ ; +wire [0:0] cby_1__1__78_left_grid_pin_18_ ; +wire [0:0] cby_1__1__78_left_grid_pin_19_ ; +wire [0:0] cby_1__1__78_left_grid_pin_20_ ; +wire [0:0] cby_1__1__78_left_grid_pin_21_ ; +wire [0:0] cby_1__1__78_left_grid_pin_22_ ; +wire [0:0] cby_1__1__78_left_grid_pin_23_ ; +wire [0:0] cby_1__1__78_left_grid_pin_24_ ; +wire [0:0] cby_1__1__78_left_grid_pin_25_ ; +wire [0:0] cby_1__1__78_left_grid_pin_26_ ; +wire [0:0] cby_1__1__78_left_grid_pin_27_ ; +wire [0:0] cby_1__1__78_left_grid_pin_28_ ; +wire [0:0] cby_1__1__78_left_grid_pin_29_ ; +wire [0:0] cby_1__1__78_left_grid_pin_30_ ; +wire [0:0] cby_1__1__78_left_grid_pin_31_ ; +wire [0:0] cby_1__1__79_ccff_tail ; +wire [0:29] cby_1__1__79_chany_bottom_out ; +wire [0:29] cby_1__1__79_chany_top_out ; +wire [0:0] cby_1__1__79_left_grid_pin_16_ ; +wire [0:0] cby_1__1__79_left_grid_pin_17_ ; +wire [0:0] cby_1__1__79_left_grid_pin_18_ ; +wire [0:0] cby_1__1__79_left_grid_pin_19_ ; +wire [0:0] cby_1__1__79_left_grid_pin_20_ ; +wire [0:0] cby_1__1__79_left_grid_pin_21_ ; +wire [0:0] cby_1__1__79_left_grid_pin_22_ ; +wire [0:0] cby_1__1__79_left_grid_pin_23_ ; +wire [0:0] cby_1__1__79_left_grid_pin_24_ ; +wire [0:0] cby_1__1__79_left_grid_pin_25_ ; +wire [0:0] cby_1__1__79_left_grid_pin_26_ ; +wire [0:0] cby_1__1__79_left_grid_pin_27_ ; +wire [0:0] cby_1__1__79_left_grid_pin_28_ ; +wire [0:0] cby_1__1__79_left_grid_pin_29_ ; +wire [0:0] cby_1__1__79_left_grid_pin_30_ ; +wire [0:0] cby_1__1__79_left_grid_pin_31_ ; +wire [0:0] cby_1__1__7_ccff_tail ; +wire [0:29] cby_1__1__7_chany_bottom_out ; +wire [0:29] cby_1__1__7_chany_top_out ; +wire [0:0] cby_1__1__7_left_grid_pin_16_ ; +wire [0:0] cby_1__1__7_left_grid_pin_17_ ; +wire [0:0] cby_1__1__7_left_grid_pin_18_ ; +wire [0:0] cby_1__1__7_left_grid_pin_19_ ; +wire [0:0] cby_1__1__7_left_grid_pin_20_ ; +wire [0:0] cby_1__1__7_left_grid_pin_21_ ; +wire [0:0] cby_1__1__7_left_grid_pin_22_ ; +wire [0:0] cby_1__1__7_left_grid_pin_23_ ; +wire [0:0] cby_1__1__7_left_grid_pin_24_ ; +wire [0:0] cby_1__1__7_left_grid_pin_25_ ; +wire [0:0] cby_1__1__7_left_grid_pin_26_ ; +wire [0:0] cby_1__1__7_left_grid_pin_27_ ; +wire [0:0] cby_1__1__7_left_grid_pin_28_ ; +wire [0:0] cby_1__1__7_left_grid_pin_29_ ; +wire [0:0] cby_1__1__7_left_grid_pin_30_ ; +wire [0:0] cby_1__1__7_left_grid_pin_31_ ; +wire [0:0] cby_1__1__80_ccff_tail ; +wire [0:29] cby_1__1__80_chany_bottom_out ; +wire [0:29] cby_1__1__80_chany_top_out ; +wire [0:0] cby_1__1__80_left_grid_pin_16_ ; +wire [0:0] cby_1__1__80_left_grid_pin_17_ ; +wire [0:0] cby_1__1__80_left_grid_pin_18_ ; +wire [0:0] cby_1__1__80_left_grid_pin_19_ ; +wire [0:0] cby_1__1__80_left_grid_pin_20_ ; +wire [0:0] cby_1__1__80_left_grid_pin_21_ ; +wire [0:0] cby_1__1__80_left_grid_pin_22_ ; +wire [0:0] cby_1__1__80_left_grid_pin_23_ ; +wire [0:0] cby_1__1__80_left_grid_pin_24_ ; +wire [0:0] cby_1__1__80_left_grid_pin_25_ ; +wire [0:0] cby_1__1__80_left_grid_pin_26_ ; +wire [0:0] cby_1__1__80_left_grid_pin_27_ ; +wire [0:0] cby_1__1__80_left_grid_pin_28_ ; +wire [0:0] cby_1__1__80_left_grid_pin_29_ ; +wire [0:0] cby_1__1__80_left_grid_pin_30_ ; +wire [0:0] cby_1__1__80_left_grid_pin_31_ ; +wire [0:0] cby_1__1__81_ccff_tail ; +wire [0:29] cby_1__1__81_chany_bottom_out ; +wire [0:29] cby_1__1__81_chany_top_out ; +wire [0:0] cby_1__1__81_left_grid_pin_16_ ; +wire [0:0] cby_1__1__81_left_grid_pin_17_ ; +wire [0:0] cby_1__1__81_left_grid_pin_18_ ; +wire [0:0] cby_1__1__81_left_grid_pin_19_ ; +wire [0:0] cby_1__1__81_left_grid_pin_20_ ; +wire [0:0] cby_1__1__81_left_grid_pin_21_ ; +wire [0:0] cby_1__1__81_left_grid_pin_22_ ; +wire [0:0] cby_1__1__81_left_grid_pin_23_ ; +wire [0:0] cby_1__1__81_left_grid_pin_24_ ; +wire [0:0] cby_1__1__81_left_grid_pin_25_ ; +wire [0:0] cby_1__1__81_left_grid_pin_26_ ; +wire [0:0] cby_1__1__81_left_grid_pin_27_ ; +wire [0:0] cby_1__1__81_left_grid_pin_28_ ; +wire [0:0] cby_1__1__81_left_grid_pin_29_ ; +wire [0:0] cby_1__1__81_left_grid_pin_30_ ; +wire [0:0] cby_1__1__81_left_grid_pin_31_ ; +wire [0:0] cby_1__1__82_ccff_tail ; +wire [0:29] cby_1__1__82_chany_bottom_out ; +wire [0:29] cby_1__1__82_chany_top_out ; +wire [0:0] cby_1__1__82_left_grid_pin_16_ ; +wire [0:0] cby_1__1__82_left_grid_pin_17_ ; +wire [0:0] cby_1__1__82_left_grid_pin_18_ ; +wire [0:0] cby_1__1__82_left_grid_pin_19_ ; +wire [0:0] cby_1__1__82_left_grid_pin_20_ ; +wire [0:0] cby_1__1__82_left_grid_pin_21_ ; +wire [0:0] cby_1__1__82_left_grid_pin_22_ ; +wire [0:0] cby_1__1__82_left_grid_pin_23_ ; +wire [0:0] cby_1__1__82_left_grid_pin_24_ ; +wire [0:0] cby_1__1__82_left_grid_pin_25_ ; +wire [0:0] cby_1__1__82_left_grid_pin_26_ ; +wire [0:0] cby_1__1__82_left_grid_pin_27_ ; +wire [0:0] cby_1__1__82_left_grid_pin_28_ ; +wire [0:0] cby_1__1__82_left_grid_pin_29_ ; +wire [0:0] cby_1__1__82_left_grid_pin_30_ ; +wire [0:0] cby_1__1__82_left_grid_pin_31_ ; +wire [0:0] cby_1__1__83_ccff_tail ; +wire [0:29] cby_1__1__83_chany_bottom_out ; +wire [0:29] cby_1__1__83_chany_top_out ; +wire [0:0] cby_1__1__83_left_grid_pin_16_ ; +wire [0:0] cby_1__1__83_left_grid_pin_17_ ; +wire [0:0] cby_1__1__83_left_grid_pin_18_ ; +wire [0:0] cby_1__1__83_left_grid_pin_19_ ; +wire [0:0] cby_1__1__83_left_grid_pin_20_ ; +wire [0:0] cby_1__1__83_left_grid_pin_21_ ; +wire [0:0] cby_1__1__83_left_grid_pin_22_ ; +wire [0:0] cby_1__1__83_left_grid_pin_23_ ; +wire [0:0] cby_1__1__83_left_grid_pin_24_ ; +wire [0:0] cby_1__1__83_left_grid_pin_25_ ; +wire [0:0] cby_1__1__83_left_grid_pin_26_ ; +wire [0:0] cby_1__1__83_left_grid_pin_27_ ; +wire [0:0] cby_1__1__83_left_grid_pin_28_ ; +wire [0:0] cby_1__1__83_left_grid_pin_29_ ; +wire [0:0] cby_1__1__83_left_grid_pin_30_ ; +wire [0:0] cby_1__1__83_left_grid_pin_31_ ; +wire [0:0] cby_1__1__84_ccff_tail ; +wire [0:29] cby_1__1__84_chany_bottom_out ; +wire [0:29] cby_1__1__84_chany_top_out ; +wire [0:0] cby_1__1__84_left_grid_pin_16_ ; +wire [0:0] cby_1__1__84_left_grid_pin_17_ ; +wire [0:0] cby_1__1__84_left_grid_pin_18_ ; +wire [0:0] cby_1__1__84_left_grid_pin_19_ ; +wire [0:0] cby_1__1__84_left_grid_pin_20_ ; +wire [0:0] cby_1__1__84_left_grid_pin_21_ ; +wire [0:0] cby_1__1__84_left_grid_pin_22_ ; +wire [0:0] cby_1__1__84_left_grid_pin_23_ ; +wire [0:0] cby_1__1__84_left_grid_pin_24_ ; +wire [0:0] cby_1__1__84_left_grid_pin_25_ ; +wire [0:0] cby_1__1__84_left_grid_pin_26_ ; +wire [0:0] cby_1__1__84_left_grid_pin_27_ ; +wire [0:0] cby_1__1__84_left_grid_pin_28_ ; +wire [0:0] cby_1__1__84_left_grid_pin_29_ ; +wire [0:0] cby_1__1__84_left_grid_pin_30_ ; +wire [0:0] cby_1__1__84_left_grid_pin_31_ ; +wire [0:0] cby_1__1__85_ccff_tail ; +wire [0:29] cby_1__1__85_chany_bottom_out ; +wire [0:29] cby_1__1__85_chany_top_out ; +wire [0:0] cby_1__1__85_left_grid_pin_16_ ; +wire [0:0] cby_1__1__85_left_grid_pin_17_ ; +wire [0:0] cby_1__1__85_left_grid_pin_18_ ; +wire [0:0] cby_1__1__85_left_grid_pin_19_ ; +wire [0:0] cby_1__1__85_left_grid_pin_20_ ; +wire [0:0] cby_1__1__85_left_grid_pin_21_ ; +wire [0:0] cby_1__1__85_left_grid_pin_22_ ; +wire [0:0] cby_1__1__85_left_grid_pin_23_ ; +wire [0:0] cby_1__1__85_left_grid_pin_24_ ; +wire [0:0] cby_1__1__85_left_grid_pin_25_ ; +wire [0:0] cby_1__1__85_left_grid_pin_26_ ; +wire [0:0] cby_1__1__85_left_grid_pin_27_ ; +wire [0:0] cby_1__1__85_left_grid_pin_28_ ; +wire [0:0] cby_1__1__85_left_grid_pin_29_ ; +wire [0:0] cby_1__1__85_left_grid_pin_30_ ; +wire [0:0] cby_1__1__85_left_grid_pin_31_ ; +wire [0:0] cby_1__1__86_ccff_tail ; +wire [0:29] cby_1__1__86_chany_bottom_out ; +wire [0:29] cby_1__1__86_chany_top_out ; +wire [0:0] cby_1__1__86_left_grid_pin_16_ ; +wire [0:0] cby_1__1__86_left_grid_pin_17_ ; +wire [0:0] cby_1__1__86_left_grid_pin_18_ ; +wire [0:0] cby_1__1__86_left_grid_pin_19_ ; +wire [0:0] cby_1__1__86_left_grid_pin_20_ ; +wire [0:0] cby_1__1__86_left_grid_pin_21_ ; +wire [0:0] cby_1__1__86_left_grid_pin_22_ ; +wire [0:0] cby_1__1__86_left_grid_pin_23_ ; +wire [0:0] cby_1__1__86_left_grid_pin_24_ ; +wire [0:0] cby_1__1__86_left_grid_pin_25_ ; +wire [0:0] cby_1__1__86_left_grid_pin_26_ ; +wire [0:0] cby_1__1__86_left_grid_pin_27_ ; +wire [0:0] cby_1__1__86_left_grid_pin_28_ ; +wire [0:0] cby_1__1__86_left_grid_pin_29_ ; +wire [0:0] cby_1__1__86_left_grid_pin_30_ ; +wire [0:0] cby_1__1__86_left_grid_pin_31_ ; +wire [0:0] cby_1__1__87_ccff_tail ; +wire [0:29] cby_1__1__87_chany_bottom_out ; +wire [0:29] cby_1__1__87_chany_top_out ; +wire [0:0] cby_1__1__87_left_grid_pin_16_ ; +wire [0:0] cby_1__1__87_left_grid_pin_17_ ; +wire [0:0] cby_1__1__87_left_grid_pin_18_ ; +wire [0:0] cby_1__1__87_left_grid_pin_19_ ; +wire [0:0] cby_1__1__87_left_grid_pin_20_ ; +wire [0:0] cby_1__1__87_left_grid_pin_21_ ; +wire [0:0] cby_1__1__87_left_grid_pin_22_ ; +wire [0:0] cby_1__1__87_left_grid_pin_23_ ; +wire [0:0] cby_1__1__87_left_grid_pin_24_ ; +wire [0:0] cby_1__1__87_left_grid_pin_25_ ; +wire [0:0] cby_1__1__87_left_grid_pin_26_ ; +wire [0:0] cby_1__1__87_left_grid_pin_27_ ; +wire [0:0] cby_1__1__87_left_grid_pin_28_ ; +wire [0:0] cby_1__1__87_left_grid_pin_29_ ; +wire [0:0] cby_1__1__87_left_grid_pin_30_ ; +wire [0:0] cby_1__1__87_left_grid_pin_31_ ; +wire [0:0] cby_1__1__88_ccff_tail ; +wire [0:29] cby_1__1__88_chany_bottom_out ; +wire [0:29] cby_1__1__88_chany_top_out ; +wire [0:0] cby_1__1__88_left_grid_pin_16_ ; +wire [0:0] cby_1__1__88_left_grid_pin_17_ ; +wire [0:0] cby_1__1__88_left_grid_pin_18_ ; +wire [0:0] cby_1__1__88_left_grid_pin_19_ ; +wire [0:0] cby_1__1__88_left_grid_pin_20_ ; +wire [0:0] cby_1__1__88_left_grid_pin_21_ ; +wire [0:0] cby_1__1__88_left_grid_pin_22_ ; +wire [0:0] cby_1__1__88_left_grid_pin_23_ ; +wire [0:0] cby_1__1__88_left_grid_pin_24_ ; +wire [0:0] cby_1__1__88_left_grid_pin_25_ ; +wire [0:0] cby_1__1__88_left_grid_pin_26_ ; +wire [0:0] cby_1__1__88_left_grid_pin_27_ ; +wire [0:0] cby_1__1__88_left_grid_pin_28_ ; +wire [0:0] cby_1__1__88_left_grid_pin_29_ ; +wire [0:0] cby_1__1__88_left_grid_pin_30_ ; +wire [0:0] cby_1__1__88_left_grid_pin_31_ ; +wire [0:0] cby_1__1__89_ccff_tail ; +wire [0:29] cby_1__1__89_chany_bottom_out ; +wire [0:29] cby_1__1__89_chany_top_out ; +wire [0:0] cby_1__1__89_left_grid_pin_16_ ; +wire [0:0] cby_1__1__89_left_grid_pin_17_ ; +wire [0:0] cby_1__1__89_left_grid_pin_18_ ; +wire [0:0] cby_1__1__89_left_grid_pin_19_ ; +wire [0:0] cby_1__1__89_left_grid_pin_20_ ; +wire [0:0] cby_1__1__89_left_grid_pin_21_ ; +wire [0:0] cby_1__1__89_left_grid_pin_22_ ; +wire [0:0] cby_1__1__89_left_grid_pin_23_ ; +wire [0:0] cby_1__1__89_left_grid_pin_24_ ; +wire [0:0] cby_1__1__89_left_grid_pin_25_ ; +wire [0:0] cby_1__1__89_left_grid_pin_26_ ; +wire [0:0] cby_1__1__89_left_grid_pin_27_ ; +wire [0:0] cby_1__1__89_left_grid_pin_28_ ; +wire [0:0] cby_1__1__89_left_grid_pin_29_ ; +wire [0:0] cby_1__1__89_left_grid_pin_30_ ; +wire [0:0] cby_1__1__89_left_grid_pin_31_ ; +wire [0:0] cby_1__1__8_ccff_tail ; +wire [0:29] cby_1__1__8_chany_bottom_out ; +wire [0:29] cby_1__1__8_chany_top_out ; +wire [0:0] cby_1__1__8_left_grid_pin_16_ ; +wire [0:0] cby_1__1__8_left_grid_pin_17_ ; +wire [0:0] cby_1__1__8_left_grid_pin_18_ ; +wire [0:0] cby_1__1__8_left_grid_pin_19_ ; +wire [0:0] cby_1__1__8_left_grid_pin_20_ ; +wire [0:0] cby_1__1__8_left_grid_pin_21_ ; +wire [0:0] cby_1__1__8_left_grid_pin_22_ ; +wire [0:0] cby_1__1__8_left_grid_pin_23_ ; +wire [0:0] cby_1__1__8_left_grid_pin_24_ ; +wire [0:0] cby_1__1__8_left_grid_pin_25_ ; +wire [0:0] cby_1__1__8_left_grid_pin_26_ ; +wire [0:0] cby_1__1__8_left_grid_pin_27_ ; +wire [0:0] cby_1__1__8_left_grid_pin_28_ ; +wire [0:0] cby_1__1__8_left_grid_pin_29_ ; +wire [0:0] cby_1__1__8_left_grid_pin_30_ ; +wire [0:0] cby_1__1__8_left_grid_pin_31_ ; +wire [0:0] cby_1__1__90_ccff_tail ; +wire [0:29] cby_1__1__90_chany_bottom_out ; +wire [0:29] cby_1__1__90_chany_top_out ; +wire [0:0] cby_1__1__90_left_grid_pin_16_ ; +wire [0:0] cby_1__1__90_left_grid_pin_17_ ; +wire [0:0] cby_1__1__90_left_grid_pin_18_ ; +wire [0:0] cby_1__1__90_left_grid_pin_19_ ; +wire [0:0] cby_1__1__90_left_grid_pin_20_ ; +wire [0:0] cby_1__1__90_left_grid_pin_21_ ; +wire [0:0] cby_1__1__90_left_grid_pin_22_ ; +wire [0:0] cby_1__1__90_left_grid_pin_23_ ; +wire [0:0] cby_1__1__90_left_grid_pin_24_ ; +wire [0:0] cby_1__1__90_left_grid_pin_25_ ; +wire [0:0] cby_1__1__90_left_grid_pin_26_ ; +wire [0:0] cby_1__1__90_left_grid_pin_27_ ; +wire [0:0] cby_1__1__90_left_grid_pin_28_ ; +wire [0:0] cby_1__1__90_left_grid_pin_29_ ; +wire [0:0] cby_1__1__90_left_grid_pin_30_ ; +wire [0:0] cby_1__1__90_left_grid_pin_31_ ; +wire [0:0] cby_1__1__91_ccff_tail ; +wire [0:29] cby_1__1__91_chany_bottom_out ; +wire [0:29] cby_1__1__91_chany_top_out ; +wire [0:0] cby_1__1__91_left_grid_pin_16_ ; +wire [0:0] cby_1__1__91_left_grid_pin_17_ ; +wire [0:0] cby_1__1__91_left_grid_pin_18_ ; +wire [0:0] cby_1__1__91_left_grid_pin_19_ ; +wire [0:0] cby_1__1__91_left_grid_pin_20_ ; +wire [0:0] cby_1__1__91_left_grid_pin_21_ ; +wire [0:0] cby_1__1__91_left_grid_pin_22_ ; +wire [0:0] cby_1__1__91_left_grid_pin_23_ ; +wire [0:0] cby_1__1__91_left_grid_pin_24_ ; +wire [0:0] cby_1__1__91_left_grid_pin_25_ ; +wire [0:0] cby_1__1__91_left_grid_pin_26_ ; +wire [0:0] cby_1__1__91_left_grid_pin_27_ ; +wire [0:0] cby_1__1__91_left_grid_pin_28_ ; +wire [0:0] cby_1__1__91_left_grid_pin_29_ ; +wire [0:0] cby_1__1__91_left_grid_pin_30_ ; +wire [0:0] cby_1__1__91_left_grid_pin_31_ ; +wire [0:0] cby_1__1__92_ccff_tail ; +wire [0:29] cby_1__1__92_chany_bottom_out ; +wire [0:29] cby_1__1__92_chany_top_out ; +wire [0:0] cby_1__1__92_left_grid_pin_16_ ; +wire [0:0] cby_1__1__92_left_grid_pin_17_ ; +wire [0:0] cby_1__1__92_left_grid_pin_18_ ; +wire [0:0] cby_1__1__92_left_grid_pin_19_ ; +wire [0:0] cby_1__1__92_left_grid_pin_20_ ; +wire [0:0] cby_1__1__92_left_grid_pin_21_ ; +wire [0:0] cby_1__1__92_left_grid_pin_22_ ; +wire [0:0] cby_1__1__92_left_grid_pin_23_ ; +wire [0:0] cby_1__1__92_left_grid_pin_24_ ; +wire [0:0] cby_1__1__92_left_grid_pin_25_ ; +wire [0:0] cby_1__1__92_left_grid_pin_26_ ; +wire [0:0] cby_1__1__92_left_grid_pin_27_ ; +wire [0:0] cby_1__1__92_left_grid_pin_28_ ; +wire [0:0] cby_1__1__92_left_grid_pin_29_ ; +wire [0:0] cby_1__1__92_left_grid_pin_30_ ; +wire [0:0] cby_1__1__92_left_grid_pin_31_ ; +wire [0:0] cby_1__1__93_ccff_tail ; +wire [0:29] cby_1__1__93_chany_bottom_out ; +wire [0:29] cby_1__1__93_chany_top_out ; +wire [0:0] cby_1__1__93_left_grid_pin_16_ ; +wire [0:0] cby_1__1__93_left_grid_pin_17_ ; +wire [0:0] cby_1__1__93_left_grid_pin_18_ ; +wire [0:0] cby_1__1__93_left_grid_pin_19_ ; +wire [0:0] cby_1__1__93_left_grid_pin_20_ ; +wire [0:0] cby_1__1__93_left_grid_pin_21_ ; +wire [0:0] cby_1__1__93_left_grid_pin_22_ ; +wire [0:0] cby_1__1__93_left_grid_pin_23_ ; +wire [0:0] cby_1__1__93_left_grid_pin_24_ ; +wire [0:0] cby_1__1__93_left_grid_pin_25_ ; +wire [0:0] cby_1__1__93_left_grid_pin_26_ ; +wire [0:0] cby_1__1__93_left_grid_pin_27_ ; +wire [0:0] cby_1__1__93_left_grid_pin_28_ ; +wire [0:0] cby_1__1__93_left_grid_pin_29_ ; +wire [0:0] cby_1__1__93_left_grid_pin_30_ ; +wire [0:0] cby_1__1__93_left_grid_pin_31_ ; +wire [0:0] cby_1__1__94_ccff_tail ; +wire [0:29] cby_1__1__94_chany_bottom_out ; +wire [0:29] cby_1__1__94_chany_top_out ; +wire [0:0] cby_1__1__94_left_grid_pin_16_ ; +wire [0:0] cby_1__1__94_left_grid_pin_17_ ; +wire [0:0] cby_1__1__94_left_grid_pin_18_ ; +wire [0:0] cby_1__1__94_left_grid_pin_19_ ; +wire [0:0] cby_1__1__94_left_grid_pin_20_ ; +wire [0:0] cby_1__1__94_left_grid_pin_21_ ; +wire [0:0] cby_1__1__94_left_grid_pin_22_ ; +wire [0:0] cby_1__1__94_left_grid_pin_23_ ; +wire [0:0] cby_1__1__94_left_grid_pin_24_ ; +wire [0:0] cby_1__1__94_left_grid_pin_25_ ; +wire [0:0] cby_1__1__94_left_grid_pin_26_ ; +wire [0:0] cby_1__1__94_left_grid_pin_27_ ; +wire [0:0] cby_1__1__94_left_grid_pin_28_ ; +wire [0:0] cby_1__1__94_left_grid_pin_29_ ; +wire [0:0] cby_1__1__94_left_grid_pin_30_ ; +wire [0:0] cby_1__1__94_left_grid_pin_31_ ; +wire [0:0] cby_1__1__95_ccff_tail ; +wire [0:29] cby_1__1__95_chany_bottom_out ; +wire [0:29] cby_1__1__95_chany_top_out ; +wire [0:0] cby_1__1__95_left_grid_pin_16_ ; +wire [0:0] cby_1__1__95_left_grid_pin_17_ ; +wire [0:0] cby_1__1__95_left_grid_pin_18_ ; +wire [0:0] cby_1__1__95_left_grid_pin_19_ ; +wire [0:0] cby_1__1__95_left_grid_pin_20_ ; +wire [0:0] cby_1__1__95_left_grid_pin_21_ ; +wire [0:0] cby_1__1__95_left_grid_pin_22_ ; +wire [0:0] cby_1__1__95_left_grid_pin_23_ ; +wire [0:0] cby_1__1__95_left_grid_pin_24_ ; +wire [0:0] cby_1__1__95_left_grid_pin_25_ ; +wire [0:0] cby_1__1__95_left_grid_pin_26_ ; +wire [0:0] cby_1__1__95_left_grid_pin_27_ ; +wire [0:0] cby_1__1__95_left_grid_pin_28_ ; +wire [0:0] cby_1__1__95_left_grid_pin_29_ ; +wire [0:0] cby_1__1__95_left_grid_pin_30_ ; +wire [0:0] cby_1__1__95_left_grid_pin_31_ ; +wire [0:0] cby_1__1__96_ccff_tail ; +wire [0:29] cby_1__1__96_chany_bottom_out ; +wire [0:29] cby_1__1__96_chany_top_out ; +wire [0:0] cby_1__1__96_left_grid_pin_16_ ; +wire [0:0] cby_1__1__96_left_grid_pin_17_ ; +wire [0:0] cby_1__1__96_left_grid_pin_18_ ; +wire [0:0] cby_1__1__96_left_grid_pin_19_ ; +wire [0:0] cby_1__1__96_left_grid_pin_20_ ; +wire [0:0] cby_1__1__96_left_grid_pin_21_ ; +wire [0:0] cby_1__1__96_left_grid_pin_22_ ; +wire [0:0] cby_1__1__96_left_grid_pin_23_ ; +wire [0:0] cby_1__1__96_left_grid_pin_24_ ; +wire [0:0] cby_1__1__96_left_grid_pin_25_ ; +wire [0:0] cby_1__1__96_left_grid_pin_26_ ; +wire [0:0] cby_1__1__96_left_grid_pin_27_ ; +wire [0:0] cby_1__1__96_left_grid_pin_28_ ; +wire [0:0] cby_1__1__96_left_grid_pin_29_ ; +wire [0:0] cby_1__1__96_left_grid_pin_30_ ; +wire [0:0] cby_1__1__96_left_grid_pin_31_ ; +wire [0:0] cby_1__1__97_ccff_tail ; +wire [0:29] cby_1__1__97_chany_bottom_out ; +wire [0:29] cby_1__1__97_chany_top_out ; +wire [0:0] cby_1__1__97_left_grid_pin_16_ ; +wire [0:0] cby_1__1__97_left_grid_pin_17_ ; +wire [0:0] cby_1__1__97_left_grid_pin_18_ ; +wire [0:0] cby_1__1__97_left_grid_pin_19_ ; +wire [0:0] cby_1__1__97_left_grid_pin_20_ ; +wire [0:0] cby_1__1__97_left_grid_pin_21_ ; +wire [0:0] cby_1__1__97_left_grid_pin_22_ ; +wire [0:0] cby_1__1__97_left_grid_pin_23_ ; +wire [0:0] cby_1__1__97_left_grid_pin_24_ ; +wire [0:0] cby_1__1__97_left_grid_pin_25_ ; +wire [0:0] cby_1__1__97_left_grid_pin_26_ ; +wire [0:0] cby_1__1__97_left_grid_pin_27_ ; +wire [0:0] cby_1__1__97_left_grid_pin_28_ ; +wire [0:0] cby_1__1__97_left_grid_pin_29_ ; +wire [0:0] cby_1__1__97_left_grid_pin_30_ ; +wire [0:0] cby_1__1__97_left_grid_pin_31_ ; +wire [0:0] cby_1__1__98_ccff_tail ; +wire [0:29] cby_1__1__98_chany_bottom_out ; +wire [0:29] cby_1__1__98_chany_top_out ; +wire [0:0] cby_1__1__98_left_grid_pin_16_ ; +wire [0:0] cby_1__1__98_left_grid_pin_17_ ; +wire [0:0] cby_1__1__98_left_grid_pin_18_ ; +wire [0:0] cby_1__1__98_left_grid_pin_19_ ; +wire [0:0] cby_1__1__98_left_grid_pin_20_ ; +wire [0:0] cby_1__1__98_left_grid_pin_21_ ; +wire [0:0] cby_1__1__98_left_grid_pin_22_ ; +wire [0:0] cby_1__1__98_left_grid_pin_23_ ; +wire [0:0] cby_1__1__98_left_grid_pin_24_ ; +wire [0:0] cby_1__1__98_left_grid_pin_25_ ; +wire [0:0] cby_1__1__98_left_grid_pin_26_ ; +wire [0:0] cby_1__1__98_left_grid_pin_27_ ; +wire [0:0] cby_1__1__98_left_grid_pin_28_ ; +wire [0:0] cby_1__1__98_left_grid_pin_29_ ; +wire [0:0] cby_1__1__98_left_grid_pin_30_ ; +wire [0:0] cby_1__1__98_left_grid_pin_31_ ; +wire [0:0] cby_1__1__99_ccff_tail ; +wire [0:29] cby_1__1__99_chany_bottom_out ; +wire [0:29] cby_1__1__99_chany_top_out ; +wire [0:0] cby_1__1__99_left_grid_pin_16_ ; +wire [0:0] cby_1__1__99_left_grid_pin_17_ ; +wire [0:0] cby_1__1__99_left_grid_pin_18_ ; +wire [0:0] cby_1__1__99_left_grid_pin_19_ ; +wire [0:0] cby_1__1__99_left_grid_pin_20_ ; +wire [0:0] cby_1__1__99_left_grid_pin_21_ ; +wire [0:0] cby_1__1__99_left_grid_pin_22_ ; +wire [0:0] cby_1__1__99_left_grid_pin_23_ ; +wire [0:0] cby_1__1__99_left_grid_pin_24_ ; +wire [0:0] cby_1__1__99_left_grid_pin_25_ ; +wire [0:0] cby_1__1__99_left_grid_pin_26_ ; +wire [0:0] cby_1__1__99_left_grid_pin_27_ ; +wire [0:0] cby_1__1__99_left_grid_pin_28_ ; +wire [0:0] cby_1__1__99_left_grid_pin_29_ ; +wire [0:0] cby_1__1__99_left_grid_pin_30_ ; +wire [0:0] cby_1__1__99_left_grid_pin_31_ ; +wire [0:0] cby_1__1__9_ccff_tail ; +wire [0:29] cby_1__1__9_chany_bottom_out ; +wire [0:29] cby_1__1__9_chany_top_out ; +wire [0:0] cby_1__1__9_left_grid_pin_16_ ; +wire [0:0] cby_1__1__9_left_grid_pin_17_ ; +wire [0:0] cby_1__1__9_left_grid_pin_18_ ; +wire [0:0] cby_1__1__9_left_grid_pin_19_ ; +wire [0:0] cby_1__1__9_left_grid_pin_20_ ; +wire [0:0] cby_1__1__9_left_grid_pin_21_ ; +wire [0:0] cby_1__1__9_left_grid_pin_22_ ; +wire [0:0] cby_1__1__9_left_grid_pin_23_ ; +wire [0:0] cby_1__1__9_left_grid_pin_24_ ; +wire [0:0] cby_1__1__9_left_grid_pin_25_ ; +wire [0:0] cby_1__1__9_left_grid_pin_26_ ; +wire [0:0] cby_1__1__9_left_grid_pin_27_ ; +wire [0:0] cby_1__1__9_left_grid_pin_28_ ; +wire [0:0] cby_1__1__9_left_grid_pin_29_ ; +wire [0:0] cby_1__1__9_left_grid_pin_30_ ; +wire [0:0] cby_1__1__9_left_grid_pin_31_ ; +wire [0:0] direct_interc_0_out ; +wire [0:0] direct_interc_100_out ; +wire [0:0] direct_interc_101_out ; +wire [0:0] direct_interc_102_out ; +wire [0:0] direct_interc_103_out ; +wire [0:0] direct_interc_104_out ; +wire [0:0] direct_interc_105_out ; +wire [0:0] direct_interc_106_out ; +wire [0:0] direct_interc_107_out ; +wire [0:0] direct_interc_108_out ; +wire [0:0] direct_interc_109_out ; +wire [0:0] direct_interc_10_out ; +wire [0:0] direct_interc_110_out ; +wire [0:0] direct_interc_111_out ; +wire [0:0] direct_interc_112_out ; +wire [0:0] direct_interc_113_out ; +wire [0:0] direct_interc_114_out ; +wire [0:0] direct_interc_115_out ; +wire [0:0] direct_interc_116_out ; +wire [0:0] direct_interc_117_out ; +wire [0:0] direct_interc_118_out ; +wire [0:0] direct_interc_119_out ; +wire [0:0] direct_interc_11_out ; +wire [0:0] direct_interc_120_out ; +wire [0:0] direct_interc_121_out ; +wire [0:0] direct_interc_122_out ; +wire [0:0] direct_interc_123_out ; +wire [0:0] direct_interc_124_out ; +wire [0:0] direct_interc_125_out ; +wire [0:0] direct_interc_126_out ; +wire [0:0] direct_interc_127_out ; +wire [0:0] direct_interc_128_out ; +wire [0:0] direct_interc_129_out ; +wire [0:0] direct_interc_12_out ; +wire [0:0] direct_interc_130_out ; +wire [0:0] direct_interc_131_out ; +wire [0:0] direct_interc_132_out ; +wire [0:0] direct_interc_133_out ; +wire [0:0] direct_interc_134_out ; +wire [0:0] direct_interc_135_out ; +wire [0:0] direct_interc_136_out ; +wire [0:0] direct_interc_137_out ; +wire [0:0] direct_interc_138_out ; +wire [0:0] direct_interc_139_out ; +wire [0:0] direct_interc_13_out ; +wire [0:0] direct_interc_140_out ; +wire [0:0] direct_interc_141_out ; +wire [0:0] direct_interc_142_out ; +wire [0:0] direct_interc_143_out ; +wire [0:0] direct_interc_144_out ; +wire [0:0] direct_interc_145_out ; +wire [0:0] direct_interc_146_out ; +wire [0:0] direct_interc_147_out ; +wire [0:0] direct_interc_148_out ; +wire [0:0] direct_interc_149_out ; +wire [0:0] direct_interc_14_out ; +wire [0:0] direct_interc_150_out ; +wire [0:0] direct_interc_151_out ; +wire [0:0] direct_interc_152_out ; +wire [0:0] direct_interc_153_out ; +wire [0:0] direct_interc_154_out ; +wire [0:0] direct_interc_155_out ; +wire [0:0] direct_interc_156_out ; +wire [0:0] direct_interc_157_out ; +wire [0:0] direct_interc_158_out ; +wire [0:0] direct_interc_159_out ; +wire [0:0] direct_interc_15_out ; +wire [0:0] direct_interc_160_out ; +wire [0:0] direct_interc_161_out ; +wire [0:0] direct_interc_162_out ; +wire [0:0] direct_interc_163_out ; +wire [0:0] direct_interc_164_out ; +wire [0:0] direct_interc_165_out ; +wire [0:0] direct_interc_166_out ; +wire [0:0] direct_interc_167_out ; +wire [0:0] direct_interc_168_out ; +wire [0:0] direct_interc_169_out ; +wire [0:0] direct_interc_16_out ; +wire [0:0] direct_interc_170_out ; +wire [0:0] direct_interc_171_out ; +wire [0:0] direct_interc_172_out ; +wire [0:0] direct_interc_173_out ; +wire [0:0] direct_interc_174_out ; +wire [0:0] direct_interc_175_out ; +wire [0:0] direct_interc_176_out ; +wire [0:0] direct_interc_177_out ; +wire [0:0] direct_interc_178_out ; +wire [0:0] direct_interc_179_out ; +wire [0:0] direct_interc_17_out ; +wire [0:0] direct_interc_180_out ; +wire [0:0] direct_interc_181_out ; +wire [0:0] direct_interc_182_out ; +wire [0:0] direct_interc_183_out ; +wire [0:0] direct_interc_184_out ; +wire [0:0] direct_interc_185_out ; +wire [0:0] direct_interc_186_out ; +wire [0:0] direct_interc_187_out ; +wire [0:0] direct_interc_188_out ; +wire [0:0] direct_interc_189_out ; +wire [0:0] direct_interc_18_out ; +wire [0:0] direct_interc_190_out ; +wire [0:0] direct_interc_191_out ; +wire [0:0] direct_interc_192_out ; +wire [0:0] direct_interc_193_out ; +wire [0:0] direct_interc_194_out ; +wire [0:0] direct_interc_195_out ; +wire [0:0] direct_interc_196_out ; +wire [0:0] direct_interc_197_out ; +wire [0:0] direct_interc_198_out ; +wire [0:0] direct_interc_199_out ; +wire [0:0] direct_interc_19_out ; +wire [0:0] direct_interc_1_out ; +wire [0:0] direct_interc_200_out ; +wire [0:0] direct_interc_201_out ; +wire [0:0] direct_interc_202_out ; +wire [0:0] direct_interc_203_out ; +wire [0:0] direct_interc_204_out ; +wire [0:0] direct_interc_205_out ; +wire [0:0] direct_interc_206_out ; +wire [0:0] direct_interc_207_out ; +wire [0:0] direct_interc_208_out ; +wire [0:0] direct_interc_209_out ; +wire [0:0] direct_interc_20_out ; +wire [0:0] direct_interc_210_out ; +wire [0:0] direct_interc_211_out ; +wire [0:0] direct_interc_212_out ; +wire [0:0] direct_interc_213_out ; +wire [0:0] direct_interc_214_out ; +wire [0:0] direct_interc_215_out ; +wire [0:0] direct_interc_216_out ; +wire [0:0] direct_interc_217_out ; +wire [0:0] direct_interc_218_out ; +wire [0:0] direct_interc_219_out ; +wire [0:0] direct_interc_21_out ; +wire [0:0] direct_interc_220_out ; +wire [0:0] direct_interc_221_out ; +wire [0:0] direct_interc_222_out ; +wire [0:0] direct_interc_223_out ; +wire [0:0] direct_interc_224_out ; +wire [0:0] direct_interc_225_out ; +wire [0:0] direct_interc_226_out ; +wire [0:0] direct_interc_227_out ; +wire [0:0] direct_interc_228_out ; +wire [0:0] direct_interc_229_out ; +wire [0:0] direct_interc_22_out ; +wire [0:0] direct_interc_230_out ; +wire [0:0] direct_interc_231_out ; +wire [0:0] direct_interc_232_out ; +wire [0:0] direct_interc_233_out ; +wire [0:0] direct_interc_234_out ; +wire [0:0] direct_interc_235_out ; +wire [0:0] direct_interc_236_out ; +wire [0:0] direct_interc_237_out ; +wire [0:0] direct_interc_238_out ; +wire [0:0] direct_interc_239_out ; +wire [0:0] direct_interc_23_out ; +wire [0:0] direct_interc_240_out ; +wire [0:0] direct_interc_241_out ; +wire [0:0] direct_interc_242_out ; +wire [0:0] direct_interc_243_out ; +wire [0:0] direct_interc_244_out ; +wire [0:0] direct_interc_245_out ; +wire [0:0] direct_interc_246_out ; +wire [0:0] direct_interc_247_out ; +wire [0:0] direct_interc_248_out ; +wire [0:0] direct_interc_249_out ; +wire [0:0] direct_interc_24_out ; +wire [0:0] direct_interc_250_out ; +wire [0:0] direct_interc_251_out ; +wire [0:0] direct_interc_252_out ; +wire [0:0] direct_interc_253_out ; +wire [0:0] direct_interc_254_out ; +wire [0:0] direct_interc_255_out ; +wire [0:0] direct_interc_256_out ; +wire [0:0] direct_interc_257_out ; +wire [0:0] direct_interc_258_out ; +wire [0:0] direct_interc_259_out ; +wire [0:0] direct_interc_25_out ; +wire [0:0] direct_interc_260_out ; +wire [0:0] direct_interc_261_out ; +wire [0:0] direct_interc_262_out ; +wire [0:0] direct_interc_263_out ; +wire [0:0] direct_interc_264_out ; +wire [0:0] direct_interc_265_out ; +wire [0:0] direct_interc_266_out ; +wire [0:0] direct_interc_267_out ; +wire [0:0] direct_interc_268_out ; +wire [0:0] direct_interc_269_out ; +wire [0:0] direct_interc_26_out ; +wire [0:0] direct_interc_270_out ; +wire [0:0] direct_interc_271_out ; +wire [0:0] direct_interc_272_out ; +wire [0:0] direct_interc_273_out ; +wire [0:0] direct_interc_274_out ; +wire [0:0] direct_interc_275_out ; +wire [0:0] direct_interc_276_out ; +wire [0:0] direct_interc_277_out ; +wire [0:0] direct_interc_278_out ; +wire [0:0] direct_interc_279_out ; +wire [0:0] direct_interc_27_out ; +wire [0:0] direct_interc_280_out ; +wire [0:0] direct_interc_281_out ; +wire [0:0] direct_interc_282_out ; +wire [0:0] direct_interc_283_out ; +wire [0:0] direct_interc_284_out ; +wire [0:0] direct_interc_285_out ; +wire [0:0] direct_interc_286_out ; +wire [0:0] direct_interc_287_out ; +wire [0:0] direct_interc_288_out ; +wire [0:0] direct_interc_289_out ; +wire [0:0] direct_interc_28_out ; +wire [0:0] direct_interc_290_out ; +wire [0:0] direct_interc_291_out ; +wire [0:0] direct_interc_292_out ; +wire [0:0] direct_interc_293_out ; +wire [0:0] direct_interc_294_out ; +wire [0:0] direct_interc_295_out ; +wire [0:0] direct_interc_296_out ; +wire [0:0] direct_interc_297_out ; +wire [0:0] direct_interc_298_out ; +wire [0:0] direct_interc_299_out ; +wire [0:0] direct_interc_29_out ; +wire [0:0] direct_interc_2_out ; +wire [0:0] direct_interc_300_out ; +wire [0:0] direct_interc_301_out ; +wire [0:0] direct_interc_302_out ; +wire [0:0] direct_interc_303_out ; +wire [0:0] direct_interc_304_out ; +wire [0:0] direct_interc_305_out ; +wire [0:0] direct_interc_306_out ; +wire [0:0] direct_interc_307_out ; +wire [0:0] direct_interc_308_out ; +wire [0:0] direct_interc_309_out ; +wire [0:0] direct_interc_30_out ; +wire [0:0] direct_interc_310_out ; +wire [0:0] direct_interc_311_out ; +wire [0:0] direct_interc_312_out ; +wire [0:0] direct_interc_313_out ; +wire [0:0] direct_interc_314_out ; +wire [0:0] direct_interc_315_out ; +wire [0:0] direct_interc_316_out ; +wire [0:0] direct_interc_317_out ; +wire [0:0] direct_interc_318_out ; +wire [0:0] direct_interc_319_out ; +wire [0:0] direct_interc_31_out ; +wire [0:0] direct_interc_320_out ; +wire [0:0] direct_interc_321_out ; +wire [0:0] direct_interc_322_out ; +wire [0:0] direct_interc_323_out ; +wire [0:0] direct_interc_324_out ; +wire [0:0] direct_interc_325_out ; +wire [0:0] direct_interc_326_out ; +wire [0:0] direct_interc_327_out ; +wire [0:0] direct_interc_328_out ; +wire [0:0] direct_interc_329_out ; +wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_330_out ; +wire [0:0] direct_interc_331_out ; +wire [0:0] direct_interc_332_out ; +wire [0:0] direct_interc_333_out ; +wire [0:0] direct_interc_334_out ; +wire [0:0] direct_interc_335_out ; +wire [0:0] direct_interc_336_out ; +wire [0:0] direct_interc_337_out ; +wire [0:0] direct_interc_338_out ; +wire [0:0] direct_interc_339_out ; +wire [0:0] direct_interc_33_out ; +wire [0:0] direct_interc_340_out ; +wire [0:0] direct_interc_341_out ; +wire [0:0] direct_interc_342_out ; +wire [0:0] direct_interc_343_out ; +wire [0:0] direct_interc_344_out ; +wire [0:0] direct_interc_345_out ; +wire [0:0] direct_interc_346_out ; +wire [0:0] direct_interc_347_out ; +wire [0:0] direct_interc_348_out ; +wire [0:0] direct_interc_349_out ; +wire [0:0] direct_interc_34_out ; +wire [0:0] direct_interc_350_out ; +wire [0:0] direct_interc_351_out ; +wire [0:0] direct_interc_352_out ; +wire [0:0] direct_interc_353_out ; +wire [0:0] direct_interc_354_out ; +wire [0:0] direct_interc_355_out ; +wire [0:0] direct_interc_356_out ; +wire [0:0] direct_interc_357_out ; +wire [0:0] direct_interc_358_out ; +wire [0:0] direct_interc_359_out ; +wire [0:0] direct_interc_35_out ; +wire [0:0] direct_interc_360_out ; +wire [0:0] direct_interc_361_out ; +wire [0:0] direct_interc_362_out ; +wire [0:0] direct_interc_363_out ; +wire [0:0] direct_interc_364_out ; +wire [0:0] direct_interc_365_out ; +wire [0:0] direct_interc_366_out ; +wire [0:0] direct_interc_367_out ; +wire [0:0] direct_interc_368_out ; +wire [0:0] direct_interc_369_out ; +wire [0:0] direct_interc_36_out ; +wire [0:0] direct_interc_370_out ; +wire [0:0] direct_interc_371_out ; +wire [0:0] direct_interc_372_out ; +wire [0:0] direct_interc_373_out ; +wire [0:0] direct_interc_374_out ; +wire [0:0] direct_interc_375_out ; +wire [0:0] direct_interc_376_out ; +wire [0:0] direct_interc_377_out ; +wire [0:0] direct_interc_378_out ; +wire [0:0] direct_interc_379_out ; +wire [0:0] direct_interc_37_out ; +wire [0:0] direct_interc_380_out ; +wire [0:0] direct_interc_381_out ; +wire [0:0] direct_interc_382_out ; +wire [0:0] direct_interc_383_out ; +wire [0:0] direct_interc_384_out ; +wire [0:0] direct_interc_385_out ; +wire [0:0] direct_interc_386_out ; +wire [0:0] direct_interc_387_out ; +wire [0:0] direct_interc_388_out ; +wire [0:0] direct_interc_389_out ; +wire [0:0] direct_interc_38_out ; +wire [0:0] direct_interc_390_out ; +wire [0:0] direct_interc_391_out ; +wire [0:0] direct_interc_392_out ; +wire [0:0] direct_interc_393_out ; +wire [0:0] direct_interc_394_out ; +wire [0:0] direct_interc_395_out ; +wire [0:0] direct_interc_396_out ; +wire [0:0] direct_interc_397_out ; +wire [0:0] direct_interc_398_out ; +wire [0:0] direct_interc_399_out ; +wire [0:0] direct_interc_39_out ; +wire [0:0] direct_interc_3_out ; +wire [0:0] direct_interc_400_out ; +wire [0:0] direct_interc_401_out ; +wire [0:0] direct_interc_402_out ; +wire [0:0] direct_interc_403_out ; +wire [0:0] direct_interc_404_out ; +wire [0:0] direct_interc_405_out ; +wire [0:0] direct_interc_406_out ; +wire [0:0] direct_interc_40_out ; +wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_42_out ; +wire [0:0] direct_interc_43_out ; +wire [0:0] direct_interc_44_out ; +wire [0:0] direct_interc_45_out ; +wire [0:0] direct_interc_46_out ; +wire [0:0] direct_interc_47_out ; +wire [0:0] direct_interc_48_out ; +wire [0:0] direct_interc_49_out ; +wire [0:0] direct_interc_4_out ; +wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_51_out ; +wire [0:0] direct_interc_52_out ; +wire [0:0] direct_interc_53_out ; +wire [0:0] direct_interc_54_out ; +wire [0:0] direct_interc_55_out ; +wire [0:0] direct_interc_56_out ; +wire [0:0] direct_interc_57_out ; +wire [0:0] direct_interc_58_out ; +wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_60_out ; +wire [0:0] direct_interc_61_out ; +wire [0:0] direct_interc_62_out ; +wire [0:0] direct_interc_63_out ; +wire [0:0] direct_interc_64_out ; +wire [0:0] direct_interc_65_out ; +wire [0:0] direct_interc_66_out ; +wire [0:0] direct_interc_67_out ; +wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_69_out ; +wire [0:0] direct_interc_6_out ; +wire [0:0] direct_interc_70_out ; +wire [0:0] direct_interc_71_out ; +wire [0:0] direct_interc_72_out ; +wire [0:0] direct_interc_73_out ; +wire [0:0] direct_interc_74_out ; +wire [0:0] direct_interc_75_out ; +wire [0:0] direct_interc_76_out ; +wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_78_out ; +wire [0:0] direct_interc_79_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] direct_interc_80_out ; +wire [0:0] direct_interc_81_out ; +wire [0:0] direct_interc_82_out ; +wire [0:0] direct_interc_83_out ; +wire [0:0] direct_interc_84_out ; +wire [0:0] direct_interc_85_out ; +wire [0:0] direct_interc_86_out ; +wire [0:0] direct_interc_87_out ; +wire [0:0] direct_interc_88_out ; +wire [0:0] direct_interc_89_out ; +wire [0:0] direct_interc_8_out ; +wire [0:0] direct_interc_90_out ; +wire [0:0] direct_interc_91_out ; +wire [0:0] direct_interc_92_out ; +wire [0:0] direct_interc_93_out ; +wire [0:0] direct_interc_94_out ; +wire [0:0] direct_interc_95_out ; +wire [0:0] direct_interc_96_out ; +wire [0:0] direct_interc_97_out ; +wire [0:0] direct_interc_98_out ; +wire [0:0] direct_interc_99_out ; +wire [0:0] direct_interc_9_out ; +wire [0:0] grid_clb_0_ccff_tail ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_100_ccff_tail ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_101_ccff_tail ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_102_ccff_tail ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_103_ccff_tail ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_104_ccff_tail ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_105_ccff_tail ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_106_ccff_tail ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_107_ccff_tail ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_108_ccff_tail ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_109_ccff_tail ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_10_ccff_tail ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_110_ccff_tail ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_111_ccff_tail ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_112_ccff_tail ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_113_ccff_tail ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_114_ccff_tail ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_115_ccff_tail ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_116_ccff_tail ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_117_ccff_tail ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_118_ccff_tail ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_119_ccff_tail ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_11_ccff_tail ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_120_ccff_tail ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_121_ccff_tail ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_122_ccff_tail ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_123_ccff_tail ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_124_ccff_tail ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_125_ccff_tail ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_126_ccff_tail ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_127_ccff_tail ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_128_ccff_tail ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_129_ccff_tail ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_53_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_12_ccff_tail ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_130_ccff_tail ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_131_ccff_tail ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_132_ccff_tail ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_133_ccff_tail ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_134_ccff_tail ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_135_ccff_tail ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_136_ccff_tail ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_137_ccff_tail ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_138_ccff_tail ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_139_ccff_tail ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_13_ccff_tail ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_140_ccff_tail ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_141_ccff_tail ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_142_ccff_tail ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_143_ccff_tail ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_14_ccff_tail ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_15_ccff_tail ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_16_ccff_tail ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_17_ccff_tail ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_18_ccff_tail ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_19_ccff_tail ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_33_ ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_1_ccff_tail ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_20_ccff_tail ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_21_ccff_tail ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_22_ccff_tail ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_23_ccff_tail ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_24_ccff_tail ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_25_ccff_tail ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_26_ccff_tail ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_27_ccff_tail ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_28_ccff_tail ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_29_ccff_tail ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_2_ccff_tail ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_30_ccff_tail ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_31_ccff_tail ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_32_ccff_tail ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_33_ccff_tail ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_34_ccff_tail ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_35_ccff_tail ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_36_ccff_tail ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_37_ccff_tail ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_38_ccff_tail ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_39_ccff_tail ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_3_ccff_tail ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_40_ccff_tail ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_41_ccff_tail ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_42_ccff_tail ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_43_ccff_tail ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_44_ccff_tail ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_45_ccff_tail ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_46_ccff_tail ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_47_ccff_tail ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_48_ccff_tail ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_49_ccff_tail ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_4_ccff_tail ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_50_ccff_tail ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_51_ccff_tail ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_52_ccff_tail ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_53_ccff_tail ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_54_ccff_tail ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_55_ccff_tail ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_56_ccff_tail ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_57_ccff_tail ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_58_ccff_tail ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_59_ccff_tail ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_5_ccff_tail ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_60_ccff_tail ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_61_ccff_tail ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_62_ccff_tail ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_63_ccff_tail ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_64_ccff_tail ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_65_ccff_tail ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_66_ccff_tail ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_67_ccff_tail ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_68_ccff_tail ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_69_ccff_tail ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_6_ccff_tail ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_70_ccff_tail ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_71_ccff_tail ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_72_ccff_tail ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_73_ccff_tail ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_74_ccff_tail ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_75_ccff_tail ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_76_ccff_tail ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_77_ccff_tail ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_78_ccff_tail ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_79_ccff_tail ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_7_ccff_tail ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_80_ccff_tail ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_81_ccff_tail ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_82_ccff_tail ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_83_ccff_tail ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_84_ccff_tail ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_85_ccff_tail ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_86_ccff_tail ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_87_ccff_tail ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_88_ccff_tail ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_89_ccff_tail ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_8_ccff_tail ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_90_ccff_tail ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_91_ccff_tail ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_92_ccff_tail ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_93_ccff_tail ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_94_ccff_tail ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_95_ccff_tail ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_96_ccff_tail ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_97_ccff_tail ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_98_ccff_tail ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_99_ccff_tail ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_9_ccff_tail ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_10_ccff_tail ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_11_ccff_tail ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_2_ccff_tail ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_3_ccff_tail ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_4_ccff_tail ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_5_ccff_tail ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_6_ccff_tail ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_7_ccff_tail ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_8_ccff_tail ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_9_ccff_tail ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_left_0_ccff_tail ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_10_ccff_tail ; +wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_11_ccff_tail ; +wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_1_ccff_tail ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_2_ccff_tail ; +wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_3_ccff_tail ; +wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_4_ccff_tail ; +wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_5_ccff_tail ; +wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_6_ccff_tail ; +wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_7_ccff_tail ; +wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_8_ccff_tail ; +wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_9_ccff_tail ; +wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_0_ccff_tail ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_10_ccff_tail ; +wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_11_ccff_tail ; +wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_1_ccff_tail ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_2_ccff_tail ; +wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_3_ccff_tail ; +wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_4_ccff_tail ; +wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_5_ccff_tail ; +wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_6_ccff_tail ; +wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_7_ccff_tail ; +wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_8_ccff_tail ; +wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_9_ccff_tail ; +wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_ccff_tail ; +wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_10_ccff_tail ; +wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_11_ccff_tail ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_1_ccff_tail ; +wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_2_ccff_tail ; +wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_3_ccff_tail ; +wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_4_ccff_tail ; +wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_5_ccff_tail ; +wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_6_ccff_tail ; +wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_7_ccff_tail ; +wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_8_ccff_tail ; +wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_9_ccff_tail ; +wire [0:29] sb_0__0__0_chanx_right_out ; +wire [0:29] sb_0__0__0_chany_top_out ; +wire [0:0] sb_0__12__0_ccff_tail ; +wire [0:29] sb_0__12__0_chanx_right_out ; +wire [0:29] sb_0__12__0_chany_bottom_out ; +wire [0:0] sb_0__1__0_ccff_tail ; +wire [0:29] sb_0__1__0_chanx_right_out ; +wire [0:29] sb_0__1__0_chany_bottom_out ; +wire [0:29] sb_0__1__0_chany_top_out ; +wire [0:0] sb_0__1__10_ccff_tail ; +wire [0:29] sb_0__1__10_chanx_right_out ; +wire [0:29] sb_0__1__10_chany_bottom_out ; +wire [0:29] sb_0__1__10_chany_top_out ; +wire [0:0] sb_0__1__1_ccff_tail ; +wire [0:29] sb_0__1__1_chanx_right_out ; +wire [0:29] sb_0__1__1_chany_bottom_out ; +wire [0:29] sb_0__1__1_chany_top_out ; +wire [0:0] sb_0__1__2_ccff_tail ; +wire [0:29] sb_0__1__2_chanx_right_out ; +wire [0:29] sb_0__1__2_chany_bottom_out ; +wire [0:29] sb_0__1__2_chany_top_out ; +wire [0:0] sb_0__1__3_ccff_tail ; +wire [0:29] sb_0__1__3_chanx_right_out ; +wire [0:29] sb_0__1__3_chany_bottom_out ; +wire [0:29] sb_0__1__3_chany_top_out ; +wire [0:0] sb_0__1__4_ccff_tail ; +wire [0:29] sb_0__1__4_chanx_right_out ; +wire [0:29] sb_0__1__4_chany_bottom_out ; +wire [0:29] sb_0__1__4_chany_top_out ; +wire [0:0] sb_0__1__5_ccff_tail ; +wire [0:29] sb_0__1__5_chanx_right_out ; +wire [0:29] sb_0__1__5_chany_bottom_out ; +wire [0:29] sb_0__1__5_chany_top_out ; +wire [0:0] sb_0__1__6_ccff_tail ; +wire [0:29] sb_0__1__6_chanx_right_out ; +wire [0:29] sb_0__1__6_chany_bottom_out ; +wire [0:29] sb_0__1__6_chany_top_out ; +wire [0:0] sb_0__1__7_ccff_tail ; +wire [0:29] sb_0__1__7_chanx_right_out ; +wire [0:29] sb_0__1__7_chany_bottom_out ; +wire [0:29] sb_0__1__7_chany_top_out ; +wire [0:0] sb_0__1__8_ccff_tail ; +wire [0:29] sb_0__1__8_chanx_right_out ; +wire [0:29] sb_0__1__8_chany_bottom_out ; +wire [0:29] sb_0__1__8_chany_top_out ; +wire [0:0] sb_0__1__9_ccff_tail ; +wire [0:29] sb_0__1__9_chanx_right_out ; +wire [0:29] sb_0__1__9_chany_bottom_out ; +wire [0:29] sb_0__1__9_chany_top_out ; +wire [0:0] sb_12__0__0_ccff_tail ; +wire [0:29] sb_12__0__0_chanx_left_out ; +wire [0:29] sb_12__0__0_chany_top_out ; +wire [0:0] sb_12__12__0_ccff_tail ; +wire [0:29] sb_12__12__0_chanx_left_out ; +wire [0:29] sb_12__12__0_chany_bottom_out ; +wire [0:0] sb_12__1__0_ccff_tail ; +wire [0:29] sb_12__1__0_chanx_left_out ; +wire [0:29] sb_12__1__0_chany_bottom_out ; +wire [0:29] sb_12__1__0_chany_top_out ; +wire [0:0] sb_12__1__10_ccff_tail ; +wire [0:29] sb_12__1__10_chanx_left_out ; +wire [0:29] sb_12__1__10_chany_bottom_out ; +wire [0:29] sb_12__1__10_chany_top_out ; +wire [0:0] sb_12__1__1_ccff_tail ; +wire [0:29] sb_12__1__1_chanx_left_out ; +wire [0:29] sb_12__1__1_chany_bottom_out ; +wire [0:29] sb_12__1__1_chany_top_out ; +wire [0:0] sb_12__1__2_ccff_tail ; +wire [0:29] sb_12__1__2_chanx_left_out ; +wire [0:29] sb_12__1__2_chany_bottom_out ; +wire [0:29] sb_12__1__2_chany_top_out ; +wire [0:0] sb_12__1__3_ccff_tail ; +wire [0:29] sb_12__1__3_chanx_left_out ; +wire [0:29] sb_12__1__3_chany_bottom_out ; +wire [0:29] sb_12__1__3_chany_top_out ; +wire [0:0] sb_12__1__4_ccff_tail ; +wire [0:29] sb_12__1__4_chanx_left_out ; +wire [0:29] sb_12__1__4_chany_bottom_out ; +wire [0:29] sb_12__1__4_chany_top_out ; +wire [0:0] sb_12__1__5_ccff_tail ; +wire [0:29] sb_12__1__5_chanx_left_out ; +wire [0:29] sb_12__1__5_chany_bottom_out ; +wire [0:29] sb_12__1__5_chany_top_out ; +wire [0:0] sb_12__1__6_ccff_tail ; +wire [0:29] sb_12__1__6_chanx_left_out ; +wire [0:29] sb_12__1__6_chany_bottom_out ; +wire [0:29] sb_12__1__6_chany_top_out ; +wire [0:0] sb_12__1__7_ccff_tail ; +wire [0:29] sb_12__1__7_chanx_left_out ; +wire [0:29] sb_12__1__7_chany_bottom_out ; +wire [0:29] sb_12__1__7_chany_top_out ; +wire [0:0] sb_12__1__8_ccff_tail ; +wire [0:29] sb_12__1__8_chanx_left_out ; +wire [0:29] sb_12__1__8_chany_bottom_out ; +wire [0:29] sb_12__1__8_chany_top_out ; +wire [0:0] sb_12__1__9_ccff_tail ; +wire [0:29] sb_12__1__9_chanx_left_out ; +wire [0:29] sb_12__1__9_chany_bottom_out ; +wire [0:29] sb_12__1__9_chany_top_out ; +wire [0:0] sb_1__0__0_ccff_tail ; +wire [0:29] sb_1__0__0_chanx_left_out ; +wire [0:29] sb_1__0__0_chanx_right_out ; +wire [0:29] sb_1__0__0_chany_top_out ; +wire [0:0] sb_1__0__10_ccff_tail ; +wire [0:29] sb_1__0__10_chanx_left_out ; +wire [0:29] sb_1__0__10_chanx_right_out ; +wire [0:29] sb_1__0__10_chany_top_out ; +wire [0:0] sb_1__0__1_ccff_tail ; +wire [0:29] sb_1__0__1_chanx_left_out ; +wire [0:29] sb_1__0__1_chanx_right_out ; +wire [0:29] sb_1__0__1_chany_top_out ; +wire [0:0] sb_1__0__2_ccff_tail ; +wire [0:29] sb_1__0__2_chanx_left_out ; +wire [0:29] sb_1__0__2_chanx_right_out ; +wire [0:29] sb_1__0__2_chany_top_out ; +wire [0:0] sb_1__0__3_ccff_tail ; +wire [0:29] sb_1__0__3_chanx_left_out ; +wire [0:29] sb_1__0__3_chanx_right_out ; +wire [0:29] sb_1__0__3_chany_top_out ; +wire [0:0] sb_1__0__4_ccff_tail ; +wire [0:29] sb_1__0__4_chanx_left_out ; +wire [0:29] sb_1__0__4_chanx_right_out ; +wire [0:29] sb_1__0__4_chany_top_out ; +wire [0:0] sb_1__0__5_ccff_tail ; +wire [0:29] sb_1__0__5_chanx_left_out ; +wire [0:29] sb_1__0__5_chanx_right_out ; +wire [0:29] sb_1__0__5_chany_top_out ; +wire [0:0] sb_1__0__6_ccff_tail ; +wire [0:29] sb_1__0__6_chanx_left_out ; +wire [0:29] sb_1__0__6_chanx_right_out ; +wire [0:29] sb_1__0__6_chany_top_out ; +wire [0:0] sb_1__0__7_ccff_tail ; +wire [0:29] sb_1__0__7_chanx_left_out ; +wire [0:29] sb_1__0__7_chanx_right_out ; +wire [0:29] sb_1__0__7_chany_top_out ; +wire [0:0] sb_1__0__8_ccff_tail ; +wire [0:29] sb_1__0__8_chanx_left_out ; +wire [0:29] sb_1__0__8_chanx_right_out ; +wire [0:29] sb_1__0__8_chany_top_out ; +wire [0:0] sb_1__0__9_ccff_tail ; +wire [0:29] sb_1__0__9_chanx_left_out ; +wire [0:29] sb_1__0__9_chanx_right_out ; +wire [0:29] sb_1__0__9_chany_top_out ; +wire [0:0] sb_1__12__0_ccff_tail ; +wire [0:29] sb_1__12__0_chanx_left_out ; +wire [0:29] sb_1__12__0_chanx_right_out ; +wire [0:29] sb_1__12__0_chany_bottom_out ; +wire [0:0] sb_1__12__10_ccff_tail ; +wire [0:29] sb_1__12__10_chanx_left_out ; +wire [0:29] sb_1__12__10_chanx_right_out ; +wire [0:29] sb_1__12__10_chany_bottom_out ; +wire [0:0] sb_1__12__1_ccff_tail ; +wire [0:29] sb_1__12__1_chanx_left_out ; +wire [0:29] sb_1__12__1_chanx_right_out ; +wire [0:29] sb_1__12__1_chany_bottom_out ; +wire [0:0] sb_1__12__2_ccff_tail ; +wire [0:29] sb_1__12__2_chanx_left_out ; +wire [0:29] sb_1__12__2_chanx_right_out ; +wire [0:29] sb_1__12__2_chany_bottom_out ; +wire [0:0] sb_1__12__3_ccff_tail ; +wire [0:29] sb_1__12__3_chanx_left_out ; +wire [0:29] sb_1__12__3_chanx_right_out ; +wire [0:29] sb_1__12__3_chany_bottom_out ; +wire [0:0] sb_1__12__4_ccff_tail ; +wire [0:29] sb_1__12__4_chanx_left_out ; +wire [0:29] sb_1__12__4_chanx_right_out ; +wire [0:29] sb_1__12__4_chany_bottom_out ; +wire [0:0] sb_1__12__5_ccff_tail ; +wire [0:29] sb_1__12__5_chanx_left_out ; +wire [0:29] sb_1__12__5_chanx_right_out ; +wire [0:29] sb_1__12__5_chany_bottom_out ; +wire [0:0] sb_1__12__6_ccff_tail ; +wire [0:29] sb_1__12__6_chanx_left_out ; +wire [0:29] sb_1__12__6_chanx_right_out ; +wire [0:29] sb_1__12__6_chany_bottom_out ; +wire [0:0] sb_1__12__7_ccff_tail ; +wire [0:29] sb_1__12__7_chanx_left_out ; +wire [0:29] sb_1__12__7_chanx_right_out ; +wire [0:29] sb_1__12__7_chany_bottom_out ; +wire [0:0] sb_1__12__8_ccff_tail ; +wire [0:29] sb_1__12__8_chanx_left_out ; +wire [0:29] sb_1__12__8_chanx_right_out ; +wire [0:29] sb_1__12__8_chany_bottom_out ; +wire [0:0] sb_1__12__9_ccff_tail ; +wire [0:29] sb_1__12__9_chanx_left_out ; +wire [0:29] sb_1__12__9_chanx_right_out ; +wire [0:29] sb_1__12__9_chany_bottom_out ; +wire [0:0] sb_1__1__0_ccff_tail ; +wire [0:29] sb_1__1__0_chanx_left_out ; +wire [0:29] sb_1__1__0_chanx_right_out ; +wire [0:29] sb_1__1__0_chany_bottom_out ; +wire [0:29] sb_1__1__0_chany_top_out ; +wire [0:0] sb_1__1__100_ccff_tail ; +wire [0:29] sb_1__1__100_chanx_left_out ; +wire [0:29] sb_1__1__100_chanx_right_out ; +wire [0:29] sb_1__1__100_chany_bottom_out ; +wire [0:29] sb_1__1__100_chany_top_out ; +wire [0:0] sb_1__1__101_ccff_tail ; +wire [0:29] sb_1__1__101_chanx_left_out ; +wire [0:29] sb_1__1__101_chanx_right_out ; +wire [0:29] sb_1__1__101_chany_bottom_out ; +wire [0:29] sb_1__1__101_chany_top_out ; +wire [0:0] sb_1__1__102_ccff_tail ; +wire [0:29] sb_1__1__102_chanx_left_out ; +wire [0:29] sb_1__1__102_chanx_right_out ; +wire [0:29] sb_1__1__102_chany_bottom_out ; +wire [0:29] sb_1__1__102_chany_top_out ; +wire [0:0] sb_1__1__103_ccff_tail ; +wire [0:29] sb_1__1__103_chanx_left_out ; +wire [0:29] sb_1__1__103_chanx_right_out ; +wire [0:29] sb_1__1__103_chany_bottom_out ; +wire [0:29] sb_1__1__103_chany_top_out ; +wire [0:0] sb_1__1__104_ccff_tail ; +wire [0:29] sb_1__1__104_chanx_left_out ; +wire [0:29] sb_1__1__104_chanx_right_out ; +wire [0:29] sb_1__1__104_chany_bottom_out ; +wire [0:29] sb_1__1__104_chany_top_out ; +wire [0:0] sb_1__1__105_ccff_tail ; +wire [0:29] sb_1__1__105_chanx_left_out ; +wire [0:29] sb_1__1__105_chanx_right_out ; +wire [0:29] sb_1__1__105_chany_bottom_out ; +wire [0:29] sb_1__1__105_chany_top_out ; +wire [0:0] sb_1__1__106_ccff_tail ; +wire [0:29] sb_1__1__106_chanx_left_out ; +wire [0:29] sb_1__1__106_chanx_right_out ; +wire [0:29] sb_1__1__106_chany_bottom_out ; +wire [0:29] sb_1__1__106_chany_top_out ; +wire [0:0] sb_1__1__107_ccff_tail ; +wire [0:29] sb_1__1__107_chanx_left_out ; +wire [0:29] sb_1__1__107_chanx_right_out ; +wire [0:29] sb_1__1__107_chany_bottom_out ; +wire [0:29] sb_1__1__107_chany_top_out ; +wire [0:0] sb_1__1__108_ccff_tail ; +wire [0:29] sb_1__1__108_chanx_left_out ; +wire [0:29] sb_1__1__108_chanx_right_out ; +wire [0:29] sb_1__1__108_chany_bottom_out ; +wire [0:29] sb_1__1__108_chany_top_out ; +wire [0:0] sb_1__1__109_ccff_tail ; +wire [0:29] sb_1__1__109_chanx_left_out ; +wire [0:29] sb_1__1__109_chanx_right_out ; +wire [0:29] sb_1__1__109_chany_bottom_out ; +wire [0:29] sb_1__1__109_chany_top_out ; +wire [0:0] sb_1__1__10_ccff_tail ; +wire [0:29] sb_1__1__10_chanx_left_out ; +wire [0:29] sb_1__1__10_chanx_right_out ; +wire [0:29] sb_1__1__10_chany_bottom_out ; +wire [0:29] sb_1__1__10_chany_top_out ; +wire [0:0] sb_1__1__110_ccff_tail ; +wire [0:29] sb_1__1__110_chanx_left_out ; +wire [0:29] sb_1__1__110_chanx_right_out ; +wire [0:29] sb_1__1__110_chany_bottom_out ; +wire [0:29] sb_1__1__110_chany_top_out ; +wire [0:0] sb_1__1__111_ccff_tail ; +wire [0:29] sb_1__1__111_chanx_left_out ; +wire [0:29] sb_1__1__111_chanx_right_out ; +wire [0:29] sb_1__1__111_chany_bottom_out ; +wire [0:29] sb_1__1__111_chany_top_out ; +wire [0:0] sb_1__1__112_ccff_tail ; +wire [0:29] sb_1__1__112_chanx_left_out ; +wire [0:29] sb_1__1__112_chanx_right_out ; +wire [0:29] sb_1__1__112_chany_bottom_out ; +wire [0:29] sb_1__1__112_chany_top_out ; +wire [0:0] sb_1__1__113_ccff_tail ; +wire [0:29] sb_1__1__113_chanx_left_out ; +wire [0:29] sb_1__1__113_chanx_right_out ; +wire [0:29] sb_1__1__113_chany_bottom_out ; +wire [0:29] sb_1__1__113_chany_top_out ; +wire [0:0] sb_1__1__114_ccff_tail ; +wire [0:29] sb_1__1__114_chanx_left_out ; +wire [0:29] sb_1__1__114_chanx_right_out ; +wire [0:29] sb_1__1__114_chany_bottom_out ; +wire [0:29] sb_1__1__114_chany_top_out ; +wire [0:0] sb_1__1__115_ccff_tail ; +wire [0:29] sb_1__1__115_chanx_left_out ; +wire [0:29] sb_1__1__115_chanx_right_out ; +wire [0:29] sb_1__1__115_chany_bottom_out ; +wire [0:29] sb_1__1__115_chany_top_out ; +wire [0:0] sb_1__1__116_ccff_tail ; +wire [0:29] sb_1__1__116_chanx_left_out ; +wire [0:29] sb_1__1__116_chanx_right_out ; +wire [0:29] sb_1__1__116_chany_bottom_out ; +wire [0:29] sb_1__1__116_chany_top_out ; +wire [0:0] sb_1__1__117_ccff_tail ; +wire [0:29] sb_1__1__117_chanx_left_out ; +wire [0:29] sb_1__1__117_chanx_right_out ; +wire [0:29] sb_1__1__117_chany_bottom_out ; +wire [0:29] sb_1__1__117_chany_top_out ; +wire [0:0] sb_1__1__118_ccff_tail ; +wire [0:29] sb_1__1__118_chanx_left_out ; +wire [0:29] sb_1__1__118_chanx_right_out ; +wire [0:29] sb_1__1__118_chany_bottom_out ; +wire [0:29] sb_1__1__118_chany_top_out ; +wire [0:0] sb_1__1__119_ccff_tail ; +wire [0:29] sb_1__1__119_chanx_left_out ; +wire [0:29] sb_1__1__119_chanx_right_out ; +wire [0:29] sb_1__1__119_chany_bottom_out ; +wire [0:29] sb_1__1__119_chany_top_out ; +wire [0:0] sb_1__1__11_ccff_tail ; +wire [0:29] sb_1__1__11_chanx_left_out ; +wire [0:29] sb_1__1__11_chanx_right_out ; +wire [0:29] sb_1__1__11_chany_bottom_out ; +wire [0:29] sb_1__1__11_chany_top_out ; +wire [0:0] sb_1__1__120_ccff_tail ; +wire [0:29] sb_1__1__120_chanx_left_out ; +wire [0:29] sb_1__1__120_chanx_right_out ; +wire [0:29] sb_1__1__120_chany_bottom_out ; +wire [0:29] sb_1__1__120_chany_top_out ; +wire [0:0] sb_1__1__12_ccff_tail ; +wire [0:29] sb_1__1__12_chanx_left_out ; +wire [0:29] sb_1__1__12_chanx_right_out ; +wire [0:29] sb_1__1__12_chany_bottom_out ; +wire [0:29] sb_1__1__12_chany_top_out ; +wire [0:0] sb_1__1__13_ccff_tail ; +wire [0:29] sb_1__1__13_chanx_left_out ; +wire [0:29] sb_1__1__13_chanx_right_out ; +wire [0:29] sb_1__1__13_chany_bottom_out ; +wire [0:29] sb_1__1__13_chany_top_out ; +wire [0:0] sb_1__1__14_ccff_tail ; +wire [0:29] sb_1__1__14_chanx_left_out ; +wire [0:29] sb_1__1__14_chanx_right_out ; +wire [0:29] sb_1__1__14_chany_bottom_out ; +wire [0:29] sb_1__1__14_chany_top_out ; +wire [0:0] sb_1__1__15_ccff_tail ; +wire [0:29] sb_1__1__15_chanx_left_out ; +wire [0:29] sb_1__1__15_chanx_right_out ; +wire [0:29] sb_1__1__15_chany_bottom_out ; +wire [0:29] sb_1__1__15_chany_top_out ; +wire [0:0] sb_1__1__16_ccff_tail ; +wire [0:29] sb_1__1__16_chanx_left_out ; +wire [0:29] sb_1__1__16_chanx_right_out ; +wire [0:29] sb_1__1__16_chany_bottom_out ; +wire [0:29] sb_1__1__16_chany_top_out ; +wire [0:0] sb_1__1__17_ccff_tail ; +wire [0:29] sb_1__1__17_chanx_left_out ; +wire [0:29] sb_1__1__17_chanx_right_out ; +wire [0:29] sb_1__1__17_chany_bottom_out ; +wire [0:29] sb_1__1__17_chany_top_out ; +wire [0:0] sb_1__1__18_ccff_tail ; +wire [0:29] sb_1__1__18_chanx_left_out ; +wire [0:29] sb_1__1__18_chanx_right_out ; +wire [0:29] sb_1__1__18_chany_bottom_out ; +wire [0:29] sb_1__1__18_chany_top_out ; +wire [0:0] sb_1__1__19_ccff_tail ; +wire [0:29] sb_1__1__19_chanx_left_out ; +wire [0:29] sb_1__1__19_chanx_right_out ; +wire [0:29] sb_1__1__19_chany_bottom_out ; +wire [0:29] sb_1__1__19_chany_top_out ; +wire [0:0] sb_1__1__1_ccff_tail ; +wire [0:29] sb_1__1__1_chanx_left_out ; +wire [0:29] sb_1__1__1_chanx_right_out ; +wire [0:29] sb_1__1__1_chany_bottom_out ; +wire [0:29] sb_1__1__1_chany_top_out ; +wire [0:0] sb_1__1__20_ccff_tail ; +wire [0:29] sb_1__1__20_chanx_left_out ; +wire [0:29] sb_1__1__20_chanx_right_out ; +wire [0:29] sb_1__1__20_chany_bottom_out ; +wire [0:29] sb_1__1__20_chany_top_out ; +wire [0:0] sb_1__1__21_ccff_tail ; +wire [0:29] sb_1__1__21_chanx_left_out ; +wire [0:29] sb_1__1__21_chanx_right_out ; +wire [0:29] sb_1__1__21_chany_bottom_out ; +wire [0:29] sb_1__1__21_chany_top_out ; +wire [0:0] sb_1__1__22_ccff_tail ; +wire [0:29] sb_1__1__22_chanx_left_out ; +wire [0:29] sb_1__1__22_chanx_right_out ; +wire [0:29] sb_1__1__22_chany_bottom_out ; +wire [0:29] sb_1__1__22_chany_top_out ; +wire [0:0] sb_1__1__23_ccff_tail ; +wire [0:29] sb_1__1__23_chanx_left_out ; +wire [0:29] sb_1__1__23_chanx_right_out ; +wire [0:29] sb_1__1__23_chany_bottom_out ; +wire [0:29] sb_1__1__23_chany_top_out ; +wire [0:0] sb_1__1__24_ccff_tail ; +wire [0:29] sb_1__1__24_chanx_left_out ; +wire [0:29] sb_1__1__24_chanx_right_out ; +wire [0:29] sb_1__1__24_chany_bottom_out ; +wire [0:29] sb_1__1__24_chany_top_out ; +wire [0:0] sb_1__1__25_ccff_tail ; +wire [0:29] sb_1__1__25_chanx_left_out ; +wire [0:29] sb_1__1__25_chanx_right_out ; +wire [0:29] sb_1__1__25_chany_bottom_out ; +wire [0:29] sb_1__1__25_chany_top_out ; +wire [0:0] sb_1__1__26_ccff_tail ; +wire [0:29] sb_1__1__26_chanx_left_out ; +wire [0:29] sb_1__1__26_chanx_right_out ; +wire [0:29] sb_1__1__26_chany_bottom_out ; +wire [0:29] sb_1__1__26_chany_top_out ; +wire [0:0] sb_1__1__27_ccff_tail ; +wire [0:29] sb_1__1__27_chanx_left_out ; +wire [0:29] sb_1__1__27_chanx_right_out ; +wire [0:29] sb_1__1__27_chany_bottom_out ; +wire [0:29] sb_1__1__27_chany_top_out ; +wire [0:0] sb_1__1__28_ccff_tail ; +wire [0:29] sb_1__1__28_chanx_left_out ; +wire [0:29] sb_1__1__28_chanx_right_out ; +wire [0:29] sb_1__1__28_chany_bottom_out ; +wire [0:29] sb_1__1__28_chany_top_out ; +wire [0:0] sb_1__1__29_ccff_tail ; +wire [0:29] sb_1__1__29_chanx_left_out ; +wire [0:29] sb_1__1__29_chanx_right_out ; +wire [0:29] sb_1__1__29_chany_bottom_out ; +wire [0:29] sb_1__1__29_chany_top_out ; +wire [0:0] sb_1__1__2_ccff_tail ; +wire [0:29] sb_1__1__2_chanx_left_out ; +wire [0:29] sb_1__1__2_chanx_right_out ; +wire [0:29] sb_1__1__2_chany_bottom_out ; +wire [0:29] sb_1__1__2_chany_top_out ; +wire [0:0] sb_1__1__30_ccff_tail ; +wire [0:29] sb_1__1__30_chanx_left_out ; +wire [0:29] sb_1__1__30_chanx_right_out ; +wire [0:29] sb_1__1__30_chany_bottom_out ; +wire [0:29] sb_1__1__30_chany_top_out ; +wire [0:0] sb_1__1__31_ccff_tail ; +wire [0:29] sb_1__1__31_chanx_left_out ; +wire [0:29] sb_1__1__31_chanx_right_out ; +wire [0:29] sb_1__1__31_chany_bottom_out ; +wire [0:29] sb_1__1__31_chany_top_out ; +wire [0:0] sb_1__1__32_ccff_tail ; +wire [0:29] sb_1__1__32_chanx_left_out ; +wire [0:29] sb_1__1__32_chanx_right_out ; +wire [0:29] sb_1__1__32_chany_bottom_out ; +wire [0:29] sb_1__1__32_chany_top_out ; +wire [0:0] sb_1__1__33_ccff_tail ; +wire [0:29] sb_1__1__33_chanx_left_out ; +wire [0:29] sb_1__1__33_chanx_right_out ; +wire [0:29] sb_1__1__33_chany_bottom_out ; +wire [0:29] sb_1__1__33_chany_top_out ; +wire [0:0] sb_1__1__34_ccff_tail ; +wire [0:29] sb_1__1__34_chanx_left_out ; +wire [0:29] sb_1__1__34_chanx_right_out ; +wire [0:29] sb_1__1__34_chany_bottom_out ; +wire [0:29] sb_1__1__34_chany_top_out ; +wire [0:0] sb_1__1__35_ccff_tail ; +wire [0:29] sb_1__1__35_chanx_left_out ; +wire [0:29] sb_1__1__35_chanx_right_out ; +wire [0:29] sb_1__1__35_chany_bottom_out ; +wire [0:29] sb_1__1__35_chany_top_out ; +wire [0:0] sb_1__1__36_ccff_tail ; +wire [0:29] sb_1__1__36_chanx_left_out ; +wire [0:29] sb_1__1__36_chanx_right_out ; +wire [0:29] sb_1__1__36_chany_bottom_out ; +wire [0:29] sb_1__1__36_chany_top_out ; +wire [0:0] sb_1__1__37_ccff_tail ; +wire [0:29] sb_1__1__37_chanx_left_out ; +wire [0:29] sb_1__1__37_chanx_right_out ; +wire [0:29] sb_1__1__37_chany_bottom_out ; +wire [0:29] sb_1__1__37_chany_top_out ; +wire [0:0] sb_1__1__38_ccff_tail ; +wire [0:29] sb_1__1__38_chanx_left_out ; +wire [0:29] sb_1__1__38_chanx_right_out ; +wire [0:29] sb_1__1__38_chany_bottom_out ; +wire [0:29] sb_1__1__38_chany_top_out ; +wire [0:0] sb_1__1__39_ccff_tail ; +wire [0:29] sb_1__1__39_chanx_left_out ; +wire [0:29] sb_1__1__39_chanx_right_out ; +wire [0:29] sb_1__1__39_chany_bottom_out ; +wire [0:29] sb_1__1__39_chany_top_out ; +wire [0:0] sb_1__1__3_ccff_tail ; +wire [0:29] sb_1__1__3_chanx_left_out ; +wire [0:29] sb_1__1__3_chanx_right_out ; +wire [0:29] sb_1__1__3_chany_bottom_out ; +wire [0:29] sb_1__1__3_chany_top_out ; +wire [0:0] sb_1__1__40_ccff_tail ; +wire [0:29] sb_1__1__40_chanx_left_out ; +wire [0:29] sb_1__1__40_chanx_right_out ; +wire [0:29] sb_1__1__40_chany_bottom_out ; +wire [0:29] sb_1__1__40_chany_top_out ; +wire [0:0] sb_1__1__41_ccff_tail ; +wire [0:29] sb_1__1__41_chanx_left_out ; +wire [0:29] sb_1__1__41_chanx_right_out ; +wire [0:29] sb_1__1__41_chany_bottom_out ; +wire [0:29] sb_1__1__41_chany_top_out ; +wire [0:0] sb_1__1__42_ccff_tail ; +wire [0:29] sb_1__1__42_chanx_left_out ; +wire [0:29] sb_1__1__42_chanx_right_out ; +wire [0:29] sb_1__1__42_chany_bottom_out ; +wire [0:29] sb_1__1__42_chany_top_out ; +wire [0:0] sb_1__1__43_ccff_tail ; +wire [0:29] sb_1__1__43_chanx_left_out ; +wire [0:29] sb_1__1__43_chanx_right_out ; +wire [0:29] sb_1__1__43_chany_bottom_out ; +wire [0:29] sb_1__1__43_chany_top_out ; +wire [0:0] sb_1__1__44_ccff_tail ; +wire [0:29] sb_1__1__44_chanx_left_out ; +wire [0:29] sb_1__1__44_chanx_right_out ; +wire [0:29] sb_1__1__44_chany_bottom_out ; +wire [0:29] sb_1__1__44_chany_top_out ; +wire [0:0] sb_1__1__45_ccff_tail ; +wire [0:29] sb_1__1__45_chanx_left_out ; +wire [0:29] sb_1__1__45_chanx_right_out ; +wire [0:29] sb_1__1__45_chany_bottom_out ; +wire [0:29] sb_1__1__45_chany_top_out ; +wire [0:0] sb_1__1__46_ccff_tail ; +wire [0:29] sb_1__1__46_chanx_left_out ; +wire [0:29] sb_1__1__46_chanx_right_out ; +wire [0:29] sb_1__1__46_chany_bottom_out ; +wire [0:29] sb_1__1__46_chany_top_out ; +wire [0:0] sb_1__1__47_ccff_tail ; +wire [0:29] sb_1__1__47_chanx_left_out ; +wire [0:29] sb_1__1__47_chanx_right_out ; +wire [0:29] sb_1__1__47_chany_bottom_out ; +wire [0:29] sb_1__1__47_chany_top_out ; +wire [0:0] sb_1__1__48_ccff_tail ; +wire [0:29] sb_1__1__48_chanx_left_out ; +wire [0:29] sb_1__1__48_chanx_right_out ; +wire [0:29] sb_1__1__48_chany_bottom_out ; +wire [0:29] sb_1__1__48_chany_top_out ; +wire [0:0] sb_1__1__49_ccff_tail ; +wire [0:29] sb_1__1__49_chanx_left_out ; +wire [0:29] sb_1__1__49_chanx_right_out ; +wire [0:29] sb_1__1__49_chany_bottom_out ; +wire [0:29] sb_1__1__49_chany_top_out ; +wire [0:0] sb_1__1__4_ccff_tail ; +wire [0:29] sb_1__1__4_chanx_left_out ; +wire [0:29] sb_1__1__4_chanx_right_out ; +wire [0:29] sb_1__1__4_chany_bottom_out ; +wire [0:29] sb_1__1__4_chany_top_out ; +wire [0:0] sb_1__1__50_ccff_tail ; +wire [0:29] sb_1__1__50_chanx_left_out ; +wire [0:29] sb_1__1__50_chanx_right_out ; +wire [0:29] sb_1__1__50_chany_bottom_out ; +wire [0:29] sb_1__1__50_chany_top_out ; +wire [0:0] sb_1__1__51_ccff_tail ; +wire [0:29] sb_1__1__51_chanx_left_out ; +wire [0:29] sb_1__1__51_chanx_right_out ; +wire [0:29] sb_1__1__51_chany_bottom_out ; +wire [0:29] sb_1__1__51_chany_top_out ; +wire [0:0] sb_1__1__52_ccff_tail ; +wire [0:29] sb_1__1__52_chanx_left_out ; +wire [0:29] sb_1__1__52_chanx_right_out ; +wire [0:29] sb_1__1__52_chany_bottom_out ; +wire [0:29] sb_1__1__52_chany_top_out ; +wire [0:0] sb_1__1__53_ccff_tail ; +wire [0:29] sb_1__1__53_chanx_left_out ; +wire [0:29] sb_1__1__53_chanx_right_out ; +wire [0:29] sb_1__1__53_chany_bottom_out ; +wire [0:29] sb_1__1__53_chany_top_out ; +wire [0:0] sb_1__1__54_ccff_tail ; +wire [0:29] sb_1__1__54_chanx_left_out ; +wire [0:29] sb_1__1__54_chanx_right_out ; +wire [0:29] sb_1__1__54_chany_bottom_out ; +wire [0:29] sb_1__1__54_chany_top_out ; +wire [0:0] sb_1__1__55_ccff_tail ; +wire [0:29] sb_1__1__55_chanx_left_out ; +wire [0:29] sb_1__1__55_chanx_right_out ; +wire [0:29] sb_1__1__55_chany_bottom_out ; +wire [0:29] sb_1__1__55_chany_top_out ; +wire [0:0] sb_1__1__56_ccff_tail ; +wire [0:29] sb_1__1__56_chanx_left_out ; +wire [0:29] sb_1__1__56_chanx_right_out ; +wire [0:29] sb_1__1__56_chany_bottom_out ; +wire [0:29] sb_1__1__56_chany_top_out ; +wire [0:0] sb_1__1__57_ccff_tail ; +wire [0:29] sb_1__1__57_chanx_left_out ; +wire [0:29] sb_1__1__57_chanx_right_out ; +wire [0:29] sb_1__1__57_chany_bottom_out ; +wire [0:29] sb_1__1__57_chany_top_out ; +wire [0:0] sb_1__1__58_ccff_tail ; +wire [0:29] sb_1__1__58_chanx_left_out ; +wire [0:29] sb_1__1__58_chanx_right_out ; +wire [0:29] sb_1__1__58_chany_bottom_out ; +wire [0:29] sb_1__1__58_chany_top_out ; +wire [0:0] sb_1__1__59_ccff_tail ; +wire [0:29] sb_1__1__59_chanx_left_out ; +wire [0:29] sb_1__1__59_chanx_right_out ; +wire [0:29] sb_1__1__59_chany_bottom_out ; +wire [0:29] sb_1__1__59_chany_top_out ; +wire [0:0] sb_1__1__5_ccff_tail ; +wire [0:29] sb_1__1__5_chanx_left_out ; +wire [0:29] sb_1__1__5_chanx_right_out ; +wire [0:29] sb_1__1__5_chany_bottom_out ; +wire [0:29] sb_1__1__5_chany_top_out ; +wire [0:0] sb_1__1__60_ccff_tail ; +wire [0:29] sb_1__1__60_chanx_left_out ; +wire [0:29] sb_1__1__60_chanx_right_out ; +wire [0:29] sb_1__1__60_chany_bottom_out ; +wire [0:29] sb_1__1__60_chany_top_out ; +wire [0:0] sb_1__1__61_ccff_tail ; +wire [0:29] sb_1__1__61_chanx_left_out ; +wire [0:29] sb_1__1__61_chanx_right_out ; +wire [0:29] sb_1__1__61_chany_bottom_out ; +wire [0:29] sb_1__1__61_chany_top_out ; +wire [0:0] sb_1__1__62_ccff_tail ; +wire [0:29] sb_1__1__62_chanx_left_out ; +wire [0:29] sb_1__1__62_chanx_right_out ; +wire [0:29] sb_1__1__62_chany_bottom_out ; +wire [0:29] sb_1__1__62_chany_top_out ; +wire [0:0] sb_1__1__63_ccff_tail ; +wire [0:29] sb_1__1__63_chanx_left_out ; +wire [0:29] sb_1__1__63_chanx_right_out ; +wire [0:29] sb_1__1__63_chany_bottom_out ; +wire [0:29] sb_1__1__63_chany_top_out ; +wire [0:0] sb_1__1__64_ccff_tail ; +wire [0:29] sb_1__1__64_chanx_left_out ; +wire [0:29] sb_1__1__64_chanx_right_out ; +wire [0:29] sb_1__1__64_chany_bottom_out ; +wire [0:29] sb_1__1__64_chany_top_out ; +wire [0:0] sb_1__1__65_ccff_tail ; +wire [0:29] sb_1__1__65_chanx_left_out ; +wire [0:29] sb_1__1__65_chanx_right_out ; +wire [0:29] sb_1__1__65_chany_bottom_out ; +wire [0:29] sb_1__1__65_chany_top_out ; +wire [0:0] sb_1__1__66_ccff_tail ; +wire [0:29] sb_1__1__66_chanx_left_out ; +wire [0:29] sb_1__1__66_chanx_right_out ; +wire [0:29] sb_1__1__66_chany_bottom_out ; +wire [0:29] sb_1__1__66_chany_top_out ; +wire [0:0] sb_1__1__67_ccff_tail ; +wire [0:29] sb_1__1__67_chanx_left_out ; +wire [0:29] sb_1__1__67_chanx_right_out ; +wire [0:29] sb_1__1__67_chany_bottom_out ; +wire [0:29] sb_1__1__67_chany_top_out ; +wire [0:0] sb_1__1__68_ccff_tail ; +wire [0:29] sb_1__1__68_chanx_left_out ; +wire [0:29] sb_1__1__68_chanx_right_out ; +wire [0:29] sb_1__1__68_chany_bottom_out ; +wire [0:29] sb_1__1__68_chany_top_out ; +wire [0:0] sb_1__1__69_ccff_tail ; +wire [0:29] sb_1__1__69_chanx_left_out ; +wire [0:29] sb_1__1__69_chanx_right_out ; +wire [0:29] sb_1__1__69_chany_bottom_out ; +wire [0:29] sb_1__1__69_chany_top_out ; +wire [0:0] sb_1__1__6_ccff_tail ; +wire [0:29] sb_1__1__6_chanx_left_out ; +wire [0:29] sb_1__1__6_chanx_right_out ; +wire [0:29] sb_1__1__6_chany_bottom_out ; +wire [0:29] sb_1__1__6_chany_top_out ; +wire [0:0] sb_1__1__70_ccff_tail ; +wire [0:29] sb_1__1__70_chanx_left_out ; +wire [0:29] sb_1__1__70_chanx_right_out ; +wire [0:29] sb_1__1__70_chany_bottom_out ; +wire [0:29] sb_1__1__70_chany_top_out ; +wire [0:0] sb_1__1__71_ccff_tail ; +wire [0:29] sb_1__1__71_chanx_left_out ; +wire [0:29] sb_1__1__71_chanx_right_out ; +wire [0:29] sb_1__1__71_chany_bottom_out ; +wire [0:29] sb_1__1__71_chany_top_out ; +wire [0:0] sb_1__1__72_ccff_tail ; +wire [0:29] sb_1__1__72_chanx_left_out ; +wire [0:29] sb_1__1__72_chanx_right_out ; +wire [0:29] sb_1__1__72_chany_bottom_out ; +wire [0:29] sb_1__1__72_chany_top_out ; +wire [0:0] sb_1__1__73_ccff_tail ; +wire [0:29] sb_1__1__73_chanx_left_out ; +wire [0:29] sb_1__1__73_chanx_right_out ; +wire [0:29] sb_1__1__73_chany_bottom_out ; +wire [0:29] sb_1__1__73_chany_top_out ; +wire [0:0] sb_1__1__74_ccff_tail ; +wire [0:29] sb_1__1__74_chanx_left_out ; +wire [0:29] sb_1__1__74_chanx_right_out ; +wire [0:29] sb_1__1__74_chany_bottom_out ; +wire [0:29] sb_1__1__74_chany_top_out ; +wire [0:0] sb_1__1__75_ccff_tail ; +wire [0:29] sb_1__1__75_chanx_left_out ; +wire [0:29] sb_1__1__75_chanx_right_out ; +wire [0:29] sb_1__1__75_chany_bottom_out ; +wire [0:29] sb_1__1__75_chany_top_out ; +wire [0:0] sb_1__1__76_ccff_tail ; +wire [0:29] sb_1__1__76_chanx_left_out ; +wire [0:29] sb_1__1__76_chanx_right_out ; +wire [0:29] sb_1__1__76_chany_bottom_out ; +wire [0:29] sb_1__1__76_chany_top_out ; +wire [0:0] sb_1__1__77_ccff_tail ; +wire [0:29] sb_1__1__77_chanx_left_out ; +wire [0:29] sb_1__1__77_chanx_right_out ; +wire [0:29] sb_1__1__77_chany_bottom_out ; +wire [0:29] sb_1__1__77_chany_top_out ; +wire [0:0] sb_1__1__78_ccff_tail ; +wire [0:29] sb_1__1__78_chanx_left_out ; +wire [0:29] sb_1__1__78_chanx_right_out ; +wire [0:29] sb_1__1__78_chany_bottom_out ; +wire [0:29] sb_1__1__78_chany_top_out ; +wire [0:0] sb_1__1__79_ccff_tail ; +wire [0:29] sb_1__1__79_chanx_left_out ; +wire [0:29] sb_1__1__79_chanx_right_out ; +wire [0:29] sb_1__1__79_chany_bottom_out ; +wire [0:29] sb_1__1__79_chany_top_out ; +wire [0:0] sb_1__1__7_ccff_tail ; +wire [0:29] sb_1__1__7_chanx_left_out ; +wire [0:29] sb_1__1__7_chanx_right_out ; +wire [0:29] sb_1__1__7_chany_bottom_out ; +wire [0:29] sb_1__1__7_chany_top_out ; +wire [0:0] sb_1__1__80_ccff_tail ; +wire [0:29] sb_1__1__80_chanx_left_out ; +wire [0:29] sb_1__1__80_chanx_right_out ; +wire [0:29] sb_1__1__80_chany_bottom_out ; +wire [0:29] sb_1__1__80_chany_top_out ; +wire [0:0] sb_1__1__81_ccff_tail ; +wire [0:29] sb_1__1__81_chanx_left_out ; +wire [0:29] sb_1__1__81_chanx_right_out ; +wire [0:29] sb_1__1__81_chany_bottom_out ; +wire [0:29] sb_1__1__81_chany_top_out ; +wire [0:0] sb_1__1__82_ccff_tail ; +wire [0:29] sb_1__1__82_chanx_left_out ; +wire [0:29] sb_1__1__82_chanx_right_out ; +wire [0:29] sb_1__1__82_chany_bottom_out ; +wire [0:29] sb_1__1__82_chany_top_out ; +wire [0:0] sb_1__1__83_ccff_tail ; +wire [0:29] sb_1__1__83_chanx_left_out ; +wire [0:29] sb_1__1__83_chanx_right_out ; +wire [0:29] sb_1__1__83_chany_bottom_out ; +wire [0:29] sb_1__1__83_chany_top_out ; +wire [0:0] sb_1__1__84_ccff_tail ; +wire [0:29] sb_1__1__84_chanx_left_out ; +wire [0:29] sb_1__1__84_chanx_right_out ; +wire [0:29] sb_1__1__84_chany_bottom_out ; +wire [0:29] sb_1__1__84_chany_top_out ; +wire [0:0] sb_1__1__85_ccff_tail ; +wire [0:29] sb_1__1__85_chanx_left_out ; +wire [0:29] sb_1__1__85_chanx_right_out ; +wire [0:29] sb_1__1__85_chany_bottom_out ; +wire [0:29] sb_1__1__85_chany_top_out ; +wire [0:0] sb_1__1__86_ccff_tail ; +wire [0:29] sb_1__1__86_chanx_left_out ; +wire [0:29] sb_1__1__86_chanx_right_out ; +wire [0:29] sb_1__1__86_chany_bottom_out ; +wire [0:29] sb_1__1__86_chany_top_out ; +wire [0:0] sb_1__1__87_ccff_tail ; +wire [0:29] sb_1__1__87_chanx_left_out ; +wire [0:29] sb_1__1__87_chanx_right_out ; +wire [0:29] sb_1__1__87_chany_bottom_out ; +wire [0:29] sb_1__1__87_chany_top_out ; +wire [0:0] sb_1__1__88_ccff_tail ; +wire [0:29] sb_1__1__88_chanx_left_out ; +wire [0:29] sb_1__1__88_chanx_right_out ; +wire [0:29] sb_1__1__88_chany_bottom_out ; +wire [0:29] sb_1__1__88_chany_top_out ; +wire [0:0] sb_1__1__89_ccff_tail ; +wire [0:29] sb_1__1__89_chanx_left_out ; +wire [0:29] sb_1__1__89_chanx_right_out ; +wire [0:29] sb_1__1__89_chany_bottom_out ; +wire [0:29] sb_1__1__89_chany_top_out ; +wire [0:0] sb_1__1__8_ccff_tail ; +wire [0:29] sb_1__1__8_chanx_left_out ; +wire [0:29] sb_1__1__8_chanx_right_out ; +wire [0:29] sb_1__1__8_chany_bottom_out ; +wire [0:29] sb_1__1__8_chany_top_out ; +wire [0:0] sb_1__1__90_ccff_tail ; +wire [0:29] sb_1__1__90_chanx_left_out ; +wire [0:29] sb_1__1__90_chanx_right_out ; +wire [0:29] sb_1__1__90_chany_bottom_out ; +wire [0:29] sb_1__1__90_chany_top_out ; +wire [0:0] sb_1__1__91_ccff_tail ; +wire [0:29] sb_1__1__91_chanx_left_out ; +wire [0:29] sb_1__1__91_chanx_right_out ; +wire [0:29] sb_1__1__91_chany_bottom_out ; +wire [0:29] sb_1__1__91_chany_top_out ; +wire [0:0] sb_1__1__92_ccff_tail ; +wire [0:29] sb_1__1__92_chanx_left_out ; +wire [0:29] sb_1__1__92_chanx_right_out ; +wire [0:29] sb_1__1__92_chany_bottom_out ; +wire [0:29] sb_1__1__92_chany_top_out ; +wire [0:0] sb_1__1__93_ccff_tail ; +wire [0:29] sb_1__1__93_chanx_left_out ; +wire [0:29] sb_1__1__93_chanx_right_out ; +wire [0:29] sb_1__1__93_chany_bottom_out ; +wire [0:29] sb_1__1__93_chany_top_out ; +wire [0:0] sb_1__1__94_ccff_tail ; +wire [0:29] sb_1__1__94_chanx_left_out ; +wire [0:29] sb_1__1__94_chanx_right_out ; +wire [0:29] sb_1__1__94_chany_bottom_out ; +wire [0:29] sb_1__1__94_chany_top_out ; +wire [0:0] sb_1__1__95_ccff_tail ; +wire [0:29] sb_1__1__95_chanx_left_out ; +wire [0:29] sb_1__1__95_chanx_right_out ; +wire [0:29] sb_1__1__95_chany_bottom_out ; +wire [0:29] sb_1__1__95_chany_top_out ; +wire [0:0] sb_1__1__96_ccff_tail ; +wire [0:29] sb_1__1__96_chanx_left_out ; +wire [0:29] sb_1__1__96_chanx_right_out ; +wire [0:29] sb_1__1__96_chany_bottom_out ; +wire [0:29] sb_1__1__96_chany_top_out ; +wire [0:0] sb_1__1__97_ccff_tail ; +wire [0:29] sb_1__1__97_chanx_left_out ; +wire [0:29] sb_1__1__97_chanx_right_out ; +wire [0:29] sb_1__1__97_chany_bottom_out ; +wire [0:29] sb_1__1__97_chany_top_out ; +wire [0:0] sb_1__1__98_ccff_tail ; +wire [0:29] sb_1__1__98_chanx_left_out ; +wire [0:29] sb_1__1__98_chanx_right_out ; +wire [0:29] sb_1__1__98_chany_bottom_out ; +wire [0:29] sb_1__1__98_chany_top_out ; +wire [0:0] sb_1__1__99_ccff_tail ; +wire [0:29] sb_1__1__99_chanx_left_out ; +wire [0:29] sb_1__1__99_chanx_right_out ; +wire [0:29] sb_1__1__99_chany_bottom_out ; +wire [0:29] sb_1__1__99_chany_top_out ; +wire [0:0] sb_1__1__9_ccff_tail ; +wire [0:29] sb_1__1__9_chanx_left_out ; +wire [0:29] sb_1__1__9_chanx_right_out ; +wire [0:29] sb_1__1__9_chany_bottom_out ; +wire [0:29] sb_1__1__9_chany_top_out ; +wire [1:0] UNCONN ; +wire [317:0] scff_Wires ; +wire [132:0] regin_feedthrough_wires ; +wire [132:0] regout_feedthrough_wires ; +wire [132:0] cin_feedthrough_wires ; +wire [132:0] cout_feedthrough_wires ; +wire [287:0] Test_enWires ; +wire [636:0] pResetWires ; +wire [287:0] ResetWires ; +wire [624:0] prog_clk_0_wires ; +wire [251:0] prog_clk_1_wires ; +wire [135:0] prog_clk_2_wires ; +wire [100:0] prog_clk_3_wires ; +wire [251:0] clk_1_wires ; +wire [135:0] clk_2_wires ; +wire [100:0] clk_3_wires ; + +grid_clb grid_clb_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[0] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[0] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_3 } ) , + .ccff_head ( grid_io_left_0_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_0_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_0_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_0_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_0_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_0_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_0_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_0_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_0_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_4 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[23] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6 ) , .SC_OUT_BOT ( scff_Wires[25] ) , + .Test_en_E_in ( Test_enWires[24] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_8 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9 ) , + .pReset_N_in ( pResetWires[63] ) , .Reset_E_in ( ResetWires[24] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_10 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_11 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_12 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[4] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_13 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[0] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[1] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[3] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_14 ) , + .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) ) ; +grid_clb grid_clb_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_16 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[1] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_17 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[1] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_18 } ) , + .ccff_head ( grid_io_left_1_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_1_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_1_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_1_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_1_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_1_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_1_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_1_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_1_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[0] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_19 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[0] ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[21] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_20 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_OUT_BOT ( scff_Wires[22] ) , + .Test_en_E_in ( Test_enWires[46] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_22 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_23 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_24 ) , + .pReset_N_in ( pResetWires[112] ) , .Reset_E_in ( ResetWires[46] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_25 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_26 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_27 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_28 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[3] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[6] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[7] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[9] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) ) ; +grid_clb grid_clb_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_31 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[2] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_32 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[2] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_33 } ) , + .ccff_head ( grid_io_left_2_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_2_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_2_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_2_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_2_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_2_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_2_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_2_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_2_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[1] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_34 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[1] ) , + .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[19] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , .SC_OUT_BOT ( scff_Wires[20] ) , + .Test_en_E_in ( Test_enWires[68] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_37 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_38 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_39 ) , + .pReset_N_in ( pResetWires[161] ) , .Reset_E_in ( ResetWires[68] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_40 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_41 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_42 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[11] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_43 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[11] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[12] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[14] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_44 ) , + .clk_0_N_in ( clk_1_wires[11] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) ) ; +grid_clb grid_clb_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_46 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[3] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_47 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[3] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_48 } ) , + .ccff_head ( grid_io_left_3_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_3_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_3_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_3_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_3_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_3_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_3_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_3_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_3_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[2] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_49 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[2] ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[17] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires[18] ) , + .Test_en_E_in ( Test_enWires[90] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_52 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_53 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_54 ) , + .pReset_N_in ( pResetWires[210] ) , .Reset_E_in ( ResetWires[90] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_55 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_56 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_57 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_58 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[10] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[16] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[17] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[19] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) , + .clk_0_S_in ( clk_1_wires[10] ) ) ; +grid_clb grid_clb_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_61 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[4] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_62 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[4] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_63 } ) , + .ccff_head ( grid_io_left_4_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_4_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_4_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_4_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_4_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_4_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_4_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_4_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_4_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[3] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_64 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[3] ) , + .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[15] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_65 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_66 ) , .SC_OUT_BOT ( scff_Wires[16] ) , + .Test_en_E_in ( Test_enWires[112] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_67 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_68 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_69 ) , + .pReset_N_in ( pResetWires[259] ) , .Reset_E_in ( ResetWires[112] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_70 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_71 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_72 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[18] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_73 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[21] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[22] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[24] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_74 ) , + .clk_0_N_in ( clk_1_wires[18] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) ) ; +grid_clb grid_clb_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_76 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[5] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_77 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[5] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_78 } ) , + .ccff_head ( grid_io_left_5_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_5_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_5_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_5_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_5_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_5_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_5_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_5_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_5_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[4] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_79 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[4] ) , + .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[13] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_80 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_81 ) , .SC_OUT_BOT ( scff_Wires[14] ) , + .Test_en_E_in ( Test_enWires[134] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_82 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_83 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_84 ) , + .pReset_N_in ( pResetWires[308] ) , .Reset_E_in ( ResetWires[134] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_85 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_86 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_87 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_88 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[17] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[26] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[27] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[29] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_90 ) , + .clk_0_S_in ( clk_1_wires[17] ) ) ; +grid_clb grid_clb_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_91 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[6] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_92 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[6] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_93 } ) , + .ccff_head ( grid_io_left_6_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_6_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_6_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_6_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_6_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_6_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_6_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_6_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_6_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[5] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_94 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[5] ) , + .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[11] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_95 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_96 ) , .SC_OUT_BOT ( scff_Wires[12] ) , + .Test_en_E_in ( Test_enWires[156] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_97 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_98 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_99 ) , + .pReset_N_in ( pResetWires[357] ) , .Reset_E_in ( ResetWires[156] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_100 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_101 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_102 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[25] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_103 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[31] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[32] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[34] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_104 ) , + .clk_0_N_in ( clk_1_wires[25] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) ) ; +grid_clb grid_clb_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_106 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[7] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_107 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[7] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_108 } ) , + .ccff_head ( grid_io_left_7_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_7_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_7_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_7_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_7_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_7_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_7_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_7_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_7_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[6] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_109 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[6] ) , + .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[9] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_110 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_111 ) , + .SC_OUT_BOT ( scff_Wires[10] ) , .Test_en_E_in ( Test_enWires[178] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_112 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_113 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_114 ) , + .pReset_N_in ( pResetWires[406] ) , .Reset_E_in ( ResetWires[178] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_115 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_116 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_117 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_118 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[24] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[36] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[37] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[39] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_119 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_120 ) , + .clk_0_S_in ( clk_1_wires[24] ) ) ; +grid_clb grid_clb_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_121 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[8] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_122 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[8] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_123 } ) , + .ccff_head ( grid_io_left_8_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_8_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_8_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_8_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_8_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_8_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_8_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_8_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_8_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[7] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_124 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[7] ) , + .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[7] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_125 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_126 ) , .SC_OUT_BOT ( scff_Wires[8] ) , + .Test_en_E_in ( Test_enWires[200] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_127 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_128 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_129 ) , + .pReset_N_in ( pResetWires[455] ) , .Reset_E_in ( ResetWires[200] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_130 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_131 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_132 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[32] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_133 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[41] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[42] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[44] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_134 ) , + .clk_0_N_in ( clk_1_wires[32] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) ) ; +grid_clb grid_clb_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_136 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[9] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_137 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[9] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_138 } ) , + .ccff_head ( grid_io_left_9_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_9_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_9_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_9_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_9_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_9_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_9_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_9_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_9_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[8] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_139 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[8] ) , + .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[5] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_140 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_141 ) , .SC_OUT_BOT ( scff_Wires[6] ) , + .Test_en_E_in ( Test_enWires[222] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_142 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_143 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_144 ) , + .pReset_N_in ( pResetWires[504] ) , .Reset_E_in ( ResetWires[222] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_145 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_146 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_147 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_148 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[31] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[46] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[47] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[49] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_149 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_150 ) , + .clk_0_S_in ( clk_1_wires[31] ) ) ; +grid_clb grid_clb_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_151 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[10] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_152 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[10] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_153 } ) , + .ccff_head ( grid_io_left_10_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_10_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_10_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_10_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_10_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_10_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_10_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_10_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_10_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[9] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_154 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[9] ) , + .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[3] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_155 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_156 ) , .SC_OUT_BOT ( scff_Wires[4] ) , + .Test_en_E_in ( Test_enWires[244] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_157 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_158 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_159 ) , + .pReset_N_in ( pResetWires[553] ) , .Reset_E_in ( ResetWires[244] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_160 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_161 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_162 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[39] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_163 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[51] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[52] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[54] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_164 ) , + .clk_0_N_in ( clk_1_wires[39] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) ) ; +grid_clb grid_clb_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_166 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_167 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_168 } ) , + .ccff_head ( grid_io_left_11_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_11_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_11_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_11_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_11_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_11_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_11_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_11_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_11_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[10] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_169 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[10] ) , + .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires[1] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_170 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_171 ) , .SC_OUT_BOT ( scff_Wires[2] ) , + .Test_en_E_in ( Test_enWires[266] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_172 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_173 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_174 ) , + .pReset_N_in ( pResetWires[602] ) , .Reset_E_in ( ResetWires[266] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_175 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_176 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_177 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_178 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[38] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[56] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[57] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[61] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[59] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) , + .clk_0_S_in ( clk_1_wires[38] ) ) ; +grid_clb grid_clb_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_180 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[11] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_181 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[11] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_182 } ) , + .ccff_head ( cby_1__1__0_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_12_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_12_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_12_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_12_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_12_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_12_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_12_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_12_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_183 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_12_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_184 ) , .SC_IN_BOT ( scff_Wires[28] ) , + .SC_OUT_TOP ( scff_Wires[29] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_185 ) , + .Test_en_E_in ( Test_enWires[25] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_186 ) , + .Test_en_W_out ( Test_enWires[26] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_187 ) , + .pReset_N_in ( pResetWires[68] ) , .Reset_E_in ( ResetWires[25] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_188 ) , + .Reset_W_out ( ResetWires[26] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_189 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[6] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_190 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[63] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[64] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_191 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_192 ) , + .clk_0_N_in ( clk_1_wires[6] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) ) ; +grid_clb grid_clb_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_194 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[12] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_195 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[12] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_196 } ) , + .ccff_head ( cby_1__1__1_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_13_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_13_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_13_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_13_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_13_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_13_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_13_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_13_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[11] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_197 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[11] ) , + .ccff_tail ( grid_clb_13_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_198 ) , .SC_IN_BOT ( scff_Wires[30] ) , + .SC_OUT_TOP ( scff_Wires[31] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_199 ) , + .Test_en_E_in ( Test_enWires[47] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_200 ) , + .Test_en_W_out ( Test_enWires[48] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_201 ) , + .pReset_N_in ( pResetWires[117] ) , .Reset_E_in ( ResetWires[47] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_202 ) , + .Reset_W_out ( ResetWires[48] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_203 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_204 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[5] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[66] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[67] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_205 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_206 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_207 ) , + .clk_0_S_in ( clk_1_wires[5] ) ) ; +grid_clb grid_clb_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_208 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[13] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_209 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[13] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_210 } ) , + .ccff_head ( cby_1__1__2_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_14_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_14_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_14_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_14_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_14_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_14_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_14_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_14_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[12] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_211 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[12] ) , + .ccff_tail ( grid_clb_14_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_212 ) , .SC_IN_BOT ( scff_Wires[32] ) , + .SC_OUT_TOP ( scff_Wires[33] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_213 ) , + .Test_en_E_in ( Test_enWires[69] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_214 ) , + .Test_en_W_out ( Test_enWires[70] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_215 ) , + .pReset_N_in ( pResetWires[166] ) , .Reset_E_in ( ResetWires[69] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_216 ) , + .Reset_W_out ( ResetWires[70] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_217 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[13] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_218 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[69] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[70] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_219 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_220 ) , + .clk_0_N_in ( clk_1_wires[13] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) ) ; +grid_clb grid_clb_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_222 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[14] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_223 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[14] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_224 } ) , + .ccff_head ( cby_1__1__3_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_15_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_15_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_15_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_15_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_15_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_15_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_15_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_15_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[13] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_225 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[13] ) , + .ccff_tail ( grid_clb_15_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_226 ) , .SC_IN_BOT ( scff_Wires[34] ) , + .SC_OUT_TOP ( scff_Wires[35] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_227 ) , + .Test_en_E_in ( Test_enWires[91] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_228 ) , + .Test_en_W_out ( Test_enWires[92] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_229 ) , + .pReset_N_in ( pResetWires[215] ) , .Reset_E_in ( ResetWires[91] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_230 ) , + .Reset_W_out ( ResetWires[92] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_231 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_232 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[12] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[72] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[73] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_233 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_234 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_235 ) , + .clk_0_S_in ( clk_1_wires[12] ) ) ; +grid_clb grid_clb_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_236 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[15] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_237 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[15] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_238 } ) , + .ccff_head ( cby_1__1__4_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_16_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_16_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_16_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_16_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_16_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_16_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_16_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_16_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[14] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_239 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[14] ) , + .ccff_tail ( grid_clb_16_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_240 ) , .SC_IN_BOT ( scff_Wires[36] ) , + .SC_OUT_TOP ( scff_Wires[37] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_241 ) , + .Test_en_E_in ( Test_enWires[113] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_242 ) , + .Test_en_W_out ( Test_enWires[114] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_243 ) , + .pReset_N_in ( pResetWires[264] ) , .Reset_E_in ( ResetWires[113] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_244 ) , + .Reset_W_out ( ResetWires[114] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_245 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[20] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_246 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[75] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[76] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_247 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_248 ) , + .clk_0_N_in ( clk_1_wires[20] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) ) ; +grid_clb grid_clb_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_250 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[16] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_251 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[16] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_252 } ) , + .ccff_head ( cby_1__1__5_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_17_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_17_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_17_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_17_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_17_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_17_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_17_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_17_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[15] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_253 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[15] ) , + .ccff_tail ( grid_clb_17_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_254 ) , .SC_IN_BOT ( scff_Wires[38] ) , + .SC_OUT_TOP ( scff_Wires[39] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_255 ) , + .Test_en_E_in ( Test_enWires[135] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_256 ) , + .Test_en_W_out ( Test_enWires[136] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_257 ) , + .pReset_N_in ( pResetWires[313] ) , .Reset_E_in ( ResetWires[135] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_258 ) , + .Reset_W_out ( ResetWires[136] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_259 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_260 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[19] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[78] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[79] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_261 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_262 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_263 ) , + .clk_0_S_in ( clk_1_wires[19] ) ) ; +grid_clb grid_clb_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_264 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[17] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_265 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[17] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_266 } ) , + .ccff_head ( cby_1__1__6_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_18_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_18_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_18_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_18_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_18_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_18_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_18_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_18_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[16] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_267 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[16] ) , + .ccff_tail ( grid_clb_18_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_268 ) , .SC_IN_BOT ( scff_Wires[40] ) , + .SC_OUT_TOP ( scff_Wires[41] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_269 ) , + .Test_en_E_in ( Test_enWires[157] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_270 ) , + .Test_en_W_out ( Test_enWires[158] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_271 ) , + .pReset_N_in ( pResetWires[362] ) , .Reset_E_in ( ResetWires[157] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_272 ) , + .Reset_W_out ( ResetWires[158] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_273 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[27] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_274 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[81] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[82] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_275 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_276 ) , + .clk_0_N_in ( clk_1_wires[27] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) ) ; +grid_clb grid_clb_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_278 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[18] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_279 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[18] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_280 } ) , + .ccff_head ( cby_1__1__7_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_19_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_19_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_19_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_19_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_19_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_19_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_19_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_19_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[17] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_281 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[17] ) , + .ccff_tail ( grid_clb_19_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_282 ) , .SC_IN_BOT ( scff_Wires[42] ) , + .SC_OUT_TOP ( scff_Wires[43] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_283 ) , + .Test_en_E_in ( Test_enWires[179] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_284 ) , + .Test_en_W_out ( Test_enWires[180] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_285 ) , + .pReset_N_in ( pResetWires[411] ) , .Reset_E_in ( ResetWires[179] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_286 ) , + .Reset_W_out ( ResetWires[180] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_287 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_288 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[26] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[84] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[85] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_289 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_290 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_291 ) , + .clk_0_S_in ( clk_1_wires[26] ) ) ; +grid_clb grid_clb_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_292 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[19] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_293 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[19] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_294 } ) , + .ccff_head ( cby_1__1__8_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_20_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_20_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_20_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_20_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_20_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_20_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_20_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_20_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[18] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_295 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[18] ) , + .ccff_tail ( grid_clb_20_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_296 ) , .SC_IN_BOT ( scff_Wires[44] ) , + .SC_OUT_TOP ( scff_Wires[45] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_297 ) , + .Test_en_E_in ( Test_enWires[201] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_298 ) , + .Test_en_W_out ( Test_enWires[202] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_299 ) , + .pReset_N_in ( pResetWires[460] ) , .Reset_E_in ( ResetWires[201] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_300 ) , + .Reset_W_out ( ResetWires[202] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_301 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[34] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_302 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[87] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[88] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_303 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_304 ) , + .clk_0_N_in ( clk_1_wires[34] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) ) ; +grid_clb grid_clb_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_306 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[20] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_307 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[20] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_308 } ) , + .ccff_head ( cby_1__1__9_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_21_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_21_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_21_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_21_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_21_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_21_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_21_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_21_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[19] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_309 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[19] ) , + .ccff_tail ( grid_clb_21_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_310 ) , .SC_IN_BOT ( scff_Wires[46] ) , + .SC_OUT_TOP ( scff_Wires[47] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_311 ) , + .Test_en_E_in ( Test_enWires[223] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_312 ) , + .Test_en_W_out ( Test_enWires[224] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_313 ) , + .pReset_N_in ( pResetWires[509] ) , .Reset_E_in ( ResetWires[223] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_314 ) , + .Reset_W_out ( ResetWires[224] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_315 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_316 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[33] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[90] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[91] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_317 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_318 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_319 ) , + .clk_0_S_in ( clk_1_wires[33] ) ) ; +grid_clb grid_clb_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_320 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[21] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_321 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[21] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_322 } ) , + .ccff_head ( cby_1__1__10_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_22_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_22_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_22_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_22_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_22_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_22_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_22_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_22_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[20] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_323 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[20] ) , + .ccff_tail ( grid_clb_22_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_324 ) , .SC_IN_BOT ( scff_Wires[48] ) , + .SC_OUT_TOP ( scff_Wires[49] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_325 ) , + .Test_en_E_in ( Test_enWires[245] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_326 ) , + .Test_en_W_out ( Test_enWires[246] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_327 ) , + .pReset_N_in ( pResetWires[558] ) , .Reset_E_in ( ResetWires[245] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_328 ) , + .Reset_W_out ( ResetWires[246] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_329 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[41] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_330 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[93] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[94] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_331 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_332 ) , + .clk_0_N_in ( clk_1_wires[41] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) ) ; +grid_clb grid_clb_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_334 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_335 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_336 } ) , + .ccff_head ( cby_1__1__11_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_23_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_23_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_23_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_23_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_23_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_23_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_23_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_23_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[21] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_337 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[21] ) , + .ccff_tail ( grid_clb_23_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_338 ) , .SC_IN_BOT ( scff_Wires[50] ) , + .SC_OUT_TOP ( scff_Wires[51] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_339 ) , + .Test_en_E_in ( Test_enWires[267] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_340 ) , + .Test_en_W_out ( Test_enWires[268] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_341 ) , + .pReset_N_in ( pResetWires[606] ) , .Reset_E_in ( ResetWires[267] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_342 ) , + .Reset_W_out ( ResetWires[268] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_343 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_344 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[40] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[96] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[97] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_345 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[99] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_346 ) , + .clk_0_S_in ( clk_1_wires[40] ) ) ; +grid_clb grid_clb_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_347 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[22] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_348 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[22] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_349 } ) , + .ccff_head ( cby_1__1__12_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_24_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_24_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_24_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_24_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_24_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_24_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_24_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_24_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_350 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[76] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_351 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_352 ) , + .SC_OUT_BOT ( scff_Wires[78] ) , .Test_en_E_in ( Test_enWires[27] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_353 ) , + .Test_en_W_out ( Test_enWires[28] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_354 ) , + .pReset_N_in ( pResetWires[72] ) , .Reset_E_in ( ResetWires[27] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_355 ) , + .Reset_W_out ( ResetWires[28] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_356 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[46] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_357 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[101] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[102] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_358 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_359 ) , + .clk_0_N_in ( clk_1_wires[46] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) ) ; +grid_clb grid_clb_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_361 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[23] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_362 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[23] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_363 } ) , + .ccff_head ( cby_1__1__13_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_25_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_25_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_25_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_25_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_25_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_25_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_25_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_25_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[22] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_364 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[22] ) , + .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[74] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_365 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_366 ) , + .SC_OUT_BOT ( scff_Wires[75] ) , .Test_en_E_in ( Test_enWires[49] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_367 ) , + .Test_en_W_out ( Test_enWires[50] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_368 ) , + .pReset_N_in ( pResetWires[121] ) , .Reset_E_in ( ResetWires[49] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_369 ) , + .Reset_W_out ( ResetWires[50] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_370 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_371 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[45] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[104] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[105] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_372 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_373 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) , + .clk_0_S_in ( clk_1_wires[45] ) ) ; +grid_clb grid_clb_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_375 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[24] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_376 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[24] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_377 } ) , + .ccff_head ( cby_1__1__14_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_26_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_26_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_26_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_26_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_26_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_26_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_26_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_26_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[23] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_378 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[23] ) , + .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[72] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_379 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_380 ) , + .SC_OUT_BOT ( scff_Wires[73] ) , .Test_en_E_in ( Test_enWires[71] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_381 ) , + .Test_en_W_out ( Test_enWires[72] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_382 ) , + .pReset_N_in ( pResetWires[170] ) , .Reset_E_in ( ResetWires[71] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_383 ) , + .Reset_W_out ( ResetWires[72] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_384 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[53] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_385 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[107] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[108] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_386 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_387 ) , + .clk_0_N_in ( clk_1_wires[53] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) ) ; +grid_clb grid_clb_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_389 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[25] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_390 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[25] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_391 } ) , + .ccff_head ( cby_1__1__15_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_27_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_27_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_27_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_27_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_27_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_27_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_27_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_27_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[24] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_392 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[24] ) , + .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[70] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_393 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_394 ) , + .SC_OUT_BOT ( scff_Wires[71] ) , .Test_en_E_in ( Test_enWires[93] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_395 ) , + .Test_en_W_out ( Test_enWires[94] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_396 ) , + .pReset_N_in ( pResetWires[219] ) , .Reset_E_in ( ResetWires[93] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_397 ) , + .Reset_W_out ( ResetWires[94] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_398 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_399 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[52] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[110] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[111] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_400 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_401 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_402 ) , + .clk_0_S_in ( clk_1_wires[52] ) ) ; +grid_clb grid_clb_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_403 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[26] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_404 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[26] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_405 } ) , + .ccff_head ( cby_1__1__16_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_28_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_28_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_28_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_28_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_28_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_28_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_28_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_28_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[25] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_406 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[25] ) , + .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[68] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_407 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_408 ) , + .SC_OUT_BOT ( scff_Wires[69] ) , .Test_en_E_in ( Test_enWires[115] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_409 ) , + .Test_en_W_out ( Test_enWires[116] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_410 ) , + .pReset_N_in ( pResetWires[268] ) , .Reset_E_in ( ResetWires[115] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_411 ) , + .Reset_W_out ( ResetWires[116] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_412 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[60] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_413 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[113] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[114] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_414 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_415 ) , + .clk_0_N_in ( clk_1_wires[60] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) ) ; +grid_clb grid_clb_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_417 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[27] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[27] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_419 } ) , + .ccff_head ( cby_1__1__17_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_29_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_29_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_29_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_29_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_29_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_29_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_29_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_29_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[26] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_420 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[26] ) , + .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[66] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_421 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_422 ) , + .SC_OUT_BOT ( scff_Wires[67] ) , .Test_en_E_in ( Test_enWires[137] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_423 ) , + .Test_en_W_out ( Test_enWires[138] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_424 ) , + .pReset_N_in ( pResetWires[317] ) , .Reset_E_in ( ResetWires[137] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_425 ) , + .Reset_W_out ( ResetWires[138] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_426 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_427 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[59] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[116] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[117] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_428 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_429 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_430 ) , + .clk_0_S_in ( clk_1_wires[59] ) ) ; +grid_clb grid_clb_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_431 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[28] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_432 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[28] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_433 } ) , + .ccff_head ( cby_1__1__18_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_30_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_30_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_30_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_30_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_30_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_30_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_30_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_30_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[27] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_434 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[27] ) , + .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[64] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_435 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_436 ) , + .SC_OUT_BOT ( scff_Wires[65] ) , .Test_en_E_in ( Test_enWires[159] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_437 ) , + .Test_en_W_out ( Test_enWires[160] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_438 ) , + .pReset_N_in ( pResetWires[366] ) , .Reset_E_in ( ResetWires[159] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_439 ) , + .Reset_W_out ( ResetWires[160] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_440 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[67] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_441 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[119] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[120] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_442 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_443 ) , + .clk_0_N_in ( clk_1_wires[67] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) ) ; +grid_clb grid_clb_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_445 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[29] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_446 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[29] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_447 } ) , + .ccff_head ( cby_1__1__19_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_31_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_31_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_31_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_31_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_31_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_31_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_31_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_31_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[28] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_448 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[28] ) , + .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[62] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_449 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_450 ) , + .SC_OUT_BOT ( scff_Wires[63] ) , .Test_en_E_in ( Test_enWires[181] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_451 ) , + .Test_en_W_out ( Test_enWires[182] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_452 ) , + .pReset_N_in ( pResetWires[415] ) , .Reset_E_in ( ResetWires[181] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_453 ) , + .Reset_W_out ( ResetWires[182] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_454 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_455 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[66] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[122] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[123] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_456 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_457 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_458 ) , + .clk_0_S_in ( clk_1_wires[66] ) ) ; +grid_clb grid_clb_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_459 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[30] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_460 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[30] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_461 } ) , + .ccff_head ( cby_1__1__20_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_32_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_32_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_32_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_32_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_32_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_32_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_32_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_32_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[29] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_462 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[29] ) , + .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[60] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_463 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_464 ) , + .SC_OUT_BOT ( scff_Wires[61] ) , .Test_en_E_in ( Test_enWires[203] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_465 ) , + .Test_en_W_out ( Test_enWires[204] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_466 ) , + .pReset_N_in ( pResetWires[464] ) , .Reset_E_in ( ResetWires[203] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_467 ) , + .Reset_W_out ( ResetWires[204] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_468 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[74] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_469 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[125] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[126] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_470 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_471 ) , + .clk_0_N_in ( clk_1_wires[74] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) ) ; +grid_clb grid_clb_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_473 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[31] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_474 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[31] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_475 } ) , + .ccff_head ( cby_1__1__21_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_33_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_33_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_33_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_33_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_33_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_33_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_33_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_33_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[30] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_476 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[30] ) , + .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires[58] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_477 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_478 ) , + .SC_OUT_BOT ( scff_Wires[59] ) , .Test_en_E_in ( Test_enWires[225] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_479 ) , + .Test_en_W_out ( Test_enWires[226] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_480 ) , + .pReset_N_in ( pResetWires[513] ) , .Reset_E_in ( ResetWires[225] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_481 ) , + .Reset_W_out ( ResetWires[226] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_482 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_483 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[73] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[128] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[129] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_486 ) , + .clk_0_S_in ( clk_1_wires[73] ) ) ; +grid_clb grid_clb_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_487 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[32] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_488 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[32] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_489 } ) , + .ccff_head ( cby_1__1__22_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_34_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_34_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_34_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_34_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_34_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_34_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_34_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_34_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[31] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_490 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[31] ) , + .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires[56] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_491 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_492 ) , + .SC_OUT_BOT ( scff_Wires[57] ) , .Test_en_E_in ( Test_enWires[247] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_493 ) , + .Test_en_W_out ( Test_enWires[248] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_494 ) , + .pReset_N_in ( pResetWires[562] ) , .Reset_E_in ( ResetWires[247] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_495 ) , + .Reset_W_out ( ResetWires[248] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_496 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[81] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_497 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[131] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[132] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_498 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_499 ) , + .clk_0_N_in ( clk_1_wires[81] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) ) ; +grid_clb grid_clb_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_501 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_502 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_503 } ) , + .ccff_head ( cby_1__1__23_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_35_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_35_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_35_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_35_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_35_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_35_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_35_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_35_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[32] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_504 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[32] ) , + .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires[54] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_505 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_506 ) , + .SC_OUT_BOT ( scff_Wires[55] ) , .Test_en_E_in ( Test_enWires[269] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_507 ) , + .Test_en_W_out ( Test_enWires[270] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_508 ) , + .pReset_N_in ( pResetWires[609] ) , .Reset_E_in ( ResetWires[269] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_509 ) , + .Reset_W_out ( ResetWires[270] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_510 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_511 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[80] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[134] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[135] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_512 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[137] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) , + .clk_0_S_in ( clk_1_wires[80] ) ) ; +grid_clb grid_clb_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_514 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[33] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_515 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[33] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_516 } ) , + .ccff_head ( cby_1__1__24_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_36_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_36_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_36_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_36_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_36_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_36_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_36_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_36_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_517 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_36_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_518 ) , .SC_IN_BOT ( scff_Wires[81] ) , + .SC_OUT_TOP ( scff_Wires[82] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_519 ) , + .Test_en_E_in ( Test_enWires[29] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_520 ) , + .Test_en_W_out ( Test_enWires[30] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_521 ) , + .pReset_N_in ( pResetWires[76] ) , .Reset_E_in ( ResetWires[29] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_522 ) , + .Reset_W_out ( ResetWires[30] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_523 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[48] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_524 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[139] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[140] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_525 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_526 ) , + .clk_0_N_in ( clk_1_wires[48] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) ) ; +grid_clb grid_clb_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_528 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[34] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_529 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[34] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_530 } ) , + .ccff_head ( cby_1__1__25_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_37_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_37_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_37_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_37_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_37_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_37_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_37_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_37_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[33] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_531 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[33] ) , + .ccff_tail ( grid_clb_37_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_532 ) , .SC_IN_BOT ( scff_Wires[83] ) , + .SC_OUT_TOP ( scff_Wires[84] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_533 ) , + .Test_en_E_in ( Test_enWires[51] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_534 ) , + .Test_en_W_out ( Test_enWires[52] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_535 ) , + .pReset_N_in ( pResetWires[125] ) , .Reset_E_in ( ResetWires[51] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_536 ) , + .Reset_W_out ( ResetWires[52] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_537 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_538 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[47] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[142] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[143] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_539 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_540 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_541 ) , + .clk_0_S_in ( clk_1_wires[47] ) ) ; +grid_clb grid_clb_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_542 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[35] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_543 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[35] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_544 } ) , + .ccff_head ( cby_1__1__26_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_38_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_38_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_38_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_38_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_38_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_38_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_38_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_38_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[34] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_545 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[34] ) , + .ccff_tail ( grid_clb_38_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_546 ) , .SC_IN_BOT ( scff_Wires[85] ) , + .SC_OUT_TOP ( scff_Wires[86] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_547 ) , + .Test_en_E_in ( Test_enWires[73] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_548 ) , + .Test_en_W_out ( Test_enWires[74] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_549 ) , + .pReset_N_in ( pResetWires[174] ) , .Reset_E_in ( ResetWires[73] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_550 ) , + .Reset_W_out ( ResetWires[74] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_551 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[55] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_552 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[145] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[146] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_553 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_554 ) , + .clk_0_N_in ( clk_1_wires[55] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) ) ; +grid_clb grid_clb_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_556 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[36] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_557 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[36] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_558 } ) , + .ccff_head ( cby_1__1__27_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_39_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_39_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_39_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_39_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_39_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_39_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_39_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_39_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[35] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_559 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[35] ) , + .ccff_tail ( grid_clb_39_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_560 ) , .SC_IN_BOT ( scff_Wires[87] ) , + .SC_OUT_TOP ( scff_Wires[88] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_561 ) , + .Test_en_E_in ( Test_enWires[95] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_562 ) , + .Test_en_W_out ( Test_enWires[96] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_563 ) , + .pReset_N_in ( pResetWires[223] ) , .Reset_E_in ( ResetWires[95] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_564 ) , + .Reset_W_out ( ResetWires[96] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_565 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_566 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[54] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[148] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[149] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_567 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_568 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_569 ) , + .clk_0_S_in ( clk_1_wires[54] ) ) ; +grid_clb grid_clb_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_570 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[37] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_571 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[37] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_572 } ) , + .ccff_head ( cby_1__1__28_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_40_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_40_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_40_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_40_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_40_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_40_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_40_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_40_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[36] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_573 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[36] ) , + .ccff_tail ( grid_clb_40_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_574 ) , .SC_IN_BOT ( scff_Wires[89] ) , + .SC_OUT_TOP ( scff_Wires[90] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_575 ) , + .Test_en_E_in ( Test_enWires[117] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_576 ) , + .Test_en_W_out ( Test_enWires[118] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_577 ) , + .pReset_N_in ( pResetWires[272] ) , .Reset_E_in ( ResetWires[117] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_578 ) , + .Reset_W_out ( ResetWires[118] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_579 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[62] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_580 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[151] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[152] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_581 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_582 ) , + .clk_0_N_in ( clk_1_wires[62] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) ) ; +grid_clb grid_clb_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_584 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[38] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_585 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[38] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_586 } ) , + .ccff_head ( cby_1__1__29_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_41_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_41_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_41_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_41_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_41_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_41_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_41_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_41_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[37] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_587 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[37] ) , + .ccff_tail ( grid_clb_41_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_588 ) , .SC_IN_BOT ( scff_Wires[91] ) , + .SC_OUT_TOP ( scff_Wires[92] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_589 ) , + .Test_en_E_in ( Test_enWires[139] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_590 ) , + .Test_en_W_out ( Test_enWires[140] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_591 ) , + .pReset_N_in ( pResetWires[321] ) , .Reset_E_in ( ResetWires[139] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_592 ) , + .Reset_W_out ( ResetWires[140] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_593 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_594 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[61] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[154] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[155] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_595 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_596 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_597 ) , + .clk_0_S_in ( clk_1_wires[61] ) ) ; +grid_clb grid_clb_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_598 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[39] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_599 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[39] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_600 } ) , + .ccff_head ( cby_1__1__30_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_42_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_42_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_42_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_42_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_42_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_42_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_42_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_42_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[38] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_601 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[38] ) , + .ccff_tail ( grid_clb_42_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_602 ) , .SC_IN_BOT ( scff_Wires[93] ) , + .SC_OUT_TOP ( scff_Wires[94] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_603 ) , + .Test_en_E_in ( Test_enWires[161] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_604 ) , + .Test_en_W_out ( Test_enWires[162] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_605 ) , + .pReset_N_in ( pResetWires[370] ) , .Reset_E_in ( ResetWires[161] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_606 ) , + .Reset_W_out ( ResetWires[162] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_607 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[69] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_608 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[157] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[158] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_609 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_610 ) , + .clk_0_N_in ( clk_1_wires[69] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) ) ; +grid_clb grid_clb_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_612 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[40] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_613 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[40] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_614 } ) , + .ccff_head ( cby_1__1__31_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_43_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_43_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_43_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_43_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_43_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_43_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_43_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_43_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[39] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_615 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[39] ) , + .ccff_tail ( grid_clb_43_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_616 ) , .SC_IN_BOT ( scff_Wires[95] ) , + .SC_OUT_TOP ( scff_Wires[96] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_617 ) , + .Test_en_E_in ( Test_enWires[183] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_618 ) , + .Test_en_W_out ( Test_enWires[184] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_619 ) , + .pReset_N_in ( pResetWires[419] ) , .Reset_E_in ( ResetWires[183] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_620 ) , + .Reset_W_out ( ResetWires[184] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_621 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_622 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[68] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[160] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[161] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_625 ) , + .clk_0_S_in ( clk_1_wires[68] ) ) ; +grid_clb grid_clb_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_626 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[41] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_627 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[41] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_628 } ) , + .ccff_head ( cby_1__1__32_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_44_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_44_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_44_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_44_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_44_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_44_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_44_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_44_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[40] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_629 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[40] ) , + .ccff_tail ( grid_clb_44_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_630 ) , .SC_IN_BOT ( scff_Wires[97] ) , + .SC_OUT_TOP ( scff_Wires[98] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_631 ) , + .Test_en_E_in ( Test_enWires[205] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_632 ) , + .Test_en_W_out ( Test_enWires[206] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_633 ) , + .pReset_N_in ( pResetWires[468] ) , .Reset_E_in ( ResetWires[205] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_634 ) , + .Reset_W_out ( ResetWires[206] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_635 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[76] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_636 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[163] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[164] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_637 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_638 ) , + .clk_0_N_in ( clk_1_wires[76] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) ) ; +grid_clb grid_clb_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_640 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[42] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_641 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[42] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_642 } ) , + .ccff_head ( cby_1__1__33_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_45_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_45_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_45_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_45_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_45_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_45_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_45_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_45_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[41] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_643 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[41] ) , + .ccff_tail ( grid_clb_45_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_644 ) , .SC_IN_BOT ( scff_Wires[99] ) , + .SC_OUT_TOP ( scff_Wires[100] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_645 ) , + .Test_en_E_in ( Test_enWires[227] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_646 ) , + .Test_en_W_out ( Test_enWires[228] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_647 ) , + .pReset_N_in ( pResetWires[517] ) , .Reset_E_in ( ResetWires[227] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_648 ) , + .Reset_W_out ( ResetWires[228] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_649 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_650 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[75] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[166] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[167] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_651 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_652 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_653 ) , + .clk_0_S_in ( clk_1_wires[75] ) ) ; +grid_clb grid_clb_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_654 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[43] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_655 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[43] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_656 } ) , + .ccff_head ( cby_1__1__34_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_46_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_46_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_46_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_46_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_46_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_46_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_46_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_46_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[42] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_657 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[42] ) , + .ccff_tail ( grid_clb_46_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_658 ) , .SC_IN_BOT ( scff_Wires[101] ) , + .SC_OUT_TOP ( scff_Wires[102] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_659 ) , + .Test_en_E_in ( Test_enWires[249] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_660 ) , + .Test_en_W_out ( Test_enWires[250] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_661 ) , + .pReset_N_in ( pResetWires[566] ) , .Reset_E_in ( ResetWires[249] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_662 ) , + .Reset_W_out ( ResetWires[250] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_663 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[83] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_664 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[169] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[170] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_665 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_666 ) , + .clk_0_N_in ( clk_1_wires[83] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) ) ; +grid_clb grid_clb_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_668 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_669 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_670 } ) , + .ccff_head ( cby_1__1__35_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_47_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_47_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_47_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_47_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_47_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_47_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_47_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_47_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[43] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_671 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[43] ) , + .ccff_tail ( grid_clb_47_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_672 ) , .SC_IN_BOT ( scff_Wires[103] ) , + .SC_OUT_TOP ( scff_Wires[104] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_673 ) , + .Test_en_E_in ( Test_enWires[271] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_674 ) , + .Test_en_W_out ( Test_enWires[272] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_675 ) , + .pReset_N_in ( pResetWires[612] ) , .Reset_E_in ( ResetWires[271] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_676 ) , + .Reset_W_out ( ResetWires[272] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_677 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_678 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[82] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[172] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[173] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_679 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[175] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_680 ) , + .clk_0_S_in ( clk_1_wires[82] ) ) ; +grid_clb grid_clb_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_681 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[44] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_682 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[44] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_683 } ) , + .ccff_head ( cby_1__1__36_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_48_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_48_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_48_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_48_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_48_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_48_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_48_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_48_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_684 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[129] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_685 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_686 ) , + .SC_OUT_BOT ( scff_Wires[131] ) , .Test_en_E_in ( Test_enWires[31] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_687 ) , + .Test_en_W_out ( Test_enWires[32] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_688 ) , + .pReset_N_in ( pResetWires[80] ) , .Reset_E_in ( ResetWires[31] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_689 ) , + .Reset_W_out ( ResetWires[32] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_690 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[88] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_691 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[177] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[178] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_692 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_693 ) , + .clk_0_N_in ( clk_1_wires[88] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) ) ; +grid_clb grid_clb_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_695 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[45] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[45] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_697 } ) , + .ccff_head ( cby_1__1__37_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_49_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_49_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_49_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_49_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_49_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_49_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_49_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_49_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[44] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_698 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[44] ) , + .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[127] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_699 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_700 ) , + .SC_OUT_BOT ( scff_Wires[128] ) , .Test_en_E_in ( Test_enWires[53] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_701 ) , + .Test_en_W_out ( Test_enWires[54] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_702 ) , + .pReset_N_in ( pResetWires[129] ) , .Reset_E_in ( ResetWires[53] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_703 ) , + .Reset_W_out ( ResetWires[54] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_704 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_705 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[87] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[180] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[181] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_706 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_707 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_708 ) , + .clk_0_S_in ( clk_1_wires[87] ) ) ; +grid_clb grid_clb_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_709 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[46] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_710 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[46] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_711 } ) , + .ccff_head ( cby_1__1__38_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_50_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_50_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_50_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_50_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_50_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_50_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_50_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_50_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[45] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_712 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[45] ) , + .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[125] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_713 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_714 ) , + .SC_OUT_BOT ( scff_Wires[126] ) , .Test_en_E_in ( Test_enWires[75] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_715 ) , + .Test_en_W_out ( Test_enWires[76] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_716 ) , + .pReset_N_in ( pResetWires[178] ) , .Reset_E_in ( ResetWires[75] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_717 ) , + .Reset_W_out ( ResetWires[76] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_718 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[95] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_719 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[183] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[184] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_720 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_721 ) , + .clk_0_N_in ( clk_1_wires[95] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) ) ; +grid_clb grid_clb_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_723 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[47] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_724 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[47] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_725 } ) , + .ccff_head ( cby_1__1__39_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_51_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_51_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_51_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_51_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_51_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_51_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_51_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_51_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[46] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_726 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[46] ) , + .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[123] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_727 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_728 ) , + .SC_OUT_BOT ( scff_Wires[124] ) , .Test_en_E_in ( Test_enWires[97] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_729 ) , + .Test_en_W_out ( Test_enWires[98] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_730 ) , + .pReset_N_in ( pResetWires[227] ) , .Reset_E_in ( ResetWires[97] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_731 ) , + .Reset_W_out ( ResetWires[98] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_732 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_733 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[94] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[186] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[187] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_734 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_735 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_736 ) , + .clk_0_S_in ( clk_1_wires[94] ) ) ; +grid_clb grid_clb_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_737 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[48] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_738 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[48] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_739 } ) , + .ccff_head ( cby_1__1__40_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_52_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_52_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_52_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_52_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_52_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_52_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_52_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_52_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[47] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_740 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[47] ) , + .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[121] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_741 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_742 ) , + .SC_OUT_BOT ( scff_Wires[122] ) , .Test_en_E_in ( Test_enWires[119] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_743 ) , + .Test_en_W_out ( Test_enWires[120] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_744 ) , + .pReset_N_in ( pResetWires[276] ) , .Reset_E_in ( ResetWires[119] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_745 ) , + .Reset_W_out ( ResetWires[120] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_746 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[102] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_747 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[189] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[190] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_748 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_749 ) , + .clk_0_N_in ( clk_1_wires[102] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) ) ; +grid_clb grid_clb_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_751 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[49] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_752 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[49] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_753 } ) , + .ccff_head ( cby_1__1__41_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_53_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_53_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_53_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_53_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_53_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_53_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_53_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_53_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[48] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_754 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[48] ) , + .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[119] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_755 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_756 ) , + .SC_OUT_BOT ( scff_Wires[120] ) , .Test_en_E_in ( Test_enWires[141] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_757 ) , + .Test_en_W_out ( Test_enWires[142] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_758 ) , + .pReset_N_in ( pResetWires[325] ) , .Reset_E_in ( ResetWires[141] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_759 ) , + .Reset_W_out ( ResetWires[142] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_760 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_761 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[101] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[192] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[193] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_764 ) , + .clk_0_S_in ( clk_1_wires[101] ) ) ; +grid_clb grid_clb_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_765 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[50] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_766 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[50] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_767 } ) , + .ccff_head ( cby_1__1__42_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_54_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_54_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_54_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_54_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_54_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_54_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_54_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_54_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[49] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_768 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[49] ) , + .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[117] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_769 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_770 ) , + .SC_OUT_BOT ( scff_Wires[118] ) , .Test_en_E_in ( Test_enWires[163] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_771 ) , + .Test_en_W_out ( Test_enWires[164] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_772 ) , + .pReset_N_in ( pResetWires[374] ) , .Reset_E_in ( ResetWires[163] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_773 ) , + .Reset_W_out ( ResetWires[164] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_774 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[109] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_775 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[195] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[196] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_776 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_777 ) , + .clk_0_N_in ( clk_1_wires[109] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) ) ; +grid_clb grid_clb_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_779 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[51] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_780 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[51] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_781 } ) , + .ccff_head ( cby_1__1__43_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_55_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_55_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_55_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_55_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_55_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_55_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_55_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_55_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[50] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_782 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[50] ) , + .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires[115] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_783 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_784 ) , + .SC_OUT_BOT ( scff_Wires[116] ) , .Test_en_E_in ( Test_enWires[185] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_785 ) , + .Test_en_W_out ( Test_enWires[186] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_786 ) , + .pReset_N_in ( pResetWires[423] ) , .Reset_E_in ( ResetWires[185] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_787 ) , + .Reset_W_out ( ResetWires[186] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_788 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_789 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[108] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[198] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[199] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_790 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_791 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_792 ) , + .clk_0_S_in ( clk_1_wires[108] ) ) ; +grid_clb grid_clb_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_793 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[52] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_794 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[52] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_795 } ) , + .ccff_head ( cby_1__1__44_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_56_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_56_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_56_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_56_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_56_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_56_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_56_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_56_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[51] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_796 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[51] ) , + .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires[113] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_797 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_798 ) , + .SC_OUT_BOT ( scff_Wires[114] ) , .Test_en_E_in ( Test_enWires[207] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_799 ) , + .Test_en_W_out ( Test_enWires[208] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_800 ) , + .pReset_N_in ( pResetWires[472] ) , .Reset_E_in ( ResetWires[207] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_801 ) , + .Reset_W_out ( ResetWires[208] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_802 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[116] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_803 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[201] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[202] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_804 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_805 ) , + .clk_0_N_in ( clk_1_wires[116] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) ) ; +grid_clb grid_clb_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_807 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[53] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_808 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[53] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_809 } ) , + .ccff_head ( cby_1__1__45_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_57_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_57_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_57_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_57_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_57_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_57_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_57_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_57_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[52] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_810 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[52] ) , + .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires[111] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_811 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_812 ) , + .SC_OUT_BOT ( scff_Wires[112] ) , .Test_en_E_in ( Test_enWires[229] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_813 ) , + .Test_en_W_out ( Test_enWires[230] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_814 ) , + .pReset_N_in ( pResetWires[521] ) , .Reset_E_in ( ResetWires[229] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_815 ) , + .Reset_W_out ( ResetWires[230] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_816 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_817 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[115] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[204] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[205] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_818 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_819 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_820 ) , + .clk_0_S_in ( clk_1_wires[115] ) ) ; +grid_clb grid_clb_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_821 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[54] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_822 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[54] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_823 } ) , + .ccff_head ( cby_1__1__46_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_58_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_58_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_58_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_58_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_58_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_58_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_58_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_58_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[53] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_824 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[53] ) , + .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires[109] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_825 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_826 ) , + .SC_OUT_BOT ( scff_Wires[110] ) , .Test_en_E_in ( Test_enWires[251] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_827 ) , + .Test_en_W_out ( Test_enWires[252] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_828 ) , + .pReset_N_in ( pResetWires[570] ) , .Reset_E_in ( ResetWires[251] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_829 ) , + .Reset_W_out ( ResetWires[252] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_830 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[123] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_831 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[207] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[208] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_833 ) , + .clk_0_N_in ( clk_1_wires[123] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) ) ; +grid_clb grid_clb_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_835 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_836 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_837 } ) , + .ccff_head ( cby_1__1__47_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_59_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_59_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_59_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_59_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_59_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_59_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_59_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_59_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[54] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_838 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[54] ) , + .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires[107] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_839 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_840 ) , + .SC_OUT_BOT ( scff_Wires[108] ) , .Test_en_E_in ( Test_enWires[273] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_841 ) , + .Test_en_W_out ( Test_enWires[274] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_842 ) , + .pReset_N_in ( pResetWires[615] ) , .Reset_E_in ( ResetWires[273] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_843 ) , + .Reset_W_out ( ResetWires[274] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_844 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_845 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[122] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[210] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[211] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_846 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[213] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_847 ) , + .clk_0_S_in ( clk_1_wires[122] ) ) ; +grid_clb grid_clb_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_848 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[55] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_849 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[55] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_850 } ) , + .ccff_head ( cby_1__1__48_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_60_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_60_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_60_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_60_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_60_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_60_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_60_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_60_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_851 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_60_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_852 ) , .SC_IN_BOT ( scff_Wires[134] ) , + .SC_OUT_TOP ( scff_Wires[135] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_853 ) , + .Test_en_E_in ( Test_enWires[33] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_854 ) , + .Test_en_W_out ( Test_enWires[34] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_855 ) , + .pReset_N_in ( pResetWires[84] ) , .Reset_E_in ( ResetWires[33] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_856 ) , + .Reset_W_out ( ResetWires[34] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_857 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[90] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_858 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[215] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[216] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_859 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_860 ) , + .clk_0_N_in ( clk_1_wires[90] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) ) ; +grid_clb grid_clb_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_862 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[56] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_863 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[56] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_864 } ) , + .ccff_head ( cby_1__1__49_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_61_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_61_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_61_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_61_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_61_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_61_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_61_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_61_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[55] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_865 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[55] ) , + .ccff_tail ( grid_clb_61_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_866 ) , .SC_IN_BOT ( scff_Wires[136] ) , + .SC_OUT_TOP ( scff_Wires[137] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_867 ) , + .Test_en_E_in ( Test_enWires[55] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_868 ) , + .Test_en_W_out ( Test_enWires[56] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_869 ) , + .pReset_N_in ( pResetWires[133] ) , .Reset_E_in ( ResetWires[55] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_870 ) , + .Reset_W_out ( ResetWires[56] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_871 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_872 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[89] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[218] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[219] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_873 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_874 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_875 ) , + .clk_0_S_in ( clk_1_wires[89] ) ) ; +grid_clb grid_clb_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_876 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[57] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_877 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[57] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_878 } ) , + .ccff_head ( cby_1__1__50_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_62_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_62_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_62_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_62_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_62_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_62_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_62_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_62_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[56] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_879 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[56] ) , + .ccff_tail ( grid_clb_62_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_880 ) , .SC_IN_BOT ( scff_Wires[138] ) , + .SC_OUT_TOP ( scff_Wires[139] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_881 ) , + .Test_en_E_in ( Test_enWires[77] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_882 ) , + .Test_en_W_out ( Test_enWires[78] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_883 ) , + .pReset_N_in ( pResetWires[182] ) , .Reset_E_in ( ResetWires[77] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_884 ) , + .Reset_W_out ( ResetWires[78] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_885 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[97] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_886 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[221] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[222] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_887 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_888 ) , + .clk_0_N_in ( clk_1_wires[97] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) ) ; +grid_clb grid_clb_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_890 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[58] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_891 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[58] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_892 } ) , + .ccff_head ( cby_1__1__51_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_63_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_63_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_63_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_63_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_63_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_63_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_63_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_63_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[57] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_893 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[57] ) , + .ccff_tail ( grid_clb_63_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_894 ) , .SC_IN_BOT ( scff_Wires[140] ) , + .SC_OUT_TOP ( scff_Wires[141] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_895 ) , + .Test_en_E_in ( Test_enWires[99] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_896 ) , + .Test_en_W_out ( Test_enWires[100] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_897 ) , + .pReset_N_in ( pResetWires[231] ) , .Reset_E_in ( ResetWires[99] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_898 ) , + .Reset_W_out ( ResetWires[100] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_899 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_900 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[96] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[224] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[225] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_903 ) , + .clk_0_S_in ( clk_1_wires[96] ) ) ; +grid_clb grid_clb_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_904 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[59] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_905 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[59] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_906 } ) , + .ccff_head ( cby_1__1__52_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_64_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_64_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_64_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_64_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_64_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_64_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_64_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_64_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[58] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_907 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[58] ) , + .ccff_tail ( grid_clb_64_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_908 ) , .SC_IN_BOT ( scff_Wires[142] ) , + .SC_OUT_TOP ( scff_Wires[143] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_909 ) , + .Test_en_E_in ( Test_enWires[121] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_910 ) , + .Test_en_W_out ( Test_enWires[122] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_911 ) , + .pReset_N_in ( pResetWires[280] ) , .Reset_E_in ( ResetWires[121] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_912 ) , + .Reset_W_out ( ResetWires[122] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_913 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[104] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_914 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[227] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[228] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_915 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_916 ) , + .clk_0_N_in ( clk_1_wires[104] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) ) ; +grid_clb grid_clb_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_918 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[60] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_919 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[60] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_920 } ) , + .ccff_head ( cby_1__1__53_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_65_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_65_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_65_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_65_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_65_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_65_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_65_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_65_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[59] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_921 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[59] ) , + .ccff_tail ( grid_clb_65_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_922 ) , .SC_IN_BOT ( scff_Wires[144] ) , + .SC_OUT_TOP ( scff_Wires[145] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_923 ) , + .Test_en_E_in ( Test_enWires[143] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_924 ) , + .Test_en_W_out ( Test_enWires[144] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_925 ) , + .pReset_N_in ( pResetWires[329] ) , .Reset_E_in ( ResetWires[143] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_926 ) , + .Reset_W_out ( ResetWires[144] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_927 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_928 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[103] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[230] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[231] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_929 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_930 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_931 ) , + .clk_0_S_in ( clk_1_wires[103] ) ) ; +grid_clb grid_clb_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_932 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[61] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_933 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[61] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_934 } ) , + .ccff_head ( cby_1__1__54_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_66_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_66_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_66_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_66_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_66_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_66_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_66_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_66_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[60] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_935 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[60] ) , + .ccff_tail ( grid_clb_66_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_936 ) , .SC_IN_BOT ( scff_Wires[146] ) , + .SC_OUT_TOP ( scff_Wires[147] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_937 ) , + .Test_en_E_in ( Test_enWires[165] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_938 ) , + .Test_en_W_out ( Test_enWires[166] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_939 ) , + .pReset_N_in ( pResetWires[378] ) , .Reset_E_in ( ResetWires[165] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_940 ) , + .Reset_W_out ( ResetWires[166] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_941 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[111] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_942 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[233] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[234] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_943 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_944 ) , + .clk_0_N_in ( clk_1_wires[111] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) ) ; +grid_clb grid_clb_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_946 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[62] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_947 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[62] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_948 } ) , + .ccff_head ( cby_1__1__55_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_67_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_67_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_67_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_67_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_67_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_67_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_67_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_67_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[61] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_949 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[61] ) , + .ccff_tail ( grid_clb_67_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_950 ) , .SC_IN_BOT ( scff_Wires[148] ) , + .SC_OUT_TOP ( scff_Wires[149] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_951 ) , + .Test_en_E_in ( Test_enWires[187] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_952 ) , + .Test_en_W_out ( Test_enWires[188] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_953 ) , + .pReset_N_in ( pResetWires[427] ) , .Reset_E_in ( ResetWires[187] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_954 ) , + .Reset_W_out ( ResetWires[188] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_955 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_956 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[110] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[236] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[237] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_957 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_958 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_959 ) , + .clk_0_S_in ( clk_1_wires[110] ) ) ; +grid_clb grid_clb_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_960 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[63] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_961 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[63] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_962 } ) , + .ccff_head ( cby_1__1__56_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_68_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_68_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_68_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_68_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_68_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_68_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_68_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_68_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[62] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_963 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[62] ) , + .ccff_tail ( grid_clb_68_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_964 ) , .SC_IN_BOT ( scff_Wires[150] ) , + .SC_OUT_TOP ( scff_Wires[151] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_965 ) , + .Test_en_E_in ( Test_enWires[209] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_966 ) , + .Test_en_W_out ( Test_enWires[210] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_967 ) , + .pReset_N_in ( pResetWires[476] ) , .Reset_E_in ( ResetWires[209] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_968 ) , + .Reset_W_out ( ResetWires[210] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_969 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[118] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_970 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[239] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[240] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_971 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_972 ) , + .clk_0_N_in ( clk_1_wires[118] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) ) ; +grid_clb grid_clb_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_974 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[64] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_975 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[64] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_976 } ) , + .ccff_head ( cby_1__1__57_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_69_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_69_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_69_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_69_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_69_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_69_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_69_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_69_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[63] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_977 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[63] ) , + .ccff_tail ( grid_clb_69_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_978 ) , .SC_IN_BOT ( scff_Wires[152] ) , + .SC_OUT_TOP ( scff_Wires[153] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_979 ) , + .Test_en_E_in ( Test_enWires[231] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_980 ) , + .Test_en_W_out ( Test_enWires[232] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_981 ) , + .pReset_N_in ( pResetWires[525] ) , .Reset_E_in ( ResetWires[231] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_982 ) , + .Reset_W_out ( ResetWires[232] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_983 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_984 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[117] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[242] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[243] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_985 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_986 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_987 ) , + .clk_0_S_in ( clk_1_wires[117] ) ) ; +grid_clb grid_clb_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_988 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[65] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_989 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[65] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_990 } ) , + .ccff_head ( cby_1__1__58_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_70_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_70_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_70_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_70_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_70_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_70_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_70_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_70_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[64] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_991 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[64] ) , + .ccff_tail ( grid_clb_70_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_992 ) , .SC_IN_BOT ( scff_Wires[154] ) , + .SC_OUT_TOP ( scff_Wires[155] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_993 ) , + .Test_en_E_in ( Test_enWires[253] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_994 ) , + .Test_en_W_out ( Test_enWires[254] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_995 ) , + .pReset_N_in ( pResetWires[574] ) , .Reset_E_in ( ResetWires[253] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_996 ) , + .Reset_W_out ( ResetWires[254] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_997 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[125] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_998 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[245] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[246] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_999 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1000 ) , + .clk_0_N_in ( clk_1_wires[125] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) ) ; +grid_clb grid_clb_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1002 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1003 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1004 } ) , + .ccff_head ( cby_1__1__59_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_71_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_71_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_71_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_71_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_71_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_71_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_71_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_71_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[65] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1005 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[65] ) , + .ccff_tail ( grid_clb_71_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1006 ) , + .SC_IN_BOT ( scff_Wires[156] ) , .SC_OUT_TOP ( scff_Wires[157] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1007 ) , + .Test_en_E_in ( Test_enWires[275] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_1008 ) , + .Test_en_W_out ( Test_enWires[276] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1009 ) , + .pReset_N_in ( pResetWires[618] ) , .Reset_E_in ( ResetWires[275] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_1010 ) , + .Reset_W_out ( ResetWires[276] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1011 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1012 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[124] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[248] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[249] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1013 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[251] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1014 ) , + .clk_0_S_in ( clk_1_wires[124] ) ) ; +grid_clb grid_clb_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1015 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[66] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1016 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[66] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1017 } ) , + .ccff_head ( cby_1__1__60_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_72_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_72_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_72_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_72_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_72_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_72_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_72_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_72_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1018 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[182] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1019 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1020 ) , + .SC_OUT_BOT ( scff_Wires[184] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1021 ) , + .Test_en_W_in ( Test_enWires[35] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1022 ) , + .Test_en_E_out ( Test_enWires[36] ) , .pReset_N_in ( pResetWires[88] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1023 ) , + .Reset_W_in ( ResetWires[35] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1024 ) , + .Reset_E_out ( ResetWires[36] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[130] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1025 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[253] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[254] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1026 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1027 ) , + .clk_0_N_in ( clk_1_wires[130] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) ) ; +grid_clb grid_clb_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1029 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[67] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1030 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[67] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1031 } ) , + .ccff_head ( cby_1__1__61_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_73_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_73_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_73_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_73_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_73_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_73_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_73_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_73_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[66] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1032 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[66] ) , + .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[180] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1033 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1034 ) , + .SC_OUT_BOT ( scff_Wires[181] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1035 ) , + .Test_en_W_in ( Test_enWires[57] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1036 ) , + .Test_en_E_out ( Test_enWires[58] ) , .pReset_N_in ( pResetWires[137] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1037 ) , + .Reset_W_in ( ResetWires[57] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1038 ) , + .Reset_E_out ( ResetWires[58] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1039 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[129] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[256] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[257] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1042 ) , + .clk_0_S_in ( clk_1_wires[129] ) ) ; +grid_clb grid_clb_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1043 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[68] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1044 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[68] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1045 } ) , + .ccff_head ( cby_1__1__62_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_74_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_74_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_74_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_74_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_74_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_74_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_74_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_74_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[67] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1046 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[67] ) , + .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[178] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1047 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1048 ) , + .SC_OUT_BOT ( scff_Wires[179] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1049 ) , + .Test_en_W_in ( Test_enWires[79] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1050 ) , + .Test_en_E_out ( Test_enWires[80] ) , .pReset_N_in ( pResetWires[186] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1051 ) , + .Reset_W_in ( ResetWires[79] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1052 ) , + .Reset_E_out ( ResetWires[80] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[137] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1053 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[259] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[260] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1054 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1055 ) , + .clk_0_N_in ( clk_1_wires[137] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) ) ; +grid_clb grid_clb_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1057 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[69] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1058 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[69] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1059 } ) , + .ccff_head ( cby_1__1__63_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_75_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_75_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_75_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_75_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_75_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_75_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_75_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_75_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[68] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1060 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[68] ) , + .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[176] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1061 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1062 ) , + .SC_OUT_BOT ( scff_Wires[177] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1063 ) , + .Test_en_W_in ( Test_enWires[101] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1064 ) , + .Test_en_E_out ( Test_enWires[102] ) , .pReset_N_in ( pResetWires[235] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1065 ) , + .Reset_W_in ( ResetWires[101] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1066 ) , + .Reset_E_out ( ResetWires[102] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1067 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[136] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[262] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[263] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1068 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1069 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1070 ) , + .clk_0_S_in ( clk_1_wires[136] ) ) ; +grid_clb grid_clb_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1071 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[70] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1072 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[70] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1073 } ) , + .ccff_head ( cby_1__1__64_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_76_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_76_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_76_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_76_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_76_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_76_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_76_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_76_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[69] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1074 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[69] ) , + .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[174] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1075 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1076 ) , + .SC_OUT_BOT ( scff_Wires[175] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1077 ) , + .Test_en_W_in ( Test_enWires[123] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1078 ) , + .Test_en_E_out ( Test_enWires[124] ) , .pReset_N_in ( pResetWires[284] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1079 ) , + .Reset_W_in ( ResetWires[123] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1080 ) , + .Reset_E_out ( ResetWires[124] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[144] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1081 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[265] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[266] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1082 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1083 ) , + .clk_0_N_in ( clk_1_wires[144] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) ) ; +grid_clb grid_clb_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1085 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[71] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1086 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[71] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1087 } ) , + .ccff_head ( cby_1__1__65_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_77_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_77_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_77_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_77_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_77_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_77_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_77_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_77_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[70] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1088 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[70] ) , + .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires[172] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1089 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1090 ) , + .SC_OUT_BOT ( scff_Wires[173] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1091 ) , + .Test_en_W_in ( Test_enWires[145] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1092 ) , + .Test_en_E_out ( Test_enWires[146] ) , .pReset_N_in ( pResetWires[333] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1093 ) , + .Reset_W_in ( ResetWires[145] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1094 ) , + .Reset_E_out ( ResetWires[146] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1095 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[143] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[268] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[269] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1096 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1097 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1098 ) , + .clk_0_S_in ( clk_1_wires[143] ) ) ; +grid_clb grid_clb_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1099 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[72] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1100 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[72] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1101 } ) , + .ccff_head ( cby_1__1__66_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_78_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_78_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_78_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_78_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_78_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_78_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_78_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_78_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[71] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1102 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[71] ) , + .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires[170] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1103 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1104 ) , + .SC_OUT_BOT ( scff_Wires[171] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1105 ) , + .Test_en_W_in ( Test_enWires[167] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1106 ) , + .Test_en_E_out ( Test_enWires[168] ) , .pReset_N_in ( pResetWires[382] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1107 ) , + .Reset_W_in ( ResetWires[167] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1108 ) , + .Reset_E_out ( ResetWires[168] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[151] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1109 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[271] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[272] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1110 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1111 ) , + .clk_0_N_in ( clk_1_wires[151] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) ) ; +grid_clb grid_clb_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1113 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[73] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1114 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[73] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1115 } ) , + .ccff_head ( cby_1__1__67_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_79_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_79_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_79_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_79_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_79_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_79_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_79_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_79_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[72] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1116 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[72] ) , + .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires[168] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1117 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1118 ) , + .SC_OUT_BOT ( scff_Wires[169] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1119 ) , + .Test_en_W_in ( Test_enWires[189] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1120 ) , + .Test_en_E_out ( Test_enWires[190] ) , .pReset_N_in ( pResetWires[431] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1121 ) , + .Reset_W_in ( ResetWires[189] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1122 ) , + .Reset_E_out ( ResetWires[190] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1123 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[150] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[274] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[275] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1124 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1125 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1126 ) , + .clk_0_S_in ( clk_1_wires[150] ) ) ; +grid_clb grid_clb_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1127 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[74] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1128 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[74] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1129 } ) , + .ccff_head ( cby_1__1__68_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_80_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_80_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_80_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_80_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_80_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_80_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_80_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_80_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[73] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1130 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[73] ) , + .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires[166] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1131 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1132 ) , + .SC_OUT_BOT ( scff_Wires[167] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1133 ) , + .Test_en_W_in ( Test_enWires[211] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1134 ) , + .Test_en_E_out ( Test_enWires[212] ) , .pReset_N_in ( pResetWires[480] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1135 ) , + .Reset_W_in ( ResetWires[211] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1136 ) , + .Reset_E_out ( ResetWires[212] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[158] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1137 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[277] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[278] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1138 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1139 ) , + .clk_0_N_in ( clk_1_wires[158] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) ) ; +grid_clb grid_clb_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1141 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[75] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1142 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[75] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1143 } ) , + .ccff_head ( cby_1__1__69_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_81_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_81_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_81_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_81_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_81_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_81_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_81_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_81_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[74] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1144 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[74] ) , + .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires[164] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1145 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1146 ) , + .SC_OUT_BOT ( scff_Wires[165] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1147 ) , + .Test_en_W_in ( Test_enWires[233] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1148 ) , + .Test_en_E_out ( Test_enWires[234] ) , .pReset_N_in ( pResetWires[529] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1149 ) , + .Reset_W_in ( ResetWires[233] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1150 ) , + .Reset_E_out ( ResetWires[234] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1151 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[157] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[280] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[281] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1152 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1153 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1154 ) , + .clk_0_S_in ( clk_1_wires[157] ) ) ; +grid_clb grid_clb_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1155 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[76] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1156 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[76] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1157 } ) , + .ccff_head ( cby_1__1__70_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_82_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_82_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_82_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_82_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_82_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_82_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_82_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_82_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[75] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1158 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[75] ) , + .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires[162] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1159 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1160 ) , + .SC_OUT_BOT ( scff_Wires[163] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1161 ) , + .Test_en_W_in ( Test_enWires[255] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1162 ) , + .Test_en_E_out ( Test_enWires[256] ) , .pReset_N_in ( pResetWires[578] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1163 ) , + .Reset_W_in ( ResetWires[255] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1164 ) , + .Reset_E_out ( ResetWires[256] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[165] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1165 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[283] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[284] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1166 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1167 ) , + .clk_0_N_in ( clk_1_wires[165] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) ) ; +grid_clb grid_clb_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1169 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1170 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1171 } ) , + .ccff_head ( cby_1__1__71_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_83_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_83_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_83_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_83_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_83_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_83_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_83_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_83_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[76] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1172 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[76] ) , + .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires[160] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1173 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1174 ) , + .SC_OUT_BOT ( scff_Wires[161] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1175 ) , + .Test_en_W_in ( Test_enWires[277] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1176 ) , + .Test_en_E_out ( Test_enWires[278] ) , .pReset_N_in ( pResetWires[621] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1177 ) , + .Reset_W_in ( ResetWires[277] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1178 ) , + .Reset_E_out ( ResetWires[278] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1179 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[164] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[286] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[287] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1180 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[289] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1181 ) , + .clk_0_S_in ( clk_1_wires[164] ) ) ; +grid_clb grid_clb_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1182 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[77] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1183 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[77] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1184 } ) , + .ccff_head ( cby_1__1__72_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_84_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_84_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_84_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_84_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_84_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_84_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_84_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_84_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1185 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_84_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1186 ) , + .SC_IN_BOT ( scff_Wires[187] ) , .SC_OUT_TOP ( scff_Wires[188] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1187 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1188 ) , + .Test_en_W_in ( Test_enWires[37] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1189 ) , + .Test_en_E_out ( Test_enWires[38] ) , .pReset_N_in ( pResetWires[92] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1190 ) , + .Reset_W_in ( ResetWires[37] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1191 ) , + .Reset_E_out ( ResetWires[38] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[132] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1192 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[291] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[292] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1193 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1194 ) , + .clk_0_N_in ( clk_1_wires[132] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) ) ; +grid_clb grid_clb_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1196 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[78] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1197 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[78] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1198 } ) , + .ccff_head ( cby_1__1__73_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_85_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_85_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_85_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_85_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_85_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_85_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_85_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_85_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[77] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1199 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[77] ) , + .ccff_tail ( grid_clb_85_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1200 ) , + .SC_IN_BOT ( scff_Wires[189] ) , .SC_OUT_TOP ( scff_Wires[190] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1201 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1202 ) , + .Test_en_W_in ( Test_enWires[59] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1203 ) , + .Test_en_E_out ( Test_enWires[60] ) , .pReset_N_in ( pResetWires[141] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1204 ) , + .Reset_W_in ( ResetWires[59] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1205 ) , + .Reset_E_out ( ResetWires[60] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1206 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[131] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[294] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[295] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1207 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1208 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1209 ) , + .clk_0_S_in ( clk_1_wires[131] ) ) ; +grid_clb grid_clb_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1210 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[79] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1211 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[79] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1212 } ) , + .ccff_head ( cby_1__1__74_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_86_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_86_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_86_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_86_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_86_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_86_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_86_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_86_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[78] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1213 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[78] ) , + .ccff_tail ( grid_clb_86_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1214 ) , + .SC_IN_BOT ( scff_Wires[191] ) , .SC_OUT_TOP ( scff_Wires[192] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1215 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1216 ) , + .Test_en_W_in ( Test_enWires[81] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1217 ) , + .Test_en_E_out ( Test_enWires[82] ) , .pReset_N_in ( pResetWires[190] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1218 ) , + .Reset_W_in ( ResetWires[81] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1219 ) , + .Reset_E_out ( ResetWires[82] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[139] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1220 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[297] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[298] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1221 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1222 ) , + .clk_0_N_in ( clk_1_wires[139] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) ) ; +grid_clb grid_clb_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1224 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[80] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1225 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[80] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1226 } ) , + .ccff_head ( cby_1__1__75_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_87_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_87_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_87_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_87_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_87_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_87_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_87_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_87_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[79] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1227 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[79] ) , + .ccff_tail ( grid_clb_87_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1228 ) , + .SC_IN_BOT ( scff_Wires[193] ) , .SC_OUT_TOP ( scff_Wires[194] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1229 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1230 ) , + .Test_en_W_in ( Test_enWires[103] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1231 ) , + .Test_en_E_out ( Test_enWires[104] ) , .pReset_N_in ( pResetWires[239] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1232 ) , + .Reset_W_in ( ResetWires[103] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1233 ) , + .Reset_E_out ( ResetWires[104] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1234 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[138] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[300] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[301] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1235 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1236 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1237 ) , + .clk_0_S_in ( clk_1_wires[138] ) ) ; +grid_clb grid_clb_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1238 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[81] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1239 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[81] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1240 } ) , + .ccff_head ( cby_1__1__76_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_88_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_88_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_88_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_88_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_88_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_88_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_88_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_88_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[80] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1241 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[80] ) , + .ccff_tail ( grid_clb_88_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1242 ) , + .SC_IN_BOT ( scff_Wires[195] ) , .SC_OUT_TOP ( scff_Wires[196] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1243 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1244 ) , + .Test_en_W_in ( Test_enWires[125] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1245 ) , + .Test_en_E_out ( Test_enWires[126] ) , .pReset_N_in ( pResetWires[288] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1246 ) , + .Reset_W_in ( ResetWires[125] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1247 ) , + .Reset_E_out ( ResetWires[126] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[146] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1248 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[303] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[304] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1249 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1250 ) , + .clk_0_N_in ( clk_1_wires[146] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) ) ; +grid_clb grid_clb_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1252 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[82] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1253 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[82] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1254 } ) , + .ccff_head ( cby_1__1__77_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_89_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_89_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_89_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_89_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_89_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_89_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_89_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_89_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[81] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1255 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[81] ) , + .ccff_tail ( grid_clb_89_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1256 ) , + .SC_IN_BOT ( scff_Wires[197] ) , .SC_OUT_TOP ( scff_Wires[198] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1257 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1258 ) , + .Test_en_W_in ( Test_enWires[147] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1259 ) , + .Test_en_E_out ( Test_enWires[148] ) , .pReset_N_in ( pResetWires[337] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1260 ) , + .Reset_W_in ( ResetWires[147] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1261 ) , + .Reset_E_out ( ResetWires[148] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1262 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[145] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[306] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[307] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1263 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1264 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1265 ) , + .clk_0_S_in ( clk_1_wires[145] ) ) ; +grid_clb grid_clb_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1266 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[83] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1267 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[83] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1268 } ) , + .ccff_head ( cby_1__1__78_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_90_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_90_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_90_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_90_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_90_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_90_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_90_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_90_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[82] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1269 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[82] ) , + .ccff_tail ( grid_clb_90_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1270 ) , + .SC_IN_BOT ( scff_Wires[199] ) , .SC_OUT_TOP ( scff_Wires[200] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1272 ) , + .Test_en_W_in ( Test_enWires[169] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1273 ) , + .Test_en_E_out ( Test_enWires[170] ) , .pReset_N_in ( pResetWires[386] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1274 ) , + .Reset_W_in ( ResetWires[169] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1275 ) , + .Reset_E_out ( ResetWires[170] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[153] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1276 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[309] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[310] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1277 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1278 ) , + .clk_0_N_in ( clk_1_wires[153] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) ) ; +grid_clb grid_clb_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1280 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[84] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1281 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[84] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1282 } ) , + .ccff_head ( cby_1__1__79_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_91_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_91_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_91_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_91_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_91_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_91_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_91_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_91_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[83] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1283 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[83] ) , + .ccff_tail ( grid_clb_91_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1284 ) , + .SC_IN_BOT ( scff_Wires[201] ) , .SC_OUT_TOP ( scff_Wires[202] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1285 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1286 ) , + .Test_en_W_in ( Test_enWires[191] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1287 ) , + .Test_en_E_out ( Test_enWires[192] ) , .pReset_N_in ( pResetWires[435] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1288 ) , + .Reset_W_in ( ResetWires[191] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1289 ) , + .Reset_E_out ( ResetWires[192] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1290 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[152] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[312] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[313] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1291 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1292 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1293 ) , + .clk_0_S_in ( clk_1_wires[152] ) ) ; +grid_clb grid_clb_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1294 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[85] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1295 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[85] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1296 } ) , + .ccff_head ( cby_1__1__80_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_92_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_92_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_92_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_92_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_92_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_92_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_92_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_92_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[84] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1297 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[84] ) , + .ccff_tail ( grid_clb_92_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1298 ) , + .SC_IN_BOT ( scff_Wires[203] ) , .SC_OUT_TOP ( scff_Wires[204] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1299 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1300 ) , + .Test_en_W_in ( Test_enWires[213] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1301 ) , + .Test_en_E_out ( Test_enWires[214] ) , .pReset_N_in ( pResetWires[484] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1302 ) , + .Reset_W_in ( ResetWires[213] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1303 ) , + .Reset_E_out ( ResetWires[214] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[160] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1304 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[315] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[316] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1305 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1306 ) , + .clk_0_N_in ( clk_1_wires[160] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) ) ; +grid_clb grid_clb_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1308 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[86] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1309 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[86] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1310 } ) , + .ccff_head ( cby_1__1__81_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_93_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_93_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_93_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_93_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_93_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_93_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_93_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_93_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[85] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1311 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[85] ) , + .ccff_tail ( grid_clb_93_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1312 ) , + .SC_IN_BOT ( scff_Wires[205] ) , .SC_OUT_TOP ( scff_Wires[206] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1313 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1314 ) , + .Test_en_W_in ( Test_enWires[235] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1315 ) , + .Test_en_E_out ( Test_enWires[236] ) , .pReset_N_in ( pResetWires[533] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1316 ) , + .Reset_W_in ( ResetWires[235] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1317 ) , + .Reset_E_out ( ResetWires[236] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1318 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[159] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[318] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[319] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1319 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1320 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1321 ) , + .clk_0_S_in ( clk_1_wires[159] ) ) ; +grid_clb grid_clb_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1322 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[87] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1323 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[87] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1324 } ) , + .ccff_head ( cby_1__1__82_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_94_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_94_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_94_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_94_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_94_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_94_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_94_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_94_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[86] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1325 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[86] ) , + .ccff_tail ( grid_clb_94_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1326 ) , + .SC_IN_BOT ( scff_Wires[207] ) , .SC_OUT_TOP ( scff_Wires[208] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1327 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1328 ) , + .Test_en_W_in ( Test_enWires[257] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1329 ) , + .Test_en_E_out ( Test_enWires[258] ) , .pReset_N_in ( pResetWires[582] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1330 ) , + .Reset_W_in ( ResetWires[257] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1331 ) , + .Reset_E_out ( ResetWires[258] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[167] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1332 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[321] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[322] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1333 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1334 ) , + .clk_0_N_in ( clk_1_wires[167] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) ) ; +grid_clb grid_clb_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1336 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1337 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1338 } ) , + .ccff_head ( cby_1__1__83_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_95_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_95_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_95_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_95_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_95_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_95_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_95_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_95_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[87] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1339 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[87] ) , + .ccff_tail ( grid_clb_95_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1340 ) , + .SC_IN_BOT ( scff_Wires[209] ) , .SC_OUT_TOP ( scff_Wires[210] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1341 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1342 ) , + .Test_en_W_in ( Test_enWires[279] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1343 ) , + .Test_en_E_out ( Test_enWires[280] ) , .pReset_N_in ( pResetWires[624] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1344 ) , + .Reset_W_in ( ResetWires[279] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1345 ) , + .Reset_E_out ( ResetWires[280] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1346 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[166] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[324] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[325] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1347 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[327] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1348 ) , + .clk_0_S_in ( clk_1_wires[166] ) ) ; +grid_clb grid_clb_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1349 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[88] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1350 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[88] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1351 } ) , + .ccff_head ( cby_1__1__84_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_96_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_96_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_96_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_96_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_96_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_96_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_96_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_96_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1352 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[235] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1353 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1354 ) , + .SC_OUT_BOT ( scff_Wires[237] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1355 ) , + .Test_en_W_in ( Test_enWires[39] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1356 ) , + .Test_en_E_out ( Test_enWires[40] ) , .pReset_N_in ( pResetWires[96] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1357 ) , + .Reset_W_in ( ResetWires[39] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1358 ) , + .Reset_E_out ( ResetWires[40] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[172] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1359 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[329] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[330] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1360 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1361 ) , + .clk_0_N_in ( clk_1_wires[172] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) ) ; +grid_clb grid_clb_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1363 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[89] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1364 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[89] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1365 } ) , + .ccff_head ( cby_1__1__85_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_97_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_97_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_97_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_97_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_97_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_97_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_97_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_97_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[88] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1366 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[88] ) , + .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[233] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1367 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1368 ) , + .SC_OUT_BOT ( scff_Wires[234] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1369 ) , + .Test_en_W_in ( Test_enWires[61] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1370 ) , + .Test_en_E_out ( Test_enWires[62] ) , .pReset_N_in ( pResetWires[145] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1371 ) , + .Reset_W_in ( ResetWires[61] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1372 ) , + .Reset_E_out ( ResetWires[62] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1373 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[171] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[332] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[333] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1374 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1375 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1376 ) , + .clk_0_S_in ( clk_1_wires[171] ) ) ; +grid_clb grid_clb_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1377 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[90] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1378 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[90] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1379 } ) , + .ccff_head ( cby_1__1__86_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_98_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_98_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_98_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_98_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_98_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_98_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_98_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_98_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[89] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1380 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[89] ) , + .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[231] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1381 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1382 ) , + .SC_OUT_BOT ( scff_Wires[232] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1383 ) , + .Test_en_W_in ( Test_enWires[83] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1384 ) , + .Test_en_E_out ( Test_enWires[84] ) , .pReset_N_in ( pResetWires[194] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1385 ) , + .Reset_W_in ( ResetWires[83] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1386 ) , + .Reset_E_out ( ResetWires[84] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[179] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1387 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[335] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[336] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1388 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1389 ) , + .clk_0_N_in ( clk_1_wires[179] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) ) ; +grid_clb grid_clb_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1391 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[91] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1392 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[91] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1393 } ) , + .ccff_head ( cby_1__1__87_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_99_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_99_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_99_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_99_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_99_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_99_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_99_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_99_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[90] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1394 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[90] ) , + .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires[229] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1395 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1396 ) , + .SC_OUT_BOT ( scff_Wires[230] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1397 ) , + .Test_en_W_in ( Test_enWires[105] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1398 ) , + .Test_en_E_out ( Test_enWires[106] ) , .pReset_N_in ( pResetWires[243] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1399 ) , + .Reset_W_in ( ResetWires[105] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1400 ) , + .Reset_E_out ( ResetWires[106] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1401 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[178] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[338] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[339] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1402 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1403 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1404 ) , + .clk_0_S_in ( clk_1_wires[178] ) ) ; +grid_clb grid_clb_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1405 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[92] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1406 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[92] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1407 } ) , + .ccff_head ( cby_1__1__88_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_100_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_100_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_100_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_100_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_100_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_100_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_100_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_100_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[91] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1408 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[91] ) , + .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires[227] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1409 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1410 ) , + .SC_OUT_BOT ( scff_Wires[228] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1411 ) , + .Test_en_W_in ( Test_enWires[127] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1412 ) , + .Test_en_E_out ( Test_enWires[128] ) , .pReset_N_in ( pResetWires[292] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1413 ) , + .Reset_W_in ( ResetWires[127] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1414 ) , + .Reset_E_out ( ResetWires[128] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[186] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1415 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[341] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[342] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1416 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1417 ) , + .clk_0_N_in ( clk_1_wires[186] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) ) ; +grid_clb grid_clb_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1419 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[93] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1420 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[93] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1421 } ) , + .ccff_head ( cby_1__1__89_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_101_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_101_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_101_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_101_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_101_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_101_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_101_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_101_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[92] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1422 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[92] ) , + .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires[225] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1423 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1424 ) , + .SC_OUT_BOT ( scff_Wires[226] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1425 ) , + .Test_en_W_in ( Test_enWires[149] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1426 ) , + .Test_en_E_out ( Test_enWires[150] ) , .pReset_N_in ( pResetWires[341] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1427 ) , + .Reset_W_in ( ResetWires[149] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1428 ) , + .Reset_E_out ( ResetWires[150] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1429 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[185] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[344] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[345] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1430 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1431 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1432 ) , + .clk_0_S_in ( clk_1_wires[185] ) ) ; +grid_clb grid_clb_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1433 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[94] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1434 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[94] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1435 } ) , + .ccff_head ( cby_1__1__90_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_102_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_102_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_102_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_102_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_102_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_102_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_102_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_102_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[93] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1436 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[93] ) , + .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires[223] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1437 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1438 ) , + .SC_OUT_BOT ( scff_Wires[224] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1439 ) , + .Test_en_W_in ( Test_enWires[171] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1440 ) , + .Test_en_E_out ( Test_enWires[172] ) , .pReset_N_in ( pResetWires[390] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1441 ) , + .Reset_W_in ( ResetWires[171] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1442 ) , + .Reset_E_out ( ResetWires[172] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[193] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1443 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[347] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[348] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1444 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1445 ) , + .clk_0_N_in ( clk_1_wires[193] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) ) ; +grid_clb grid_clb_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1447 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[95] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1448 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[95] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1449 } ) , + .ccff_head ( cby_1__1__91_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_103_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_103_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_103_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_103_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_103_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_103_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_103_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_103_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[94] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1450 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[94] ) , + .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires[221] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1451 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1452 ) , + .SC_OUT_BOT ( scff_Wires[222] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1453 ) , + .Test_en_W_in ( Test_enWires[193] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1454 ) , + .Test_en_E_out ( Test_enWires[194] ) , .pReset_N_in ( pResetWires[439] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1455 ) , + .Reset_W_in ( ResetWires[193] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1456 ) , + .Reset_E_out ( ResetWires[194] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1457 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[192] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[350] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[351] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1458 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1459 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1460 ) , + .clk_0_S_in ( clk_1_wires[192] ) ) ; +grid_clb grid_clb_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1461 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[96] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1462 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[96] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1463 } ) , + .ccff_head ( cby_1__1__92_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_104_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_104_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_104_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_104_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_104_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_104_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_104_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_104_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[95] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1464 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[95] ) , + .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires[219] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1465 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1466 ) , + .SC_OUT_BOT ( scff_Wires[220] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1467 ) , + .Test_en_W_in ( Test_enWires[215] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1468 ) , + .Test_en_E_out ( Test_enWires[216] ) , .pReset_N_in ( pResetWires[488] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1469 ) , + .Reset_W_in ( ResetWires[215] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1470 ) , + .Reset_E_out ( ResetWires[216] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[200] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1471 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[353] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[354] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1472 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1473 ) , + .clk_0_N_in ( clk_1_wires[200] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) ) ; +grid_clb grid_clb_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1475 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[97] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1476 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[97] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1477 } ) , + .ccff_head ( cby_1__1__93_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_105_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_105_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_105_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_105_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_105_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_105_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_105_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_105_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[96] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1478 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[96] ) , + .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires[217] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1479 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1480 ) , + .SC_OUT_BOT ( scff_Wires[218] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1481 ) , + .Test_en_W_in ( Test_enWires[237] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1482 ) , + .Test_en_E_out ( Test_enWires[238] ) , .pReset_N_in ( pResetWires[537] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1483 ) , + .Reset_W_in ( ResetWires[237] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1484 ) , + .Reset_E_out ( ResetWires[238] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1485 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[199] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[356] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[357] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1486 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1487 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1488 ) , + .clk_0_S_in ( clk_1_wires[199] ) ) ; +grid_clb grid_clb_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1489 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[98] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1490 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[98] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1491 } ) , + .ccff_head ( cby_1__1__94_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_106_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_106_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_106_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_106_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_106_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_106_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_106_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_106_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[97] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1492 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[97] ) , + .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires[215] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1493 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1494 ) , + .SC_OUT_BOT ( scff_Wires[216] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1495 ) , + .Test_en_W_in ( Test_enWires[259] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1496 ) , + .Test_en_E_out ( Test_enWires[260] ) , .pReset_N_in ( pResetWires[586] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1497 ) , + .Reset_W_in ( ResetWires[259] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1498 ) , + .Reset_E_out ( ResetWires[260] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[207] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1499 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[359] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[360] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1500 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1501 ) , + .clk_0_N_in ( clk_1_wires[207] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) ) ; +grid_clb grid_clb_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1503 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1504 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1505 } ) , + .ccff_head ( cby_1__1__95_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_107_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_107_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_107_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_107_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_107_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_107_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_107_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_107_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[98] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1506 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[98] ) , + .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires[213] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1507 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1508 ) , + .SC_OUT_BOT ( scff_Wires[214] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1509 ) , + .Test_en_W_in ( Test_enWires[281] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1510 ) , + .Test_en_E_out ( Test_enWires[282] ) , .pReset_N_in ( pResetWires[627] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1511 ) , + .Reset_W_in ( ResetWires[281] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1512 ) , + .Reset_E_out ( ResetWires[282] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1513 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[206] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[362] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[363] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1514 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[365] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1515 ) , + .clk_0_S_in ( clk_1_wires[206] ) ) ; +grid_clb grid_clb_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1516 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[99] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1517 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[99] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1518 } ) , + .ccff_head ( cby_1__1__96_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_108_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_108_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_108_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_108_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_108_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_108_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_108_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_108_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1519 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_108_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1520 ) , + .SC_IN_BOT ( scff_Wires[240] ) , .SC_OUT_TOP ( scff_Wires[241] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1521 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1522 ) , + .Test_en_W_in ( Test_enWires[41] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1523 ) , + .Test_en_E_out ( Test_enWires[42] ) , .pReset_N_in ( pResetWires[100] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1524 ) , + .Reset_W_in ( ResetWires[41] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1525 ) , + .Reset_E_out ( ResetWires[42] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[174] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1526 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[367] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[368] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1527 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1528 ) , + .clk_0_N_in ( clk_1_wires[174] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) ) ; +grid_clb grid_clb_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1530 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[100] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1531 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[100] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1532 } ) , + .ccff_head ( cby_1__1__97_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_109_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_109_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_109_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_109_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_109_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_109_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_109_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_109_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[99] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1533 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[99] ) , + .ccff_tail ( grid_clb_109_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1534 ) , + .SC_IN_BOT ( scff_Wires[242] ) , .SC_OUT_TOP ( scff_Wires[243] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1535 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1536 ) , + .Test_en_W_in ( Test_enWires[63] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1537 ) , + .Test_en_E_out ( Test_enWires[64] ) , .pReset_N_in ( pResetWires[149] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1538 ) , + .Reset_W_in ( ResetWires[63] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1539 ) , + .Reset_E_out ( ResetWires[64] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1540 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[173] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[370] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[371] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1541 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1542 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1543 ) , + .clk_0_S_in ( clk_1_wires[173] ) ) ; +grid_clb grid_clb_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1544 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[101] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1545 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[101] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1546 } ) , + .ccff_head ( cby_1__1__98_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_110_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_110_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_110_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_110_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_110_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_110_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_110_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_110_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[100] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1547 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[100] ) , + .ccff_tail ( grid_clb_110_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1548 ) , + .SC_IN_BOT ( scff_Wires[244] ) , .SC_OUT_TOP ( scff_Wires[245] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1549 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1550 ) , + .Test_en_W_in ( Test_enWires[85] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1551 ) , + .Test_en_E_out ( Test_enWires[86] ) , .pReset_N_in ( pResetWires[198] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1552 ) , + .Reset_W_in ( ResetWires[85] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1553 ) , + .Reset_E_out ( ResetWires[86] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[181] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1554 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[373] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[374] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1555 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1556 ) , + .clk_0_N_in ( clk_1_wires[181] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) ) ; +grid_clb grid_clb_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1558 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[102] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1559 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[102] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1560 } ) , + .ccff_head ( cby_1__1__99_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_111_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_111_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_111_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_111_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_111_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_111_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_111_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_111_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[101] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1561 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[101] ) , + .ccff_tail ( grid_clb_111_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1562 ) , + .SC_IN_BOT ( scff_Wires[246] ) , .SC_OUT_TOP ( scff_Wires[247] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1563 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1564 ) , + .Test_en_W_in ( Test_enWires[107] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1565 ) , + .Test_en_E_out ( Test_enWires[108] ) , .pReset_N_in ( pResetWires[247] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1566 ) , + .Reset_W_in ( ResetWires[107] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1567 ) , + .Reset_E_out ( ResetWires[108] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1568 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[180] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[376] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[377] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1569 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1570 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1571 ) , + .clk_0_S_in ( clk_1_wires[180] ) ) ; +grid_clb grid_clb_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1572 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[103] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1573 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[103] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1574 } ) , + .ccff_head ( cby_1__1__100_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_112_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_112_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_112_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_112_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_112_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_112_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_112_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_112_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[102] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1575 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[102] ) , + .ccff_tail ( grid_clb_112_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1576 ) , + .SC_IN_BOT ( scff_Wires[248] ) , .SC_OUT_TOP ( scff_Wires[249] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1577 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1578 ) , + .Test_en_W_in ( Test_enWires[129] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1579 ) , + .Test_en_E_out ( Test_enWires[130] ) , .pReset_N_in ( pResetWires[296] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1580 ) , + .Reset_W_in ( ResetWires[129] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1581 ) , + .Reset_E_out ( ResetWires[130] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[188] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1582 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[379] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[380] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1583 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1584 ) , + .clk_0_N_in ( clk_1_wires[188] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) ) ; +grid_clb grid_clb_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1586 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[104] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1587 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[104] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1588 } ) , + .ccff_head ( cby_1__1__101_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_113_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_113_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_113_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_113_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_113_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_113_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_113_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_113_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[103] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1589 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[103] ) , + .ccff_tail ( grid_clb_113_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1590 ) , + .SC_IN_BOT ( scff_Wires[250] ) , .SC_OUT_TOP ( scff_Wires[251] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1591 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1592 ) , + .Test_en_W_in ( Test_enWires[151] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1593 ) , + .Test_en_E_out ( Test_enWires[152] ) , .pReset_N_in ( pResetWires[345] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1594 ) , + .Reset_W_in ( ResetWires[151] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1595 ) , + .Reset_E_out ( ResetWires[152] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1596 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[187] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[382] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[383] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1597 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1598 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1599 ) , + .clk_0_S_in ( clk_1_wires[187] ) ) ; +grid_clb grid_clb_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1600 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[105] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1601 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[105] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1602 } ) , + .ccff_head ( cby_1__1__102_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_114_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_114_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_114_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_114_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_114_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_114_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_114_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_114_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[104] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1603 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[104] ) , + .ccff_tail ( grid_clb_114_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1604 ) , + .SC_IN_BOT ( scff_Wires[252] ) , .SC_OUT_TOP ( scff_Wires[253] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1605 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1606 ) , + .Test_en_W_in ( Test_enWires[173] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1607 ) , + .Test_en_E_out ( Test_enWires[174] ) , .pReset_N_in ( pResetWires[394] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1608 ) , + .Reset_W_in ( ResetWires[173] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1609 ) , + .Reset_E_out ( ResetWires[174] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[195] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1610 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[385] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[386] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1611 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1612 ) , + .clk_0_N_in ( clk_1_wires[195] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) ) ; +grid_clb grid_clb_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1614 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[106] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1615 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[106] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1616 } ) , + .ccff_head ( cby_1__1__103_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_115_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_115_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_115_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_115_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_115_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_115_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_115_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_115_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[105] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1617 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[105] ) , + .ccff_tail ( grid_clb_115_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1618 ) , + .SC_IN_BOT ( scff_Wires[254] ) , .SC_OUT_TOP ( scff_Wires[255] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1619 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1620 ) , + .Test_en_W_in ( Test_enWires[195] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1621 ) , + .Test_en_E_out ( Test_enWires[196] ) , .pReset_N_in ( pResetWires[443] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1622 ) , + .Reset_W_in ( ResetWires[195] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1623 ) , + .Reset_E_out ( ResetWires[196] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1624 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[194] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[388] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[389] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1625 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1626 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1627 ) , + .clk_0_S_in ( clk_1_wires[194] ) ) ; +grid_clb grid_clb_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1628 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[107] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1629 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[107] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1630 } ) , + .ccff_head ( cby_1__1__104_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_116_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_116_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_116_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_116_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_116_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_116_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_116_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_116_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[106] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1631 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[106] ) , + .ccff_tail ( grid_clb_116_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1632 ) , + .SC_IN_BOT ( scff_Wires[256] ) , .SC_OUT_TOP ( scff_Wires[257] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1633 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1634 ) , + .Test_en_W_in ( Test_enWires[217] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1635 ) , + .Test_en_E_out ( Test_enWires[218] ) , .pReset_N_in ( pResetWires[492] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1636 ) , + .Reset_W_in ( ResetWires[217] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1637 ) , + .Reset_E_out ( ResetWires[218] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[202] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1638 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[391] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[392] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1639 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1640 ) , + .clk_0_N_in ( clk_1_wires[202] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) ) ; +grid_clb grid_clb_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1642 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[108] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1643 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[108] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1644 } ) , + .ccff_head ( cby_1__1__105_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_117_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_117_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_117_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_117_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_117_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_117_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_117_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_117_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[107] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1645 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[107] ) , + .ccff_tail ( grid_clb_117_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1646 ) , + .SC_IN_BOT ( scff_Wires[258] ) , .SC_OUT_TOP ( scff_Wires[259] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1647 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1648 ) , + .Test_en_W_in ( Test_enWires[239] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1649 ) , + .Test_en_E_out ( Test_enWires[240] ) , .pReset_N_in ( pResetWires[541] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1650 ) , + .Reset_W_in ( ResetWires[239] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1651 ) , + .Reset_E_out ( ResetWires[240] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1652 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[201] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[394] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[395] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1653 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1654 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1655 ) , + .clk_0_S_in ( clk_1_wires[201] ) ) ; +grid_clb grid_clb_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1656 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[109] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1657 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[109] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1658 } ) , + .ccff_head ( cby_1__1__106_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_118_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_118_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_118_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_118_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_118_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_118_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_118_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_118_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[108] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1659 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[108] ) , + .ccff_tail ( grid_clb_118_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1660 ) , + .SC_IN_BOT ( scff_Wires[260] ) , .SC_OUT_TOP ( scff_Wires[261] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1661 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1662 ) , + .Test_en_W_in ( Test_enWires[261] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1663 ) , + .Test_en_E_out ( Test_enWires[262] ) , .pReset_N_in ( pResetWires[590] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1664 ) , + .Reset_W_in ( ResetWires[261] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1665 ) , + .Reset_E_out ( ResetWires[262] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[209] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1666 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[397] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[398] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1667 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1668 ) , + .clk_0_N_in ( clk_1_wires[209] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) ) ; +grid_clb grid_clb_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1670 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1671 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1672 } ) , + .ccff_head ( cby_1__1__107_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_119_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_119_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_119_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_119_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_119_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_119_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_119_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_119_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[109] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1673 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[109] ) , + .ccff_tail ( grid_clb_119_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1674 ) , + .SC_IN_BOT ( scff_Wires[262] ) , .SC_OUT_TOP ( scff_Wires[263] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1675 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1676 ) , + .Test_en_W_in ( Test_enWires[283] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1677 ) , + .Test_en_E_out ( Test_enWires[284] ) , .pReset_N_in ( pResetWires[630] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1678 ) , + .Reset_W_in ( ResetWires[283] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1679 ) , + .Reset_E_out ( ResetWires[284] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1680 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[208] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[400] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[401] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1681 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[403] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1682 ) , + .clk_0_S_in ( clk_1_wires[208] ) ) ; +grid_clb grid_clb_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1683 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[110] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1684 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[110] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1685 } ) , + .ccff_head ( cby_1__1__108_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_120_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_120_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_120_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_120_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_120_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_120_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_120_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_120_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1686 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[288] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1687 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1688 ) , + .SC_OUT_BOT ( scff_Wires[290] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1689 ) , + .Test_en_W_in ( Test_enWires[43] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1690 ) , + .Test_en_E_out ( Test_enWires[44] ) , .pReset_N_in ( pResetWires[104] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1691 ) , + .Reset_W_in ( ResetWires[43] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1692 ) , + .Reset_E_out ( ResetWires[44] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[214] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1693 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[405] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[406] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1694 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1695 ) , + .clk_0_N_in ( clk_1_wires[214] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) ) ; +grid_clb grid_clb_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1697 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[111] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1698 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[111] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1699 } ) , + .ccff_head ( cby_1__1__109_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_121_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_121_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_121_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_121_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_121_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_121_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_121_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_121_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[110] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1700 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[110] ) , + .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires[286] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1701 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1702 ) , + .SC_OUT_BOT ( scff_Wires[287] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1703 ) , + .Test_en_W_in ( Test_enWires[65] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1704 ) , + .Test_en_E_out ( Test_enWires[66] ) , .pReset_N_in ( pResetWires[153] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1705 ) , + .Reset_W_in ( ResetWires[65] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1706 ) , + .Reset_E_out ( ResetWires[66] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1707 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[213] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[408] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[409] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1708 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1709 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1710 ) , + .clk_0_S_in ( clk_1_wires[213] ) ) ; +grid_clb grid_clb_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1711 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[112] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1712 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[112] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1713 } ) , + .ccff_head ( cby_1__1__110_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_122_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_122_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_122_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_122_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_122_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_122_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_122_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_122_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[111] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1714 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[111] ) , + .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires[284] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1715 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1716 ) , + .SC_OUT_BOT ( scff_Wires[285] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1717 ) , + .Test_en_W_in ( Test_enWires[87] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1718 ) , + .Test_en_E_out ( Test_enWires[88] ) , .pReset_N_in ( pResetWires[202] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1719 ) , + .Reset_W_in ( ResetWires[87] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1720 ) , + .Reset_E_out ( ResetWires[88] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[221] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1721 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[411] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[412] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1722 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1723 ) , + .clk_0_N_in ( clk_1_wires[221] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) ) ; +grid_clb grid_clb_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1725 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[113] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1726 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[113] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1727 } ) , + .ccff_head ( cby_1__1__111_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_123_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_123_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_123_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_123_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_123_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_123_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_123_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_123_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[112] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1728 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[112] ) , + .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires[282] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1729 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1730 ) , + .SC_OUT_BOT ( scff_Wires[283] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1731 ) , + .Test_en_W_in ( Test_enWires[109] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1732 ) , + .Test_en_E_out ( Test_enWires[110] ) , .pReset_N_in ( pResetWires[251] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1733 ) , + .Reset_W_in ( ResetWires[109] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1734 ) , + .Reset_E_out ( ResetWires[110] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1735 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[220] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[414] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[415] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1736 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1737 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1738 ) , + .clk_0_S_in ( clk_1_wires[220] ) ) ; +grid_clb grid_clb_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1739 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[114] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1740 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[114] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1741 } ) , + .ccff_head ( cby_1__1__112_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_124_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_124_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_124_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_124_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_124_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_124_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_124_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_124_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[113] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1742 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[113] ) , + .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires[280] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1743 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1744 ) , + .SC_OUT_BOT ( scff_Wires[281] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1745 ) , + .Test_en_W_in ( Test_enWires[131] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1746 ) , + .Test_en_E_out ( Test_enWires[132] ) , .pReset_N_in ( pResetWires[300] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1747 ) , + .Reset_W_in ( ResetWires[131] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1748 ) , + .Reset_E_out ( ResetWires[132] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[228] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1749 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[417] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[418] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1750 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1751 ) , + .clk_0_N_in ( clk_1_wires[228] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) ) ; +grid_clb grid_clb_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1753 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[115] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1754 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[115] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1755 } ) , + .ccff_head ( cby_1__1__113_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_125_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_125_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_125_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_125_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_125_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_125_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_125_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_125_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[114] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1756 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[114] ) , + .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires[278] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1757 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1758 ) , + .SC_OUT_BOT ( scff_Wires[279] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1759 ) , + .Test_en_W_in ( Test_enWires[153] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1760 ) , + .Test_en_E_out ( Test_enWires[154] ) , .pReset_N_in ( pResetWires[349] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1761 ) , + .Reset_W_in ( ResetWires[153] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1762 ) , + .Reset_E_out ( ResetWires[154] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1763 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[227] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[420] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[421] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1764 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1765 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1766 ) , + .clk_0_S_in ( clk_1_wires[227] ) ) ; +grid_clb grid_clb_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1767 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[116] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1768 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[116] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1769 } ) , + .ccff_head ( cby_1__1__114_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_126_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_126_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_126_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_126_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_126_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_126_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_126_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_126_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[115] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1770 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[115] ) , + .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires[276] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1771 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1772 ) , + .SC_OUT_BOT ( scff_Wires[277] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1773 ) , + .Test_en_W_in ( Test_enWires[175] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1774 ) , + .Test_en_E_out ( Test_enWires[176] ) , .pReset_N_in ( pResetWires[398] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1775 ) , + .Reset_W_in ( ResetWires[175] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1776 ) , + .Reset_E_out ( ResetWires[176] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[235] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1777 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[423] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[424] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1778 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1779 ) , + .clk_0_N_in ( clk_1_wires[235] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) ) ; +grid_clb grid_clb_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1781 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[117] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1782 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[117] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1783 } ) , + .ccff_head ( cby_1__1__115_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_127_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_127_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_127_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_127_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_127_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_127_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_127_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_127_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[116] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1784 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[116] ) , + .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires[274] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1785 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1786 ) , + .SC_OUT_BOT ( scff_Wires[275] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1787 ) , + .Test_en_W_in ( Test_enWires[197] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1788 ) , + .Test_en_E_out ( Test_enWires[198] ) , .pReset_N_in ( pResetWires[447] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1789 ) , + .Reset_W_in ( ResetWires[197] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1790 ) , + .Reset_E_out ( ResetWires[198] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1791 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[234] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[426] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[427] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1792 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1793 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1794 ) , + .clk_0_S_in ( clk_1_wires[234] ) ) ; +grid_clb grid_clb_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1795 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[118] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1796 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[118] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1797 } ) , + .ccff_head ( cby_1__1__116_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_128_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_128_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_128_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_128_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_128_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_128_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_128_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_128_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[117] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1798 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[117] ) , + .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires[272] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1799 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1800 ) , + .SC_OUT_BOT ( scff_Wires[273] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1801 ) , + .Test_en_W_in ( Test_enWires[219] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1802 ) , + .Test_en_E_out ( Test_enWires[220] ) , .pReset_N_in ( pResetWires[496] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1803 ) , + .Reset_W_in ( ResetWires[219] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1804 ) , + .Reset_E_out ( ResetWires[220] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[242] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1805 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[429] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[430] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1806 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1807 ) , + .clk_0_N_in ( clk_1_wires[242] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) ) ; +grid_clb grid_clb_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1809 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[119] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1810 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[119] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1811 } ) , + .ccff_head ( cby_1__1__117_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_129_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_129_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_129_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_129_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_129_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_129_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_129_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_129_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[118] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1812 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[118] ) , + .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires[270] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1813 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1814 ) , + .SC_OUT_BOT ( scff_Wires[271] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1815 ) , + .Test_en_W_in ( Test_enWires[241] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1816 ) , + .Test_en_E_out ( Test_enWires[242] ) , .pReset_N_in ( pResetWires[545] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1817 ) , + .Reset_W_in ( ResetWires[241] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1818 ) , + .Reset_E_out ( ResetWires[242] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1819 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[241] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[432] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[433] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1820 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1821 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1822 ) , + .clk_0_S_in ( clk_1_wires[241] ) ) ; +grid_clb grid_clb_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1823 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[120] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1824 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[120] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1825 } ) , + .ccff_head ( cby_1__1__118_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_130_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_130_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_130_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_130_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_130_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_130_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_130_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_130_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[119] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1826 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[119] ) , + .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires[268] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1827 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1828 ) , + .SC_OUT_BOT ( scff_Wires[269] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1829 ) , + .Test_en_W_in ( Test_enWires[263] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1830 ) , + .Test_en_E_out ( Test_enWires[264] ) , .pReset_N_in ( pResetWires[594] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1831 ) , + .Reset_W_in ( ResetWires[263] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1832 ) , + .Reset_E_out ( ResetWires[264] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[249] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1833 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[435] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[436] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1834 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1835 ) , + .clk_0_N_in ( clk_1_wires[249] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) ) ; +grid_clb grid_clb_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1837 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1838 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1839 } ) , + .ccff_head ( cby_1__1__119_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_131_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_131_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_131_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_131_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_131_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_131_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_131_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_131_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[120] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1840 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[120] ) , + .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires[266] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1841 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1842 ) , + .SC_OUT_BOT ( scff_Wires[267] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1843 ) , + .Test_en_W_in ( Test_enWires[285] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1844 ) , + .Test_en_E_out ( Test_enWires[286] ) , .pReset_N_in ( pResetWires[633] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1845 ) , + .Reset_W_in ( ResetWires[285] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1846 ) , + .Reset_E_out ( ResetWires[286] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1847 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[248] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[438] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[439] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1848 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[441] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1849 ) , + .clk_0_S_in ( clk_1_wires[248] ) ) ; +grid_clb grid_clb_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1850 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[121] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1851 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[121] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1852 } ) , + .ccff_head ( cby_1__1__120_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_132_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_132_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_132_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_132_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_132_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_132_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_132_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_132_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1853 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_132_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1854 ) , + .SC_IN_BOT ( scff_Wires[293] ) , .SC_OUT_TOP ( scff_Wires[294] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1855 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1856 ) , + .Test_en_W_in ( Test_enWires[45] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1857 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1858 ) , + .pReset_N_in ( pResetWires[108] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1859 ) , + .Reset_W_in ( ResetWires[45] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1860 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1861 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[216] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1862 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[443] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[444] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1863 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1864 ) , + .clk_0_N_in ( clk_1_wires[216] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) ) ; +grid_clb grid_clb_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1866 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[122] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1867 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[122] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1868 } ) , + .ccff_head ( cby_1__1__121_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_133_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_133_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_133_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_133_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_133_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_133_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_133_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_133_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[121] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1869 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[121] ) , + .ccff_tail ( grid_clb_133_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1870 ) , + .SC_IN_BOT ( scff_Wires[295] ) , .SC_OUT_TOP ( scff_Wires[296] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1871 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1872 ) , + .Test_en_W_in ( Test_enWires[67] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1873 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1874 ) , + .pReset_N_in ( pResetWires[157] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1875 ) , + .Reset_W_in ( ResetWires[67] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1876 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1877 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1878 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[215] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[446] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[447] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1879 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1880 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1881 ) , + .clk_0_S_in ( clk_1_wires[215] ) ) ; +grid_clb grid_clb_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1882 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[123] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1883 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[123] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1884 } ) , + .ccff_head ( cby_1__1__122_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_134_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_134_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_134_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_134_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_134_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_134_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_134_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_134_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[122] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1885 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[122] ) , + .ccff_tail ( grid_clb_134_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1886 ) , + .SC_IN_BOT ( scff_Wires[297] ) , .SC_OUT_TOP ( scff_Wires[298] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1887 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1888 ) , + .Test_en_W_in ( Test_enWires[89] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1889 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1890 ) , + .pReset_N_in ( pResetWires[206] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1891 ) , + .Reset_W_in ( ResetWires[89] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1892 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1893 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[223] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1894 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[449] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[450] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1895 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1896 ) , + .clk_0_N_in ( clk_1_wires[223] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) ) ; +grid_clb grid_clb_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1898 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[124] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1899 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[124] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1900 } ) , + .ccff_head ( cby_1__1__123_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_135_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_135_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_135_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_135_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_135_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_135_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_135_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_135_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[123] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1901 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[123] ) , + .ccff_tail ( grid_clb_135_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1902 ) , + .SC_IN_BOT ( scff_Wires[299] ) , .SC_OUT_TOP ( scff_Wires[300] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1903 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1904 ) , + .Test_en_W_in ( Test_enWires[111] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1905 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1906 ) , + .pReset_N_in ( pResetWires[255] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1907 ) , + .Reset_W_in ( ResetWires[111] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1908 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1909 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1910 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[222] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[452] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[453] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1911 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1912 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1913 ) , + .clk_0_S_in ( clk_1_wires[222] ) ) ; +grid_clb grid_clb_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1914 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[125] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1915 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[125] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1916 } ) , + .ccff_head ( cby_1__1__124_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_136_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_136_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_136_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_136_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_136_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_136_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_136_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_136_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[124] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1917 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[124] ) , + .ccff_tail ( grid_clb_136_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1918 ) , + .SC_IN_BOT ( scff_Wires[301] ) , .SC_OUT_TOP ( scff_Wires[302] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1919 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1920 ) , + .Test_en_W_in ( Test_enWires[133] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1921 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1922 ) , + .pReset_N_in ( pResetWires[304] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1923 ) , + .Reset_W_in ( ResetWires[133] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1924 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1925 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[230] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1926 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[455] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[456] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1927 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1928 ) , + .clk_0_N_in ( clk_1_wires[230] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) ) ; +grid_clb grid_clb_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1930 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[126] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1931 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[126] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1932 } ) , + .ccff_head ( cby_1__1__125_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_137_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_137_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_137_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_137_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_137_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_137_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_137_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_137_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[125] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1933 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[125] ) , + .ccff_tail ( grid_clb_137_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1934 ) , + .SC_IN_BOT ( scff_Wires[303] ) , .SC_OUT_TOP ( scff_Wires[304] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1935 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1936 ) , + .Test_en_W_in ( Test_enWires[155] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1937 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1938 ) , + .pReset_N_in ( pResetWires[353] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1939 ) , + .Reset_W_in ( ResetWires[155] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1940 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1941 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1942 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[229] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[458] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[459] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1943 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1944 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1945 ) , + .clk_0_S_in ( clk_1_wires[229] ) ) ; +grid_clb grid_clb_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1946 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[127] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1947 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[127] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1948 } ) , + .ccff_head ( cby_1__1__126_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_138_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_138_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_138_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_138_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_138_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_138_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_138_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_138_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[126] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1949 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[126] ) , + .ccff_tail ( grid_clb_138_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1950 ) , + .SC_IN_BOT ( scff_Wires[305] ) , .SC_OUT_TOP ( scff_Wires[306] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1951 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1952 ) , + .Test_en_W_in ( Test_enWires[177] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1953 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1954 ) , + .pReset_N_in ( pResetWires[402] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1955 ) , + .Reset_W_in ( ResetWires[177] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1956 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1957 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[237] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1958 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[461] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[462] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1959 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1960 ) , + .clk_0_N_in ( clk_1_wires[237] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) ) ; +grid_clb grid_clb_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1962 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[128] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1963 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[128] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1964 } ) , + .ccff_head ( cby_1__1__127_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_139_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_139_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_139_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_139_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_139_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_139_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_139_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_139_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[127] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1965 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[127] ) , + .ccff_tail ( grid_clb_139_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1966 ) , + .SC_IN_BOT ( scff_Wires[307] ) , .SC_OUT_TOP ( scff_Wires[308] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1967 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1968 ) , + .Test_en_W_in ( Test_enWires[199] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1969 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1970 ) , + .pReset_N_in ( pResetWires[451] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1971 ) , + .Reset_W_in ( ResetWires[199] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1972 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1973 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1974 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[236] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[464] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[465] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1975 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1976 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1977 ) , + .clk_0_S_in ( clk_1_wires[236] ) ) ; +grid_clb grid_clb_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1978 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[129] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1979 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[129] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1980 } ) , + .ccff_head ( cby_1__1__128_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_140_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_140_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_140_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_140_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_140_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_140_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_140_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_140_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[128] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1981 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[128] ) , + .ccff_tail ( grid_clb_140_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1982 ) , + .SC_IN_BOT ( scff_Wires[309] ) , .SC_OUT_TOP ( scff_Wires[310] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1983 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1984 ) , + .Test_en_W_in ( Test_enWires[221] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1985 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1986 ) , + .pReset_N_in ( pResetWires[500] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1987 ) , + .Reset_W_in ( ResetWires[221] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1988 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1989 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[244] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1990 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[467] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[468] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1991 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1992 ) , + .clk_0_N_in ( clk_1_wires[244] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) ) ; +grid_clb grid_clb_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1994 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[130] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1995 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[130] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1996 } ) , + .ccff_head ( cby_1__1__129_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_141_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_141_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_141_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_141_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_141_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_141_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_141_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_141_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[129] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1997 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[129] ) , + .ccff_tail ( grid_clb_141_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1998 ) , + .SC_IN_BOT ( scff_Wires[311] ) , .SC_OUT_TOP ( scff_Wires[312] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1999 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2000 ) , + .Test_en_W_in ( Test_enWires[243] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2001 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2002 ) , + .pReset_N_in ( pResetWires[549] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2003 ) , + .Reset_W_in ( ResetWires[243] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2004 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2005 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2006 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[243] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[470] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[471] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2007 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2008 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2009 ) , + .clk_0_S_in ( clk_1_wires[243] ) ) ; +grid_clb grid_clb_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2010 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[131] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2011 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[131] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_2012 } ) , + .ccff_head ( cby_1__1__130_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_142_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_142_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_142_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_142_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_142_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_142_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_142_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_142_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[130] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2013 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[130] ) , + .ccff_tail ( grid_clb_142_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2014 ) , + .SC_IN_BOT ( scff_Wires[313] ) , .SC_OUT_TOP ( scff_Wires[314] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2015 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2016 ) , + .Test_en_W_in ( Test_enWires[265] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2017 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2018 ) , + .pReset_N_in ( pResetWires[598] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2019 ) , + .Reset_W_in ( ResetWires[265] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2020 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2021 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[251] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_2022 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[473] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[474] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2023 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2024 ) , + .clk_0_N_in ( clk_1_wires[251] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) ) ; +grid_clb grid_clb_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2026 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2027 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_2028 } ) , + .ccff_head ( cby_1__1__131_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_143_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_143_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_143_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_143_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_143_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_143_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_143_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_143_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[131] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2029 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[131] ) , + .ccff_tail ( grid_clb_143_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2030 ) , + .SC_IN_BOT ( scff_Wires[315] ) , .SC_OUT_TOP ( scff_Wires[316] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2031 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2032 ) , + .Test_en_W_in ( Test_enWires[287] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2033 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2034 ) , + .pReset_N_in ( pResetWires[636] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2035 ) , + .Reset_W_in ( ResetWires[287] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2036 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2037 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2038 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[250] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[476] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[477] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2039 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[479] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2040 ) , + .clk_0_S_in ( clk_1_wires[250] ) ) ; +sb_0__0_ sb_0__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2041 } ) , + .chany_top_in ( cby_0__1__0_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , + .ccff_head ( grid_io_bottom_11_ccff_tail ) , + .chany_top_out ( sb_0__0__0_chany_top_out ) , + .chanx_right_out ( sb_0__0__0_chanx_right_out ) , + .ccff_tail ( ccff_tail ) , .pReset_E_in ( pResetWires[25] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[5] ) ) ; +sb_0__1_ sb_0__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2042 } ) , + .chany_top_in ( cby_0__1__1_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__0_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__0_ccff_tail ) , + .chany_top_out ( sb_0__1__0_chany_top_out ) , + .chanx_right_out ( sb_0__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , .pReset_E_in ( pResetWires[61] ) , + .pReset_S_out ( pResetWires[64] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[4] ) ) ; +sb_0__1_ sb_0__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2043 } ) , + .chany_top_in ( cby_0__1__2_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__1_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__1_ccff_tail ) , + .chany_top_out ( sb_0__1__1_chany_top_out ) , + .chanx_right_out ( sb_0__1__1_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) , + .ccff_tail ( sb_0__1__1_ccff_tail ) , .pReset_E_in ( pResetWires[110] ) , + .pReset_S_out ( pResetWires[113] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[10] ) ) ; +sb_0__1_ sb_0__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2044 } ) , + .chany_top_in ( cby_0__1__3_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__2_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__2_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__2_ccff_tail ) , + .chany_top_out ( sb_0__1__2_chany_top_out ) , + .chanx_right_out ( sb_0__1__2_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) , + .ccff_tail ( sb_0__1__2_ccff_tail ) , .pReset_E_in ( pResetWires[159] ) , + .pReset_S_out ( pResetWires[162] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[15] ) ) ; +sb_0__1_ sb_0__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2045 } ) , + .chany_top_in ( cby_0__1__4_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__3_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__3_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__3_ccff_tail ) , + .chany_top_out ( sb_0__1__3_chany_top_out ) , + .chanx_right_out ( sb_0__1__3_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) , + .ccff_tail ( sb_0__1__3_ccff_tail ) , .pReset_E_in ( pResetWires[208] ) , + .pReset_S_out ( pResetWires[211] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[20] ) ) ; +sb_0__1_ sb_0__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2046 } ) , + .chany_top_in ( cby_0__1__5_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__4_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__4_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__4_ccff_tail ) , + .chany_top_out ( sb_0__1__4_chany_top_out ) , + .chanx_right_out ( sb_0__1__4_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) , + .ccff_tail ( sb_0__1__4_ccff_tail ) , .pReset_E_in ( pResetWires[257] ) , + .pReset_S_out ( pResetWires[260] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[25] ) ) ; +sb_0__1_ sb_0__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2047 } ) , + .chany_top_in ( cby_0__1__6_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__5_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__5_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__5_ccff_tail ) , + .chany_top_out ( sb_0__1__5_chany_top_out ) , + .chanx_right_out ( sb_0__1__5_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) , + .ccff_tail ( sb_0__1__5_ccff_tail ) , .pReset_E_in ( pResetWires[306] ) , + .pReset_S_out ( pResetWires[309] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[30] ) ) ; +sb_0__1_ sb_0__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2048 } ) , + .chany_top_in ( cby_0__1__7_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__6_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__6_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__6_ccff_tail ) , + .chany_top_out ( sb_0__1__6_chany_top_out ) , + .chanx_right_out ( sb_0__1__6_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) , + .ccff_tail ( sb_0__1__6_ccff_tail ) , .pReset_E_in ( pResetWires[355] ) , + .pReset_S_out ( pResetWires[358] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[35] ) ) ; +sb_0__1_ sb_0__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2049 } ) , + .chany_top_in ( cby_0__1__8_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__7_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__7_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__7_ccff_tail ) , + .chany_top_out ( sb_0__1__7_chany_top_out ) , + .chanx_right_out ( sb_0__1__7_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) , + .ccff_tail ( sb_0__1__7_ccff_tail ) , .pReset_E_in ( pResetWires[404] ) , + .pReset_S_out ( pResetWires[407] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[40] ) ) ; +sb_0__1_ sb_0__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2050 } ) , + .chany_top_in ( cby_0__1__9_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__8_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__8_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__8_ccff_tail ) , + .chany_top_out ( sb_0__1__8_chany_top_out ) , + .chanx_right_out ( sb_0__1__8_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) , + .ccff_tail ( sb_0__1__8_ccff_tail ) , .pReset_E_in ( pResetWires[453] ) , + .pReset_S_out ( pResetWires[456] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[45] ) ) ; +sb_0__1_ sb_0__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2051 } ) , + .chany_top_in ( cby_0__1__10_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__9_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__9_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__9_ccff_tail ) , + .chany_top_out ( sb_0__1__9_chany_top_out ) , + .chanx_right_out ( sb_0__1__9_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) , + .ccff_tail ( sb_0__1__9_ccff_tail ) , .pReset_E_in ( pResetWires[502] ) , + .pReset_S_out ( pResetWires[505] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[50] ) ) ; +sb_0__1_ sb_0__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2052 } ) , + .chany_top_in ( cby_0__1__11_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__10_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__10_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__10_ccff_tail ) , + .chany_top_out ( sb_0__1__10_chany_top_out ) , + .chanx_right_out ( sb_0__1__10_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) , + .ccff_tail ( sb_0__1__10_ccff_tail ) , .pReset_E_in ( pResetWires[551] ) , + .pReset_S_out ( pResetWires[554] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[55] ) ) ; +sb_0__2_ sb_0__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2053 } ) , + .chanx_right_in ( cbx_1__12__0_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__11_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( grid_io_top_0_ccff_tail ) , + .chanx_right_out ( sb_0__12__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) , + .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , + .SC_OUT_BOT ( scff_Wires[0] ) , .pReset_E_in ( pResetWires[600] ) , + .pReset_S_out ( pResetWires[603] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[62] ) ) ; +sb_1__0_ sb_1__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2054 } ) , + .chany_top_in ( cby_1__1__0_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_10_ccff_tail ) , + .chany_top_out ( sb_1__0__0_chany_top_out ) , + .chanx_right_out ( sb_1__0__0_chanx_right_out ) , + .chanx_left_out ( sb_1__0__0_chanx_left_out ) , + .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) , + .pReset_E_in ( pResetWires[28] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) , + .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ; +sb_1__0_ sb_2__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) , + .chany_top_in ( cby_1__1__12_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__2_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_9_ccff_tail ) , + .chany_top_out ( sb_1__0__1_chany_top_out ) , + .chanx_right_out ( sb_1__0__1_chanx_right_out ) , + .chanx_left_out ( sb_1__0__1_chanx_left_out ) , + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , + .pReset_E_in ( pResetWires[31] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) , + .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ; +sb_1__0_ sb_3__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) , + .chany_top_in ( cby_1__1__24_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__3_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__2_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_8_ccff_tail ) , + .chany_top_out ( sb_1__0__2_chany_top_out ) , + .chanx_right_out ( sb_1__0__2_chanx_right_out ) , + .chanx_left_out ( sb_1__0__2_chanx_left_out ) , + .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) , + .pReset_E_in ( pResetWires[34] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) , + .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ; +sb_1__0_ sb_4__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) , + .chany_top_in ( cby_1__1__36_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__4_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__3_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_7_ccff_tail ) , + .chany_top_out ( sb_1__0__3_chany_top_out ) , + .chanx_right_out ( sb_1__0__3_chanx_right_out ) , + .chanx_left_out ( sb_1__0__3_chanx_left_out ) , + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) , + .pReset_E_in ( pResetWires[37] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , + .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ; +sb_1__0_ sb_5__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) , + .chany_top_in ( cby_1__1__48_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__5_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__4_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_6_ccff_tail ) , + .chany_top_out ( sb_1__0__4_chany_top_out ) , + .chanx_right_out ( sb_1__0__4_chanx_right_out ) , + .chanx_left_out ( sb_1__0__4_chanx_left_out ) , + .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , + .pReset_E_in ( pResetWires[40] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) , + .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ; +sb_1__0_ sb_6__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) , + .chany_top_in ( cby_1__1__60_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__6_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__5_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_5_ccff_tail ) , + .chany_top_out ( sb_1__0__5_chany_top_out ) , + .chanx_right_out ( sb_1__0__5_chanx_right_out ) , + .chanx_left_out ( sb_1__0__5_chanx_left_out ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) , + .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) , + .pReset_E_in ( h_incr0 ) , .pReset_W_in ( h_incr0 ) , + .pReset_N_out ( pResetWires[42] ) , .pReset_W_out ( pResetWires[41] ) , + .pReset_E_out ( pResetWires[43] ) , .Reset_S_in ( Reset[0] ) , + .Reset_N_out ( ResetWires[1] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[217] ) , + .prog_clk_3_S_in ( prog_clk[0] ) , + .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) , + .clk_3_N_out ( clk_3_wires[90] ) ) ; +sb_1__0_ sb_7__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2098 } ) , + .chany_top_in ( cby_1__1__72_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__7_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__6_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_4_ccff_tail ) , + .chany_top_out ( sb_1__0__6_chany_top_out ) , + .chanx_right_out ( sb_1__0__6_chanx_right_out ) , + .chanx_left_out ( sb_1__0__6_chanx_left_out ) , + .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2099 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2100 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2101 ) , + .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2102 ) , + .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2103 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2104 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2105 ) ) ; +sb_1__0_ sb_8__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2106 } ) , + .chany_top_in ( cby_1__1__84_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__8_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__7_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_3_ccff_tail ) , + .chany_top_out ( sb_1__0__7_chany_top_out ) , + .chanx_right_out ( sb_1__0__7_chanx_right_out ) , + .chanx_left_out ( sb_1__0__7_chanx_left_out ) , + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2107 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2108 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2109 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2110 ) , + .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2111 ) , + .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2112 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2113 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2114 ) ) ; +sb_1__0_ sb_9__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2115 } ) , + .chany_top_in ( cby_1__1__96_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__9_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__8_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_2_ccff_tail ) , + .chany_top_out ( sb_1__0__8_chany_top_out ) , + .chanx_right_out ( sb_1__0__8_chanx_right_out ) , + .chanx_left_out ( sb_1__0__8_chanx_left_out ) , + .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2116 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2117 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2118 ) , + .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2119 ) , + .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2120 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2121 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2122 ) ) ; +sb_1__0_ sb_10__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2123 } ) , + .chany_top_in ( cby_1__1__108_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__10_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__9_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_1_ccff_tail ) , + .chany_top_out ( sb_1__0__9_chany_top_out ) , + .chanx_right_out ( sb_1__0__9_chanx_right_out ) , + .chanx_left_out ( sb_1__0__9_chanx_left_out ) , + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2124 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2125 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2126 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2127 ) , + .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2128 ) , + .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2129 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2130 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2131 ) ) ; +sb_1__0_ sb_11__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2132 } ) , + .chany_top_in ( cby_1__1__120_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__11_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__10_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_0_ccff_tail ) , + .chany_top_out ( sb_1__0__10_chany_top_out ) , + .chanx_right_out ( sb_1__0__10_chanx_right_out ) , + .chanx_left_out ( sb_1__0__10_chanx_left_out ) , + .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2133 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2134 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2135 ) , + .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2136 ) , + .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2137 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2138 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2139 ) ) ; +sb_1__1_ sb_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2140 } ) , + .chany_top_in ( cby_1__1__1_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__11_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__0_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__11_ccff_tail ) , + .chany_top_out ( sb_1__1__0_chany_top_out ) , + .chanx_right_out ( sb_1__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__0_chanx_left_out ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2141 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2142 ) , + .pReset_E_in ( pResetWires[66] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2143 ) , + .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2144 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2145 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2146 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( h_incr0 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2147 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2148 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2149 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2150 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2151 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2152 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2154 ) , + .clk_1_N_in ( clk_2_wires[4] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2155 ) , + .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2156 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2157 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2159 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2160 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2161 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2162 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2163 ) ) ; +sb_1__1_ sb_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2164 } ) , + .chany_top_in ( cby_1__1__2_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__12_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__1_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__12_ccff_tail ) , + .chany_top_out ( sb_1__1__1_chany_top_out ) , + .chanx_right_out ( sb_1__1__1_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__1_chanx_left_out ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2165 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2166 ) , + .pReset_E_in ( pResetWires[115] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2167 ) , + .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2168 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2169 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2171 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2172 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[1] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2173 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2174 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2175 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2176 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2177 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2178 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2179 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2180 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2181 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2182 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2183 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2184 ) , + .clk_2_E_in ( clk_2_wires[1] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2185 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2186 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2187 ) , + .clk_2_S_out ( clk_2_wires[3] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2188 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2189 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2190 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2191 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2192 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2193 ) ) ; +sb_1__1_ sb_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2194 } ) , + .chany_top_in ( cby_1__1__3_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__13_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__2_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__13_ccff_tail ) , + .chany_top_out ( sb_1__1__2_chany_top_out ) , + .chanx_right_out ( sb_1__1__2_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__2_chanx_left_out ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2195 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2196 ) , + .pReset_E_in ( pResetWires[164] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2197 ) , + .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2198 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2199 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2200 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( h_incr0 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2201 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2202 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2203 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2204 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2205 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2206 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2207 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2208 ) , + .clk_1_N_in ( clk_2_wires[11] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2209 ) , + .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2210 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2211 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2213 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2214 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2215 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2216 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2217 ) ) ; +sb_1__1_ sb_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2218 } ) , + .chany_top_in ( cby_1__1__4_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__14_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__3_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__14_ccff_tail ) , + .chany_top_out ( sb_1__1__3_chany_top_out ) , + .chanx_right_out ( sb_1__1__3_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__3_chanx_left_out ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2219 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2220 ) , + .pReset_E_in ( pResetWires[213] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2221 ) , + .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2222 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2223 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2225 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2226 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[6] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2227 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2228 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2229 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2230 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2231 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2232 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2233 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2234 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2235 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2236 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2237 ) , + .clk_2_E_in ( clk_2_wires[6] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2238 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2239 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2240 ) , + .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2241 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2242 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2243 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2244 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2245 ) ) ; +sb_1__1_ sb_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2246 } ) , + .chany_top_in ( cby_1__1__5_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__15_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__4_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__4_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__15_ccff_tail ) , + .chany_top_out ( sb_1__1__4_chany_top_out ) , + .chanx_right_out ( sb_1__1__4_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__4_chanx_left_out ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2247 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2248 ) , + .pReset_E_in ( pResetWires[262] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2249 ) , + .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2250 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2251 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2252 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2253 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2254 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2255 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2256 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2257 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2258 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2259 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2260 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2261 ) , + .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2262 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2263 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2264 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2265 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2266 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2267 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2268 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2269 ) ) ; +sb_1__1_ sb_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2270 } ) , + .chany_top_in ( cby_1__1__6_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__16_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__5_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__5_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__16_ccff_tail ) , + .chany_top_out ( sb_1__1__5_chany_top_out ) , + .chanx_right_out ( sb_1__1__5_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__5_chanx_left_out ) , + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2271 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2272 ) , + .pReset_E_in ( pResetWires[311] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2273 ) , + .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2274 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2275 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2277 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2278 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2279 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2280 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2281 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2282 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2283 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2284 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2285 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2286 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2288 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2289 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2290 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2291 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2292 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2293 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2294 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2295 ) ) ; +sb_1__1_ sb_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2296 } ) , + .chany_top_in ( cby_1__1__7_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__17_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__6_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__6_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__17_ccff_tail ) , + .chany_top_out ( sb_1__1__6_chany_top_out ) , + .chanx_right_out ( sb_1__1__6_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__6_chanx_left_out ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2297 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2298 ) , + .pReset_E_in ( pResetWires[360] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2299 ) , + .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2300 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2301 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2302 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2303 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2304 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2305 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2306 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2307 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2308 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2309 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2310 ) , + .clk_1_N_in ( clk_2_wires[18] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2311 ) , + .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2312 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2313 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2315 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2316 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2317 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2318 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2319 ) ) ; +sb_1__1_ sb_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2320 } ) , + .chany_top_in ( cby_1__1__8_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__18_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__7_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__7_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__18_ccff_tail ) , + .chany_top_out ( sb_1__1__7_chany_top_out ) , + .chanx_right_out ( sb_1__1__7_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__7_chanx_left_out ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2321 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2322 ) , + .pReset_E_in ( pResetWires[409] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2323 ) , + .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2324 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2325 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2327 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2328 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[13] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2329 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2330 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2331 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2332 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2333 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2334 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2335 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2336 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2337 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2338 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2339 ) , + .clk_2_E_in ( clk_2_wires[13] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2340 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2341 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2342 ) , + .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2343 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2345 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2346 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2347 ) ) ; +sb_1__1_ sb_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2348 } ) , + .chany_top_in ( cby_1__1__9_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__19_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__8_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__8_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__19_ccff_tail ) , + .chany_top_out ( sb_1__1__8_chany_top_out ) , + .chanx_right_out ( sb_1__1__8_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__8_chanx_left_out ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2349 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2350 ) , + .pReset_E_in ( pResetWires[458] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2351 ) , + .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2352 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2353 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2354 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2355 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2356 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2357 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2358 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2359 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2360 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2361 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2362 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2363 ) , + .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2364 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2365 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2366 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2367 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2368 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2369 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2370 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2371 ) ) ; +sb_1__1_ sb_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2372 } ) , + .chany_top_in ( cby_1__1__10_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__20_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__9_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__9_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__20_ccff_tail ) , + .chany_top_out ( sb_1__1__9_chany_top_out ) , + .chanx_right_out ( sb_1__1__9_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__9_chanx_left_out ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2373 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2374 ) , + .pReset_E_in ( pResetWires[507] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2375 ) , + .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2376 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2377 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2379 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2380 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[20] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2381 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2382 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2383 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2384 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2385 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2386 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2387 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2388 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2389 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2390 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2391 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2392 ) , + .clk_2_E_in ( clk_2_wires[20] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2393 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2394 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2395 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2396 ) , + .clk_2_N_out ( clk_2_wires[22] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2397 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2398 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2399 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2400 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2401 ) ) ; +sb_1__1_ sb_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2402 } ) , + .chany_top_in ( cby_1__1__11_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__21_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__10_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__10_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__21_ccff_tail ) , + .chany_top_out ( sb_1__1__10_chany_top_out ) , + .chanx_right_out ( sb_1__1__10_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__10_chanx_left_out ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2403 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2404 ) , + .pReset_E_in ( pResetWires[556] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2405 ) , + .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2406 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2407 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2408 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2409 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2410 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2411 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2412 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2413 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2414 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2415 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2416 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2417 ) , + .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2418 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2419 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2422 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2423 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2424 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2425 ) ) ; +sb_1__1_ sb_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2426 } ) , + .chany_top_in ( cby_1__1__13_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__22_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__12_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__11_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__22_ccff_tail ) , + .chany_top_out ( sb_1__1__11_chany_top_out ) , + .chanx_right_out ( sb_1__1__11_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__11_chanx_left_out ) , + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2427 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2428 ) , + .pReset_E_in ( pResetWires[70] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2429 ) , + .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2430 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2431 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2433 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2434 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2435 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2436 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2437 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2438 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2439 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2440 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2441 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2442 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2445 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2446 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2447 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2449 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2450 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2451 ) ) ; +sb_1__1_ sb_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2452 } ) , + .chany_top_in ( cby_1__1__14_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__23_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__13_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__12_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__23_ccff_tail ) , + .chany_top_out ( sb_1__1__12_chany_top_out ) , + .chanx_right_out ( sb_1__1__12_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__12_chanx_left_out ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2453 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2454 ) , + .pReset_E_in ( pResetWires[119] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2455 ) , + .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2456 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2459 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2460 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2461 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2462 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[2] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2463 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2464 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2465 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2466 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2467 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2468 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2469 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2470 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2471 ) , + .clk_2_N_in ( clk_3_wires[69] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2472 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2473 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2474 ) , + .clk_2_W_out ( clk_2_wires[2] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2475 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2476 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2477 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2478 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2479 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2480 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2481 ) ) ; +sb_1__1_ sb_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2482 } ) , + .chany_top_in ( cby_1__1__15_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__24_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__14_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__13_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__24_ccff_tail ) , + .chany_top_out ( sb_1__1__13_chany_top_out ) , + .chanx_right_out ( sb_1__1__13_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__13_chanx_left_out ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2483 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2484 ) , + .pReset_E_in ( pResetWires[168] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2485 ) , + .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2486 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2487 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2489 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2490 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2491 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2492 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2493 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2494 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2495 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2496 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[65] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2497 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2498 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2499 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2500 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2501 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2502 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2503 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2504 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2505 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2506 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2507 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2508 ) , + .clk_3_N_in ( clk_3_wires[65] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2509 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2510 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2511 ) , + .clk_3_S_out ( clk_3_wires[68] ) ) ; +sb_1__1_ sb_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2512 } ) , + .chany_top_in ( cby_1__1__16_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__25_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__15_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__14_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__25_ccff_tail ) , + .chany_top_out ( sb_1__1__14_chany_top_out ) , + .chanx_right_out ( sb_1__1__14_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__14_chanx_left_out ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2513 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2514 ) , + .pReset_E_in ( pResetWires[217] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2515 ) , + .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2516 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2517 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2519 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2520 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2521 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2522 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[7] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2523 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2524 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2525 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2526 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2527 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2528 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[59] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2529 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2530 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2531 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2532 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2533 ) , + .clk_2_N_in ( clk_3_wires[59] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2534 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2535 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2536 ) , + .clk_2_W_out ( clk_2_wires[7] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2537 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2538 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2539 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2540 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2541 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2542 ) , + .clk_3_N_in ( clk_3_wires[59] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2543 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2544 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2545 ) , + .clk_3_S_out ( clk_3_wires[64] ) ) ; +sb_1__1_ sb_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2546 } ) , + .chany_top_in ( cby_1__1__17_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__26_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__16_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__15_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__26_ccff_tail ) , + .chany_top_out ( sb_1__1__15_chany_top_out ) , + .chanx_right_out ( sb_1__1__15_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__15_chanx_left_out ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2547 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2548 ) , + .pReset_E_in ( pResetWires[266] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2549 ) , + .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2550 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2551 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2553 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2554 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2555 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2556 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2557 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2558 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2559 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2560 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[55] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2561 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2562 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2563 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2564 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2565 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2567 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2569 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2570 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2571 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2572 ) , + .clk_3_N_in ( clk_3_wires[55] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2573 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2574 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2575 ) , + .clk_3_S_out ( clk_3_wires[58] ) ) ; +sb_1__1_ sb_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2576 } ) , + .chany_top_in ( cby_1__1__18_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__27_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__17_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__16_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__27_ccff_tail ) , + .chany_top_out ( sb_1__1__16_chany_top_out ) , + .chanx_right_out ( sb_1__1__16_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__16_chanx_left_out ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2577 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2578 ) , + .pReset_E_in ( pResetWires[315] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2579 ) , + .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2580 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2581 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2583 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2584 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2585 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2586 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2587 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2588 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[51] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2589 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2590 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2591 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2592 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2595 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2596 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2597 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2598 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2599 ) , + .clk_3_E_in ( clk_3_wires[51] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2600 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2601 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2603 ) , + .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ; +sb_1__1_ sb_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2604 } ) , + .chany_top_in ( cby_1__1__19_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__28_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__18_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__17_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__28_ccff_tail ) , + .chany_top_out ( sb_1__1__17_chany_top_out ) , + .chanx_right_out ( sb_1__1__17_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__17_chanx_left_out ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2605 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2606 ) , + .pReset_E_in ( pResetWires[364] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2607 ) , + .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2608 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2609 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2611 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2612 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2613 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2614 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2615 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2616 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2617 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[53] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2618 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2619 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2620 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2621 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2622 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2625 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2626 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2627 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2628 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2629 ) , + .clk_3_S_in ( clk_3_wires[53] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2630 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2631 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2632 ) , + .clk_3_N_out ( clk_3_wires[56] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2633 ) ) ; +sb_1__1_ sb_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2634 } ) , + .chany_top_in ( cby_1__1__20_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__29_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__19_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__18_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__29_ccff_tail ) , + .chany_top_out ( sb_1__1__18_chany_top_out ) , + .chanx_right_out ( sb_1__1__18_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__18_chanx_left_out ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2635 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2636 ) , + .pReset_E_in ( pResetWires[413] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2637 ) , + .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2638 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2639 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2641 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2642 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2643 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[57] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2644 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[14] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2645 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2646 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2647 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2648 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2649 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[57] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2650 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2651 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2652 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2653 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2654 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2655 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2656 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2657 ) , + .clk_2_S_in ( clk_3_wires[57] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2658 ) , + .clk_2_W_out ( clk_2_wires[14] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2659 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2660 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2661 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2662 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2663 ) , + .clk_3_S_in ( clk_3_wires[57] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2664 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2665 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2666 ) , + .clk_3_N_out ( clk_3_wires[62] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2667 ) ) ; +sb_1__1_ sb_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2668 } ) , + .chany_top_in ( cby_1__1__21_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__30_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__20_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__19_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__30_ccff_tail ) , + .chany_top_out ( sb_1__1__19_chany_top_out ) , + .chanx_right_out ( sb_1__1__19_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__19_chanx_left_out ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2669 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2670 ) , + .pReset_E_in ( pResetWires[462] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2671 ) , + .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2672 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2673 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2675 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2676 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2677 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2678 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2679 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2680 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2681 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[63] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2682 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2683 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2684 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2685 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2686 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2688 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2689 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2691 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2692 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2693 ) , + .clk_3_S_in ( clk_3_wires[63] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2694 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2695 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2696 ) , + .clk_3_N_out ( clk_3_wires[66] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2697 ) ) ; +sb_1__1_ sb_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2698 } ) , + .chany_top_in ( cby_1__1__22_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__31_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__21_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__20_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__31_ccff_tail ) , + .chany_top_out ( sb_1__1__20_chany_top_out ) , + .chanx_right_out ( sb_1__1__20_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__20_chanx_left_out ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2699 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2700 ) , + .pReset_E_in ( pResetWires[511] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2701 ) , + .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2702 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2703 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2705 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2706 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2707 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[67] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2708 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[21] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2709 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2710 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2711 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2712 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2713 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2714 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2715 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2716 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2717 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2718 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2719 ) , + .clk_2_S_in ( clk_3_wires[67] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2720 ) , + .clk_2_W_out ( clk_2_wires[21] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2721 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2723 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2724 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2725 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2726 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2727 ) ) ; +sb_1__1_ sb_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2728 } ) , + .chany_top_in ( cby_1__1__23_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__32_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__22_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__21_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__32_ccff_tail ) , + .chany_top_out ( sb_1__1__21_chany_top_out ) , + .chanx_right_out ( sb_1__1__21_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__21_chanx_left_out ) , + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2729 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2730 ) , + .pReset_E_in ( pResetWires[560] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2731 ) , + .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2732 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2733 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2735 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2736 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2737 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2738 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2739 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2740 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2741 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2742 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2743 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2744 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2747 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2748 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2749 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2750 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2751 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2752 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2753 ) ) ; +sb_1__1_ sb_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2754 } ) , + .chany_top_in ( cby_1__1__25_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__33_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__24_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__22_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__33_ccff_tail ) , + .chany_top_out ( sb_1__1__22_chany_top_out ) , + .chanx_right_out ( sb_1__1__22_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__22_chanx_left_out ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2755 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2756 ) , + .pReset_E_in ( pResetWires[74] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2757 ) , + .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2758 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2760 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2761 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2762 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2763 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2764 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2765 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2766 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2767 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2768 ) , + .clk_1_N_in ( clk_2_wires[30] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2769 ) , + .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2770 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2771 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2772 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2773 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2774 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2775 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2776 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2777 ) ) ; +sb_1__1_ sb_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2778 } ) , + .chany_top_in ( cby_1__1__26_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__34_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__25_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__23_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__34_ccff_tail ) , + .chany_top_out ( sb_1__1__23_chany_top_out ) , + .chanx_right_out ( sb_1__1__23_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__23_chanx_left_out ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2779 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2780 ) , + .pReset_E_in ( pResetWires[123] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2781 ) , + .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2782 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2783 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2785 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2786 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[28] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2787 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2788 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2789 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2790 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2791 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2792 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2793 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2794 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2795 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2796 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2797 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2798 ) , + .clk_2_E_in ( clk_2_wires[28] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2799 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2800 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2801 ) , + .clk_2_S_out ( clk_2_wires[29] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2802 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2803 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2805 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2806 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2807 ) ) ; +sb_1__1_ sb_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2808 } ) , + .chany_top_in ( cby_1__1__27_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__35_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__26_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__24_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__35_ccff_tail ) , + .chany_top_out ( sb_1__1__24_chany_top_out ) , + .chanx_right_out ( sb_1__1__24_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__24_chanx_left_out ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2809 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2810 ) , + .pReset_E_in ( pResetWires[172] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2811 ) , + .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2812 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2813 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2814 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2815 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2816 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2817 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2818 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2819 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2820 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2821 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2822 ) , + .clk_1_N_in ( clk_2_wires[41] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2823 ) , + .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2824 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2825 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2827 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2828 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2829 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2830 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2831 ) ) ; +sb_1__1_ sb_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2832 } ) , + .chany_top_in ( cby_1__1__28_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__36_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__27_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__25_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__36_ccff_tail ) , + .chany_top_out ( sb_1__1__25_chany_top_out ) , + .chanx_right_out ( sb_1__1__25_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__25_chanx_left_out ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2833 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2834 ) , + .pReset_E_in ( pResetWires[221] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2835 ) , + .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2836 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2837 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2839 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2840 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[37] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2841 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2842 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2843 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2844 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2845 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2846 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2847 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2848 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2849 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2850 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2851 ) , + .clk_2_E_in ( clk_2_wires[37] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2852 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2853 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2854 ) , + .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2855 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2856 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2857 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2858 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2859 ) ) ; +sb_1__1_ sb_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2860 } ) , + .chany_top_in ( cby_1__1__29_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__37_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__28_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__26_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__37_ccff_tail ) , + .chany_top_out ( sb_1__1__26_chany_top_out ) , + .chanx_right_out ( sb_1__1__26_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__26_chanx_left_out ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2861 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2862 ) , + .pReset_E_in ( pResetWires[270] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2863 ) , + .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2864 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2865 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2866 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2867 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2869 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2870 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2871 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2872 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2873 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2874 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2875 ) , + .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2876 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2877 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2878 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2879 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2880 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2881 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2882 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2883 ) ) ; +sb_1__1_ sb_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2884 } ) , + .chany_top_in ( cby_1__1__30_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__38_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__29_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__27_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__38_ccff_tail ) , + .chany_top_out ( sb_1__1__27_chany_top_out ) , + .chanx_right_out ( sb_1__1__27_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__27_chanx_left_out ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2885 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2886 ) , + .pReset_E_in ( pResetWires[319] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2887 ) , + .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2888 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2889 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2891 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2892 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2893 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2894 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2895 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2896 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[47] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2897 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2898 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2899 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2900 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2901 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2902 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2904 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2905 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2906 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2907 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2908 ) , + .clk_3_E_in ( clk_3_wires[47] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2909 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2910 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2911 ) , + .clk_3_W_out ( clk_3_wires[50] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2912 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2913 ) ) ; +sb_1__1_ sb_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2914 } ) , + .chany_top_in ( cby_1__1__31_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__39_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__30_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__28_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__39_ccff_tail ) , + .chany_top_out ( sb_1__1__28_chany_top_out ) , + .chanx_right_out ( sb_1__1__28_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__28_chanx_left_out ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2915 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2916 ) , + .pReset_E_in ( pResetWires[368] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2917 ) , + .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2918 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2919 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2920 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2921 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2922 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2923 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2924 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2925 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2926 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2927 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2928 ) , + .clk_1_N_in ( clk_2_wires[54] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2929 ) , + .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2930 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2931 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2933 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2934 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2935 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2936 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2937 ) ) ; +sb_1__1_ sb_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2938 } ) , + .chany_top_in ( cby_1__1__32_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__40_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__31_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__29_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__40_ccff_tail ) , + .chany_top_out ( sb_1__1__29_chany_top_out ) , + .chanx_right_out ( sb_1__1__29_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__29_chanx_left_out ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2939 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2940 ) , + .pReset_E_in ( pResetWires[417] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2941 ) , + .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2942 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2943 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2945 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2946 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[50] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2947 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2948 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2949 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2950 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2951 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2952 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2953 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2954 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2955 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2956 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2957 ) , + .clk_2_E_in ( clk_2_wires[50] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2958 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2959 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2960 ) , + .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2961 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2962 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2963 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2964 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2965 ) ) ; +sb_1__1_ sb_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2966 } ) , + .chany_top_in ( cby_1__1__33_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__41_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__32_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__30_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__41_ccff_tail ) , + .chany_top_out ( sb_1__1__30_chany_top_out ) , + .chanx_right_out ( sb_1__1__30_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__30_chanx_left_out ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2967 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2968 ) , + .pReset_E_in ( pResetWires[466] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2969 ) , + .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2970 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2971 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2972 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2973 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2974 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2975 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2976 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2978 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2979 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2980 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2981 ) , + .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2982 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2983 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2984 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2985 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2986 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2987 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2988 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2989 ) ) ; +sb_1__1_ sb_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2990 } ) , + .chany_top_in ( cby_1__1__34_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__42_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__33_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__31_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__42_ccff_tail ) , + .chany_top_out ( sb_1__1__31_chany_top_out ) , + .chanx_right_out ( sb_1__1__31_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__31_chanx_left_out ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2991 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2992 ) , + .pReset_E_in ( pResetWires[515] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2993 ) , + .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2994 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2995 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2997 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2998 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[63] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2999 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3000 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3001 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3002 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3003 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3004 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3005 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3007 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3008 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3009 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3010 ) , + .clk_2_E_in ( clk_2_wires[63] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3011 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3012 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3013 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3014 ) , + .clk_2_N_out ( clk_2_wires[64] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3015 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3016 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3017 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3018 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3019 ) ) ; +sb_1__1_ sb_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3020 } ) , + .chany_top_in ( cby_1__1__35_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__43_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__34_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__32_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__43_ccff_tail ) , + .chany_top_out ( sb_1__1__32_chany_top_out ) , + .chanx_right_out ( sb_1__1__32_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__32_chanx_left_out ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3021 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3022 ) , + .pReset_E_in ( pResetWires[564] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3023 ) , + .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3024 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3025 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3026 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3027 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3028 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3029 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3030 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3031 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3032 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3033 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3034 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3035 ) , + .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3036 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3037 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3039 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3040 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3041 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3042 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3043 ) ) ; +sb_1__1_ sb_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3044 } ) , + .chany_top_in ( cby_1__1__37_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__44_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__36_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__33_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__44_ccff_tail ) , + .chany_top_out ( sb_1__1__33_chany_top_out ) , + .chanx_right_out ( sb_1__1__33_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__33_chanx_left_out ) , + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3045 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3046 ) , + .pReset_E_in ( pResetWires[78] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3047 ) , + .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3048 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3049 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3051 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3052 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3053 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3054 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3055 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3056 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3057 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3058 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3059 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3060 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3064 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3065 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3066 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3067 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3068 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3069 ) ) ; +sb_1__1_ sb_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3070 } ) , + .chany_top_in ( cby_1__1__38_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__45_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__37_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__34_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__45_ccff_tail ) , + .chany_top_out ( sb_1__1__34_chany_top_out ) , + .chanx_right_out ( sb_1__1__34_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__34_chanx_left_out ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3071 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3072 ) , + .pReset_E_in ( pResetWires[127] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3073 ) , + .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3074 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3075 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3077 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3078 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3079 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3080 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3081 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3082 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3083 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3084 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3085 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3086 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3087 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3088 ) , + .clk_2_N_in ( clk_3_wires[25] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3089 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3090 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3091 ) , + .clk_2_W_out ( clk_2_wires[27] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3092 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3093 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3094 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3095 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3096 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3097 ) ) ; +sb_1__1_ sb_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3098 } ) , + .chany_top_in ( cby_1__1__39_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__46_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__38_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__35_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__46_ccff_tail ) , + .chany_top_out ( sb_1__1__35_chany_top_out ) , + .chanx_right_out ( sb_1__1__35_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__35_chanx_left_out ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3099 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3100 ) , + .pReset_E_in ( pResetWires[176] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3101 ) , + .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3102 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3103 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3105 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3106 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3107 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3108 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3109 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3110 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3111 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3112 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[21] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3113 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3114 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3115 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3116 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3117 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3118 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3119 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3120 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3121 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3122 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3123 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3124 ) , + .clk_3_N_in ( clk_3_wires[21] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3125 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3126 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3127 ) , + .clk_3_S_out ( clk_3_wires[24] ) ) ; +sb_1__1_ sb_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3128 } ) , + .chany_top_in ( cby_1__1__40_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__47_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__39_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__36_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__47_ccff_tail ) , + .chany_top_out ( sb_1__1__36_chany_top_out ) , + .chanx_right_out ( sb_1__1__36_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__36_chanx_left_out ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3129 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3130 ) , + .pReset_E_in ( pResetWires[225] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3131 ) , + .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3132 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3133 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3135 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3136 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3137 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3138 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[36] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3139 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3140 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[34] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3141 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3142 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3143 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[15] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3144 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3145 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3146 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3147 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3148 ) , + .clk_2_N_in ( clk_3_wires[15] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3149 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3150 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3151 ) , + .clk_2_W_out ( clk_2_wires[36] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3152 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3153 ) , + .clk_2_E_out ( clk_2_wires[34] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3154 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3155 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3156 ) , + .clk_3_N_in ( clk_3_wires[15] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3157 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3158 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3159 ) , + .clk_3_S_out ( clk_3_wires[20] ) ) ; +sb_1__1_ sb_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3160 } ) , + .chany_top_in ( cby_1__1__41_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__48_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__40_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__37_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__48_ccff_tail ) , + .chany_top_out ( sb_1__1__37_chany_top_out ) , + .chanx_right_out ( sb_1__1__37_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__37_chanx_left_out ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3161 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3162 ) , + .pReset_E_in ( pResetWires[274] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3163 ) , + .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3164 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3165 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3167 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3168 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3169 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3170 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3171 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3172 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3173 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3174 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[11] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3175 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3176 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3177 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3178 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3179 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3181 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3182 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3183 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3184 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3185 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3186 ) , + .clk_3_N_in ( clk_3_wires[11] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3187 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3188 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3189 ) , + .clk_3_S_out ( clk_3_wires[14] ) ) ; +sb_1__1_ sb_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3190 } ) , + .chany_top_in ( cby_1__1__42_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__49_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__41_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__38_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__49_ccff_tail ) , + .chany_top_out ( sb_1__1__38_chany_top_out ) , + .chanx_right_out ( sb_1__1__38_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__38_chanx_left_out ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3191 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3192 ) , + .pReset_E_in ( pResetWires[323] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3193 ) , + .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3194 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3195 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3197 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3198 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3199 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3200 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3201 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3202 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[7] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3203 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3204 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3205 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , + .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3206 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3207 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3209 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3210 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3211 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3212 ) , + .clk_3_E_in ( clk_3_wires[7] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3213 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3214 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3215 ) , + .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) , + .clk_3_S_out ( clk_3_wires[10] ) ) ; +sb_1__1_ sb_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3216 } ) , + .chany_top_in ( cby_1__1__43_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__50_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__42_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__39_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__50_ccff_tail ) , + .chany_top_out ( sb_1__1__39_chany_top_out ) , + .chanx_right_out ( sb_1__1__39_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__39_chanx_left_out ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3217 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3218 ) , + .pReset_E_in ( pResetWires[372] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3219 ) , + .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3220 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3221 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3223 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3224 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3225 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3226 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3227 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3228 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3229 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[9] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3230 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3231 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3232 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3233 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3234 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3237 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3238 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3239 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3240 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3241 ) , + .clk_3_S_in ( clk_3_wires[9] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3242 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3243 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3244 ) , + .clk_3_N_out ( clk_3_wires[12] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3245 ) ) ; +sb_1__1_ sb_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3246 } ) , + .chany_top_in ( cby_1__1__44_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__51_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__43_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__40_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__51_ccff_tail ) , + .chany_top_out ( sb_1__1__40_chany_top_out ) , + .chanx_right_out ( sb_1__1__40_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__40_chanx_left_out ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3247 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3248 ) , + .pReset_E_in ( pResetWires[421] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3249 ) , + .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3250 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3251 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3253 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3254 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3255 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[13] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3256 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[49] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3257 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3258 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[47] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3259 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3260 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[13] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3261 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3262 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3263 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3264 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3265 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3266 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3267 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3268 ) , + .clk_2_S_in ( clk_3_wires[13] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3269 ) , + .clk_2_W_out ( clk_2_wires[49] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3270 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3271 ) , + .clk_2_E_out ( clk_2_wires[47] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3272 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3273 ) , + .clk_3_S_in ( clk_3_wires[13] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3274 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3275 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3276 ) , + .clk_3_N_out ( clk_3_wires[18] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3277 ) ) ; +sb_1__1_ sb_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3278 } ) , + .chany_top_in ( cby_1__1__45_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__52_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__44_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__41_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__52_ccff_tail ) , + .chany_top_out ( sb_1__1__41_chany_top_out ) , + .chanx_right_out ( sb_1__1__41_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__41_chanx_left_out ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3279 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3280 ) , + .pReset_E_in ( pResetWires[470] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3281 ) , + .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3282 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3283 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3285 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3286 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3287 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3288 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3289 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3290 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3291 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[19] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3292 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3293 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3294 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3295 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3296 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3299 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3301 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3302 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3303 ) , + .clk_3_S_in ( clk_3_wires[19] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3304 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3305 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3306 ) , + .clk_3_N_out ( clk_3_wires[22] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3307 ) ) ; +sb_1__1_ sb_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3308 } ) , + .chany_top_in ( cby_1__1__46_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__53_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__45_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__42_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__53_ccff_tail ) , + .chany_top_out ( sb_1__1__42_chany_top_out ) , + .chanx_right_out ( sb_1__1__42_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__42_chanx_left_out ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3309 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3310 ) , + .pReset_E_in ( pResetWires[519] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3311 ) , + .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3312 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3313 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3315 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3316 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3317 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[23] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3318 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3319 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3320 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3322 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3323 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3324 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3325 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3326 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3327 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3328 ) , + .clk_2_S_in ( clk_3_wires[23] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3329 ) , + .clk_2_W_out ( clk_2_wires[62] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3330 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3331 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3332 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3333 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3334 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3335 ) ) ; +sb_1__1_ sb_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3336 } ) , + .chany_top_in ( cby_1__1__47_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__54_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__46_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__43_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__54_ccff_tail ) , + .chany_top_out ( sb_1__1__43_chany_top_out ) , + .chanx_right_out ( sb_1__1__43_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__43_chanx_left_out ) , + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3337 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3338 ) , + .pReset_E_in ( pResetWires[568] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3339 ) , + .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3340 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3341 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3343 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3344 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3345 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3346 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3347 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3348 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3349 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3350 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3351 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3352 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3355 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3356 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3357 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3358 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3359 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3360 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3361 ) ) ; +sb_1__1_ sb_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3362 } ) , + .chany_top_in ( cby_1__1__49_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__55_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__48_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__44_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__55_ccff_tail ) , + .chany_top_out ( sb_1__1__44_chany_top_out ) , + .chanx_right_out ( sb_1__1__44_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__44_chanx_left_out ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3363 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3364 ) , + .pReset_E_in ( pResetWires[82] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3365 ) , + .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3366 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3367 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3368 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3369 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3370 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3371 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3372 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3373 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3374 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3375 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3376 ) , + .clk_1_N_in ( clk_2_wires[32] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3377 ) , + .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3378 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3379 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3381 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3382 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3383 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3384 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3385 ) ) ; +sb_1__1_ sb_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3386 } ) , + .chany_top_in ( cby_1__1__50_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__56_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__49_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__45_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__56_ccff_tail ) , + .chany_top_out ( sb_1__1__45_chany_top_out ) , + .chanx_right_out ( sb_1__1__45_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__45_chanx_left_out ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3387 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3388 ) , + .pReset_E_in ( pResetWires[131] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3389 ) , + .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3390 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3391 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3393 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3394 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3395 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3396 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[26] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3397 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3398 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3399 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3400 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3401 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3402 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3403 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3404 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3405 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3406 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3407 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3408 ) , + .clk_2_W_in ( clk_2_wires[26] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3409 ) , + .clk_2_S_out ( clk_2_wires[31] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3410 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3411 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3412 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3413 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3414 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3415 ) ) ; +sb_1__1_ sb_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3416 } ) , + .chany_top_in ( cby_1__1__51_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__57_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__50_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__46_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__57_ccff_tail ) , + .chany_top_out ( sb_1__1__46_chany_top_out ) , + .chanx_right_out ( sb_1__1__46_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__46_chanx_left_out ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3417 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3418 ) , + .pReset_E_in ( pResetWires[180] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3419 ) , + .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3420 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3421 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3422 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3423 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3424 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3425 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3426 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3427 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3428 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3429 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3430 ) , + .clk_1_N_in ( clk_2_wires[45] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3431 ) , + .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3432 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3433 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3435 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3436 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3437 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3438 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3439 ) ) ; +sb_1__1_ sb_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3440 } ) , + .chany_top_in ( cby_1__1__52_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__58_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__51_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__47_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__58_ccff_tail ) , + .chany_top_out ( sb_1__1__47_chany_top_out ) , + .chanx_right_out ( sb_1__1__47_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__47_chanx_left_out ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3441 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3442 ) , + .pReset_E_in ( pResetWires[229] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3443 ) , + .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3444 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3445 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3447 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3448 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3449 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3450 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[35] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3451 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3452 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3453 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3454 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3455 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3456 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3457 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3458 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3459 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3460 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3461 ) , + .clk_2_W_in ( clk_2_wires[35] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3462 ) , + .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3463 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3464 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3465 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3466 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3467 ) ) ; +sb_1__1_ sb_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3468 } ) , + .chany_top_in ( cby_1__1__53_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__59_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__52_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__48_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__59_ccff_tail ) , + .chany_top_out ( sb_1__1__48_chany_top_out ) , + .chanx_right_out ( sb_1__1__48_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__48_chanx_left_out ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3469 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3470 ) , + .pReset_E_in ( pResetWires[278] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3471 ) , + .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3472 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3473 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3474 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3475 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3476 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3477 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3478 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3479 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3480 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3481 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3482 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3483 ) , + .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3484 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3485 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3486 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3487 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3488 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3489 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3490 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3491 ) ) ; +sb_1__1_ sb_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3492 } ) , + .chany_top_in ( cby_1__1__54_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__60_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__53_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__49_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__60_ccff_tail ) , + .chany_top_out ( sb_1__1__49_chany_top_out ) , + .chanx_right_out ( sb_1__1__49_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__49_chanx_left_out ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3493 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3494 ) , + .pReset_E_in ( pResetWires[327] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3495 ) , + .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3496 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3497 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3499 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3500 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3501 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3502 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3503 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3504 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[3] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3505 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3506 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3507 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3508 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3509 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3510 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3513 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3514 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3515 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3516 ) , + .clk_3_E_in ( clk_3_wires[3] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3517 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3518 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3519 ) , + .clk_3_W_out ( clk_3_wires[6] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3520 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3521 ) ) ; +sb_1__1_ sb_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3522 } ) , + .chany_top_in ( cby_1__1__55_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__61_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__54_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__50_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__61_ccff_tail ) , + .chany_top_out ( sb_1__1__50_chany_top_out ) , + .chanx_right_out ( sb_1__1__50_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__50_chanx_left_out ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3523 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3524 ) , + .pReset_E_in ( pResetWires[376] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3525 ) , + .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3526 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3527 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3528 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3529 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3530 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3531 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3532 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3533 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3534 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3535 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3536 ) , + .clk_1_N_in ( clk_2_wires[58] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3537 ) , + .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3538 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3539 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3540 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3541 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3542 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3543 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3544 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3545 ) ) ; +sb_1__1_ sb_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3546 } ) , + .chany_top_in ( cby_1__1__56_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__62_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__55_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__51_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__62_ccff_tail ) , + .chany_top_out ( sb_1__1__51_chany_top_out ) , + .chanx_right_out ( sb_1__1__51_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__51_chanx_left_out ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3547 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3548 ) , + .pReset_E_in ( pResetWires[425] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3549 ) , + .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3550 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3551 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3553 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3554 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3555 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3556 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[48] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3557 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3558 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3559 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3560 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3561 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3562 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3563 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3564 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3565 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3566 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3567 ) , + .clk_2_W_in ( clk_2_wires[48] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3568 ) , + .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3569 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3570 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3571 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3572 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3573 ) ) ; +sb_1__1_ sb_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3574 } ) , + .chany_top_in ( cby_1__1__57_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__63_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__56_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__52_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__63_ccff_tail ) , + .chany_top_out ( sb_1__1__52_chany_top_out ) , + .chanx_right_out ( sb_1__1__52_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__52_chanx_left_out ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3575 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3576 ) , + .pReset_E_in ( pResetWires[474] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3577 ) , + .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3578 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3579 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3580 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3581 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3582 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3583 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3584 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3585 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3586 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3587 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3588 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3589 ) , + .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3590 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3591 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3592 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3594 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3595 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3596 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3597 ) ) ; +sb_1__1_ sb_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3598 } ) , + .chany_top_in ( cby_1__1__58_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__64_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__57_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__53_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__64_ccff_tail ) , + .chany_top_out ( sb_1__1__53_chany_top_out ) , + .chanx_right_out ( sb_1__1__53_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__53_chanx_left_out ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3599 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3600 ) , + .pReset_E_in ( pResetWires[523] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3601 ) , + .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3602 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3603 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3605 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3606 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3607 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3608 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[61] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3609 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3610 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3611 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3612 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3613 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3614 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3615 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3616 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3617 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3618 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3619 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3620 ) , + .clk_2_W_in ( clk_2_wires[61] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3621 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3622 ) , + .clk_2_N_out ( clk_2_wires[66] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3623 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3624 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3625 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3626 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3627 ) ) ; +sb_1__1_ sb_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3628 } ) , + .chany_top_in ( cby_1__1__59_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__65_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__58_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__54_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__65_ccff_tail ) , + .chany_top_out ( sb_1__1__54_chany_top_out ) , + .chanx_right_out ( sb_1__1__54_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__54_chanx_left_out ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3629 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3630 ) , + .pReset_E_in ( pResetWires[572] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3631 ) , + .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3632 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3633 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3634 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3635 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3636 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3637 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3638 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3639 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3640 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3641 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3642 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3643 ) , + .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3644 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3645 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3646 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3647 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3648 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3649 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3650 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3651 ) ) ; +sb_1__1_ sb_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3652 } ) , + .chany_top_in ( cby_1__1__61_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__66_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__60_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__55_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__66_ccff_tail ) , + .chany_top_out ( sb_1__1__55_chany_top_out ) , + .chanx_right_out ( sb_1__1__55_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__55_chanx_left_out ) , + .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) , + .Test_en_N_out ( Test_enWires[3] ) , .pReset_S_in ( pResetWires[2] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3653 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3654 ) , + .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) , + .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) , + .Reset_N_out ( ResetWires[3] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3655 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3656 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3657 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3658 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3659 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3660 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3661 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3662 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[89] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3663 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3664 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3665 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3666 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3667 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3669 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3670 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3671 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3672 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3673 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3674 ) , + .clk_3_S_in ( clk_3_wires[89] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3675 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3676 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3677 ) , + .clk_3_N_out ( clk_3_wires[92] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3678 ) ) ; +sb_1__1_ sb_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3679 } ) , + .chany_top_in ( cby_1__1__62_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__67_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__61_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__56_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__67_ccff_tail ) , + .chany_top_out ( sb_1__1__56_chany_top_out ) , + .chanx_right_out ( sb_1__1__56_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__56_chanx_left_out ) , + .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) , + .Test_en_N_out ( Test_enWires[5] ) , .pReset_S_in ( pResetWires[4] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3680 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3681 ) , + .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) , + .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) , + .Reset_N_out ( ResetWires[5] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3682 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3683 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3684 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3685 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3686 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3687 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3688 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3689 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[91] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3690 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3691 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3692 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3693 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3694 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3697 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3698 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3699 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3700 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3701 ) , + .clk_3_S_in ( clk_3_wires[91] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3702 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3703 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3704 ) , + .clk_3_N_out ( clk_3_wires[94] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3705 ) ) ; +sb_1__1_ sb_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3706 } ) , + .chany_top_in ( cby_1__1__63_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__68_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__62_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__57_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__68_ccff_tail ) , + .chany_top_out ( sb_1__1__57_chany_top_out ) , + .chanx_right_out ( sb_1__1__57_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__57_chanx_left_out ) , + .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) , + .Test_en_N_out ( Test_enWires[7] ) , .pReset_S_in ( pResetWires[6] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3707 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3708 ) , + .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) , + .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) , + .Reset_N_out ( ResetWires[7] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3709 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3710 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3711 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3712 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3713 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3714 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3715 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3716 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[93] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3717 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3718 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3719 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3720 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3721 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3723 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3724 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3725 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3726 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3727 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3728 ) , + .clk_3_S_in ( clk_3_wires[93] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3729 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3730 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3731 ) , + .clk_3_N_out ( clk_3_wires[96] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3732 ) ) ; +sb_1__1_ sb_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3733 } ) , + .chany_top_in ( cby_1__1__64_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__69_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__63_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__58_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__69_ccff_tail ) , + .chany_top_out ( sb_1__1__58_chany_top_out ) , + .chanx_right_out ( sb_1__1__58_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__58_chanx_left_out ) , + .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) , + .Test_en_N_out ( Test_enWires[9] ) , .pReset_S_in ( pResetWires[8] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3734 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3735 ) , + .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) , + .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) , + .Reset_N_out ( ResetWires[9] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3736 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3737 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3738 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3739 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3740 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3741 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3742 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3743 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[95] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3744 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3745 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3746 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3747 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3748 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3751 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3752 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3753 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3754 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3755 ) , + .clk_3_S_in ( clk_3_wires[95] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3756 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3757 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3758 ) , + .clk_3_N_out ( clk_3_wires[98] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3759 ) ) ; +sb_1__1_ sb_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3760 } ) , + .chany_top_in ( cby_1__1__65_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__70_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__64_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__59_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__70_ccff_tail ) , + .chany_top_out ( sb_1__1__59_chany_top_out ) , + .chanx_right_out ( sb_1__1__59_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__59_chanx_left_out ) , + .ccff_tail ( sb_1__1__59_ccff_tail ) , + .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) , + .pReset_S_in ( pResetWires[10] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3761 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3762 ) , + .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) , + .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) , + .Reset_N_out ( ResetWires[11] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3763 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3764 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3765 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3766 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3767 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3768 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3769 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3770 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[97] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3771 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3772 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3773 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3774 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3775 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3778 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3779 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3780 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3781 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3782 ) , + .clk_3_S_in ( clk_3_wires[97] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3783 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3784 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3785 ) , + .clk_3_N_out ( clk_3_wires[100] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3786 ) ) ; +sb_1__1_ sb_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3787 } ) , + .chany_top_in ( cby_1__1__66_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__71_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__65_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__60_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__71_ccff_tail ) , + .chany_top_out ( sb_1__1__60_chany_top_out ) , + .chanx_right_out ( sb_1__1__60_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__60_chanx_left_out ) , + .ccff_tail ( sb_1__1__60_ccff_tail ) , + .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) , + .pReset_S_in ( pResetWires[12] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3788 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3789 ) , + .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) , + .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) , + .Reset_N_out ( ResetWires[13] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3790 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3791 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3792 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3793 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3795 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3796 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3797 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[99] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3798 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , + .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3799 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3800 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3801 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3804 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3805 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3806 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3807 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3808 ) , + .clk_3_S_in ( clk_3_wires[99] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3809 ) , + .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3810 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3811 ) ) ; +sb_1__1_ sb_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3812 } ) , + .chany_top_in ( cby_1__1__67_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__72_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__66_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__61_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__72_ccff_tail ) , + .chany_top_out ( sb_1__1__61_chany_top_out ) , + .chanx_right_out ( sb_1__1__61_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__61_chanx_left_out ) , + .ccff_tail ( sb_1__1__61_ccff_tail ) , + .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) , + .pReset_S_in ( pResetWires[14] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3813 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3814 ) , + .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) , + .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) , + .Reset_N_out ( ResetWires[15] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3815 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3816 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3817 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3818 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3819 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3820 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3821 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3822 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3823 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3824 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3825 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3828 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3829 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3831 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3832 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3833 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3834 ) ) ; +sb_1__1_ sb_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3835 } ) , + .chany_top_in ( cby_1__1__68_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__73_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__67_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__62_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__73_ccff_tail ) , + .chany_top_out ( sb_1__1__62_chany_top_out ) , + .chanx_right_out ( sb_1__1__62_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__62_chanx_left_out ) , + .ccff_tail ( sb_1__1__62_ccff_tail ) , + .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) , + .pReset_S_in ( pResetWires[16] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3836 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3837 ) , + .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) , + .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) , + .Reset_N_out ( ResetWires[17] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3838 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3839 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3840 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3841 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3842 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3843 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3844 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3845 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3846 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3847 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3848 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3850 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3853 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3854 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3855 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3856 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3857 ) ) ; +sb_1__1_ sb_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3858 } ) , + .chany_top_in ( cby_1__1__69_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__74_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__68_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__63_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__74_ccff_tail ) , + .chany_top_out ( sb_1__1__63_chany_top_out ) , + .chanx_right_out ( sb_1__1__63_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__63_chanx_left_out ) , + .ccff_tail ( sb_1__1__63_ccff_tail ) , + .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) , + .pReset_S_in ( pResetWires[18] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3859 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3860 ) , + .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) , + .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) , + .Reset_N_out ( ResetWires[19] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3861 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3862 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3863 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3864 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3865 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3866 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3867 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3868 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3869 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3870 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3871 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3874 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3875 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3876 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3878 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3879 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3880 ) ) ; +sb_1__1_ sb_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3881 } ) , + .chany_top_in ( cby_1__1__70_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__75_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__69_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__64_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__75_ccff_tail ) , + .chany_top_out ( sb_1__1__64_chany_top_out ) , + .chanx_right_out ( sb_1__1__64_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__64_chanx_left_out ) , + .ccff_tail ( sb_1__1__64_ccff_tail ) , + .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) , + .pReset_S_in ( pResetWires[20] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3882 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3883 ) , + .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) , + .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) , + .Reset_N_out ( ResetWires[21] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3884 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3885 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3886 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3887 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3888 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3889 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3890 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3891 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3892 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3893 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3894 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3897 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3898 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3899 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3901 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3902 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3903 ) ) ; +sb_1__1_ sb_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3904 } ) , + .chany_top_in ( cby_1__1__71_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__76_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__70_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__65_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__76_ccff_tail ) , + .chany_top_out ( sb_1__1__65_chany_top_out ) , + .chanx_right_out ( sb_1__1__65_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__65_chanx_left_out ) , + .ccff_tail ( sb_1__1__65_ccff_tail ) , + .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) , + .pReset_S_in ( pResetWires[22] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3905 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3906 ) , + .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) , + .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) , + .Reset_N_out ( ResetWires[23] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3907 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3908 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3909 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3910 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3911 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3912 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3913 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3914 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3915 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3916 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3917 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3919 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3920 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3921 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3922 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3923 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3924 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3925 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3926 ) ) ; +sb_1__1_ sb_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3927 } ) , + .chany_top_in ( cby_1__1__73_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__77_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__72_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__66_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__77_ccff_tail ) , + .chany_top_out ( sb_1__1__66_chany_top_out ) , + .chanx_right_out ( sb_1__1__66_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__66_chanx_left_out ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3928 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3929 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3930 ) , + .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3931 ) , + .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3932 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3933 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3934 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3935 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3936 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3937 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3938 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3939 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3940 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3941 ) , + .clk_1_N_in ( clk_2_wires[74] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3942 ) , + .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3943 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3944 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3946 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3947 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3948 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3949 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3950 ) ) ; +sb_1__1_ sb_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3951 } ) , + .chany_top_in ( cby_1__1__74_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__78_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__73_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__67_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__78_ccff_tail ) , + .chany_top_out ( sb_1__1__67_chany_top_out ) , + .chanx_right_out ( sb_1__1__67_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__67_chanx_left_out ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3952 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3953 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3954 ) , + .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3955 ) , + .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3956 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3957 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3958 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3959 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[72] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3960 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3961 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3962 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3963 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3964 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3965 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3966 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3967 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3968 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3969 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3970 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3971 ) , + .clk_2_E_in ( clk_2_wires[72] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3972 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3973 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3974 ) , + .clk_2_S_out ( clk_2_wires[73] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3975 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3976 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3977 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3978 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3979 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3980 ) ) ; +sb_1__1_ sb_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3981 } ) , + .chany_top_in ( cby_1__1__75_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__79_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__74_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__68_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__79_ccff_tail ) , + .chany_top_out ( sb_1__1__68_chany_top_out ) , + .chanx_right_out ( sb_1__1__68_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__68_chanx_left_out ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3982 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3983 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3984 ) , + .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3985 ) , + .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3986 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3987 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3988 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3989 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3990 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3991 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3992 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3993 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3994 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3995 ) , + .clk_1_N_in ( clk_2_wires[85] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3996 ) , + .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3997 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3998 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4002 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4003 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4004 ) ) ; +sb_1__1_ sb_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4005 } ) , + .chany_top_in ( cby_1__1__76_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__80_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__75_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__69_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__80_ccff_tail ) , + .chany_top_out ( sb_1__1__69_chany_top_out ) , + .chanx_right_out ( sb_1__1__69_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__69_chanx_left_out ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4006 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4007 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4008 ) , + .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4009 ) , + .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4010 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4011 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4012 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4013 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[81] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4014 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4015 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4016 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4017 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4018 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4019 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4020 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4021 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4022 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4023 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4024 ) , + .clk_2_E_in ( clk_2_wires[81] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4025 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4026 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4027 ) , + .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4028 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4029 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4030 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4031 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4032 ) ) ; +sb_1__1_ sb_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4033 } ) , + .chany_top_in ( cby_1__1__77_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__81_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__76_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__70_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__81_ccff_tail ) , + .chany_top_out ( sb_1__1__70_chany_top_out ) , + .chanx_right_out ( sb_1__1__70_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__70_chanx_left_out ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4034 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4035 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4036 ) , + .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4037 ) , + .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4038 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4039 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4040 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4041 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4042 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4043 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4044 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4045 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4046 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4047 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4048 ) , + .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4049 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4050 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4051 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4052 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4053 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4054 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4055 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4056 ) ) ; +sb_1__1_ sb_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4057 } ) , + .chany_top_in ( cby_1__1__78_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__82_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__77_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__71_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__82_ccff_tail ) , + .chany_top_out ( sb_1__1__71_chany_top_out ) , + .chanx_right_out ( sb_1__1__71_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__71_chanx_left_out ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4058 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4059 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4060 ) , + .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4061 ) , + .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4062 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4063 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4064 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4065 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4066 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4067 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4068 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[1] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4069 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4070 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4071 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4072 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4073 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4074 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4075 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4078 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4079 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4080 ) , + .clk_3_W_in ( clk_3_wires[1] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4081 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4082 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4083 ) , + .clk_3_E_out ( clk_3_wires[4] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4084 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4085 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4086 ) ) ; +sb_1__1_ sb_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4087 } ) , + .chany_top_in ( cby_1__1__79_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__83_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__78_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__72_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__83_ccff_tail ) , + .chany_top_out ( sb_1__1__72_chany_top_out ) , + .chanx_right_out ( sb_1__1__72_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__72_chanx_left_out ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4088 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4089 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4090 ) , + .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4091 ) , + .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4092 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4093 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4094 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4095 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4096 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4097 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4098 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4099 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4100 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4101 ) , + .clk_1_N_in ( clk_2_wires[98] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4102 ) , + .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4103 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4104 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4105 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4106 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4107 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4108 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4109 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4110 ) ) ; +sb_1__1_ sb_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4111 } ) , + .chany_top_in ( cby_1__1__80_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__84_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__79_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__73_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__84_ccff_tail ) , + .chany_top_out ( sb_1__1__73_chany_top_out ) , + .chanx_right_out ( sb_1__1__73_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__73_chanx_left_out ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4112 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4113 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4114 ) , + .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4115 ) , + .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4116 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4117 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4118 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4119 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[94] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4120 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4121 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4122 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4123 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4124 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4125 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4126 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4127 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4128 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4129 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4130 ) , + .clk_2_E_in ( clk_2_wires[94] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4131 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4132 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4133 ) , + .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4134 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4135 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4136 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4137 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4138 ) ) ; +sb_1__1_ sb_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4139 } ) , + .chany_top_in ( cby_1__1__81_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__85_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__80_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__74_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__85_ccff_tail ) , + .chany_top_out ( sb_1__1__74_chany_top_out ) , + .chanx_right_out ( sb_1__1__74_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__74_chanx_left_out ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4140 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4141 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4142 ) , + .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4143 ) , + .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4144 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4145 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4146 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4147 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4148 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4149 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4150 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4151 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4152 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4153 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4154 ) , + .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4155 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4156 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4157 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4158 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4159 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4160 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4161 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4162 ) ) ; +sb_1__1_ sb_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4163 } ) , + .chany_top_in ( cby_1__1__82_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__86_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__81_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__75_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__86_ccff_tail ) , + .chany_top_out ( sb_1__1__75_chany_top_out ) , + .chanx_right_out ( sb_1__1__75_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__75_chanx_left_out ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4164 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4165 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4166 ) , + .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4167 ) , + .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4168 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4169 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4170 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4171 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[107] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4172 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4173 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4174 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4175 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4176 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4177 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4178 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4179 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4180 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4181 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4182 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4183 ) , + .clk_2_E_in ( clk_2_wires[107] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4184 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4185 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4186 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4187 ) , + .clk_2_N_out ( clk_2_wires[108] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4188 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4189 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4190 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4192 ) ) ; +sb_1__1_ sb_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4193 } ) , + .chany_top_in ( cby_1__1__83_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__87_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__82_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__76_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__87_ccff_tail ) , + .chany_top_out ( sb_1__1__76_chany_top_out ) , + .chanx_right_out ( sb_1__1__76_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__76_chanx_left_out ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4194 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4195 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4196 ) , + .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4197 ) , + .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4198 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4199 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4200 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4201 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4202 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4203 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4204 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4205 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4206 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4207 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4208 ) , + .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4209 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4210 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4211 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4212 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4213 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4214 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4215 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4216 ) ) ; +sb_1__1_ sb_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4217 } ) , + .chany_top_in ( cby_1__1__85_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__88_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__84_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__77_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__88_ccff_tail ) , + .chany_top_out ( sb_1__1__77_chany_top_out ) , + .chanx_right_out ( sb_1__1__77_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__77_chanx_left_out ) , + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4218 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4219 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4220 ) , + .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4221 ) , + .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4222 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4223 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4224 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4225 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4226 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4227 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4228 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4229 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4230 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4231 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4232 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4233 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4236 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4237 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4239 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4240 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4241 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4242 ) ) ; +sb_1__1_ sb_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4243 } ) , + .chany_top_in ( cby_1__1__86_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__89_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__85_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__78_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__89_ccff_tail ) , + .chany_top_out ( sb_1__1__78_chany_top_out ) , + .chanx_right_out ( sb_1__1__78_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__78_chanx_left_out ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4244 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4245 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4246 ) , + .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4247 ) , + .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4248 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4249 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4250 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4251 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4252 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4253 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4254 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4255 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4256 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4257 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4258 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4259 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4260 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4261 ) , + .clk_2_N_in ( clk_3_wires[43] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4262 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4263 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4264 ) , + .clk_2_W_out ( clk_2_wires[71] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4265 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4266 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4267 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4268 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4269 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4270 ) ) ; +sb_1__1_ sb_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4271 } ) , + .chany_top_in ( cby_1__1__87_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__90_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__86_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__79_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__90_ccff_tail ) , + .chany_top_out ( sb_1__1__79_chany_top_out ) , + .chanx_right_out ( sb_1__1__79_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__79_chanx_left_out ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4272 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4273 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4274 ) , + .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4275 ) , + .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4276 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4277 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4278 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4279 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4280 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4281 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4282 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4283 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4284 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4285 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[39] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4286 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4287 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4288 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4289 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4290 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4292 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4293 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4294 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4295 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4296 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4297 ) , + .clk_3_N_in ( clk_3_wires[39] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4298 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4299 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4300 ) , + .clk_3_S_out ( clk_3_wires[42] ) ) ; +sb_1__1_ sb_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4301 } ) , + .chany_top_in ( cby_1__1__88_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__91_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__87_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__80_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__91_ccff_tail ) , + .chany_top_out ( sb_1__1__80_chany_top_out ) , + .chanx_right_out ( sb_1__1__80_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__80_chanx_left_out ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4302 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4303 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4304 ) , + .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4305 ) , + .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4306 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4307 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4308 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4309 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4310 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4311 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[80] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4312 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4313 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[78] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4314 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4315 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4316 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[33] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4317 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4318 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4319 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4320 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4321 ) , + .clk_2_N_in ( clk_3_wires[33] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4322 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4323 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4324 ) , + .clk_2_W_out ( clk_2_wires[80] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4325 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4326 ) , + .clk_2_E_out ( clk_2_wires[78] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4327 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4328 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4329 ) , + .clk_3_N_in ( clk_3_wires[33] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4330 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4331 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4332 ) , + .clk_3_S_out ( clk_3_wires[38] ) ) ; +sb_1__1_ sb_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4333 } ) , + .chany_top_in ( cby_1__1__89_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__92_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__88_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__81_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__92_ccff_tail ) , + .chany_top_out ( sb_1__1__81_chany_top_out ) , + .chanx_right_out ( sb_1__1__81_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__81_chanx_left_out ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4334 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4335 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4336 ) , + .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4337 ) , + .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4338 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4339 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4340 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4341 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4342 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4343 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4344 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4345 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4346 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4347 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[29] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4348 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4349 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4350 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4351 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4352 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4353 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4354 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4355 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4356 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4357 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4358 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4359 ) , + .clk_3_N_in ( clk_3_wires[29] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4360 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4361 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4362 ) , + .clk_3_S_out ( clk_3_wires[32] ) ) ; +sb_1__1_ sb_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4363 } ) , + .chany_top_in ( cby_1__1__90_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__93_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__89_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__82_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__93_ccff_tail ) , + .chany_top_out ( sb_1__1__82_chany_top_out ) , + .chanx_right_out ( sb_1__1__82_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__82_chanx_left_out ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4364 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4365 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4366 ) , + .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4367 ) , + .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4368 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4369 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4370 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4371 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4372 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4373 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4374 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[5] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4375 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4376 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4377 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4378 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4379 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4380 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4382 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4383 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4384 ) , + .clk_3_W_in ( clk_3_wires[5] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4385 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4386 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4387 ) , + .clk_3_E_out ( clk_3_wires[44] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4388 ) , + .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ; +sb_1__1_ sb_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4389 } ) , + .chany_top_in ( cby_1__1__91_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__94_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__90_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__83_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__94_ccff_tail ) , + .chany_top_out ( sb_1__1__83_chany_top_out ) , + .chanx_right_out ( sb_1__1__83_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__83_chanx_left_out ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4390 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4391 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4392 ) , + .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4393 ) , + .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4394 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4395 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4396 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4397 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4398 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4399 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4400 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4401 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4402 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[27] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4403 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4404 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4405 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4406 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4407 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4410 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4411 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4412 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4413 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4414 ) , + .clk_3_S_in ( clk_3_wires[27] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4415 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4416 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4417 ) , + .clk_3_N_out ( clk_3_wires[30] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4418 ) ) ; +sb_1__1_ sb_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4419 } ) , + .chany_top_in ( cby_1__1__92_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__95_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__91_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__84_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__95_ccff_tail ) , + .chany_top_out ( sb_1__1__84_chany_top_out ) , + .chanx_right_out ( sb_1__1__84_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__84_chanx_left_out ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4420 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4421 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4422 ) , + .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4423 ) , + .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4424 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4425 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4426 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4427 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4428 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[31] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4429 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[93] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4430 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4431 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[91] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4432 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4433 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[31] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4434 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4436 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4437 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4438 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4439 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4440 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4441 ) , + .clk_2_S_in ( clk_3_wires[31] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4442 ) , + .clk_2_W_out ( clk_2_wires[93] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4443 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4444 ) , + .clk_2_E_out ( clk_2_wires[91] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4445 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4446 ) , + .clk_3_S_in ( clk_3_wires[31] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4447 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4449 ) , + .clk_3_N_out ( clk_3_wires[36] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4450 ) ) ; +sb_1__1_ sb_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4451 } ) , + .chany_top_in ( cby_1__1__93_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__96_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__92_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__85_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__96_ccff_tail ) , + .chany_top_out ( sb_1__1__85_chany_top_out ) , + .chanx_right_out ( sb_1__1__85_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__85_chanx_left_out ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4452 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4453 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4454 ) , + .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4455 ) , + .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4456 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4457 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4458 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4459 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4460 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4461 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4462 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4463 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4464 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[37] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4465 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4466 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4467 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4468 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4469 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4471 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4472 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4473 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4474 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4475 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4476 ) , + .clk_3_S_in ( clk_3_wires[37] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4477 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4478 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4479 ) , + .clk_3_N_out ( clk_3_wires[40] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4480 ) ) ; +sb_1__1_ sb_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4481 } ) , + .chany_top_in ( cby_1__1__94_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__97_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__93_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__86_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__97_ccff_tail ) , + .chany_top_out ( sb_1__1__86_chany_top_out ) , + .chanx_right_out ( sb_1__1__86_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__86_chanx_left_out ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4482 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4483 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4484 ) , + .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4485 ) , + .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4486 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4487 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4488 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4489 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4490 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[41] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4491 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4492 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4493 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4494 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4495 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4496 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4497 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4498 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4499 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4500 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4501 ) , + .clk_2_S_in ( clk_3_wires[41] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4502 ) , + .clk_2_W_out ( clk_2_wires[106] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4503 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4504 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4505 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4506 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4507 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4508 ) ) ; +sb_1__1_ sb_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4509 } ) , + .chany_top_in ( cby_1__1__95_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__98_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__94_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__87_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__98_ccff_tail ) , + .chany_top_out ( sb_1__1__87_chany_top_out ) , + .chanx_right_out ( sb_1__1__87_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__87_chanx_left_out ) , + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4510 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4511 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4512 ) , + .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4513 ) , + .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4514 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4515 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4516 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4517 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4518 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4519 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4520 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4521 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4522 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4523 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4524 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4525 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4527 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4528 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4529 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4530 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4531 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4532 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4533 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4534 ) ) ; +sb_1__1_ sb_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4535 } ) , + .chany_top_in ( cby_1__1__97_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__99_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__96_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__88_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__99_ccff_tail ) , + .chany_top_out ( sb_1__1__88_chany_top_out ) , + .chanx_right_out ( sb_1__1__88_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__88_chanx_left_out ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4536 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4537 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4538 ) , + .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4539 ) , + .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4540 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4541 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4542 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4543 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4544 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4545 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4546 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4547 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4548 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4549 ) , + .clk_1_N_in ( clk_2_wires[76] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4550 ) , + .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4551 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4552 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4553 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4554 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4555 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4556 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4557 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4558 ) ) ; +sb_1__1_ sb_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4559 } ) , + .chany_top_in ( cby_1__1__98_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__100_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__97_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__89_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__100_ccff_tail ) , + .chany_top_out ( sb_1__1__89_chany_top_out ) , + .chanx_right_out ( sb_1__1__89_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__89_chanx_left_out ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4560 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4561 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4562 ) , + .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4563 ) , + .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4564 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4565 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4566 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4567 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4568 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4569 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[70] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4570 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4571 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4572 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4573 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4574 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4575 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4576 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4577 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4578 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4579 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4580 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4581 ) , + .clk_2_W_in ( clk_2_wires[70] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4582 ) , + .clk_2_S_out ( clk_2_wires[75] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4583 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4584 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4585 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4586 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4587 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4588 ) ) ; +sb_1__1_ sb_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4589 } ) , + .chany_top_in ( cby_1__1__99_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__101_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__98_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__90_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__101_ccff_tail ) , + .chany_top_out ( sb_1__1__90_chany_top_out ) , + .chanx_right_out ( sb_1__1__90_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__90_chanx_left_out ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4590 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4591 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4592 ) , + .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4593 ) , + .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4594 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4595 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4596 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4597 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4598 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4599 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4600 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4601 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4602 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4603 ) , + .clk_1_N_in ( clk_2_wires[89] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4604 ) , + .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4605 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4606 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4607 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4608 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4609 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4610 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4611 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4612 ) ) ; +sb_1__1_ sb_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4613 } ) , + .chany_top_in ( cby_1__1__100_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__102_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__99_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__91_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__102_ccff_tail ) , + .chany_top_out ( sb_1__1__91_chany_top_out ) , + .chanx_right_out ( sb_1__1__91_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__91_chanx_left_out ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4614 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4615 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4616 ) , + .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4617 ) , + .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4618 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4619 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4620 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4621 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4622 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4623 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[79] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4624 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4625 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4626 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4627 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4628 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4629 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4630 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4631 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4632 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4633 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4634 ) , + .clk_2_W_in ( clk_2_wires[79] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4635 ) , + .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4636 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4637 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4638 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4639 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4640 ) ) ; +sb_1__1_ sb_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4641 } ) , + .chany_top_in ( cby_1__1__101_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__103_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__100_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__92_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__103_ccff_tail ) , + .chany_top_out ( sb_1__1__92_chany_top_out ) , + .chanx_right_out ( sb_1__1__92_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__92_chanx_left_out ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4642 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4643 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4644 ) , + .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4645 ) , + .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4646 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4647 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4648 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4649 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4650 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4651 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4652 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4653 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4654 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4655 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4656 ) , + .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4657 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4658 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4659 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4660 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4661 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4662 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4663 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4664 ) ) ; +sb_1__1_ sb_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4665 } ) , + .chany_top_in ( cby_1__1__102_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__104_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__101_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__93_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__104_ccff_tail ) , + .chany_top_out ( sb_1__1__93_chany_top_out ) , + .chanx_right_out ( sb_1__1__93_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__93_chanx_left_out ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4666 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4667 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4668 ) , + .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4669 ) , + .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4670 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4671 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4672 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4673 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4674 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4675 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4676 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[45] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4677 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4678 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4679 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4680 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4682 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4683 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4686 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4687 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4688 ) , + .clk_3_W_in ( clk_3_wires[45] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4689 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4690 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4691 ) , + .clk_3_E_out ( clk_3_wires[48] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4692 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4693 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4694 ) ) ; +sb_1__1_ sb_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4695 } ) , + .chany_top_in ( cby_1__1__103_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__105_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__102_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__94_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__105_ccff_tail ) , + .chany_top_out ( sb_1__1__94_chany_top_out ) , + .chanx_right_out ( sb_1__1__94_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__94_chanx_left_out ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4696 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4697 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4698 ) , + .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4699 ) , + .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4700 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4701 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4702 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4703 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4704 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4705 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4706 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4707 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4708 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4709 ) , + .clk_1_N_in ( clk_2_wires[102] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4710 ) , + .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4711 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4712 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4713 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4714 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4715 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4716 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4717 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4718 ) ) ; +sb_1__1_ sb_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4719 } ) , + .chany_top_in ( cby_1__1__104_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__106_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__103_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__95_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__106_ccff_tail ) , + .chany_top_out ( sb_1__1__95_chany_top_out ) , + .chanx_right_out ( sb_1__1__95_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__95_chanx_left_out ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4720 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4721 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4722 ) , + .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4723 ) , + .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4724 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4725 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4726 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4727 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4728 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4729 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[92] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4730 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4731 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4733 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4734 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4735 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4736 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4737 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4738 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4739 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4740 ) , + .clk_2_W_in ( clk_2_wires[92] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4741 ) , + .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4742 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4743 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4744 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4745 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4746 ) ) ; +sb_1__1_ sb_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4747 } ) , + .chany_top_in ( cby_1__1__105_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__107_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__104_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__96_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__107_ccff_tail ) , + .chany_top_out ( sb_1__1__96_chany_top_out ) , + .chanx_right_out ( sb_1__1__96_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__96_chanx_left_out ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4748 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4749 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4750 ) , + .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4751 ) , + .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4752 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4753 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4754 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4755 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4756 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4757 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4758 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4759 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4760 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4761 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4762 ) , + .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4763 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4764 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4765 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4766 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4767 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4768 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4769 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4770 ) ) ; +sb_1__1_ sb_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4771 } ) , + .chany_top_in ( cby_1__1__106_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__108_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__105_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__97_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__108_ccff_tail ) , + .chany_top_out ( sb_1__1__97_chany_top_out ) , + .chanx_right_out ( sb_1__1__97_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__97_chanx_left_out ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4772 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4773 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4774 ) , + .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4775 ) , + .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4776 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4777 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4778 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4779 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4780 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4781 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[105] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4782 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4783 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4784 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4785 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4786 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4787 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4788 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4789 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4790 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4791 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4792 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4793 ) , + .clk_2_W_in ( clk_2_wires[105] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4794 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4795 ) , + .clk_2_N_out ( clk_2_wires[110] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4796 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4797 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4798 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4799 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4800 ) ) ; +sb_1__1_ sb_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4801 } ) , + .chany_top_in ( cby_1__1__107_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__109_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__106_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__98_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__109_ccff_tail ) , + .chany_top_out ( sb_1__1__98_chany_top_out ) , + .chanx_right_out ( sb_1__1__98_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__98_chanx_left_out ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4802 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4803 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4804 ) , + .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4805 ) , + .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4806 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4807 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4808 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4809 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4810 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4811 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4812 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4813 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4814 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4815 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4816 ) , + .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4817 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4818 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4819 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4820 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4821 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4822 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4823 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4824 ) ) ; +sb_1__1_ sb_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4825 } ) , + .chany_top_in ( cby_1__1__109_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__110_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__108_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__99_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__110_ccff_tail ) , + .chany_top_out ( sb_1__1__99_chany_top_out ) , + .chanx_right_out ( sb_1__1__99_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__99_chanx_left_out ) , + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4826 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4827 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4828 ) , + .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4829 ) , + .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4830 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4831 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4832 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4833 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4834 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4835 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4836 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4837 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4838 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4839 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4840 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4841 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4844 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4845 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4846 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4847 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4848 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4849 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4850 ) ) ; +sb_1__1_ sb_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4851 } ) , + .chany_top_in ( cby_1__1__110_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__111_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__109_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__100_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__111_ccff_tail ) , + .chany_top_out ( sb_1__1__100_chany_top_out ) , + .chanx_right_out ( sb_1__1__100_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__100_chanx_left_out ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4852 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4853 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4854 ) , + .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4855 ) , + .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4856 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4857 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4858 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4859 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4860 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4861 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4862 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4863 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4864 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4865 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4866 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4867 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4868 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4869 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4870 ) , + .clk_2_N_in ( clk_3_wires[87] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4871 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4872 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4873 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4874 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4875 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4876 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4878 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4879 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4880 ) ) ; +sb_1__1_ sb_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4881 } ) , + .chany_top_in ( cby_1__1__111_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__112_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__110_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__101_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__112_ccff_tail ) , + .chany_top_out ( sb_1__1__101_chany_top_out ) , + .chanx_right_out ( sb_1__1__101_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__101_chanx_left_out ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4882 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4883 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4884 ) , + .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4885 ) , + .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4886 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4887 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4888 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4889 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4890 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4891 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4892 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4893 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4894 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4895 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[83] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4896 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4897 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4898 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4899 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4900 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4902 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4903 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4904 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4905 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4906 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4907 ) , + .clk_3_N_in ( clk_3_wires[83] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4908 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4909 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4910 ) , + .clk_3_S_out ( clk_3_wires[86] ) ) ; +sb_1__1_ sb_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4911 } ) , + .chany_top_in ( cby_1__1__112_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__113_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__111_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__102_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__113_ccff_tail ) , + .chany_top_out ( sb_1__1__102_chany_top_out ) , + .chanx_right_out ( sb_1__1__102_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__102_chanx_left_out ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4912 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4913 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4914 ) , + .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4915 ) , + .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4916 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4917 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4918 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4919 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4920 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4921 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4922 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4923 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4924 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[119] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4925 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4926 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4927 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[77] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4928 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4929 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4930 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4931 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4932 ) , + .clk_2_N_in ( clk_3_wires[77] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4933 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4934 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4935 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4936 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4937 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4938 ) , + .clk_2_E_out ( clk_2_wires[119] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4939 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4940 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4941 ) , + .clk_3_N_in ( clk_3_wires[77] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4942 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4943 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4944 ) , + .clk_3_S_out ( clk_3_wires[82] ) ) ; +sb_1__1_ sb_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4945 } ) , + .chany_top_in ( cby_1__1__113_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__114_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__112_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__103_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__114_ccff_tail ) , + .chany_top_out ( sb_1__1__103_chany_top_out ) , + .chanx_right_out ( sb_1__1__103_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__103_chanx_left_out ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4946 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4947 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4948 ) , + .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4949 ) , + .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4950 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4951 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4952 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4953 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4954 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4955 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4956 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4957 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4958 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4959 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[73] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4960 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4961 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4962 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4963 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4964 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4965 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4966 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4967 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4968 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4969 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4970 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4971 ) , + .clk_3_N_in ( clk_3_wires[73] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4972 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4973 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4974 ) , + .clk_3_S_out ( clk_3_wires[76] ) ) ; +sb_1__1_ sb_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4975 } ) , + .chany_top_in ( cby_1__1__114_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__115_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__113_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__104_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__115_ccff_tail ) , + .chany_top_out ( sb_1__1__104_chany_top_out ) , + .chanx_right_out ( sb_1__1__104_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__104_chanx_left_out ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4976 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4977 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4978 ) , + .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4979 ) , + .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4980 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4981 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4982 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4983 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4984 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4985 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4986 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[49] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4987 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4988 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4989 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4990 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4991 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4992 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4993 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4995 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4996 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4997 ) , + .clk_3_W_in ( clk_3_wires[49] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4998 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4999 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5000 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5002 ) , + .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ; +sb_1__1_ sb_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5003 } ) , + .chany_top_in ( cby_1__1__115_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__116_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__114_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__105_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__116_ccff_tail ) , + .chany_top_out ( sb_1__1__105_chany_top_out ) , + .chanx_right_out ( sb_1__1__105_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__105_chanx_left_out ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5004 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5005 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5006 ) , + .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5007 ) , + .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5008 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5009 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5010 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5011 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5012 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5013 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5014 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5015 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5016 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[71] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5017 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5018 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5019 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5020 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5021 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5023 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5024 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5025 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5026 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5027 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5028 ) , + .clk_3_S_in ( clk_3_wires[71] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5029 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5030 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5031 ) , + .clk_3_N_out ( clk_3_wires[74] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5032 ) ) ; +sb_1__1_ sb_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5033 } ) , + .chany_top_in ( cby_1__1__116_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__117_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__115_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__106_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__117_ccff_tail ) , + .chany_top_out ( sb_1__1__106_chany_top_out ) , + .chanx_right_out ( sb_1__1__106_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__106_chanx_left_out ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5034 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5035 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5036 ) , + .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5037 ) , + .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5038 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5039 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5040 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5041 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5042 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[75] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5043 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5044 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5045 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5046 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[126] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5047 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5048 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[75] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5049 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5050 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5051 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5052 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5053 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5054 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5055 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5056 ) , + .clk_2_S_in ( clk_3_wires[75] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5057 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5058 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5059 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5060 ) , + .clk_2_E_out ( clk_2_wires[126] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5061 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5062 ) , + .clk_3_S_in ( clk_3_wires[75] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5063 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5064 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5065 ) , + .clk_3_N_out ( clk_3_wires[80] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5066 ) ) ; +sb_1__1_ sb_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5067 } ) , + .chany_top_in ( cby_1__1__117_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__118_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__116_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__107_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__118_ccff_tail ) , + .chany_top_out ( sb_1__1__107_chany_top_out ) , + .chanx_right_out ( sb_1__1__107_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__107_chanx_left_out ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5068 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5069 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5070 ) , + .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5071 ) , + .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5072 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5073 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5074 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5075 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5076 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5077 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5078 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5079 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5080 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[81] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5081 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5082 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5083 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5084 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5085 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5087 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5088 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5089 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5090 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5091 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5092 ) , + .clk_3_S_in ( clk_3_wires[81] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5093 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5094 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5095 ) , + .clk_3_N_out ( clk_3_wires[84] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5096 ) ) ; +sb_1__1_ sb_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5097 } ) , + .chany_top_in ( cby_1__1__118_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__119_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__117_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__108_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__119_ccff_tail ) , + .chany_top_out ( sb_1__1__108_chany_top_out ) , + .chanx_right_out ( sb_1__1__108_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__108_chanx_left_out ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5098 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5099 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5100 ) , + .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5101 ) , + .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5102 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5103 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5104 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5105 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5106 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[85] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5107 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5108 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5109 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5110 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5111 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5112 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5113 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5114 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5115 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5116 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5117 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5118 ) , + .clk_2_S_in ( clk_3_wires[85] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5119 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5120 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5121 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5122 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5123 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5124 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5125 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5126 ) ) ; +sb_1__1_ sb_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5127 } ) , + .chany_top_in ( cby_1__1__119_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__120_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__118_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__109_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__120_ccff_tail ) , + .chany_top_out ( sb_1__1__109_chany_top_out ) , + .chanx_right_out ( sb_1__1__109_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__109_chanx_left_out ) , + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5128 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5129 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5130 ) , + .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5131 ) , + .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5132 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5133 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5134 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5135 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5136 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5137 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5138 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5139 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5140 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5141 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5142 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5143 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5146 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5147 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5148 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5149 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5150 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5151 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5152 ) ) ; +sb_1__1_ sb_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5153 } ) , + .chany_top_in ( cby_1__1__121_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__121_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__120_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__110_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__121_ccff_tail ) , + .chany_top_out ( sb_1__1__110_chany_top_out ) , + .chanx_right_out ( sb_1__1__110_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__110_chanx_left_out ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5154 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5155 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5156 ) , + .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5157 ) , + .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5158 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5159 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5160 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5161 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5162 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5163 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5164 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5165 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5166 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5167 ) , + .clk_1_N_in ( clk_2_wires[116] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5168 ) , + .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5169 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5170 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5172 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5173 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5174 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5175 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5176 ) ) ; +sb_1__1_ sb_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5177 } ) , + .chany_top_in ( cby_1__1__122_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__122_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__121_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__111_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__122_ccff_tail ) , + .chany_top_out ( sb_1__1__111_chany_top_out ) , + .chanx_right_out ( sb_1__1__111_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__111_chanx_left_out ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5178 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5179 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5180 ) , + .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5181 ) , + .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5182 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5183 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5184 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5185 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5186 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5187 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[113] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5188 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5189 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5190 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5191 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5192 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5193 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5194 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5195 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5196 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5197 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5198 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5199 ) , + .clk_2_W_in ( clk_2_wires[113] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5200 ) , + .clk_2_S_out ( clk_2_wires[115] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5201 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5202 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5203 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5204 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5205 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5206 ) ) ; +sb_1__1_ sb_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5207 } ) , + .chany_top_in ( cby_1__1__123_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__123_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__122_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__112_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__123_ccff_tail ) , + .chany_top_out ( sb_1__1__112_chany_top_out ) , + .chanx_right_out ( sb_1__1__112_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__112_chanx_left_out ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5208 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5209 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5210 ) , + .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5211 ) , + .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5212 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5213 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5214 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5215 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5216 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5217 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5218 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5219 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5220 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5221 ) , + .clk_1_N_in ( clk_2_wires[123] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5222 ) , + .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5223 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5224 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5225 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5227 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5228 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5229 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5230 ) ) ; +sb_1__1_ sb_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5231 } ) , + .chany_top_in ( cby_1__1__124_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__124_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__123_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__113_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__124_ccff_tail ) , + .chany_top_out ( sb_1__1__113_chany_top_out ) , + .chanx_right_out ( sb_1__1__113_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__113_chanx_left_out ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5232 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5233 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5234 ) , + .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5235 ) , + .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5236 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5237 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5238 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5239 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5240 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5241 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[118] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5242 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5243 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5245 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5246 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5247 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5248 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5249 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5250 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5251 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5252 ) , + .clk_2_W_in ( clk_2_wires[118] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5253 ) , + .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5254 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5255 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5256 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5257 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5258 ) ) ; +sb_1__1_ sb_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5259 } ) , + .chany_top_in ( cby_1__1__125_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__125_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__124_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__114_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__125_ccff_tail ) , + .chany_top_out ( sb_1__1__114_chany_top_out ) , + .chanx_right_out ( sb_1__1__114_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__114_chanx_left_out ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5260 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5261 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5262 ) , + .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5263 ) , + .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5264 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5265 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5266 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5267 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5268 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5269 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5270 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5271 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5272 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5273 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5274 ) , + .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5275 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5276 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5277 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5278 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5279 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5280 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5281 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5282 ) ) ; +sb_1__1_ sb_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5283 } ) , + .chany_top_in ( cby_1__1__126_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__126_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__125_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__115_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__126_ccff_tail ) , + .chany_top_out ( sb_1__1__115_chany_top_out ) , + .chanx_right_out ( sb_1__1__115_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__115_chanx_left_out ) , + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5284 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5285 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5286 ) , + .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5287 ) , + .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5288 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5289 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5290 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5291 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5292 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5293 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5294 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5295 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5296 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5297 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5298 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5299 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5301 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5302 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5303 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5305 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5306 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5307 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5308 ) ) ; +sb_1__1_ sb_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5309 } ) , + .chany_top_in ( cby_1__1__127_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__127_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__126_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__116_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__127_ccff_tail ) , + .chany_top_out ( sb_1__1__116_chany_top_out ) , + .chanx_right_out ( sb_1__1__116_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__116_chanx_left_out ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5310 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5311 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5312 ) , + .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5313 ) , + .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5314 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5315 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5316 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5317 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5318 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5319 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5320 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5321 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5322 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5323 ) , + .clk_1_N_in ( clk_2_wires[130] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5324 ) , + .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5325 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5326 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5327 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5328 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5329 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5330 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5331 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5332 ) ) ; +sb_1__1_ sb_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5333 } ) , + .chany_top_in ( cby_1__1__128_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__128_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__127_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__117_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__128_ccff_tail ) , + .chany_top_out ( sb_1__1__117_chany_top_out ) , + .chanx_right_out ( sb_1__1__117_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__117_chanx_left_out ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5334 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5335 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5336 ) , + .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5337 ) , + .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5338 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5339 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5340 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5341 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5342 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5343 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[125] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5344 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5345 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5346 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5347 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5348 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5349 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5350 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5351 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5352 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5353 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5354 ) , + .clk_2_W_in ( clk_2_wires[125] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5355 ) , + .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5356 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5357 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5358 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5359 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5360 ) ) ; +sb_1__1_ sb_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5361 } ) , + .chany_top_in ( cby_1__1__129_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__129_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__128_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__118_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__129_ccff_tail ) , + .chany_top_out ( sb_1__1__118_chany_top_out ) , + .chanx_right_out ( sb_1__1__118_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__118_chanx_left_out ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5362 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5363 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5364 ) , + .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5365 ) , + .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5366 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5367 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5368 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5369 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5370 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5371 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5372 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5373 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5374 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5375 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5376 ) , + .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5377 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5378 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5379 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5380 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5381 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5382 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5383 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5384 ) ) ; +sb_1__1_ sb_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5385 } ) , + .chany_top_in ( cby_1__1__130_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__130_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__129_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__119_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__130_ccff_tail ) , + .chany_top_out ( sb_1__1__119_chany_top_out ) , + .chanx_right_out ( sb_1__1__119_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__119_chanx_left_out ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5386 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5387 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5388 ) , + .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5389 ) , + .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5390 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5391 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5392 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5393 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5394 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5395 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[132] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5396 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5397 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5398 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5399 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5400 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5402 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5403 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5404 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5405 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5406 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5407 ) , + .clk_2_W_in ( clk_2_wires[132] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5408 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5409 ) , + .clk_2_N_out ( clk_2_wires[134] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5410 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5411 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5412 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5413 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5414 ) ) ; +sb_1__1_ sb_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5415 } ) , + .chany_top_in ( cby_1__1__131_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__131_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__130_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__120_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__131_ccff_tail ) , + .chany_top_out ( sb_1__1__120_chany_top_out ) , + .chanx_right_out ( sb_1__1__120_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__120_chanx_left_out ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5416 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5417 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5418 ) , + .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5419 ) , + .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5420 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5421 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5422 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5423 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5424 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5425 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5426 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5427 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5428 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5429 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5430 ) , + .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5431 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5432 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5433 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5434 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5435 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5436 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5437 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5438 ) ) ; +sb_1__2_ sb_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5439 } ) , + .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__11_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__0_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_1_ccff_tail ) , + .chanx_right_out ( sb_1__12__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__0_chanx_left_out ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5440 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5441 ) , + .pReset_E_in ( pResetWires[604] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5442 ) , + .pReset_W_out ( pResetWires[601] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5443 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ; +sb_1__2_ sb_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5444 } ) , + .chanx_right_in ( cbx_1__12__2_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__23_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__1_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_2_ccff_tail ) , + .chanx_right_out ( sb_1__12__1_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__1_chanx_left_out ) , + .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_BOT ( scff_Wires[52] ) , + .SC_OUT_BOT ( scff_Wires[53] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5445 ) , + .pReset_E_in ( pResetWires[607] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5446 ) , + .pReset_W_out ( pResetWires[605] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5447 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[100] ) ) ; +sb_1__2_ sb_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5448 } ) , + .chanx_right_in ( cbx_1__12__3_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__35_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__2_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_3_ccff_tail ) , + .chanx_right_out ( sb_1__12__2_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__2_chanx_left_out ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5449 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5450 ) , + .pReset_E_in ( pResetWires[610] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5451 ) , + .pReset_W_out ( pResetWires[608] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5452 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ; +sb_1__2_ sb_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5453 } ) , + .chanx_right_in ( cbx_1__12__4_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__47_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__3_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_4_ccff_tail ) , + .chanx_right_out ( sb_1__12__3_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__3_chanx_left_out ) , + .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_BOT ( scff_Wires[105] ) , + .SC_OUT_BOT ( scff_Wires[106] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5454 ) , + .pReset_E_in ( pResetWires[613] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5455 ) , + .pReset_W_out ( pResetWires[611] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5456 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[176] ) ) ; +sb_1__2_ sb_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5457 } ) , + .chanx_right_in ( cbx_1__12__5_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__59_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__4_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_5_ccff_tail ) , + .chanx_right_out ( sb_1__12__4_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__4_chanx_left_out ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5458 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5459 ) , + .pReset_E_in ( pResetWires[616] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5460 ) , + .pReset_W_out ( pResetWires[614] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5461 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ; +sb_1__2_ sb_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5462 } ) , + .chanx_right_in ( cbx_1__12__6_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__71_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__5_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_6_ccff_tail ) , + .chanx_right_out ( sb_1__12__5_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__5_chanx_left_out ) , + .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_BOT ( scff_Wires[158] ) , + .SC_OUT_BOT ( scff_Wires[159] ) , .pReset_S_in ( pResetWires[24] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5463 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5464 ) , + .pReset_W_out ( pResetWires[617] ) , .pReset_E_out ( pResetWires[619] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[252] ) ) ; +sb_1__2_ sb_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5465 } ) , + .chanx_right_in ( cbx_1__12__7_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__83_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__6_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_7_ccff_tail ) , + .chanx_right_out ( sb_1__12__6_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__6_chanx_left_out ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5466 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5467 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5468 ) , + .pReset_W_in ( pResetWires[620] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5469 ) , + .pReset_E_out ( pResetWires[622] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ; +sb_1__2_ sb_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5470 } ) , + .chanx_right_in ( cbx_1__12__8_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__95_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__7_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_8_ccff_tail ) , + .chanx_right_out ( sb_1__12__7_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__7_chanx_left_out ) , + .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_BOT ( scff_Wires[211] ) , + .SC_OUT_BOT ( scff_Wires[212] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5471 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5472 ) , + .pReset_W_in ( pResetWires[623] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5473 ) , + .pReset_E_out ( pResetWires[625] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[328] ) ) ; +sb_1__2_ sb_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5474 } ) , + .chanx_right_in ( cbx_1__12__9_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__107_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__8_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_9_ccff_tail ) , + .chanx_right_out ( sb_1__12__8_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__8_chanx_left_out ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5475 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5476 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5477 ) , + .pReset_W_in ( pResetWires[626] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5478 ) , + .pReset_E_out ( pResetWires[628] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ; +sb_1__2_ sb_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5479 } ) , + .chanx_right_in ( cbx_1__12__10_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__119_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__9_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_10_ccff_tail ) , + .chanx_right_out ( sb_1__12__9_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__9_chanx_left_out ) , + .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_BOT ( scff_Wires[264] ) , + .SC_OUT_BOT ( scff_Wires[265] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5480 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5481 ) , + .pReset_W_in ( pResetWires[629] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5482 ) , + .pReset_E_out ( pResetWires[631] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[404] ) ) ; +sb_1__2_ sb_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5483 } ) , + .chanx_right_in ( cbx_1__12__11_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__131_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__10_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_11_ccff_tail ) , + .chanx_right_out ( sb_1__12__10_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__10_chanx_left_out ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5484 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5485 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5486 ) , + .pReset_W_in ( pResetWires[632] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5487 ) , + .pReset_E_out ( pResetWires[634] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ; +sb_2__0_ sb_12__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5488 } ) , + .chany_top_in ( cby_12__1__0_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , + .chanx_left_in ( cbx_1__0__11_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_right_11_ccff_tail ) , + .chany_top_out ( sb_12__0__0_chany_top_out ) , + .chanx_left_out ( sb_12__0__0_chanx_left_out ) , + .ccff_tail ( sb_12__0__0_ccff_tail ) , .pReset_W_in ( pResetWires[59] ) , + .pReset_N_out ( pResetWires[60] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[445] ) ) ; +sb_2__1_ sb_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5489 } ) , + .chany_top_in ( cby_12__1__1_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__0_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__121_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_10_ccff_tail ) , + .chany_top_out ( sb_12__1__0_chany_top_out ) , + .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__0_chanx_left_out ) , + .ccff_tail ( sb_12__1__0_ccff_tail ) , .pReset_W_in ( pResetWires[107] ) , + .pReset_N_out ( pResetWires[109] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[448] ) ) ; +sb_2__1_ sb_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5490 } ) , + .chany_top_in ( cby_12__1__2_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__1_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__122_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_9_ccff_tail ) , + .chany_top_out ( sb_12__1__1_chany_top_out ) , + .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__1_chanx_left_out ) , + .ccff_tail ( sb_12__1__1_ccff_tail ) , .pReset_W_in ( pResetWires[156] ) , + .pReset_N_out ( pResetWires[158] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[451] ) ) ; +sb_2__1_ sb_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5491 } ) , + .chany_top_in ( cby_12__1__3_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__2_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__123_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_8_ccff_tail ) , + .chany_top_out ( sb_12__1__2_chany_top_out ) , + .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__2_chanx_left_out ) , + .ccff_tail ( sb_12__1__2_ccff_tail ) , .pReset_W_in ( pResetWires[205] ) , + .pReset_N_out ( pResetWires[207] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[454] ) ) ; +sb_2__1_ sb_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5492 } ) , + .chany_top_in ( cby_12__1__4_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__3_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__124_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_7_ccff_tail ) , + .chany_top_out ( sb_12__1__3_chany_top_out ) , + .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__3_chanx_left_out ) , + .ccff_tail ( sb_12__1__3_ccff_tail ) , .pReset_W_in ( pResetWires[254] ) , + .pReset_N_out ( pResetWires[256] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[457] ) ) ; +sb_2__1_ sb_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5493 } ) , + .chany_top_in ( cby_12__1__5_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__4_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__125_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_6_ccff_tail ) , + .chany_top_out ( sb_12__1__4_chany_top_out ) , + .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__4_chanx_left_out ) , + .ccff_tail ( sb_12__1__4_ccff_tail ) , .pReset_W_in ( pResetWires[303] ) , + .pReset_N_out ( pResetWires[305] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[460] ) ) ; +sb_2__1_ sb_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5494 } ) , + .chany_top_in ( cby_12__1__6_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__5_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__126_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_5_ccff_tail ) , + .chany_top_out ( sb_12__1__5_chany_top_out ) , + .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__5_chanx_left_out ) , + .ccff_tail ( sb_12__1__5_ccff_tail ) , .pReset_W_in ( pResetWires[352] ) , + .pReset_N_out ( pResetWires[354] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[463] ) ) ; +sb_2__1_ sb_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5495 } ) , + .chany_top_in ( cby_12__1__7_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__6_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__127_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_4_ccff_tail ) , + .chany_top_out ( sb_12__1__6_chany_top_out ) , + .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__6_chanx_left_out ) , + .ccff_tail ( sb_12__1__6_ccff_tail ) , .pReset_W_in ( pResetWires[401] ) , + .pReset_N_out ( pResetWires[403] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[466] ) ) ; +sb_2__1_ sb_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5496 } ) , + .chany_top_in ( cby_12__1__8_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__7_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__128_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_3_ccff_tail ) , + .chany_top_out ( sb_12__1__7_chany_top_out ) , + .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__7_chanx_left_out ) , + .ccff_tail ( sb_12__1__7_ccff_tail ) , .pReset_W_in ( pResetWires[450] ) , + .pReset_N_out ( pResetWires[452] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[469] ) ) ; +sb_2__1_ sb_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5497 } ) , + .chany_top_in ( cby_12__1__9_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__8_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__129_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_2_ccff_tail ) , + .chany_top_out ( sb_12__1__8_chany_top_out ) , + .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__8_chanx_left_out ) , + .ccff_tail ( sb_12__1__8_ccff_tail ) , .pReset_W_in ( pResetWires[499] ) , + .pReset_N_out ( pResetWires[501] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[472] ) ) ; +sb_2__1_ sb_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5498 } ) , + .chany_top_in ( cby_12__1__10_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__9_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__130_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_1_ccff_tail ) , + .chany_top_out ( sb_12__1__9_chany_top_out ) , + .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__9_chanx_left_out ) , + .ccff_tail ( sb_12__1__9_ccff_tail ) , .pReset_W_in ( pResetWires[548] ) , + .pReset_N_out ( pResetWires[550] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[475] ) ) ; +sb_2__1_ sb_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5499 } ) , + .chany_top_in ( cby_12__1__11_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__10_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__131_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_0_ccff_tail ) , + .chany_top_out ( sb_12__1__10_chany_top_out ) , + .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__10_chanx_left_out ) , + .ccff_tail ( sb_12__1__10_ccff_tail ) , + .pReset_W_in ( pResetWires[597] ) , .pReset_N_out ( pResetWires[599] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[478] ) ) ; +sb_2__2_ sb_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5500 } ) , + .chany_bottom_in ( cby_12__1__11_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__11_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( ccff_head ) , + .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) , + .chanx_left_out ( sb_12__12__0_chanx_left_out ) , + .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) , + .SC_OUT_BOT ( sc_tail ) , .pReset_W_in ( pResetWires[635] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[480] ) ) ; +cbx_1__0_ cbx_1__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5501 } ) , + .chanx_left_in ( sb_0__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__0_chanx_left_out ) , + .ccff_head ( sb_1__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123:131] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123:131] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123:131] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5502 ) , + .pReset_E_in ( pResetWires[26] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5503 ) , + .pReset_W_out ( pResetWires[25] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5504 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[0] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ; +cbx_1__0_ cbx_2__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5505 } ) , + .chanx_left_in ( sb_1__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__1_chanx_left_out ) , + .ccff_head ( sb_1__0__1_ccff_tail ) , + .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114:122] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114:122] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114:122] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5506 ) , + .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , + .pReset_E_in ( pResetWires[29] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5507 ) , + .pReset_W_out ( pResetWires[28] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5508 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[63] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5509 ) ) ; +cbx_1__0_ cbx_3__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5510 } ) , + .chanx_left_in ( sb_1__0__1_chanx_right_out ) , + .chanx_right_in ( sb_1__0__2_chanx_left_out ) , + .ccff_head ( sb_1__0__2_ccff_tail ) , + .chanx_left_out ( cbx_1__0__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__2_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105:113] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105:113] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105:113] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5511 ) , + .pReset_E_in ( pResetWires[32] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5512 ) , + .pReset_W_out ( pResetWires[31] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5513 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[101] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5514 ) ) ; +cbx_1__0_ cbx_4__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5515 } ) , + .chanx_left_in ( sb_1__0__2_chanx_right_out ) , + .chanx_right_in ( sb_1__0__3_chanx_left_out ) , + .ccff_head ( sb_1__0__3_ccff_tail ) , + .chanx_left_out ( cbx_1__0__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__3_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:104] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:104] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:104] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5516 ) , + .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , + .pReset_E_in ( pResetWires[35] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5517 ) , + .pReset_W_out ( pResetWires[34] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5518 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[139] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5519 ) ) ; +cbx_1__0_ cbx_5__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5520 } ) , + .chanx_left_in ( sb_1__0__3_chanx_right_out ) , + .chanx_right_in ( sb_1__0__4_chanx_left_out ) , + .ccff_head ( sb_1__0__4_ccff_tail ) , + .chanx_left_out ( cbx_1__0__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__4_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87:95] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87:95] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87:95] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5521 ) , + .pReset_E_in ( pResetWires[38] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5522 ) , + .pReset_W_out ( pResetWires[37] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[177] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5524 ) ) ; +cbx_1__0_ cbx_6__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5525 } ) , + .chanx_left_in ( sb_1__0__4_chanx_right_out ) , + .chanx_right_in ( sb_1__0__5_chanx_left_out ) , + .ccff_head ( sb_1__0__5_ccff_tail ) , + .chanx_left_out ( cbx_1__0__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__5_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78:86] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78:86] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78:86] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5526 ) , + .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , + .pReset_E_in ( pResetWires[41] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5527 ) , + .pReset_W_out ( pResetWires[40] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5528 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[215] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5529 ) ) ; +cbx_1__0_ cbx_7__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5530 } ) , + .chanx_left_in ( sb_1__0__5_chanx_right_out ) , + .chanx_right_in ( sb_1__0__6_chanx_left_out ) , + .ccff_head ( sb_1__0__6_ccff_tail ) , + .chanx_left_out ( cbx_1__0__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__6_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69:77] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69:77] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69:77] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5531 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5532 ) , + .pReset_W_in ( pResetWires[43] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5533 ) , + .pReset_E_out ( pResetWires[44] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[253] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5534 ) ) ; +cbx_1__0_ cbx_8__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5535 } ) , + .chanx_left_in ( sb_1__0__6_chanx_right_out ) , + .chanx_right_in ( sb_1__0__7_chanx_left_out ) , + .ccff_head ( sb_1__0__7_ccff_tail ) , + .chanx_left_out ( cbx_1__0__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__7_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:68] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:68] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:68] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5536 ) , + .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5537 ) , + .pReset_W_in ( pResetWires[46] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5538 ) , + .pReset_E_out ( pResetWires[47] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[291] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5539 ) ) ; +cbx_1__0_ cbx_9__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5540 } ) , + .chanx_left_in ( sb_1__0__7_chanx_right_out ) , + .chanx_right_in ( sb_1__0__8_chanx_left_out ) , + .ccff_head ( sb_1__0__8_ccff_tail ) , + .chanx_left_out ( cbx_1__0__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__8_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51:59] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51:59] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51:59] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5541 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5542 ) , + .pReset_W_in ( pResetWires[49] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5543 ) , + .pReset_E_out ( pResetWires[50] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[329] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5544 ) ) ; +cbx_1__0_ cbx_10__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5545 } ) , + .chanx_left_in ( sb_1__0__8_chanx_right_out ) , + .chanx_right_in ( sb_1__0__9_chanx_left_out ) , + .ccff_head ( sb_1__0__9_ccff_tail ) , + .chanx_left_out ( cbx_1__0__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__9_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42:50] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42:50] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42:50] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5546 ) , + .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5547 ) , + .pReset_W_in ( pResetWires[52] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5548 ) , + .pReset_E_out ( pResetWires[53] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[367] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5549 ) ) ; +cbx_1__0_ cbx_11__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5550 } ) , + .chanx_left_in ( sb_1__0__9_chanx_right_out ) , + .chanx_right_in ( sb_1__0__10_chanx_left_out ) , + .ccff_head ( sb_1__0__10_ccff_tail ) , + .chanx_left_out ( cbx_1__0__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__10_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33:41] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33:41] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33:41] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5551 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5552 ) , + .pReset_W_in ( pResetWires[55] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5553 ) , + .pReset_E_out ( pResetWires[56] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[405] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5554 ) ) ; +cbx_1__0_ cbx_12__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5555 } ) , + .chanx_left_in ( sb_1__0__10_chanx_right_out ) , + .chanx_right_in ( sb_12__0__0_chanx_left_out ) , + .ccff_head ( sb_12__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__11_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:32] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:32] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:32] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5556 ) , + .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5557 ) , + .pReset_W_in ( pResetWires[58] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5558 ) , + .pReset_E_out ( pResetWires[59] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[443] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5559 ) ) ; +cbx_1__1_ cbx_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5560 } ) , + .chanx_left_in ( sb_0__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__0_chanx_left_out ) , + .ccff_head ( sb_1__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5561 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[0] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[0] ) , + .pReset_E_in ( pResetWires[62] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5562 ) , + .pReset_W_out ( pResetWires[61] ) , .pReset_S_out ( pResetWires[63] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5563 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[6] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[4] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5564 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5565 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5566 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5567 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5568 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5569 ) , + .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5570 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5571 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5572 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5573 ) ) ; +cbx_1__1_ cbx_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5574 } ) , + .chanx_left_in ( sb_0__1__1_chanx_right_out ) , + .chanx_right_in ( sb_1__1__1_chanx_left_out ) , + .ccff_head ( sb_1__1__1_ccff_tail ) , + .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5575 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[1] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[1] ) , + .pReset_E_in ( pResetWires[111] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5576 ) , + .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5577 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5578 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5579 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5580 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5581 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5582 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5583 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5584 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5589 ) ) ; +cbx_1__1_ cbx_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5590 } ) , + .chanx_left_in ( sb_0__1__2_chanx_right_out ) , + .chanx_right_in ( sb_1__1__2_chanx_left_out ) , + .ccff_head ( sb_1__1__2_ccff_tail ) , + .chanx_left_out ( cbx_1__1__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__2_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5591 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[2] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[2] ) , + .pReset_E_in ( pResetWires[160] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5592 ) , + .pReset_W_out ( pResetWires[159] ) , .pReset_S_out ( pResetWires[161] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5593 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[16] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[15] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5594 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5595 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5596 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5597 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5598 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5599 ) , + .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5603 ) ) ; +cbx_1__1_ cbx_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5604 } ) , + .chanx_left_in ( sb_0__1__3_chanx_right_out ) , + .chanx_right_in ( sb_1__1__3_chanx_left_out ) , + .ccff_head ( sb_1__1__3_ccff_tail ) , + .chanx_left_out ( cbx_1__1__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__3_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5605 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[3] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[3] ) , + .pReset_E_in ( pResetWires[209] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5606 ) , + .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5607 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5608 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5609 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5610 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5611 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5612 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5613 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5614 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5618 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5619 ) ) ; +cbx_1__1_ cbx_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5620 } ) , + .chanx_left_in ( sb_0__1__4_chanx_right_out ) , + .chanx_right_in ( sb_1__1__4_chanx_left_out ) , + .ccff_head ( sb_1__1__4_ccff_tail ) , + .chanx_left_out ( cbx_1__1__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__4_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5621 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[4] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[4] ) , + .pReset_E_in ( pResetWires[258] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5622 ) , + .pReset_W_out ( pResetWires[257] ) , .pReset_S_out ( pResetWires[259] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5623 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[26] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[25] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5624 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5625 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5626 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5627 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5628 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5629 ) , + .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5631 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5632 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5633 ) ) ; +cbx_1__1_ cbx_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5634 } ) , + .chanx_left_in ( sb_0__1__5_chanx_right_out ) , + .chanx_right_in ( sb_1__1__5_chanx_left_out ) , + .ccff_head ( sb_1__1__5_ccff_tail ) , + .chanx_left_out ( cbx_1__1__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__5_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5635 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[5] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[5] ) , + .pReset_E_in ( pResetWires[307] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5636 ) , + .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5637 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5638 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5639 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5640 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5641 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5642 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5643 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5644 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5649 ) ) ; +cbx_1__1_ cbx_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5650 } ) , + .chanx_left_in ( sb_0__1__6_chanx_right_out ) , + .chanx_right_in ( sb_1__1__6_chanx_left_out ) , + .ccff_head ( sb_1__1__6_ccff_tail ) , + .chanx_left_out ( cbx_1__1__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__6_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5651 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[6] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[6] ) , + .pReset_E_in ( pResetWires[356] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5652 ) , + .pReset_W_out ( pResetWires[355] ) , .pReset_S_out ( pResetWires[357] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5653 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[36] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[35] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5654 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5655 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5656 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5657 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5658 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5659 ) , + .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5660 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5661 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5663 ) ) ; +cbx_1__1_ cbx_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5664 } ) , + .chanx_left_in ( sb_0__1__7_chanx_right_out ) , + .chanx_right_in ( sb_1__1__7_chanx_left_out ) , + .ccff_head ( sb_1__1__7_ccff_tail ) , + .chanx_left_out ( cbx_1__1__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__7_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5665 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[7] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[7] ) , + .pReset_E_in ( pResetWires[405] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5666 ) , + .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5667 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5668 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5669 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5670 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5671 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5672 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5673 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5674 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5678 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5679 ) ) ; +cbx_1__1_ cbx_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5680 } ) , + .chanx_left_in ( sb_0__1__8_chanx_right_out ) , + .chanx_right_in ( sb_1__1__8_chanx_left_out ) , + .ccff_head ( sb_1__1__8_ccff_tail ) , + .chanx_left_out ( cbx_1__1__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__8_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5681 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[8] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[8] ) , + .pReset_E_in ( pResetWires[454] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5682 ) , + .pReset_W_out ( pResetWires[453] ) , .pReset_S_out ( pResetWires[455] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5683 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[46] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[45] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5684 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5686 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5687 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5688 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5689 ) , + .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5693 ) ) ; +cbx_1__1_ cbx_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5694 } ) , + .chanx_left_in ( sb_0__1__9_chanx_right_out ) , + .chanx_right_in ( sb_1__1__9_chanx_left_out ) , + .ccff_head ( sb_1__1__9_ccff_tail ) , + .chanx_left_out ( cbx_1__1__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__9_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5695 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[9] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[9] ) , + .pReset_E_in ( pResetWires[503] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5696 ) , + .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5697 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5698 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5699 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5700 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5701 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5702 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5703 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5704 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5708 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5709 ) ) ; +cbx_1__1_ cbx_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5710 } ) , + .chanx_left_in ( sb_0__1__10_chanx_right_out ) , + .chanx_right_in ( sb_1__1__10_chanx_left_out ) , + .ccff_head ( sb_1__1__10_ccff_tail ) , + .chanx_left_out ( cbx_1__1__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__10_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5711 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[10] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[10] ) , + .pReset_E_in ( pResetWires[552] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5712 ) , + .pReset_W_out ( pResetWires[551] ) , .pReset_S_out ( pResetWires[553] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5713 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[56] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[55] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5714 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5715 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5716 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5717 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5718 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5719 ) , + .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5720 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5721 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5723 ) ) ; +cbx_1__1_ cbx_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5724 } ) , + .chanx_left_in ( sb_1__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__11_chanx_left_out ) , + .ccff_head ( sb_1__1__11_ccff_tail ) , + .chanx_left_out ( cbx_1__1__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__11_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5725 ) , + .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[11] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[11] ) , + .pReset_E_in ( pResetWires[67] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5726 ) , + .pReset_W_out ( pResetWires[66] ) , .pReset_S_out ( pResetWires[68] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5727 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[66] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5728 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5729 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5730 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5731 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5733 ) , + .clk_1_W_in ( clk_1_wires[1] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5734 ) , + .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5736 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5737 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5738 ) ) ; +cbx_1__1_ cbx_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5739 } ) , + .chanx_left_in ( sb_1__1__1_chanx_right_out ) , + .chanx_right_in ( sb_1__1__12_chanx_left_out ) , + .ccff_head ( sb_1__1__12_ccff_tail ) , + .chanx_left_out ( cbx_1__1__12_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__12_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5740 ) , + .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[12] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[12] ) , + .pReset_E_in ( pResetWires[116] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5741 ) , + .pReset_W_out ( pResetWires[115] ) , .pReset_S_out ( pResetWires[117] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5742 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5743 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5744 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5745 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5746 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5747 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5748 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5749 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5750 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5751 ) , + .clk_2_E_in ( clk_2_wires[2] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5752 ) , + .clk_2_W_out ( clk_2_wires[1] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5754 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5755 ) ) ; +cbx_1__1_ cbx_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5756 } ) , + .chanx_left_in ( sb_1__1__2_chanx_right_out ) , + .chanx_right_in ( sb_1__1__13_chanx_left_out ) , + .ccff_head ( sb_1__1__13_ccff_tail ) , + .chanx_left_out ( cbx_1__1__13_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__13_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5757 ) , + .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[13] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[13] ) , + .pReset_E_in ( pResetWires[165] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5758 ) , + .pReset_W_out ( pResetWires[164] ) , .pReset_S_out ( pResetWires[166] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[72] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5760 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5761 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5762 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5763 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5764 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5765 ) , + .clk_1_W_in ( clk_1_wires[8] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5766 ) , + .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5767 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5768 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5769 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5770 ) ) ; +cbx_1__1_ cbx_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5771 } ) , + .chanx_left_in ( sb_1__1__3_chanx_right_out ) , + .chanx_right_in ( sb_1__1__14_chanx_left_out ) , + .ccff_head ( sb_1__1__14_ccff_tail ) , + .chanx_left_out ( cbx_1__1__14_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__14_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5772 ) , + .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[14] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[14] ) , + .pReset_E_in ( pResetWires[214] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5773 ) , + .pReset_W_out ( pResetWires[213] ) , .pReset_S_out ( pResetWires[215] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5774 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5775 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5776 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5777 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5778 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5779 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5780 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5781 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5782 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5783 ) , + .clk_2_E_in ( clk_2_wires[7] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5784 ) , + .clk_2_W_out ( clk_2_wires[6] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5785 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5786 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5787 ) ) ; +cbx_1__1_ cbx_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5788 } ) , + .chanx_left_in ( sb_1__1__4_chanx_right_out ) , + .chanx_right_in ( sb_1__1__15_chanx_left_out ) , + .ccff_head ( sb_1__1__15_ccff_tail ) , + .chanx_left_out ( cbx_1__1__15_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__15_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5789 ) , + .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[15] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[15] ) , + .pReset_E_in ( pResetWires[263] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5790 ) , + .pReset_W_out ( pResetWires[262] ) , .pReset_S_out ( pResetWires[264] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5791 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[78] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5792 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5793 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5795 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5796 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5797 ) , + .clk_1_W_in ( clk_1_wires[15] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5798 ) , + .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5800 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5801 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5802 ) ) ; +cbx_1__1_ cbx_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5803 } ) , + .chanx_left_in ( sb_1__1__5_chanx_right_out ) , + .chanx_right_in ( sb_1__1__16_chanx_left_out ) , + .ccff_head ( sb_1__1__16_ccff_tail ) , + .chanx_left_out ( cbx_1__1__16_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__16_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5804 ) , + .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[16] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[16] ) , + .pReset_E_in ( pResetWires[312] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5805 ) , + .pReset_W_out ( pResetWires[311] ) , .pReset_S_out ( pResetWires[313] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5806 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5807 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5808 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5809 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5810 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5811 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5812 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5813 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5814 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5819 ) ) ; +cbx_1__1_ cbx_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5820 } ) , + .chanx_left_in ( sb_1__1__6_chanx_right_out ) , + .chanx_right_in ( sb_1__1__17_chanx_left_out ) , + .ccff_head ( sb_1__1__17_ccff_tail ) , + .chanx_left_out ( cbx_1__1__17_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__17_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5821 ) , + .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[17] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[17] ) , + .pReset_E_in ( pResetWires[361] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5822 ) , + .pReset_W_out ( pResetWires[360] ) , .pReset_S_out ( pResetWires[362] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5823 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[84] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5824 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5825 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5826 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5827 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5828 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5829 ) , + .clk_1_W_in ( clk_1_wires[22] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5830 ) , + .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5832 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5833 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5834 ) ) ; +cbx_1__1_ cbx_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5835 } ) , + .chanx_left_in ( sb_1__1__7_chanx_right_out ) , + .chanx_right_in ( sb_1__1__18_chanx_left_out ) , + .ccff_head ( sb_1__1__18_ccff_tail ) , + .chanx_left_out ( cbx_1__1__18_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__18_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5836 ) , + .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[18] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[18] ) , + .pReset_E_in ( pResetWires[410] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5837 ) , + .pReset_W_out ( pResetWires[409] ) , .pReset_S_out ( pResetWires[411] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5838 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5839 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5840 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5841 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5842 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5843 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5844 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5845 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5846 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5847 ) , + .clk_2_E_in ( clk_2_wires[14] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5848 ) , + .clk_2_W_out ( clk_2_wires[13] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5849 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5850 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5851 ) ) ; +cbx_1__1_ cbx_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5852 } ) , + .chanx_left_in ( sb_1__1__8_chanx_right_out ) , + .chanx_right_in ( sb_1__1__19_chanx_left_out ) , + .ccff_head ( sb_1__1__19_ccff_tail ) , + .chanx_left_out ( cbx_1__1__19_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__19_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5853 ) , + .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[19] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[19] ) , + .pReset_E_in ( pResetWires[459] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5854 ) , + .pReset_W_out ( pResetWires[458] ) , .pReset_S_out ( pResetWires[460] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5855 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[90] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5856 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5857 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5858 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5859 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5860 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5861 ) , + .clk_1_W_in ( clk_1_wires[29] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5862 ) , + .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5864 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5865 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5866 ) ) ; +cbx_1__1_ cbx_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5867 } ) , + .chanx_left_in ( sb_1__1__9_chanx_right_out ) , + .chanx_right_in ( sb_1__1__20_chanx_left_out ) , + .ccff_head ( sb_1__1__20_ccff_tail ) , + .chanx_left_out ( cbx_1__1__20_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__20_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5868 ) , + .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[20] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[20] ) , + .pReset_E_in ( pResetWires[508] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5869 ) , + .pReset_W_out ( pResetWires[507] ) , .pReset_S_out ( pResetWires[509] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5870 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5871 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5872 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5873 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5874 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5875 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5876 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5877 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5878 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5879 ) , + .clk_2_E_in ( clk_2_wires[21] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5880 ) , + .clk_2_W_out ( clk_2_wires[20] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5881 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5882 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5883 ) ) ; +cbx_1__1_ cbx_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5884 } ) , + .chanx_left_in ( sb_1__1__10_chanx_right_out ) , + .chanx_right_in ( sb_1__1__21_chanx_left_out ) , + .ccff_head ( sb_1__1__21_ccff_tail ) , + .chanx_left_out ( cbx_1__1__21_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__21_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5885 ) , + .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[21] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[21] ) , + .pReset_E_in ( pResetWires[557] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5886 ) , + .pReset_W_out ( pResetWires[556] ) , .pReset_S_out ( pResetWires[558] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5887 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[96] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5888 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5889 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5890 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5891 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5892 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5893 ) , + .clk_1_W_in ( clk_1_wires[36] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5894 ) , + .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5896 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5897 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5898 ) ) ; +cbx_1__1_ cbx_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5899 } ) , + .chanx_left_in ( sb_1__1__11_chanx_right_out ) , + .chanx_right_in ( sb_1__1__22_chanx_left_out ) , + .ccff_head ( sb_1__1__22_ccff_tail ) , + .chanx_left_out ( cbx_1__1__22_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__22_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5900 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[22] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[22] ) , + .pReset_E_in ( pResetWires[71] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5901 ) , + .pReset_W_out ( pResetWires[70] ) , .pReset_S_out ( pResetWires[72] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5902 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[104] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5903 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5904 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5905 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5906 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5907 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5908 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5909 ) , + .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5913 ) ) ; +cbx_1__1_ cbx_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5914 } ) , + .chanx_left_in ( sb_1__1__12_chanx_right_out ) , + .chanx_right_in ( sb_1__1__23_chanx_left_out ) , + .ccff_head ( sb_1__1__23_ccff_tail ) , + .chanx_left_out ( cbx_1__1__23_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__23_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5915 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[23] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[23] ) , + .pReset_E_in ( pResetWires[120] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5916 ) , + .pReset_W_out ( pResetWires[119] ) , .pReset_S_out ( pResetWires[121] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5917 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5918 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5919 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5920 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5921 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5922 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5923 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5924 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5925 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5927 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5929 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5930 ) ) ; +cbx_1__1_ cbx_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5931 } ) , + .chanx_left_in ( sb_1__1__13_chanx_right_out ) , + .chanx_right_in ( sb_1__1__24_chanx_left_out ) , + .ccff_head ( sb_1__1__24_ccff_tail ) , + .chanx_left_out ( cbx_1__1__24_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__24_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5932 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[24] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[24] ) , + .pReset_E_in ( pResetWires[169] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5933 ) , + .pReset_W_out ( pResetWires[168] ) , .pReset_S_out ( pResetWires[170] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5934 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[110] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5935 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5936 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5937 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5938 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5939 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5940 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5941 ) , + .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5943 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5945 ) ) ; +cbx_1__1_ cbx_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5946 } ) , + .chanx_left_in ( sb_1__1__14_chanx_right_out ) , + .chanx_right_in ( sb_1__1__25_chanx_left_out ) , + .ccff_head ( sb_1__1__25_ccff_tail ) , + .chanx_left_out ( cbx_1__1__25_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__25_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5947 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[25] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[25] ) , + .pReset_E_in ( pResetWires[218] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5948 ) , + .pReset_W_out ( pResetWires[217] ) , .pReset_S_out ( pResetWires[219] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5949 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5950 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5951 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5952 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5953 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5954 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5955 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5956 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5957 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5959 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5962 ) ) ; +cbx_1__1_ cbx_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5963 } ) , + .chanx_left_in ( sb_1__1__15_chanx_right_out ) , + .chanx_right_in ( sb_1__1__26_chanx_left_out ) , + .ccff_head ( sb_1__1__26_ccff_tail ) , + .chanx_left_out ( cbx_1__1__26_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__26_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5964 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[26] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[26] ) , + .pReset_E_in ( pResetWires[267] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5965 ) , + .pReset_W_out ( pResetWires[266] ) , .pReset_S_out ( pResetWires[268] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5966 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[116] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5967 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5968 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5969 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5970 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5971 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5972 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5973 ) , + .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5974 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5975 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5976 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5977 ) ) ; +cbx_1__1_ cbx_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5978 } ) , + .chanx_left_in ( sb_1__1__16_chanx_right_out ) , + .chanx_right_in ( sb_1__1__27_chanx_left_out ) , + .ccff_head ( sb_1__1__27_ccff_tail ) , + .chanx_left_out ( cbx_1__1__27_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__27_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5979 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[27] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[27] ) , + .pReset_E_in ( pResetWires[316] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5980 ) , + .pReset_W_out ( pResetWires[315] ) , .pReset_S_out ( pResetWires[317] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5981 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5982 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5983 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5984 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5985 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5986 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5987 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5988 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5989 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5990 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5991 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5992 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5993 ) , + .clk_3_E_in ( clk_3_wires[50] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5994 ) , + .clk_3_W_out ( clk_3_wires[51] ) ) ; +cbx_1__1_ cbx_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5995 } ) , + .chanx_left_in ( sb_1__1__17_chanx_right_out ) , + .chanx_right_in ( sb_1__1__28_chanx_left_out ) , + .ccff_head ( sb_1__1__28_ccff_tail ) , + .chanx_left_out ( cbx_1__1__28_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__28_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5996 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[28] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[28] ) , + .pReset_E_in ( pResetWires[365] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5997 ) , + .pReset_W_out ( pResetWires[364] ) , .pReset_S_out ( pResetWires[366] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5998 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[122] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5999 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6000 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6001 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6002 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6003 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6004 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6005 ) , + .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6006 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6007 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6009 ) ) ; +cbx_1__1_ cbx_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6010 } ) , + .chanx_left_in ( sb_1__1__18_chanx_right_out ) , + .chanx_right_in ( sb_1__1__29_chanx_left_out ) , + .ccff_head ( sb_1__1__29_ccff_tail ) , + .chanx_left_out ( cbx_1__1__29_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__29_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6011 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[29] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[29] ) , + .pReset_E_in ( pResetWires[414] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6012 ) , + .pReset_W_out ( pResetWires[413] ) , .pReset_S_out ( pResetWires[415] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6013 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6014 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6015 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6016 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6017 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6018 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6019 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6020 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6021 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6023 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6025 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6026 ) ) ; +cbx_1__1_ cbx_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6027 } ) , + .chanx_left_in ( sb_1__1__19_chanx_right_out ) , + .chanx_right_in ( sb_1__1__30_chanx_left_out ) , + .ccff_head ( sb_1__1__30_ccff_tail ) , + .chanx_left_out ( cbx_1__1__30_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__30_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6028 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[30] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[30] ) , + .pReset_E_in ( pResetWires[463] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6029 ) , + .pReset_W_out ( pResetWires[462] ) , .pReset_S_out ( pResetWires[464] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6030 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[128] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6031 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6032 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6033 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6034 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6035 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6036 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6037 ) , + .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6039 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6040 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6041 ) ) ; +cbx_1__1_ cbx_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6042 } ) , + .chanx_left_in ( sb_1__1__20_chanx_right_out ) , + .chanx_right_in ( sb_1__1__31_chanx_left_out ) , + .ccff_head ( sb_1__1__31_ccff_tail ) , + .chanx_left_out ( cbx_1__1__31_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__31_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6043 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[31] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[31] ) , + .pReset_E_in ( pResetWires[512] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6044 ) , + .pReset_W_out ( pResetWires[511] ) , .pReset_S_out ( pResetWires[513] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6045 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6046 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6047 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6048 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6049 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6050 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6051 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6052 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6053 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6055 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6057 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6058 ) ) ; +cbx_1__1_ cbx_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6059 } ) , + .chanx_left_in ( sb_1__1__21_chanx_right_out ) , + .chanx_right_in ( sb_1__1__32_chanx_left_out ) , + .ccff_head ( sb_1__1__32_ccff_tail ) , + .chanx_left_out ( cbx_1__1__32_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__32_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6060 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[32] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[32] ) , + .pReset_E_in ( pResetWires[561] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6061 ) , + .pReset_W_out ( pResetWires[560] ) , .pReset_S_out ( pResetWires[562] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6062 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[134] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6063 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6064 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6065 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6066 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6067 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6068 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6069 ) , + .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6070 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6071 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6072 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6073 ) ) ; +cbx_1__1_ cbx_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6074 } ) , + .chanx_left_in ( sb_1__1__22_chanx_right_out ) , + .chanx_right_in ( sb_1__1__33_chanx_left_out ) , + .ccff_head ( sb_1__1__33_ccff_tail ) , + .chanx_left_out ( cbx_1__1__33_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__33_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6075 ) , + .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[33] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[33] ) , + .pReset_E_in ( pResetWires[75] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6076 ) , + .pReset_W_out ( pResetWires[74] ) , .pReset_S_out ( pResetWires[76] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6077 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[142] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6078 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6079 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6080 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6081 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6082 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6083 ) , + .clk_1_W_in ( clk_1_wires[43] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6084 ) , + .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6085 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6086 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6087 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6088 ) ) ; +cbx_1__1_ cbx_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6089 } ) , + .chanx_left_in ( sb_1__1__23_chanx_right_out ) , + .chanx_right_in ( sb_1__1__34_chanx_left_out ) , + .ccff_head ( sb_1__1__34_ccff_tail ) , + .chanx_left_out ( cbx_1__1__34_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__34_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6090 ) , + .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[34] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[34] ) , + .pReset_E_in ( pResetWires[124] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6091 ) , + .pReset_W_out ( pResetWires[123] ) , .pReset_S_out ( pResetWires[125] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6092 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6093 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6094 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6095 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6096 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6097 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6098 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6099 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6100 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6101 ) , + .clk_2_E_in ( clk_2_wires[27] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6102 ) , + .clk_2_W_out ( clk_2_wires[28] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6103 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6104 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6105 ) ) ; +cbx_1__1_ cbx_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6106 } ) , + .chanx_left_in ( sb_1__1__24_chanx_right_out ) , + .chanx_right_in ( sb_1__1__35_chanx_left_out ) , + .ccff_head ( sb_1__1__35_ccff_tail ) , + .chanx_left_out ( cbx_1__1__35_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__35_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6107 ) , + .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[35] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[35] ) , + .pReset_E_in ( pResetWires[173] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6108 ) , + .pReset_W_out ( pResetWires[172] ) , .pReset_S_out ( pResetWires[174] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6109 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[148] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6110 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6111 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6112 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6113 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6114 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6115 ) , + .clk_1_W_in ( clk_1_wires[50] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6116 ) , + .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6117 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6118 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6119 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6120 ) ) ; +cbx_1__1_ cbx_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6121 } ) , + .chanx_left_in ( sb_1__1__25_chanx_right_out ) , + .chanx_right_in ( sb_1__1__36_chanx_left_out ) , + .ccff_head ( sb_1__1__36_ccff_tail ) , + .chanx_left_out ( cbx_1__1__36_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__36_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6122 ) , + .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[36] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[36] ) , + .pReset_E_in ( pResetWires[222] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6123 ) , + .pReset_W_out ( pResetWires[221] ) , .pReset_S_out ( pResetWires[223] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6124 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6125 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6126 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6127 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6128 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6129 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6130 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6131 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6132 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6133 ) , + .clk_2_E_in ( clk_2_wires[36] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6134 ) , + .clk_2_W_out ( clk_2_wires[37] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6135 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6136 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6137 ) ) ; +cbx_1__1_ cbx_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6138 } ) , + .chanx_left_in ( sb_1__1__26_chanx_right_out ) , + .chanx_right_in ( sb_1__1__37_chanx_left_out ) , + .ccff_head ( sb_1__1__37_ccff_tail ) , + .chanx_left_out ( cbx_1__1__37_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__37_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6139 ) , + .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[37] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[37] ) , + .pReset_E_in ( pResetWires[271] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6140 ) , + .pReset_W_out ( pResetWires[270] ) , .pReset_S_out ( pResetWires[272] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6141 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[154] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6142 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6143 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6144 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6145 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6146 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6147 ) , + .clk_1_W_in ( clk_1_wires[57] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6148 ) , + .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6149 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6150 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6151 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6152 ) ) ; +cbx_1__1_ cbx_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6153 } ) , + .chanx_left_in ( sb_1__1__27_chanx_right_out ) , + .chanx_right_in ( sb_1__1__38_chanx_left_out ) , + .ccff_head ( sb_1__1__38_ccff_tail ) , + .chanx_left_out ( cbx_1__1__38_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__38_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6154 ) , + .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[38] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[38] ) , + .pReset_E_in ( pResetWires[320] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6155 ) , + .pReset_W_out ( pResetWires[319] ) , .pReset_S_out ( pResetWires[321] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6156 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6157 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6158 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6159 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6160 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6161 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6162 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6163 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6164 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6165 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6167 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6168 ) , + .clk_3_E_in ( clk_3_wires[46] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , + .clk_3_W_out ( clk_3_wires[47] ) ) ; +cbx_1__1_ cbx_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6170 } ) , + .chanx_left_in ( sb_1__1__28_chanx_right_out ) , + .chanx_right_in ( sb_1__1__39_chanx_left_out ) , + .ccff_head ( sb_1__1__39_ccff_tail ) , + .chanx_left_out ( cbx_1__1__39_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__39_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6171 ) , + .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[39] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[39] ) , + .pReset_E_in ( pResetWires[369] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6172 ) , + .pReset_W_out ( pResetWires[368] ) , .pReset_S_out ( pResetWires[370] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6173 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[160] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6174 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6175 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6176 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6177 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6178 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6179 ) , + .clk_1_W_in ( clk_1_wires[64] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6180 ) , + .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6181 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6182 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6183 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6184 ) ) ; +cbx_1__1_ cbx_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6185 } ) , + .chanx_left_in ( sb_1__1__29_chanx_right_out ) , + .chanx_right_in ( sb_1__1__40_chanx_left_out ) , + .ccff_head ( sb_1__1__40_ccff_tail ) , + .chanx_left_out ( cbx_1__1__40_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__40_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6186 ) , + .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[40] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[40] ) , + .pReset_E_in ( pResetWires[418] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6187 ) , + .pReset_W_out ( pResetWires[417] ) , .pReset_S_out ( pResetWires[419] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6188 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6189 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6190 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6191 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6192 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6193 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6194 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6195 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6196 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6197 ) , + .clk_2_E_in ( clk_2_wires[49] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6198 ) , + .clk_2_W_out ( clk_2_wires[50] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6199 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6200 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6201 ) ) ; +cbx_1__1_ cbx_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6202 } ) , + .chanx_left_in ( sb_1__1__30_chanx_right_out ) , + .chanx_right_in ( sb_1__1__41_chanx_left_out ) , + .ccff_head ( sb_1__1__41_ccff_tail ) , + .chanx_left_out ( cbx_1__1__41_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__41_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6203 ) , + .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[41] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[41] ) , + .pReset_E_in ( pResetWires[467] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6204 ) , + .pReset_W_out ( pResetWires[466] ) , .pReset_S_out ( pResetWires[468] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6205 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[166] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6206 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6207 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6208 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6209 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6210 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6211 ) , + .clk_1_W_in ( clk_1_wires[71] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6212 ) , + .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6213 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6214 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6215 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6216 ) ) ; +cbx_1__1_ cbx_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6217 } ) , + .chanx_left_in ( sb_1__1__31_chanx_right_out ) , + .chanx_right_in ( sb_1__1__42_chanx_left_out ) , + .ccff_head ( sb_1__1__42_ccff_tail ) , + .chanx_left_out ( cbx_1__1__42_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__42_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6218 ) , + .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[42] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[42] ) , + .pReset_E_in ( pResetWires[516] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6219 ) , + .pReset_W_out ( pResetWires[515] ) , .pReset_S_out ( pResetWires[517] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6220 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6221 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6222 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6223 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6224 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6225 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6226 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6227 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6228 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6229 ) , + .clk_2_E_in ( clk_2_wires[62] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6230 ) , + .clk_2_W_out ( clk_2_wires[63] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6231 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6232 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6233 ) ) ; +cbx_1__1_ cbx_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6234 } ) , + .chanx_left_in ( sb_1__1__32_chanx_right_out ) , + .chanx_right_in ( sb_1__1__43_chanx_left_out ) , + .ccff_head ( sb_1__1__43_ccff_tail ) , + .chanx_left_out ( cbx_1__1__43_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__43_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6235 ) , + .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[43] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[43] ) , + .pReset_E_in ( pResetWires[565] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6236 ) , + .pReset_W_out ( pResetWires[564] ) , .pReset_S_out ( pResetWires[566] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6237 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[172] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6238 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6239 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6240 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6241 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6242 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6243 ) , + .clk_1_W_in ( clk_1_wires[78] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6244 ) , + .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6245 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6246 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6247 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6248 ) ) ; +cbx_1__1_ cbx_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6249 } ) , + .chanx_left_in ( sb_1__1__33_chanx_right_out ) , + .chanx_right_in ( sb_1__1__44_chanx_left_out ) , + .ccff_head ( sb_1__1__44_ccff_tail ) , + .chanx_left_out ( cbx_1__1__44_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__44_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6250 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[44] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[44] ) , + .pReset_E_in ( pResetWires[79] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6251 ) , + .pReset_W_out ( pResetWires[78] ) , .pReset_S_out ( pResetWires[80] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6252 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[180] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6253 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6254 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6255 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6256 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6257 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6258 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6259 ) , + .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6261 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6262 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6263 ) ) ; +cbx_1__1_ cbx_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6264 } ) , + .chanx_left_in ( sb_1__1__34_chanx_right_out ) , + .chanx_right_in ( sb_1__1__45_chanx_left_out ) , + .ccff_head ( sb_1__1__45_ccff_tail ) , + .chanx_left_out ( cbx_1__1__45_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__45_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6265 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[45] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[45] ) , + .pReset_E_in ( pResetWires[128] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6266 ) , + .pReset_W_out ( pResetWires[127] ) , .pReset_S_out ( pResetWires[129] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6267 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6268 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6269 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6270 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6271 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6272 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6273 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6274 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6275 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6276 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6277 ) , + .clk_2_W_in ( clk_2_wires[25] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6278 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6279 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6280 ) ) ; +cbx_1__1_ cbx_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6281 } ) , + .chanx_left_in ( sb_1__1__35_chanx_right_out ) , + .chanx_right_in ( sb_1__1__46_chanx_left_out ) , + .ccff_head ( sb_1__1__46_ccff_tail ) , + .chanx_left_out ( cbx_1__1__46_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__46_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6282 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[46] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[46] ) , + .pReset_E_in ( pResetWires[177] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6283 ) , + .pReset_W_out ( pResetWires[176] ) , .pReset_S_out ( pResetWires[178] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6284 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[186] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6285 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6286 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6287 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6288 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6289 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6290 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6291 ) , + .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6293 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6294 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6295 ) ) ; +cbx_1__1_ cbx_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6296 } ) , + .chanx_left_in ( sb_1__1__36_chanx_right_out ) , + .chanx_right_in ( sb_1__1__47_chanx_left_out ) , + .ccff_head ( sb_1__1__47_ccff_tail ) , + .chanx_left_out ( cbx_1__1__47_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__47_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6297 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[47] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[47] ) , + .pReset_E_in ( pResetWires[226] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6298 ) , + .pReset_W_out ( pResetWires[225] ) , .pReset_S_out ( pResetWires[227] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6299 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6300 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6301 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6302 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6303 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6304 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6305 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6306 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6307 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6308 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6309 ) , + .clk_2_W_in ( clk_2_wires[34] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6310 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6311 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6312 ) ) ; +cbx_1__1_ cbx_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6313 } ) , + .chanx_left_in ( sb_1__1__37_chanx_right_out ) , + .chanx_right_in ( sb_1__1__48_chanx_left_out ) , + .ccff_head ( sb_1__1__48_ccff_tail ) , + .chanx_left_out ( cbx_1__1__48_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__48_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6314 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[48] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[48] ) , + .pReset_E_in ( pResetWires[275] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6315 ) , + .pReset_W_out ( pResetWires[274] ) , .pReset_S_out ( pResetWires[276] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6316 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[192] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6317 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6318 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6319 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6320 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6322 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6323 ) , + .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6324 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6325 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6326 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6327 ) ) ; +cbx_1__1_ cbx_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6328 } ) , + .chanx_left_in ( sb_1__1__38_chanx_right_out ) , + .chanx_right_in ( sb_1__1__49_chanx_left_out ) , + .ccff_head ( sb_1__1__49_ccff_tail ) , + .chanx_left_out ( cbx_1__1__49_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__49_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6329 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[49] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[49] ) , + .pReset_E_in ( pResetWires[324] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6330 ) , + .pReset_W_out ( pResetWires[323] ) , .pReset_S_out ( pResetWires[325] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6331 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6332 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6333 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6334 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6335 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6336 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6337 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6338 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6339 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6340 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6342 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6343 ) , + .clk_3_E_in ( clk_3_wires[6] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6344 ) , + .clk_3_W_out ( clk_3_wires[7] ) ) ; +cbx_1__1_ cbx_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6345 } ) , + .chanx_left_in ( sb_1__1__39_chanx_right_out ) , + .chanx_right_in ( sb_1__1__50_chanx_left_out ) , + .ccff_head ( sb_1__1__50_ccff_tail ) , + .chanx_left_out ( cbx_1__1__50_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__50_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6346 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[50] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[50] ) , + .pReset_E_in ( pResetWires[373] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6347 ) , + .pReset_W_out ( pResetWires[372] ) , .pReset_S_out ( pResetWires[374] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6348 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[198] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6349 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6350 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6351 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6352 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6353 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6354 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6355 ) , + .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6356 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6357 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6359 ) ) ; +cbx_1__1_ cbx_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6360 } ) , + .chanx_left_in ( sb_1__1__40_chanx_right_out ) , + .chanx_right_in ( sb_1__1__51_chanx_left_out ) , + .ccff_head ( sb_1__1__51_ccff_tail ) , + .chanx_left_out ( cbx_1__1__51_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__51_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6361 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[51] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[51] ) , + .pReset_E_in ( pResetWires[422] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6362 ) , + .pReset_W_out ( pResetWires[421] ) , .pReset_S_out ( pResetWires[423] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6363 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6364 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6365 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6366 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6367 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6368 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6369 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6370 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6371 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6372 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6373 ) , + .clk_2_W_in ( clk_2_wires[47] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6374 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6375 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6376 ) ) ; +cbx_1__1_ cbx_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6377 } ) , + .chanx_left_in ( sb_1__1__41_chanx_right_out ) , + .chanx_right_in ( sb_1__1__52_chanx_left_out ) , + .ccff_head ( sb_1__1__52_ccff_tail ) , + .chanx_left_out ( cbx_1__1__52_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__52_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6378 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[52] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[52] ) , + .pReset_E_in ( pResetWires[471] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6379 ) , + .pReset_W_out ( pResetWires[470] ) , .pReset_S_out ( pResetWires[472] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6380 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[204] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6381 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6382 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6383 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6384 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6385 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6386 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6387 ) , + .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6388 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6389 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6390 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6391 ) ) ; +cbx_1__1_ cbx_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6392 } ) , + .chanx_left_in ( sb_1__1__42_chanx_right_out ) , + .chanx_right_in ( sb_1__1__53_chanx_left_out ) , + .ccff_head ( sb_1__1__53_ccff_tail ) , + .chanx_left_out ( cbx_1__1__53_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__53_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6393 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[53] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[53] ) , + .pReset_E_in ( pResetWires[520] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6394 ) , + .pReset_W_out ( pResetWires[519] ) , .pReset_S_out ( pResetWires[521] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6395 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6396 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6397 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6398 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6399 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6400 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6401 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6402 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6403 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6404 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6405 ) , + .clk_2_W_in ( clk_2_wires[60] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6406 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6407 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6408 ) ) ; +cbx_1__1_ cbx_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6409 } ) , + .chanx_left_in ( sb_1__1__43_chanx_right_out ) , + .chanx_right_in ( sb_1__1__54_chanx_left_out ) , + .ccff_head ( sb_1__1__54_ccff_tail ) , + .chanx_left_out ( cbx_1__1__54_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__54_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6410 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[54] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[54] ) , + .pReset_E_in ( pResetWires[569] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6411 ) , + .pReset_W_out ( pResetWires[568] ) , .pReset_S_out ( pResetWires[570] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6412 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[210] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6413 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6414 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6415 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6416 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6417 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6418 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6419 ) , + .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6421 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6423 ) ) ; +cbx_1__1_ cbx_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6424 } ) , + .chanx_left_in ( sb_1__1__44_chanx_right_out ) , + .chanx_right_in ( sb_1__1__55_chanx_left_out ) , + .ccff_head ( sb_1__1__55_ccff_tail ) , + .chanx_left_out ( cbx_1__1__55_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__55_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6425 ) , + .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[55] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[55] ) , + .pReset_E_in ( pResetWires[83] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6426 ) , + .pReset_W_out ( pResetWires[82] ) , .pReset_S_out ( pResetWires[84] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6427 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[218] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6428 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6429 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6430 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6431 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6432 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6433 ) , + .clk_1_W_in ( clk_1_wires[85] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6434 ) , + .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6435 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6436 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6437 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6438 ) ) ; +cbx_1__1_ cbx_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6439 } ) , + .chanx_left_in ( sb_1__1__45_chanx_right_out ) , + .chanx_right_in ( sb_1__1__56_chanx_left_out ) , + .ccff_head ( sb_1__1__56_ccff_tail ) , + .chanx_left_out ( cbx_1__1__56_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__56_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6440 ) , + .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[56] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[56] ) , + .pReset_E_in ( pResetWires[132] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6441 ) , + .pReset_W_out ( pResetWires[131] ) , .pReset_S_out ( pResetWires[133] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6442 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6443 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6444 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6445 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6446 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6447 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6448 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6449 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6450 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6452 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6454 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6455 ) ) ; +cbx_1__1_ cbx_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6456 } ) , + .chanx_left_in ( sb_1__1__46_chanx_right_out ) , + .chanx_right_in ( sb_1__1__57_chanx_left_out ) , + .ccff_head ( sb_1__1__57_ccff_tail ) , + .chanx_left_out ( cbx_1__1__57_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__57_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6457 ) , + .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[57] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[57] ) , + .pReset_E_in ( pResetWires[181] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6458 ) , + .pReset_W_out ( pResetWires[180] ) , .pReset_S_out ( pResetWires[182] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6459 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[224] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6460 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6461 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6462 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6463 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6464 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6465 ) , + .clk_1_W_in ( clk_1_wires[92] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6466 ) , + .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6467 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6468 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6469 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6470 ) ) ; +cbx_1__1_ cbx_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6471 } ) , + .chanx_left_in ( sb_1__1__47_chanx_right_out ) , + .chanx_right_in ( sb_1__1__58_chanx_left_out ) , + .ccff_head ( sb_1__1__58_ccff_tail ) , + .chanx_left_out ( cbx_1__1__58_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__58_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6472 ) , + .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[58] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[58] ) , + .pReset_E_in ( pResetWires[230] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6473 ) , + .pReset_W_out ( pResetWires[229] ) , .pReset_S_out ( pResetWires[231] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6474 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6475 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6476 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6477 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6478 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6479 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6480 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6481 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6482 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6486 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6487 ) ) ; +cbx_1__1_ cbx_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6488 } ) , + .chanx_left_in ( sb_1__1__48_chanx_right_out ) , + .chanx_right_in ( sb_1__1__59_chanx_left_out ) , + .ccff_head ( sb_1__1__59_ccff_tail ) , + .chanx_left_out ( cbx_1__1__59_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__59_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6489 ) , + .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[59] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[59] ) , + .pReset_E_in ( pResetWires[279] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6490 ) , + .pReset_W_out ( pResetWires[278] ) , .pReset_S_out ( pResetWires[280] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6491 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[230] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6492 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6493 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6494 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6495 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6496 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6497 ) , + .clk_1_W_in ( clk_1_wires[99] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6498 ) , + .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6500 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6501 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6502 ) ) ; +cbx_1__1_ cbx_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6503 } ) , + .chanx_left_in ( sb_1__1__49_chanx_right_out ) , + .chanx_right_in ( sb_1__1__60_chanx_left_out ) , + .ccff_head ( sb_1__1__60_ccff_tail ) , + .chanx_left_out ( cbx_1__1__60_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__60_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6504 ) , + .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[60] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[60] ) , + .pReset_E_in ( pResetWires[328] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6505 ) , + .pReset_W_out ( pResetWires[327] ) , .pReset_S_out ( pResetWires[329] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6506 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6507 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6508 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6509 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6510 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6511 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6512 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6513 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6514 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6515 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6516 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6517 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6518 ) , + .clk_3_E_in ( clk_3_wires[2] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6519 ) , + .clk_3_W_out ( clk_3_wires[3] ) ) ; +cbx_1__1_ cbx_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6520 } ) , + .chanx_left_in ( sb_1__1__50_chanx_right_out ) , + .chanx_right_in ( sb_1__1__61_chanx_left_out ) , + .ccff_head ( sb_1__1__61_ccff_tail ) , + .chanx_left_out ( cbx_1__1__61_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__61_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6521 ) , + .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[61] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[61] ) , + .pReset_E_in ( pResetWires[377] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6522 ) , + .pReset_W_out ( pResetWires[376] ) , .pReset_S_out ( pResetWires[378] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[236] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6524 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6525 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6526 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6527 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6528 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6529 ) , + .clk_1_W_in ( clk_1_wires[106] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6530 ) , + .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6531 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6532 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6533 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6534 ) ) ; +cbx_1__1_ cbx_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6535 } ) , + .chanx_left_in ( sb_1__1__51_chanx_right_out ) , + .chanx_right_in ( sb_1__1__62_chanx_left_out ) , + .ccff_head ( sb_1__1__62_ccff_tail ) , + .chanx_left_out ( cbx_1__1__62_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__62_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6536 ) , + .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[62] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[62] ) , + .pReset_E_in ( pResetWires[426] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6537 ) , + .pReset_W_out ( pResetWires[425] ) , .pReset_S_out ( pResetWires[427] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6538 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6539 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6540 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6541 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6542 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6543 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6544 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6545 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6546 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6548 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6551 ) ) ; +cbx_1__1_ cbx_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6552 } ) , + .chanx_left_in ( sb_1__1__52_chanx_right_out ) , + .chanx_right_in ( sb_1__1__63_chanx_left_out ) , + .ccff_head ( sb_1__1__63_ccff_tail ) , + .chanx_left_out ( cbx_1__1__63_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__63_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6553 ) , + .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[63] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[63] ) , + .pReset_E_in ( pResetWires[475] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6554 ) , + .pReset_W_out ( pResetWires[474] ) , .pReset_S_out ( pResetWires[476] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6555 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[242] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6556 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6557 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6558 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6559 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6560 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6561 ) , + .clk_1_W_in ( clk_1_wires[113] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6562 ) , + .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6563 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6564 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6565 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6566 ) ) ; +cbx_1__1_ cbx_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6567 } ) , + .chanx_left_in ( sb_1__1__53_chanx_right_out ) , + .chanx_right_in ( sb_1__1__64_chanx_left_out ) , + .ccff_head ( sb_1__1__64_ccff_tail ) , + .chanx_left_out ( cbx_1__1__64_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__64_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6568 ) , + .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[64] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[64] ) , + .pReset_E_in ( pResetWires[524] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6569 ) , + .pReset_W_out ( pResetWires[523] ) , .pReset_S_out ( pResetWires[525] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6570 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6571 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6572 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6573 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6574 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6575 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6576 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6577 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6578 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6580 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6582 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6583 ) ) ; +cbx_1__1_ cbx_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6584 } ) , + .chanx_left_in ( sb_1__1__54_chanx_right_out ) , + .chanx_right_in ( sb_1__1__65_chanx_left_out ) , + .ccff_head ( sb_1__1__65_ccff_tail ) , + .chanx_left_out ( cbx_1__1__65_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__65_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6585 ) , + .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[65] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[65] ) , + .pReset_E_in ( pResetWires[573] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6586 ) , + .pReset_W_out ( pResetWires[572] ) , .pReset_S_out ( pResetWires[574] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6587 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[248] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6588 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6589 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6590 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6591 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6592 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6593 ) , + .clk_1_W_in ( clk_1_wires[120] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6594 ) , + .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6595 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6596 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6597 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6598 ) ) ; +cbx_1__1_ cbx_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6599 } ) , + .chanx_left_in ( sb_1__1__55_chanx_right_out ) , + .chanx_right_in ( sb_1__1__66_chanx_left_out ) , + .ccff_head ( sb_1__1__66_ccff_tail ) , + .chanx_left_out ( cbx_1__1__66_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__66_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6600 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[66] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[66] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6601 ) , + .pReset_W_in ( pResetWires[86] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6602 ) , + .pReset_S_out ( pResetWires[88] ) , .pReset_E_out ( pResetWires[87] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[256] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6603 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6604 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6605 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6606 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6607 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6608 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6609 ) , + .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6610 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6611 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6612 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6613 ) ) ; +cbx_1__1_ cbx_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6614 } ) , + .chanx_left_in ( sb_1__1__56_chanx_right_out ) , + .chanx_right_in ( sb_1__1__67_chanx_left_out ) , + .ccff_head ( sb_1__1__67_ccff_tail ) , + .chanx_left_out ( cbx_1__1__67_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__67_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6615 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[67] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[67] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6616 ) , + .pReset_W_in ( pResetWires[135] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6617 ) , + .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6618 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6619 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6620 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6621 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6622 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6623 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6624 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6625 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6630 ) ) ; +cbx_1__1_ cbx_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6631 } ) , + .chanx_left_in ( sb_1__1__57_chanx_right_out ) , + .chanx_right_in ( sb_1__1__68_chanx_left_out ) , + .ccff_head ( sb_1__1__68_ccff_tail ) , + .chanx_left_out ( cbx_1__1__68_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__68_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6632 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[68] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[68] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6633 ) , + .pReset_W_in ( pResetWires[184] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6634 ) , + .pReset_S_out ( pResetWires[186] ) , .pReset_E_out ( pResetWires[185] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[262] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6635 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6636 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6637 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6638 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6639 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6640 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6641 ) , + .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6645 ) ) ; +cbx_1__1_ cbx_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6646 } ) , + .chanx_left_in ( sb_1__1__58_chanx_right_out ) , + .chanx_right_in ( sb_1__1__69_chanx_left_out ) , + .ccff_head ( sb_1__1__69_ccff_tail ) , + .chanx_left_out ( cbx_1__1__69_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__69_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6647 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[69] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[69] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6648 ) , + .pReset_W_in ( pResetWires[233] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6649 ) , + .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6650 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6651 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6652 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6653 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6654 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6655 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6656 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6657 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6661 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6662 ) ) ; +cbx_1__1_ cbx_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6663 } ) , + .chanx_left_in ( sb_1__1__59_chanx_right_out ) , + .chanx_right_in ( sb_1__1__70_chanx_left_out ) , + .ccff_head ( sb_1__1__70_ccff_tail ) , + .chanx_left_out ( cbx_1__1__70_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__70_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6664 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[70] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[70] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6665 ) , + .pReset_W_in ( pResetWires[282] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6666 ) , + .pReset_S_out ( pResetWires[284] ) , .pReset_E_out ( pResetWires[283] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[268] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6667 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6668 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6669 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6670 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6671 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6672 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6673 ) , + .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6674 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6675 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6676 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6677 ) ) ; +cbx_1__1_ cbx_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6678 } ) , + .chanx_left_in ( sb_1__1__60_chanx_right_out ) , + .chanx_right_in ( sb_1__1__71_chanx_left_out ) , + .ccff_head ( sb_1__1__71_ccff_tail ) , + .chanx_left_out ( cbx_1__1__71_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__71_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6679 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[71] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[71] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6680 ) , + .pReset_W_in ( pResetWires[331] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6681 ) , + .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6682 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6683 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6684 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6686 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6687 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6688 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6689 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6692 ) , + .clk_3_W_in ( clk_3_wires[0] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6693 ) , + .clk_3_E_out ( clk_3_wires[1] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6694 ) ) ; +cbx_1__1_ cbx_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6695 } ) , + .chanx_left_in ( sb_1__1__61_chanx_right_out ) , + .chanx_right_in ( sb_1__1__72_chanx_left_out ) , + .ccff_head ( sb_1__1__72_ccff_tail ) , + .chanx_left_out ( cbx_1__1__72_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__72_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6696 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[72] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[72] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6697 ) , + .pReset_W_in ( pResetWires[380] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6698 ) , + .pReset_S_out ( pResetWires[382] ) , .pReset_E_out ( pResetWires[381] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[274] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6699 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6700 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6701 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6702 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6703 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6704 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6705 ) , + .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6709 ) ) ; +cbx_1__1_ cbx_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6710 } ) , + .chanx_left_in ( sb_1__1__62_chanx_right_out ) , + .chanx_right_in ( sb_1__1__73_chanx_left_out ) , + .ccff_head ( sb_1__1__73_ccff_tail ) , + .chanx_left_out ( cbx_1__1__73_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__73_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6711 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[73] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[73] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6712 ) , + .pReset_W_in ( pResetWires[429] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6713 ) , + .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6714 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6715 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6716 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6717 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6718 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6719 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6720 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6721 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6723 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6726 ) ) ; +cbx_1__1_ cbx_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6727 } ) , + .chanx_left_in ( sb_1__1__63_chanx_right_out ) , + .chanx_right_in ( sb_1__1__74_chanx_left_out ) , + .ccff_head ( sb_1__1__74_ccff_tail ) , + .chanx_left_out ( cbx_1__1__74_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__74_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6728 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[74] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[74] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6729 ) , + .pReset_W_in ( pResetWires[478] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6730 ) , + .pReset_S_out ( pResetWires[480] ) , .pReset_E_out ( pResetWires[479] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[280] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6731 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6732 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6733 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6734 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6735 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6736 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6737 ) , + .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6738 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6739 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6740 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6741 ) ) ; +cbx_1__1_ cbx_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6742 } ) , + .chanx_left_in ( sb_1__1__64_chanx_right_out ) , + .chanx_right_in ( sb_1__1__75_chanx_left_out ) , + .ccff_head ( sb_1__1__75_ccff_tail ) , + .chanx_left_out ( cbx_1__1__75_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__75_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6743 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[75] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[75] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6744 ) , + .pReset_W_in ( pResetWires[527] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6745 ) , + .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6746 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6747 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6748 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6749 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6750 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6751 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6752 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6753 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6755 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6757 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6758 ) ) ; +cbx_1__1_ cbx_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6759 } ) , + .chanx_left_in ( sb_1__1__65_chanx_right_out ) , + .chanx_right_in ( sb_1__1__76_chanx_left_out ) , + .ccff_head ( sb_1__1__76_ccff_tail ) , + .chanx_left_out ( cbx_1__1__76_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__76_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6760 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[76] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[76] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6761 ) , + .pReset_W_in ( pResetWires[576] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6762 ) , + .pReset_S_out ( pResetWires[578] ) , .pReset_E_out ( pResetWires[577] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[286] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6763 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6764 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6765 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6766 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6767 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6768 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6769 ) , + .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6770 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6771 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6772 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6773 ) ) ; +cbx_1__1_ cbx_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6774 } ) , + .chanx_left_in ( sb_1__1__66_chanx_right_out ) , + .chanx_right_in ( sb_1__1__77_chanx_left_out ) , + .ccff_head ( sb_1__1__77_ccff_tail ) , + .chanx_left_out ( cbx_1__1__77_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__77_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6775 ) , + .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[77] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[77] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6776 ) , + .pReset_W_in ( pResetWires[90] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6777 ) , + .pReset_S_out ( pResetWires[92] ) , .pReset_E_out ( pResetWires[91] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[294] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6778 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6779 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6780 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6781 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6782 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6783 ) , + .clk_1_W_in ( clk_1_wires[127] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6784 ) , + .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6785 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6787 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6788 ) ) ; +cbx_1__1_ cbx_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6789 } ) , + .chanx_left_in ( sb_1__1__67_chanx_right_out ) , + .chanx_right_in ( sb_1__1__78_chanx_left_out ) , + .ccff_head ( sb_1__1__78_ccff_tail ) , + .chanx_left_out ( cbx_1__1__78_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__78_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6790 ) , + .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[78] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[78] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6791 ) , + .pReset_W_in ( pResetWires[139] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6792 ) , + .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6793 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6794 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6795 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6796 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6797 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6798 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6799 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6800 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6801 ) , + .clk_2_E_in ( clk_2_wires[71] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6802 ) , + .clk_2_W_out ( clk_2_wires[72] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6803 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6805 ) ) ; +cbx_1__1_ cbx_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6806 } ) , + .chanx_left_in ( sb_1__1__68_chanx_right_out ) , + .chanx_right_in ( sb_1__1__79_chanx_left_out ) , + .ccff_head ( sb_1__1__79_ccff_tail ) , + .chanx_left_out ( cbx_1__1__79_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__79_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6807 ) , + .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[79] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[79] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6808 ) , + .pReset_W_in ( pResetWires[188] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6809 ) , + .pReset_S_out ( pResetWires[190] ) , .pReset_E_out ( pResetWires[189] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[300] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6810 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6811 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6812 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6813 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6814 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6815 ) , + .clk_1_W_in ( clk_1_wires[134] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6816 ) , + .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6817 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6818 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6819 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6820 ) ) ; +cbx_1__1_ cbx_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6821 } ) , + .chanx_left_in ( sb_1__1__69_chanx_right_out ) , + .chanx_right_in ( sb_1__1__80_chanx_left_out ) , + .ccff_head ( sb_1__1__80_ccff_tail ) , + .chanx_left_out ( cbx_1__1__80_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__80_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6822 ) , + .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[80] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[80] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6823 ) , + .pReset_W_in ( pResetWires[237] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6824 ) , + .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6825 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6826 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6827 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6828 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6829 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6830 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6831 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6832 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6833 ) , + .clk_2_E_in ( clk_2_wires[80] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6834 ) , + .clk_2_W_out ( clk_2_wires[81] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6835 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6836 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6837 ) ) ; +cbx_1__1_ cbx_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6838 } ) , + .chanx_left_in ( sb_1__1__70_chanx_right_out ) , + .chanx_right_in ( sb_1__1__81_chanx_left_out ) , + .ccff_head ( sb_1__1__81_ccff_tail ) , + .chanx_left_out ( cbx_1__1__81_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__81_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6839 ) , + .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[81] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[81] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6840 ) , + .pReset_W_in ( pResetWires[286] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6841 ) , + .pReset_S_out ( pResetWires[288] ) , .pReset_E_out ( pResetWires[287] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[306] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6842 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6843 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6844 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6845 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6846 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6847 ) , + .clk_1_W_in ( clk_1_wires[141] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6848 ) , + .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6849 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6850 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6851 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6852 ) ) ; +cbx_1__1_ cbx_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6853 } ) , + .chanx_left_in ( sb_1__1__71_chanx_right_out ) , + .chanx_right_in ( sb_1__1__82_chanx_left_out ) , + .ccff_head ( sb_1__1__82_ccff_tail ) , + .chanx_left_out ( cbx_1__1__82_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__82_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6854 ) , + .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[82] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[82] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6855 ) , + .pReset_W_in ( pResetWires[335] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6856 ) , + .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6857 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6858 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6859 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6860 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6861 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6862 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6863 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6864 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6866 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6867 ) , + .clk_3_W_in ( clk_3_wires[4] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6868 ) , + .clk_3_E_out ( clk_3_wires[5] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6869 ) ) ; +cbx_1__1_ cbx_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6870 } ) , + .chanx_left_in ( sb_1__1__72_chanx_right_out ) , + .chanx_right_in ( sb_1__1__83_chanx_left_out ) , + .ccff_head ( sb_1__1__83_ccff_tail ) , + .chanx_left_out ( cbx_1__1__83_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__83_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6871 ) , + .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[83] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[83] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6872 ) , + .pReset_W_in ( pResetWires[384] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6873 ) , + .pReset_S_out ( pResetWires[386] ) , .pReset_E_out ( pResetWires[385] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[312] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6874 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6875 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6876 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6877 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6878 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6879 ) , + .clk_1_W_in ( clk_1_wires[148] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6880 ) , + .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6881 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6882 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6883 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6884 ) ) ; +cbx_1__1_ cbx_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6885 } ) , + .chanx_left_in ( sb_1__1__73_chanx_right_out ) , + .chanx_right_in ( sb_1__1__84_chanx_left_out ) , + .ccff_head ( sb_1__1__84_ccff_tail ) , + .chanx_left_out ( cbx_1__1__84_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__84_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6886 ) , + .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[84] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[84] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6887 ) , + .pReset_W_in ( pResetWires[433] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6888 ) , + .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6889 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6890 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6891 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6892 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6893 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6894 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6895 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6896 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6897 ) , + .clk_2_E_in ( clk_2_wires[93] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6898 ) , + .clk_2_W_out ( clk_2_wires[94] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6899 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6901 ) ) ; +cbx_1__1_ cbx_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6902 } ) , + .chanx_left_in ( sb_1__1__74_chanx_right_out ) , + .chanx_right_in ( sb_1__1__85_chanx_left_out ) , + .ccff_head ( sb_1__1__85_ccff_tail ) , + .chanx_left_out ( cbx_1__1__85_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__85_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6903 ) , + .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[85] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[85] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6904 ) , + .pReset_W_in ( pResetWires[482] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6905 ) , + .pReset_S_out ( pResetWires[484] ) , .pReset_E_out ( pResetWires[483] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[318] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6906 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6907 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6908 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6909 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6910 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6911 ) , + .clk_1_W_in ( clk_1_wires[155] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6912 ) , + .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6913 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6914 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6915 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6916 ) ) ; +cbx_1__1_ cbx_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6917 } ) , + .chanx_left_in ( sb_1__1__75_chanx_right_out ) , + .chanx_right_in ( sb_1__1__86_chanx_left_out ) , + .ccff_head ( sb_1__1__86_ccff_tail ) , + .chanx_left_out ( cbx_1__1__86_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__86_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6918 ) , + .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[86] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[86] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6919 ) , + .pReset_W_in ( pResetWires[531] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6920 ) , + .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6921 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6922 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6923 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6924 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6925 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6926 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6927 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6928 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6929 ) , + .clk_2_E_in ( clk_2_wires[106] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6930 ) , + .clk_2_W_out ( clk_2_wires[107] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6931 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6932 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6933 ) ) ; +cbx_1__1_ cbx_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6934 } ) , + .chanx_left_in ( sb_1__1__76_chanx_right_out ) , + .chanx_right_in ( sb_1__1__87_chanx_left_out ) , + .ccff_head ( sb_1__1__87_ccff_tail ) , + .chanx_left_out ( cbx_1__1__87_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__87_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6935 ) , + .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[87] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[87] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6936 ) , + .pReset_W_in ( pResetWires[580] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6937 ) , + .pReset_S_out ( pResetWires[582] ) , .pReset_E_out ( pResetWires[581] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[324] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6938 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6939 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6940 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6941 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6942 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6943 ) , + .clk_1_W_in ( clk_1_wires[162] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6944 ) , + .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6945 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6946 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6947 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6948 ) ) ; +cbx_1__1_ cbx_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6949 } ) , + .chanx_left_in ( sb_1__1__77_chanx_right_out ) , + .chanx_right_in ( sb_1__1__88_chanx_left_out ) , + .ccff_head ( sb_1__1__88_ccff_tail ) , + .chanx_left_out ( cbx_1__1__88_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__88_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6950 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[88] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[88] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6951 ) , + .pReset_W_in ( pResetWires[94] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6952 ) , + .pReset_S_out ( pResetWires[96] ) , .pReset_E_out ( pResetWires[95] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[332] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6953 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6954 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6955 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6956 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6957 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6958 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6959 ) , + .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6960 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6961 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6962 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6963 ) ) ; +cbx_1__1_ cbx_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6964 } ) , + .chanx_left_in ( sb_1__1__78_chanx_right_out ) , + .chanx_right_in ( sb_1__1__89_chanx_left_out ) , + .ccff_head ( sb_1__1__89_ccff_tail ) , + .chanx_left_out ( cbx_1__1__89_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__89_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6965 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[89] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[89] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6966 ) , + .pReset_W_in ( pResetWires[143] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6967 ) , + .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6968 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6969 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6970 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6971 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6972 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6973 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6974 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6975 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6976 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6977 ) , + .clk_2_W_in ( clk_2_wires[69] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6978 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6979 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6980 ) ) ; +cbx_1__1_ cbx_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6981 } ) , + .chanx_left_in ( sb_1__1__79_chanx_right_out ) , + .chanx_right_in ( sb_1__1__90_chanx_left_out ) , + .ccff_head ( sb_1__1__90_ccff_tail ) , + .chanx_left_out ( cbx_1__1__90_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__90_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6982 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[90] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[90] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6983 ) , + .pReset_W_in ( pResetWires[192] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6984 ) , + .pReset_S_out ( pResetWires[194] ) , .pReset_E_out ( pResetWires[193] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[338] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6985 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6986 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6987 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6988 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6989 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6990 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6991 ) , + .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6992 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6993 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6994 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6995 ) ) ; +cbx_1__1_ cbx_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6996 } ) , + .chanx_left_in ( sb_1__1__80_chanx_right_out ) , + .chanx_right_in ( sb_1__1__91_chanx_left_out ) , + .ccff_head ( sb_1__1__91_ccff_tail ) , + .chanx_left_out ( cbx_1__1__91_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__91_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6997 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[91] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[91] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6998 ) , + .pReset_W_in ( pResetWires[241] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6999 ) , + .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7000 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7001 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7002 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7003 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7004 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7005 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7006 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7007 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7008 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7009 ) , + .clk_2_W_in ( clk_2_wires[78] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7010 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7011 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7012 ) ) ; +cbx_1__1_ cbx_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7013 } ) , + .chanx_left_in ( sb_1__1__81_chanx_right_out ) , + .chanx_right_in ( sb_1__1__92_chanx_left_out ) , + .ccff_head ( sb_1__1__92_ccff_tail ) , + .chanx_left_out ( cbx_1__1__92_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__92_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7014 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[92] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[92] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7015 ) , + .pReset_W_in ( pResetWires[290] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7016 ) , + .pReset_S_out ( pResetWires[292] ) , .pReset_E_out ( pResetWires[291] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[344] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7017 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7018 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7019 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7020 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7021 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7022 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7023 ) , + .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7024 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7025 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7026 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7027 ) ) ; +cbx_1__1_ cbx_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7028 } ) , + .chanx_left_in ( sb_1__1__82_chanx_right_out ) , + .chanx_right_in ( sb_1__1__93_chanx_left_out ) , + .ccff_head ( sb_1__1__93_ccff_tail ) , + .chanx_left_out ( cbx_1__1__93_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__93_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7029 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[93] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[93] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7030 ) , + .pReset_W_in ( pResetWires[339] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7031 ) , + .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7032 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7033 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7034 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7035 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7036 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7037 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7038 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7039 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7041 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7042 ) , + .clk_3_W_in ( clk_3_wires[44] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7043 ) , + .clk_3_E_out ( clk_3_wires[45] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7044 ) ) ; +cbx_1__1_ cbx_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7045 } ) , + .chanx_left_in ( sb_1__1__83_chanx_right_out ) , + .chanx_right_in ( sb_1__1__94_chanx_left_out ) , + .ccff_head ( sb_1__1__94_ccff_tail ) , + .chanx_left_out ( cbx_1__1__94_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__94_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7046 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[94] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[94] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7047 ) , + .pReset_W_in ( pResetWires[388] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7048 ) , + .pReset_S_out ( pResetWires[390] ) , .pReset_E_out ( pResetWires[389] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[350] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7049 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7050 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7051 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7052 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7053 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7054 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7055 ) , + .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7056 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7057 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7058 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7059 ) ) ; +cbx_1__1_ cbx_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7060 } ) , + .chanx_left_in ( sb_1__1__84_chanx_right_out ) , + .chanx_right_in ( sb_1__1__95_chanx_left_out ) , + .ccff_head ( sb_1__1__95_ccff_tail ) , + .chanx_left_out ( cbx_1__1__95_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__95_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7061 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[95] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[95] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7062 ) , + .pReset_W_in ( pResetWires[437] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7063 ) , + .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7064 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7065 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7066 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7067 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7068 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7069 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7070 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7071 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7072 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7073 ) , + .clk_2_W_in ( clk_2_wires[91] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7074 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7075 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7076 ) ) ; +cbx_1__1_ cbx_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7077 } ) , + .chanx_left_in ( sb_1__1__85_chanx_right_out ) , + .chanx_right_in ( sb_1__1__96_chanx_left_out ) , + .ccff_head ( sb_1__1__96_ccff_tail ) , + .chanx_left_out ( cbx_1__1__96_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__96_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7078 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[96] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[96] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7079 ) , + .pReset_W_in ( pResetWires[486] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7080 ) , + .pReset_S_out ( pResetWires[488] ) , .pReset_E_out ( pResetWires[487] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[356] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7081 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7082 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7083 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7084 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7085 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7086 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7087 ) , + .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7089 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7090 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7091 ) ) ; +cbx_1__1_ cbx_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7092 } ) , + .chanx_left_in ( sb_1__1__86_chanx_right_out ) , + .chanx_right_in ( sb_1__1__97_chanx_left_out ) , + .ccff_head ( sb_1__1__97_ccff_tail ) , + .chanx_left_out ( cbx_1__1__97_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__97_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7093 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[97] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[97] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7094 ) , + .pReset_W_in ( pResetWires[535] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7095 ) , + .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7096 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7097 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7098 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7099 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7100 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7101 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7103 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7104 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7105 ) , + .clk_2_W_in ( clk_2_wires[104] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7106 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7107 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7108 ) ) ; +cbx_1__1_ cbx_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7109 } ) , + .chanx_left_in ( sb_1__1__87_chanx_right_out ) , + .chanx_right_in ( sb_1__1__98_chanx_left_out ) , + .ccff_head ( sb_1__1__98_ccff_tail ) , + .chanx_left_out ( cbx_1__1__98_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__98_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7110 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[98] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[98] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7111 ) , + .pReset_W_in ( pResetWires[584] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7112 ) , + .pReset_S_out ( pResetWires[586] ) , .pReset_E_out ( pResetWires[585] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[362] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7113 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7114 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7115 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7116 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7117 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7118 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7119 ) , + .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7120 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7121 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7122 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7123 ) ) ; +cbx_1__1_ cbx_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7124 } ) , + .chanx_left_in ( sb_1__1__88_chanx_right_out ) , + .chanx_right_in ( sb_1__1__99_chanx_left_out ) , + .ccff_head ( sb_1__1__99_ccff_tail ) , + .chanx_left_out ( cbx_1__1__99_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__99_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7125 ) , + .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[99] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[99] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7126 ) , + .pReset_W_in ( pResetWires[98] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7127 ) , + .pReset_S_out ( pResetWires[100] ) , .pReset_E_out ( pResetWires[99] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[370] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7128 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7129 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7130 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7131 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7132 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7133 ) , + .clk_1_W_in ( clk_1_wires[169] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7134 ) , + .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7135 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7136 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7137 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7138 ) ) ; +cbx_1__1_ cbx_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7139 } ) , + .chanx_left_in ( sb_1__1__89_chanx_right_out ) , + .chanx_right_in ( sb_1__1__100_chanx_left_out ) , + .ccff_head ( sb_1__1__100_ccff_tail ) , + .chanx_left_out ( cbx_1__1__100_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__100_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7140 ) , + .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[100] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[100] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7141 ) , + .pReset_W_in ( pResetWires[147] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7142 ) , + .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7143 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7144 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7145 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7146 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7147 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7148 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7149 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7150 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7154 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7155 ) ) ; +cbx_1__1_ cbx_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7156 } ) , + .chanx_left_in ( sb_1__1__90_chanx_right_out ) , + .chanx_right_in ( sb_1__1__101_chanx_left_out ) , + .ccff_head ( sb_1__1__101_ccff_tail ) , + .chanx_left_out ( cbx_1__1__101_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__101_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7157 ) , + .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[101] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[101] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7158 ) , + .pReset_W_in ( pResetWires[196] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7159 ) , + .pReset_S_out ( pResetWires[198] ) , .pReset_E_out ( pResetWires[197] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[376] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7160 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7161 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7162 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7163 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7164 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7165 ) , + .clk_1_W_in ( clk_1_wires[176] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7166 ) , + .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7168 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7169 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7170 ) ) ; +cbx_1__1_ cbx_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7171 } ) , + .chanx_left_in ( sb_1__1__91_chanx_right_out ) , + .chanx_right_in ( sb_1__1__102_chanx_left_out ) , + .ccff_head ( sb_1__1__102_ccff_tail ) , + .chanx_left_out ( cbx_1__1__102_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__102_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7172 ) , + .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[102] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[102] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7173 ) , + .pReset_W_in ( pResetWires[245] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7174 ) , + .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7175 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7176 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7177 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7178 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7179 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7180 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7181 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7182 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7187 ) ) ; +cbx_1__1_ cbx_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7188 } ) , + .chanx_left_in ( sb_1__1__92_chanx_right_out ) , + .chanx_right_in ( sb_1__1__103_chanx_left_out ) , + .ccff_head ( sb_1__1__103_ccff_tail ) , + .chanx_left_out ( cbx_1__1__103_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__103_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7189 ) , + .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[103] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[103] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7190 ) , + .pReset_W_in ( pResetWires[294] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7191 ) , + .pReset_S_out ( pResetWires[296] ) , .pReset_E_out ( pResetWires[295] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[382] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7192 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7193 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7194 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7195 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7196 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7197 ) , + .clk_1_W_in ( clk_1_wires[183] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7198 ) , + .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7199 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7200 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7201 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7202 ) ) ; +cbx_1__1_ cbx_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7203 } ) , + .chanx_left_in ( sb_1__1__93_chanx_right_out ) , + .chanx_right_in ( sb_1__1__104_chanx_left_out ) , + .ccff_head ( sb_1__1__104_ccff_tail ) , + .chanx_left_out ( cbx_1__1__104_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__104_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7204 ) , + .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[104] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[104] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7205 ) , + .pReset_W_in ( pResetWires[343] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7206 ) , + .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7207 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7208 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7209 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7210 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7211 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7212 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7213 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7214 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7217 ) , + .clk_3_W_in ( clk_3_wires[48] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7218 ) , + .clk_3_E_out ( clk_3_wires[49] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7219 ) ) ; +cbx_1__1_ cbx_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7220 } ) , + .chanx_left_in ( sb_1__1__94_chanx_right_out ) , + .chanx_right_in ( sb_1__1__105_chanx_left_out ) , + .ccff_head ( sb_1__1__105_ccff_tail ) , + .chanx_left_out ( cbx_1__1__105_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__105_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7221 ) , + .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[105] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[105] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7222 ) , + .pReset_W_in ( pResetWires[392] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7223 ) , + .pReset_S_out ( pResetWires[394] ) , .pReset_E_out ( pResetWires[393] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[388] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7224 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7225 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7226 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7227 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7228 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7229 ) , + .clk_1_W_in ( clk_1_wires[190] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7230 ) , + .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7231 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7232 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7233 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7234 ) ) ; +cbx_1__1_ cbx_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7235 } ) , + .chanx_left_in ( sb_1__1__95_chanx_right_out ) , + .chanx_right_in ( sb_1__1__106_chanx_left_out ) , + .ccff_head ( sb_1__1__106_ccff_tail ) , + .chanx_left_out ( cbx_1__1__106_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__106_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7236 ) , + .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[106] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[106] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7237 ) , + .pReset_W_in ( pResetWires[441] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7238 ) , + .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7239 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7240 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7241 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7242 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7243 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7245 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7246 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7248 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7250 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7251 ) ) ; +cbx_1__1_ cbx_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7252 } ) , + .chanx_left_in ( sb_1__1__96_chanx_right_out ) , + .chanx_right_in ( sb_1__1__107_chanx_left_out ) , + .ccff_head ( sb_1__1__107_ccff_tail ) , + .chanx_left_out ( cbx_1__1__107_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__107_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7253 ) , + .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[107] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[107] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7254 ) , + .pReset_W_in ( pResetWires[490] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7255 ) , + .pReset_S_out ( pResetWires[492] ) , .pReset_E_out ( pResetWires[491] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[394] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7256 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7257 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7258 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7259 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7260 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7261 ) , + .clk_1_W_in ( clk_1_wires[197] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7262 ) , + .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7263 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7264 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7265 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7266 ) ) ; +cbx_1__1_ cbx_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7267 } ) , + .chanx_left_in ( sb_1__1__97_chanx_right_out ) , + .chanx_right_in ( sb_1__1__108_chanx_left_out ) , + .ccff_head ( sb_1__1__108_ccff_tail ) , + .chanx_left_out ( cbx_1__1__108_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__108_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7268 ) , + .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[108] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[108] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7269 ) , + .pReset_W_in ( pResetWires[539] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7270 ) , + .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7271 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7272 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7273 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7274 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7275 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7276 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7277 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7278 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7283 ) ) ; +cbx_1__1_ cbx_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7284 } ) , + .chanx_left_in ( sb_1__1__98_chanx_right_out ) , + .chanx_right_in ( sb_1__1__109_chanx_left_out ) , + .ccff_head ( sb_1__1__109_ccff_tail ) , + .chanx_left_out ( cbx_1__1__109_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__109_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7285 ) , + .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[109] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[109] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7286 ) , + .pReset_W_in ( pResetWires[588] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7287 ) , + .pReset_S_out ( pResetWires[590] ) , .pReset_E_out ( pResetWires[589] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[400] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7288 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7289 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7290 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7291 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7292 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7293 ) , + .clk_1_W_in ( clk_1_wires[204] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7294 ) , + .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7295 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7296 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7297 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7298 ) ) ; +cbx_1__1_ cbx_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7299 } ) , + .chanx_left_in ( sb_1__1__99_chanx_right_out ) , + .chanx_right_in ( sb_1__1__110_chanx_left_out ) , + .ccff_head ( sb_1__1__110_ccff_tail ) , + .chanx_left_out ( cbx_1__1__110_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__110_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7300 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[110] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[110] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7301 ) , + .pReset_W_in ( pResetWires[102] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7302 ) , + .pReset_S_out ( pResetWires[104] ) , .pReset_E_out ( pResetWires[103] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[408] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7303 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7304 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7305 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7306 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7307 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7308 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7309 ) , + .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7310 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7311 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7312 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7313 ) ) ; +cbx_1__1_ cbx_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7314 } ) , + .chanx_left_in ( sb_1__1__100_chanx_right_out ) , + .chanx_right_in ( sb_1__1__111_chanx_left_out ) , + .ccff_head ( sb_1__1__111_ccff_tail ) , + .chanx_left_out ( cbx_1__1__111_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__111_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7315 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[111] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[111] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7316 ) , + .pReset_W_in ( pResetWires[151] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7317 ) , + .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7318 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7319 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7320 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7321 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7322 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7323 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7325 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7326 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7327 ) , + .clk_2_W_in ( clk_2_wires[114] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7328 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7329 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7330 ) ) ; +cbx_1__1_ cbx_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7331 } ) , + .chanx_left_in ( sb_1__1__101_chanx_right_out ) , + .chanx_right_in ( sb_1__1__112_chanx_left_out ) , + .ccff_head ( sb_1__1__112_ccff_tail ) , + .chanx_left_out ( cbx_1__1__112_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__112_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7332 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[112] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[112] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7333 ) , + .pReset_W_in ( pResetWires[200] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7334 ) , + .pReset_S_out ( pResetWires[202] ) , .pReset_E_out ( pResetWires[201] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[414] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7335 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7336 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7337 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7338 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7339 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7340 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7341 ) , + .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7342 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7343 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7345 ) ) ; +cbx_1__1_ cbx_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7346 } ) , + .chanx_left_in ( sb_1__1__102_chanx_right_out ) , + .chanx_right_in ( sb_1__1__113_chanx_left_out ) , + .ccff_head ( sb_1__1__113_ccff_tail ) , + .chanx_left_out ( cbx_1__1__113_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__113_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7347 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[113] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[113] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7348 ) , + .pReset_W_in ( pResetWires[249] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7349 ) , + .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7350 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7351 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7352 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7353 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7354 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7355 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7356 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7357 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7358 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7359 ) , + .clk_2_W_in ( clk_2_wires[119] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7360 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7361 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7362 ) ) ; +cbx_1__1_ cbx_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7363 } ) , + .chanx_left_in ( sb_1__1__103_chanx_right_out ) , + .chanx_right_in ( sb_1__1__114_chanx_left_out ) , + .ccff_head ( sb_1__1__114_ccff_tail ) , + .chanx_left_out ( cbx_1__1__114_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__114_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7364 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[114] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[114] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7365 ) , + .pReset_W_in ( pResetWires[298] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7366 ) , + .pReset_S_out ( pResetWires[300] ) , .pReset_E_out ( pResetWires[299] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[420] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7367 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7368 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7369 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7370 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7371 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7372 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7373 ) , + .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7374 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7375 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7377 ) ) ; +cbx_1__1_ cbx_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7378 } ) , + .chanx_left_in ( sb_1__1__104_chanx_right_out ) , + .chanx_right_in ( sb_1__1__115_chanx_left_out ) , + .ccff_head ( sb_1__1__115_ccff_tail ) , + .chanx_left_out ( cbx_1__1__115_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__115_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7379 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[115] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[115] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7380 ) , + .pReset_W_in ( pResetWires[347] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7381 ) , + .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7382 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7383 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7384 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7385 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7386 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7387 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7388 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7389 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7393 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7394 ) ) ; +cbx_1__1_ cbx_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7395 } ) , + .chanx_left_in ( sb_1__1__105_chanx_right_out ) , + .chanx_right_in ( sb_1__1__116_chanx_left_out ) , + .ccff_head ( sb_1__1__116_ccff_tail ) , + .chanx_left_out ( cbx_1__1__116_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__116_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7396 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[116] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[116] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7397 ) , + .pReset_W_in ( pResetWires[396] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7398 ) , + .pReset_S_out ( pResetWires[398] ) , .pReset_E_out ( pResetWires[397] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[426] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7399 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7400 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7401 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7402 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7403 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7404 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7405 ) , + .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7407 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7408 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7409 ) ) ; +cbx_1__1_ cbx_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7410 } ) , + .chanx_left_in ( sb_1__1__106_chanx_right_out ) , + .chanx_right_in ( sb_1__1__117_chanx_left_out ) , + .ccff_head ( sb_1__1__117_ccff_tail ) , + .chanx_left_out ( cbx_1__1__117_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__117_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7411 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[117] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[117] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7412 ) , + .pReset_W_in ( pResetWires[445] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7413 ) , + .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7414 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7415 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7416 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7417 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7418 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7419 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7420 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7421 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7422 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7423 ) , + .clk_2_W_in ( clk_2_wires[126] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7424 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7425 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7426 ) ) ; +cbx_1__1_ cbx_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7427 } ) , + .chanx_left_in ( sb_1__1__107_chanx_right_out ) , + .chanx_right_in ( sb_1__1__118_chanx_left_out ) , + .ccff_head ( sb_1__1__118_ccff_tail ) , + .chanx_left_out ( cbx_1__1__118_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__118_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7428 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[118] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[118] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7429 ) , + .pReset_W_in ( pResetWires[494] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7430 ) , + .pReset_S_out ( pResetWires[496] ) , .pReset_E_out ( pResetWires[495] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[432] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7431 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7432 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7433 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7434 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7436 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7437 ) , + .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7438 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7439 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7440 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7441 ) ) ; +cbx_1__1_ cbx_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7442 } ) , + .chanx_left_in ( sb_1__1__108_chanx_right_out ) , + .chanx_right_in ( sb_1__1__119_chanx_left_out ) , + .ccff_head ( sb_1__1__119_ccff_tail ) , + .chanx_left_out ( cbx_1__1__119_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__119_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7443 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[119] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[119] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7444 ) , + .pReset_W_in ( pResetWires[543] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7445 ) , + .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7446 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7447 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7448 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7449 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7450 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7451 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7453 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7454 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7455 ) , + .clk_2_W_in ( clk_2_wires[133] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7456 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7457 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7458 ) ) ; +cbx_1__1_ cbx_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7459 } ) , + .chanx_left_in ( sb_1__1__109_chanx_right_out ) , + .chanx_right_in ( sb_1__1__120_chanx_left_out ) , + .ccff_head ( sb_1__1__120_ccff_tail ) , + .chanx_left_out ( cbx_1__1__120_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__120_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7460 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[120] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[120] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7461 ) , + .pReset_W_in ( pResetWires[592] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7462 ) , + .pReset_S_out ( pResetWires[594] ) , .pReset_E_out ( pResetWires[593] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[438] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7463 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7464 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7465 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7466 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7467 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7468 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7469 ) , + .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7470 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7471 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7472 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7473 ) ) ; +cbx_1__1_ cbx_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7474 } ) , + .chanx_left_in ( sb_1__1__110_chanx_right_out ) , + .chanx_right_in ( sb_12__1__0_chanx_left_out ) , + .ccff_head ( sb_12__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__121_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__121_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7475 ) , + .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[121] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[121] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7476 ) , + .pReset_W_in ( pResetWires[106] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7477 ) , + .pReset_S_out ( pResetWires[108] ) , .pReset_E_out ( pResetWires[107] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[446] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7478 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7479 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7480 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7481 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7482 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7483 ) , + .clk_1_W_in ( clk_1_wires[211] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7484 ) , + .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7485 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7487 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7488 ) ) ; +cbx_1__1_ cbx_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7489 } ) , + .chanx_left_in ( sb_1__1__111_chanx_right_out ) , + .chanx_right_in ( sb_12__1__1_chanx_left_out ) , + .ccff_head ( sb_12__1__1_ccff_tail ) , + .chanx_left_out ( cbx_1__1__122_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__122_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7490 ) , + .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[122] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[122] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7491 ) , + .pReset_W_in ( pResetWires[155] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7492 ) , + .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7493 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7494 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7495 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7496 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7497 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7498 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7499 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7500 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7502 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7504 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7505 ) ) ; +cbx_1__1_ cbx_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7506 } ) , + .chanx_left_in ( sb_1__1__112_chanx_right_out ) , + .chanx_right_in ( sb_12__1__2_chanx_left_out ) , + .ccff_head ( sb_12__1__2_ccff_tail ) , + .chanx_left_out ( cbx_1__1__123_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__123_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7507 ) , + .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[123] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[123] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7508 ) , + .pReset_W_in ( pResetWires[204] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7509 ) , + .pReset_S_out ( pResetWires[206] ) , .pReset_E_out ( pResetWires[205] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[452] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7510 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7511 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7512 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7513 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7514 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7515 ) , + .clk_1_W_in ( clk_1_wires[218] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7516 ) , + .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7518 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7519 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7520 ) ) ; +cbx_1__1_ cbx_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7521 } ) , + .chanx_left_in ( sb_1__1__113_chanx_right_out ) , + .chanx_right_in ( sb_12__1__3_chanx_left_out ) , + .ccff_head ( sb_12__1__3_ccff_tail ) , + .chanx_left_out ( cbx_1__1__124_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__124_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7522 ) , + .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[124] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[124] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7523 ) , + .pReset_W_in ( pResetWires[253] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7524 ) , + .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7525 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7526 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7527 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7528 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7529 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7530 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7531 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7532 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7537 ) ) ; +cbx_1__1_ cbx_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7538 } ) , + .chanx_left_in ( sb_1__1__114_chanx_right_out ) , + .chanx_right_in ( sb_12__1__4_chanx_left_out ) , + .ccff_head ( sb_12__1__4_ccff_tail ) , + .chanx_left_out ( cbx_1__1__125_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__125_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7539 ) , + .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[125] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[125] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7540 ) , + .pReset_W_in ( pResetWires[302] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7541 ) , + .pReset_S_out ( pResetWires[304] ) , .pReset_E_out ( pResetWires[303] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[458] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7542 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7543 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7544 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7545 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7546 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7547 ) , + .clk_1_W_in ( clk_1_wires[225] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7548 ) , + .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7549 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7551 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7552 ) ) ; +cbx_1__1_ cbx_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7553 } ) , + .chanx_left_in ( sb_1__1__115_chanx_right_out ) , + .chanx_right_in ( sb_12__1__5_chanx_left_out ) , + .ccff_head ( sb_12__1__5_ccff_tail ) , + .chanx_left_out ( cbx_1__1__126_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__126_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7554 ) , + .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[126] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[126] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7555 ) , + .pReset_W_in ( pResetWires[351] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7556 ) , + .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7557 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7558 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7559 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7560 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7561 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7562 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7563 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7564 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7568 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7569 ) ) ; +cbx_1__1_ cbx_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7570 } ) , + .chanx_left_in ( sb_1__1__116_chanx_right_out ) , + .chanx_right_in ( sb_12__1__6_chanx_left_out ) , + .ccff_head ( sb_12__1__6_ccff_tail ) , + .chanx_left_out ( cbx_1__1__127_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__127_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7571 ) , + .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[127] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[127] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7572 ) , + .pReset_W_in ( pResetWires[400] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7573 ) , + .pReset_S_out ( pResetWires[402] ) , .pReset_E_out ( pResetWires[401] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[464] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7574 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7575 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7576 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7577 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7578 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7579 ) , + .clk_1_W_in ( clk_1_wires[232] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7580 ) , + .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7582 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7583 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7584 ) ) ; +cbx_1__1_ cbx_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7585 } ) , + .chanx_left_in ( sb_1__1__117_chanx_right_out ) , + .chanx_right_in ( sb_12__1__7_chanx_left_out ) , + .ccff_head ( sb_12__1__7_ccff_tail ) , + .chanx_left_out ( cbx_1__1__128_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__128_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7586 ) , + .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[128] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[128] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7587 ) , + .pReset_W_in ( pResetWires[449] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7588 ) , + .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7589 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7590 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7591 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7592 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7593 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7594 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7595 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7596 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7601 ) ) ; +cbx_1__1_ cbx_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7602 } ) , + .chanx_left_in ( sb_1__1__118_chanx_right_out ) , + .chanx_right_in ( sb_12__1__8_chanx_left_out ) , + .ccff_head ( sb_12__1__8_ccff_tail ) , + .chanx_left_out ( cbx_1__1__129_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__129_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7603 ) , + .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[129] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[129] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7604 ) , + .pReset_W_in ( pResetWires[498] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7605 ) , + .pReset_S_out ( pResetWires[500] ) , .pReset_E_out ( pResetWires[499] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[470] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7606 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7607 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7608 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7609 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7610 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7611 ) , + .clk_1_W_in ( clk_1_wires[239] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7612 ) , + .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7613 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7615 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7616 ) ) ; +cbx_1__1_ cbx_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7617 } ) , + .chanx_left_in ( sb_1__1__119_chanx_right_out ) , + .chanx_right_in ( sb_12__1__9_chanx_left_out ) , + .ccff_head ( sb_12__1__9_ccff_tail ) , + .chanx_left_out ( cbx_1__1__130_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__130_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7618 ) , + .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[130] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[130] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7619 ) , + .pReset_W_in ( pResetWires[547] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7620 ) , + .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7621 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7622 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7623 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7624 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7625 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7626 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7627 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7628 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7632 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7633 ) ) ; +cbx_1__1_ cbx_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7634 } ) , + .chanx_left_in ( sb_1__1__120_chanx_right_out ) , + .chanx_right_in ( sb_12__1__10_chanx_left_out ) , + .ccff_head ( sb_12__1__10_ccff_tail ) , + .chanx_left_out ( cbx_1__1__131_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__131_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7635 ) , + .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[131] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[131] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7636 ) , + .pReset_W_in ( pResetWires[596] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7637 ) , + .pReset_S_out ( pResetWires[598] ) , .pReset_E_out ( pResetWires[597] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[476] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7638 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7639 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7640 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7641 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7642 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7643 ) , + .clk_1_W_in ( clk_1_wires[246] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7644 ) , + .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7645 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7646 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7647 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7648 ) ) ; +cbx_1__2_ cbx_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7649 } ) , + .chanx_left_in ( sb_0__12__0_chanx_right_out ) , + .chanx_right_in ( sb_1__12__0_chanx_left_out ) , + .ccff_head ( sb_1__12__0_ccff_tail ) , + .chanx_left_out ( cbx_1__12__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__0_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7650 ) , + .pReset_E_in ( pResetWires[601] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7651 ) , + .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7652 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[59] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ; +cbx_1__2_ cbx_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7653 } ) , + .chanx_left_in ( sb_1__12__0_chanx_right_out ) , + .chanx_right_in ( sb_1__12__1_chanx_left_out ) , + .ccff_head ( sb_1__12__1_ccff_tail ) , + .chanx_left_out ( cbx_1__12__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__1_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7654 ) , + .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , + .pReset_E_in ( pResetWires[605] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7655 ) , + .pReset_W_out ( pResetWires[604] ) , .pReset_S_out ( pResetWires[606] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7656 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[99] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7657 ) ) ; +cbx_1__2_ cbx_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7658 } ) , + .chanx_left_in ( sb_1__12__1_chanx_right_out ) , + .chanx_right_in ( sb_1__12__2_chanx_left_out ) , + .ccff_head ( sb_1__12__2_ccff_tail ) , + .chanx_left_out ( cbx_1__12__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__2_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7659 ) , + .pReset_E_in ( pResetWires[608] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7660 ) , + .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7661 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[137] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7662 ) ) ; +cbx_1__2_ cbx_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7663 } ) , + .chanx_left_in ( sb_1__12__2_chanx_right_out ) , + .chanx_right_in ( sb_1__12__3_chanx_left_out ) , + .ccff_head ( sb_1__12__3_ccff_tail ) , + .chanx_left_out ( cbx_1__12__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__3_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7664 ) , + .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , + .pReset_E_in ( pResetWires[611] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7665 ) , + .pReset_W_out ( pResetWires[610] ) , .pReset_S_out ( pResetWires[612] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7666 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[175] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7667 ) ) ; +cbx_1__2_ cbx_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7668 } ) , + .chanx_left_in ( sb_1__12__3_chanx_right_out ) , + .chanx_right_in ( sb_1__12__4_chanx_left_out ) , + .ccff_head ( sb_1__12__4_ccff_tail ) , + .chanx_left_out ( cbx_1__12__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__4_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7669 ) , + .pReset_E_in ( pResetWires[614] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7670 ) , + .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7671 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[213] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7672 ) ) ; +cbx_1__2_ cbx_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7673 } ) , + .chanx_left_in ( sb_1__12__4_chanx_right_out ) , + .chanx_right_in ( sb_1__12__5_chanx_left_out ) , + .ccff_head ( sb_1__12__5_ccff_tail ) , + .chanx_left_out ( cbx_1__12__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__5_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7674 ) , + .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , + .pReset_E_in ( pResetWires[617] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7675 ) , + .pReset_W_out ( pResetWires[616] ) , .pReset_S_out ( pResetWires[618] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7676 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[251] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7677 ) ) ; +cbx_1__2_ cbx_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7678 } ) , + .chanx_left_in ( sb_1__12__5_chanx_right_out ) , + .chanx_right_in ( sb_1__12__6_chanx_left_out ) , + .ccff_head ( sb_1__12__6_ccff_tail ) , + .chanx_left_out ( cbx_1__12__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__6_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7679 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7680 ) , + .pReset_W_in ( pResetWires[619] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7681 ) , + .pReset_S_out ( pResetWires[621] ) , .pReset_E_out ( pResetWires[620] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[289] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7682 ) ) ; +cbx_1__2_ cbx_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7683 } ) , + .chanx_left_in ( sb_1__12__6_chanx_right_out ) , + .chanx_right_in ( sb_1__12__7_chanx_left_out ) , + .ccff_head ( sb_1__12__7_ccff_tail ) , + .chanx_left_out ( cbx_1__12__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__7_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7684 ) , + .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7685 ) , + .pReset_W_in ( pResetWires[622] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7686 ) , + .pReset_S_out ( pResetWires[624] ) , .pReset_E_out ( pResetWires[623] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[327] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7687 ) ) ; +cbx_1__2_ cbx_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7688 } ) , + .chanx_left_in ( sb_1__12__7_chanx_right_out ) , + .chanx_right_in ( sb_1__12__8_chanx_left_out ) , + .ccff_head ( sb_1__12__8_ccff_tail ) , + .chanx_left_out ( cbx_1__12__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__8_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7689 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7690 ) , + .pReset_W_in ( pResetWires[625] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7691 ) , + .pReset_S_out ( pResetWires[627] ) , .pReset_E_out ( pResetWires[626] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[365] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7692 ) ) ; +cbx_1__2_ cbx_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7693 } ) , + .chanx_left_in ( sb_1__12__8_chanx_right_out ) , + .chanx_right_in ( sb_1__12__9_chanx_left_out ) , + .ccff_head ( sb_1__12__9_ccff_tail ) , + .chanx_left_out ( cbx_1__12__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__9_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7694 ) , + .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7695 ) , + .pReset_W_in ( pResetWires[628] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7696 ) , + .pReset_S_out ( pResetWires[630] ) , .pReset_E_out ( pResetWires[629] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[403] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7697 ) ) ; +cbx_1__2_ cbx_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7698 } ) , + .chanx_left_in ( sb_1__12__9_chanx_right_out ) , + .chanx_right_in ( sb_1__12__10_chanx_left_out ) , + .ccff_head ( sb_1__12__10_ccff_tail ) , + .chanx_left_out ( cbx_1__12__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__10_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7699 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7700 ) , + .pReset_W_in ( pResetWires[631] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7701 ) , + .pReset_S_out ( pResetWires[633] ) , .pReset_E_out ( pResetWires[632] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[441] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7702 ) ) ; +cbx_1__2_ cbx_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7703 } ) , + .chanx_left_in ( sb_1__12__10_chanx_right_out ) , + .chanx_right_in ( sb_12__12__0_chanx_left_out ) , + .ccff_head ( sb_12__12__0_ccff_tail ) , + .chanx_left_out ( cbx_1__12__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__11_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7704 ) , + .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7705 ) , + .pReset_W_in ( pResetWires[634] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7706 ) , + .pReset_S_out ( pResetWires[636] ) , .pReset_E_out ( pResetWires[635] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[479] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7707 ) ) ; +cby_0__1_ cby_0__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7708 } ) , + .chany_bottom_in ( sb_0__0__0_chany_top_out ) , + .chany_top_in ( sb_0__1__0_chany_bottom_out ) , + .ccff_head ( sb_0__1__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , + .chany_top_out ( cby_0__1__0_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[64] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[3] ) ) ; +cby_0__1_ cby_0__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7709 } ) , + .chany_bottom_in ( sb_0__1__0_chany_top_out ) , + .chany_top_in ( sb_0__1__1_chany_bottom_out ) , + .ccff_head ( sb_0__1__1_ccff_tail ) , + .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , + .chany_top_out ( cby_0__1__1_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[113] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[9] ) ) ; +cby_0__1_ cby_0__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7710 } ) , + .chany_bottom_in ( sb_0__1__1_chany_top_out ) , + .chany_top_in ( sb_0__1__2_chany_bottom_out ) , + .ccff_head ( sb_0__1__2_ccff_tail ) , + .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) , + .chany_top_out ( cby_0__1__2_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[162] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[14] ) ) ; +cby_0__1_ cby_0__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7711 } ) , + .chany_bottom_in ( sb_0__1__2_chany_top_out ) , + .chany_top_in ( sb_0__1__3_chany_bottom_out ) , + .ccff_head ( sb_0__1__3_ccff_tail ) , + .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) , + .chany_top_out ( cby_0__1__3_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[211] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[19] ) ) ; +cby_0__1_ cby_0__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7712 } ) , + .chany_bottom_in ( sb_0__1__3_chany_top_out ) , + .chany_top_in ( sb_0__1__4_chany_bottom_out ) , + .ccff_head ( sb_0__1__4_ccff_tail ) , + .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) , + .chany_top_out ( cby_0__1__4_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[260] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[24] ) ) ; +cby_0__1_ cby_0__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7713 } ) , + .chany_bottom_in ( sb_0__1__4_chany_top_out ) , + .chany_top_in ( sb_0__1__5_chany_bottom_out ) , + .ccff_head ( sb_0__1__5_ccff_tail ) , + .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) , + .chany_top_out ( cby_0__1__5_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[309] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[29] ) ) ; +cby_0__1_ cby_0__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7714 } ) , + .chany_bottom_in ( sb_0__1__5_chany_top_out ) , + .chany_top_in ( sb_0__1__6_chany_bottom_out ) , + .ccff_head ( sb_0__1__6_ccff_tail ) , + .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) , + .chany_top_out ( cby_0__1__6_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[358] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[34] ) ) ; +cby_0__1_ cby_0__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7715 } ) , + .chany_bottom_in ( sb_0__1__6_chany_top_out ) , + .chany_top_in ( sb_0__1__7_chany_bottom_out ) , + .ccff_head ( sb_0__1__7_ccff_tail ) , + .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) , + .chany_top_out ( cby_0__1__7_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[407] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[39] ) ) ; +cby_0__1_ cby_0__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7716 } ) , + .chany_bottom_in ( sb_0__1__7_chany_top_out ) , + .chany_top_in ( sb_0__1__8_chany_bottom_out ) , + .ccff_head ( sb_0__1__8_ccff_tail ) , + .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) , + .chany_top_out ( cby_0__1__8_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[456] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[44] ) ) ; +cby_0__1_ cby_0__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7717 } ) , + .chany_bottom_in ( sb_0__1__8_chany_top_out ) , + .chany_top_in ( sb_0__1__9_chany_bottom_out ) , + .ccff_head ( sb_0__1__9_ccff_tail ) , + .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) , + .chany_top_out ( cby_0__1__9_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[505] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[49] ) ) ; +cby_0__1_ cby_0__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7718 } ) , + .chany_bottom_in ( sb_0__1__9_chany_top_out ) , + .chany_top_in ( sb_0__1__10_chany_bottom_out ) , + .ccff_head ( sb_0__1__10_ccff_tail ) , + .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) , + .chany_top_out ( cby_0__1__10_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[554] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[54] ) ) ; +cby_0__1_ cby_0__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7719 } ) , + .chany_bottom_in ( sb_0__1__10_chany_top_out ) , + .chany_top_in ( sb_0__12__0_chany_bottom_out ) , + .ccff_head ( sb_0__12__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) , + .chany_top_out ( cby_0__1__11_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[603] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[61] ) ) ; +cby_1__1_ cby_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7720 } ) , + .chany_bottom_in ( sb_1__0__0_chany_top_out ) , + .chany_top_in ( sb_1__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_0_ccff_tail ) , + .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , + .chany_top_out ( cby_1__1__0_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7721 ) , + .Test_en_E_in ( Test_enWires[26] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7722 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7723 ) , + .Test_en_W_out ( Test_enWires[24] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7724 ) , + .pReset_S_in ( pResetWires[27] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7725 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7726 ) , + .Reset_E_in ( ResetWires[26] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7727 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7728 ) , + .Reset_W_out ( ResetWires[24] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7729 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7730 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7731 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7732 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7733 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7734 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7735 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7737 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7738 ) ) ; +cby_1__1_ cby_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7739 } ) , + .chany_bottom_in ( sb_1__1__0_chany_top_out ) , + .chany_top_in ( sb_1__1__1_chany_bottom_out ) , + .ccff_head ( grid_clb_1_ccff_tail ) , + .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , + .chany_top_out ( cby_1__1__1_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7740 ) , + .Test_en_E_in ( Test_enWires[48] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7741 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7742 ) , + .Test_en_W_out ( Test_enWires[46] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7743 ) , + .pReset_S_in ( pResetWires[65] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7744 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7745 ) , + .Reset_E_in ( ResetWires[48] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7746 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7747 ) , + .Reset_W_out ( ResetWires[46] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7748 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[7] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[8] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7749 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[3] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7750 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7751 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7752 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7753 ) , + .clk_2_N_in ( clk_2_wires[3] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7754 ) , + .clk_2_S_out ( clk_2_wires[4] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7755 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7756 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7757 ) ) ; +cby_1__1_ cby_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7758 } ) , + .chany_bottom_in ( sb_1__1__1_chany_top_out ) , + .chany_top_in ( sb_1__1__2_chany_bottom_out ) , + .ccff_head ( grid_clb_2_ccff_tail ) , + .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , + .chany_top_out ( cby_1__1__2_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__2_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7759 ) , + .Test_en_E_in ( Test_enWires[70] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7760 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7761 ) , + .Test_en_W_out ( Test_enWires[68] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7762 ) , + .pReset_S_in ( pResetWires[114] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7763 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7764 ) , + .Reset_E_in ( ResetWires[70] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7765 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7766 ) , + .Reset_W_out ( ResetWires[68] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7767 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7768 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7769 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7770 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7771 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7772 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7773 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7775 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7776 ) ) ; +cby_1__1_ cby_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7777 } ) , + .chany_bottom_in ( sb_1__1__2_chany_top_out ) , + .chany_top_in ( sb_1__1__3_chany_bottom_out ) , + .ccff_head ( grid_clb_3_ccff_tail ) , + .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , + .chany_top_out ( cby_1__1__3_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__3_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7778 ) , + .Test_en_E_in ( Test_enWires[92] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7779 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7780 ) , + .Test_en_W_out ( Test_enWires[90] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7781 ) , + .pReset_S_in ( pResetWires[163] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7782 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7783 ) , + .Reset_E_in ( ResetWires[92] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7784 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7785 ) , + .Reset_W_out ( ResetWires[90] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7786 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[17] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[18] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7787 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[10] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7788 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7789 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7790 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7791 ) , + .clk_2_N_in ( clk_2_wires[10] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7792 ) , + .clk_2_S_out ( clk_2_wires[11] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7793 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7794 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7795 ) ) ; +cby_1__1_ cby_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7796 } ) , + .chany_bottom_in ( sb_1__1__3_chany_top_out ) , + .chany_top_in ( sb_1__1__4_chany_bottom_out ) , + .ccff_head ( grid_clb_4_ccff_tail ) , + .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) , + .chany_top_out ( cby_1__1__4_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__4_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7797 ) , + .Test_en_E_in ( Test_enWires[114] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7798 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7799 ) , + .Test_en_W_out ( Test_enWires[112] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7800 ) , + .pReset_S_in ( pResetWires[212] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7801 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7802 ) , + .Reset_E_in ( ResetWires[114] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7803 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7804 ) , + .Reset_W_out ( ResetWires[112] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7805 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[22] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[23] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7806 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7807 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7808 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7809 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7810 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7811 ) , + .clk_2_S_in ( clk_2_wires[8] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7812 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7813 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7814 ) ) ; +cby_1__1_ cby_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7815 } ) , + .chany_bottom_in ( sb_1__1__4_chany_top_out ) , + .chany_top_in ( sb_1__1__5_chany_bottom_out ) , + .ccff_head ( grid_clb_5_ccff_tail ) , + .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) , + .chany_top_out ( cby_1__1__5_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__5_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7816 ) , + .Test_en_E_in ( Test_enWires[136] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7817 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7818 ) , + .Test_en_W_out ( Test_enWires[134] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7819 ) , + .pReset_S_in ( pResetWires[261] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7820 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7821 ) , + .Reset_E_in ( ResetWires[136] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7822 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7823 ) , + .Reset_W_out ( ResetWires[134] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7824 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7825 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7826 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7827 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7828 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7829 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7830 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7832 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7833 ) ) ; +cby_1__1_ cby_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7834 } ) , + .chany_bottom_in ( sb_1__1__5_chany_top_out ) , + .chany_top_in ( sb_1__1__6_chany_bottom_out ) , + .ccff_head ( grid_clb_6_ccff_tail ) , + .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) , + .chany_top_out ( cby_1__1__6_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__6_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7835 ) , + .Test_en_E_in ( Test_enWires[158] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7836 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7837 ) , + .Test_en_W_out ( Test_enWires[156] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7838 ) , + .pReset_S_in ( pResetWires[310] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7839 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7840 ) , + .Reset_E_in ( ResetWires[158] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7841 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7842 ) , + .Reset_W_out ( ResetWires[156] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7843 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7844 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7845 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7846 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7847 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7848 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7849 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7851 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7852 ) ) ; +cby_1__1_ cby_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7853 } ) , + .chany_bottom_in ( sb_1__1__6_chany_top_out ) , + .chany_top_in ( sb_1__1__7_chany_bottom_out ) , + .ccff_head ( grid_clb_7_ccff_tail ) , + .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) , + .chany_top_out ( cby_1__1__7_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__7_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7854 ) , + .Test_en_E_in ( Test_enWires[180] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7855 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7856 ) , + .Test_en_W_out ( Test_enWires[178] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7857 ) , + .pReset_S_in ( pResetWires[359] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7858 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7859 ) , + .Reset_E_in ( ResetWires[180] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7860 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7861 ) , + .Reset_W_out ( ResetWires[178] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7862 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[37] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[38] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7863 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[17] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7864 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7865 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7866 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7867 ) , + .clk_2_N_in ( clk_2_wires[17] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7868 ) , + .clk_2_S_out ( clk_2_wires[18] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7869 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7870 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7871 ) ) ; +cby_1__1_ cby_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7872 } ) , + .chany_bottom_in ( sb_1__1__7_chany_top_out ) , + .chany_top_in ( sb_1__1__8_chany_bottom_out ) , + .ccff_head ( grid_clb_8_ccff_tail ) , + .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) , + .chany_top_out ( cby_1__1__8_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__8_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7873 ) , + .Test_en_E_in ( Test_enWires[202] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7874 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7875 ) , + .Test_en_W_out ( Test_enWires[200] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7876 ) , + .pReset_S_in ( pResetWires[408] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7877 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7878 ) , + .Reset_E_in ( ResetWires[202] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7879 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7880 ) , + .Reset_W_out ( ResetWires[200] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7881 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[42] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[43] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7882 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7883 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7884 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7885 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7886 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7887 ) , + .clk_2_S_in ( clk_2_wires[15] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7888 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7889 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7890 ) ) ; +cby_1__1_ cby_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7891 } ) , + .chany_bottom_in ( sb_1__1__8_chany_top_out ) , + .chany_top_in ( sb_1__1__9_chany_bottom_out ) , + .ccff_head ( grid_clb_9_ccff_tail ) , + .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) , + .chany_top_out ( cby_1__1__9_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__9_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7892 ) , + .Test_en_E_in ( Test_enWires[224] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7893 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7894 ) , + .Test_en_W_out ( Test_enWires[222] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7895 ) , + .pReset_S_in ( pResetWires[457] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7896 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7897 ) , + .Reset_E_in ( ResetWires[224] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7898 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7899 ) , + .Reset_W_out ( ResetWires[222] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7900 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7901 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7902 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7903 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7904 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7905 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7906 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7908 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7909 ) ) ; +cby_1__1_ cby_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7910 } ) , + .chany_bottom_in ( sb_1__1__9_chany_top_out ) , + .chany_top_in ( sb_1__1__10_chany_bottom_out ) , + .ccff_head ( grid_clb_10_ccff_tail ) , + .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) , + .chany_top_out ( cby_1__1__10_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__10_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7911 ) , + .Test_en_E_in ( Test_enWires[246] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7912 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7913 ) , + .Test_en_W_out ( Test_enWires[244] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7914 ) , + .pReset_S_in ( pResetWires[506] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7915 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7916 ) , + .Reset_E_in ( ResetWires[246] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7917 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7918 ) , + .Reset_W_out ( ResetWires[244] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7919 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[52] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[53] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7920 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7921 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7922 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7924 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7925 ) , + .clk_2_S_in ( clk_2_wires[22] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7926 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7927 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7928 ) ) ; +cby_1__1_ cby_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7929 } ) , + .chany_bottom_in ( sb_1__1__10_chany_top_out ) , + .chany_top_in ( sb_1__12__0_chany_bottom_out ) , + .ccff_head ( grid_clb_11_ccff_tail ) , + .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) , + .chany_top_out ( cby_1__1__11_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__11_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7930 ) , + .Test_en_E_in ( Test_enWires[268] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7931 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7932 ) , + .Test_en_W_out ( Test_enWires[266] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7933 ) , + .pReset_S_in ( pResetWires[555] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7934 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7935 ) , + .Reset_E_in ( ResetWires[268] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7936 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7937 ) , + .Reset_W_out ( ResetWires[266] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7938 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7939 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7940 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7941 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7942 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7943 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7945 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7946 ) ) ; +cby_1__1_ cby_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7947 } ) , + .chany_bottom_in ( sb_1__0__1_chany_top_out ) , + .chany_top_in ( sb_1__1__11_chany_bottom_out ) , + .ccff_head ( grid_clb_12_ccff_tail ) , + .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) , + .chany_top_out ( cby_1__1__12_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__12_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7948 ) , + .Test_en_E_in ( Test_enWires[28] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7949 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7950 ) , + .Test_en_W_out ( Test_enWires[25] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7951 ) , + .pReset_S_in ( pResetWires[30] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7952 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7953 ) , + .Reset_E_in ( ResetWires[28] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7954 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7955 ) , + .Reset_W_out ( ResetWires[25] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7956 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7957 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7958 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7959 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7960 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7961 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7962 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7964 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7965 ) ) ; +cby_1__1_ cby_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7966 } ) , + .chany_bottom_in ( sb_1__1__11_chany_top_out ) , + .chany_top_in ( sb_1__1__12_chany_bottom_out ) , + .ccff_head ( grid_clb_13_ccff_tail ) , + .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) , + .chany_top_out ( cby_1__1__13_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__13_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7967 ) , + .Test_en_E_in ( Test_enWires[50] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7968 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7969 ) , + .Test_en_W_out ( Test_enWires[47] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7970 ) , + .pReset_S_in ( pResetWires[69] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7971 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7972 ) , + .Reset_E_in ( ResetWires[50] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7973 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7974 ) , + .Reset_W_out ( ResetWires[47] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7975 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7976 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7977 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7978 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7979 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7980 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7981 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7983 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7984 ) ) ; +cby_1__1_ cby_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7985 } ) , + .chany_bottom_in ( sb_1__1__12_chany_top_out ) , + .chany_top_in ( sb_1__1__13_chany_bottom_out ) , + .ccff_head ( grid_clb_14_ccff_tail ) , + .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) , + .chany_top_out ( cby_1__1__14_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__14_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7986 ) , + .Test_en_E_in ( Test_enWires[72] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7987 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7988 ) , + .Test_en_W_out ( Test_enWires[69] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7989 ) , + .pReset_S_in ( pResetWires[118] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7990 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7991 ) , + .Reset_E_in ( ResetWires[72] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7992 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7993 ) , + .Reset_W_out ( ResetWires[69] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7994 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7995 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7996 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7997 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7998 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7999 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8000 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8001 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8002 ) , + .clk_3_N_in ( clk_3_wires[68] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8003 ) , + .clk_3_S_out ( clk_3_wires[69] ) ) ; +cby_1__1_ cby_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8004 } ) , + .chany_bottom_in ( sb_1__1__13_chany_top_out ) , + .chany_top_in ( sb_1__1__14_chany_bottom_out ) , + .ccff_head ( grid_clb_15_ccff_tail ) , + .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) , + .chany_top_out ( cby_1__1__15_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__15_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8005 ) , + .Test_en_E_in ( Test_enWires[94] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8006 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8007 ) , + .Test_en_W_out ( Test_enWires[91] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8008 ) , + .pReset_S_in ( pResetWires[167] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8009 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8010 ) , + .Reset_E_in ( ResetWires[94] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8011 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8012 ) , + .Reset_W_out ( ResetWires[91] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8013 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8014 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8015 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8016 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8017 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8018 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8019 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8020 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8021 ) , + .clk_3_N_in ( clk_3_wires[64] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8022 ) , + .clk_3_S_out ( clk_3_wires[65] ) ) ; +cby_1__1_ cby_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8023 } ) , + .chany_bottom_in ( sb_1__1__14_chany_top_out ) , + .chany_top_in ( sb_1__1__15_chany_bottom_out ) , + .ccff_head ( grid_clb_16_ccff_tail ) , + .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) , + .chany_top_out ( cby_1__1__16_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__16_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8024 ) , + .Test_en_E_in ( Test_enWires[116] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8025 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8026 ) , + .Test_en_W_out ( Test_enWires[113] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8027 ) , + .pReset_S_in ( pResetWires[216] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8028 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8029 ) , + .Reset_E_in ( ResetWires[116] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8030 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8031 ) , + .Reset_W_out ( ResetWires[113] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8032 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8033 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8034 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8035 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8036 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8037 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8038 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8039 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8040 ) , + .clk_3_N_in ( clk_3_wires[58] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8041 ) , + .clk_3_S_out ( clk_3_wires[59] ) ) ; +cby_1__1_ cby_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8042 } ) , + .chany_bottom_in ( sb_1__1__15_chany_top_out ) , + .chany_top_in ( sb_1__1__16_chany_bottom_out ) , + .ccff_head ( grid_clb_17_ccff_tail ) , + .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) , + .chany_top_out ( cby_1__1__17_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__17_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8043 ) , + .Test_en_E_in ( Test_enWires[138] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8044 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8045 ) , + .Test_en_W_out ( Test_enWires[135] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8046 ) , + .pReset_S_in ( pResetWires[265] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8047 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8048 ) , + .Reset_E_in ( ResetWires[138] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8049 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8050 ) , + .Reset_W_out ( ResetWires[135] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8051 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8052 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8053 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8054 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8055 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8056 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8057 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8058 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8059 ) , + .clk_3_N_in ( clk_3_wires[54] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8060 ) , + .clk_3_S_out ( clk_3_wires[55] ) ) ; +cby_1__1_ cby_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8061 } ) , + .chany_bottom_in ( sb_1__1__16_chany_top_out ) , + .chany_top_in ( sb_1__1__17_chany_bottom_out ) , + .ccff_head ( grid_clb_18_ccff_tail ) , + .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) , + .chany_top_out ( cby_1__1__18_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__18_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8062 ) , + .Test_en_E_in ( Test_enWires[160] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8063 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8064 ) , + .Test_en_W_out ( Test_enWires[157] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8065 ) , + .pReset_S_in ( pResetWires[314] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8066 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8067 ) , + .Reset_E_in ( ResetWires[160] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8068 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8069 ) , + .Reset_W_out ( ResetWires[157] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8070 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8071 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8072 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8073 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8074 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8075 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8076 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8077 ) , + .clk_3_S_in ( clk_3_wires[52] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8078 ) , + .clk_3_N_out ( clk_3_wires[53] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8079 ) ) ; +cby_1__1_ cby_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8080 } ) , + .chany_bottom_in ( sb_1__1__17_chany_top_out ) , + .chany_top_in ( sb_1__1__18_chany_bottom_out ) , + .ccff_head ( grid_clb_19_ccff_tail ) , + .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) , + .chany_top_out ( cby_1__1__19_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__19_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8081 ) , + .Test_en_E_in ( Test_enWires[182] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8082 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8083 ) , + .Test_en_W_out ( Test_enWires[179] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8084 ) , + .pReset_S_in ( pResetWires[363] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8085 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8086 ) , + .Reset_E_in ( ResetWires[182] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8087 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8088 ) , + .Reset_W_out ( ResetWires[179] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8089 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8090 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8091 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8092 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8093 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8094 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8095 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8096 ) , + .clk_3_S_in ( clk_3_wires[56] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8097 ) , + .clk_3_N_out ( clk_3_wires[57] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8098 ) ) ; +cby_1__1_ cby_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8099 } ) , + .chany_bottom_in ( sb_1__1__18_chany_top_out ) , + .chany_top_in ( sb_1__1__19_chany_bottom_out ) , + .ccff_head ( grid_clb_20_ccff_tail ) , + .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) , + .chany_top_out ( cby_1__1__20_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__20_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8100 ) , + .Test_en_E_in ( Test_enWires[204] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8101 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8102 ) , + .Test_en_W_out ( Test_enWires[201] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8103 ) , + .pReset_S_in ( pResetWires[412] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8104 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8105 ) , + .Reset_E_in ( ResetWires[204] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8106 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8107 ) , + .Reset_W_out ( ResetWires[201] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8108 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8109 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8110 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8111 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8112 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8113 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8114 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8115 ) , + .clk_3_S_in ( clk_3_wires[62] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8116 ) , + .clk_3_N_out ( clk_3_wires[63] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8117 ) ) ; +cby_1__1_ cby_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8118 } ) , + .chany_bottom_in ( sb_1__1__19_chany_top_out ) , + .chany_top_in ( sb_1__1__20_chany_bottom_out ) , + .ccff_head ( grid_clb_21_ccff_tail ) , + .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) , + .chany_top_out ( cby_1__1__21_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__21_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8119 ) , + .Test_en_E_in ( Test_enWires[226] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8120 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8121 ) , + .Test_en_W_out ( Test_enWires[223] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8122 ) , + .pReset_S_in ( pResetWires[461] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8123 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8124 ) , + .Reset_E_in ( ResetWires[226] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8125 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8126 ) , + .Reset_W_out ( ResetWires[223] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8127 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8128 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8129 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8130 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8131 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8132 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8133 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8134 ) , + .clk_3_S_in ( clk_3_wires[66] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8135 ) , + .clk_3_N_out ( clk_3_wires[67] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8136 ) ) ; +cby_1__1_ cby_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8137 } ) , + .chany_bottom_in ( sb_1__1__20_chany_top_out ) , + .chany_top_in ( sb_1__1__21_chany_bottom_out ) , + .ccff_head ( grid_clb_22_ccff_tail ) , + .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) , + .chany_top_out ( cby_1__1__22_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__22_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8138 ) , + .Test_en_E_in ( Test_enWires[248] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8139 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8140 ) , + .Test_en_W_out ( Test_enWires[245] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8141 ) , + .pReset_S_in ( pResetWires[510] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8142 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8143 ) , + .Reset_E_in ( ResetWires[248] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8144 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8145 ) , + .Reset_W_out ( ResetWires[245] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8146 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8147 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8148 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8150 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8151 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8152 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8155 ) ) ; +cby_1__1_ cby_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8156 } ) , + .chany_bottom_in ( sb_1__1__21_chany_top_out ) , + .chany_top_in ( sb_1__12__1_chany_bottom_out ) , + .ccff_head ( grid_clb_23_ccff_tail ) , + .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) , + .chany_top_out ( cby_1__1__23_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__23_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8157 ) , + .Test_en_E_in ( Test_enWires[270] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8158 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8159 ) , + .Test_en_W_out ( Test_enWires[267] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8160 ) , + .pReset_S_in ( pResetWires[559] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8161 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8162 ) , + .Reset_E_in ( ResetWires[270] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8163 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8164 ) , + .Reset_W_out ( ResetWires[267] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8165 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8166 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8167 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8168 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8169 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8170 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8172 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8173 ) ) ; +cby_1__1_ cby_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8174 } ) , + .chany_bottom_in ( sb_1__0__2_chany_top_out ) , + .chany_top_in ( sb_1__1__22_chany_bottom_out ) , + .ccff_head ( grid_clb_24_ccff_tail ) , + .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) , + .chany_top_out ( cby_1__1__24_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__24_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8175 ) , + .Test_en_E_in ( Test_enWires[30] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8176 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8177 ) , + .Test_en_W_out ( Test_enWires[27] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8178 ) , + .pReset_S_in ( pResetWires[33] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8179 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8180 ) , + .Reset_E_in ( ResetWires[30] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8181 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8182 ) , + .Reset_W_out ( ResetWires[27] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8183 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8184 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8185 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8186 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8187 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8188 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8189 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8192 ) ) ; +cby_1__1_ cby_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8193 } ) , + .chany_bottom_in ( sb_1__1__22_chany_top_out ) , + .chany_top_in ( sb_1__1__23_chany_bottom_out ) , + .ccff_head ( grid_clb_25_ccff_tail ) , + .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) , + .chany_top_out ( cby_1__1__25_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__25_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8194 ) , + .Test_en_E_in ( Test_enWires[52] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8195 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8196 ) , + .Test_en_W_out ( Test_enWires[49] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8197 ) , + .pReset_S_in ( pResetWires[73] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8198 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8199 ) , + .Reset_E_in ( ResetWires[52] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8200 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8201 ) , + .Reset_W_out ( ResetWires[49] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8202 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[105] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[106] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8203 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[29] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8204 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8205 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8206 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8207 ) , + .clk_2_N_in ( clk_2_wires[29] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8208 ) , + .clk_2_S_out ( clk_2_wires[30] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8209 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8210 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8211 ) ) ; +cby_1__1_ cby_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8212 } ) , + .chany_bottom_in ( sb_1__1__23_chany_top_out ) , + .chany_top_in ( sb_1__1__24_chany_bottom_out ) , + .ccff_head ( grid_clb_26_ccff_tail ) , + .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) , + .chany_top_out ( cby_1__1__26_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__26_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8213 ) , + .Test_en_E_in ( Test_enWires[74] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8214 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8215 ) , + .Test_en_W_out ( Test_enWires[71] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8216 ) , + .pReset_S_in ( pResetWires[122] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8217 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8218 ) , + .Reset_E_in ( ResetWires[74] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8219 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8220 ) , + .Reset_W_out ( ResetWires[71] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8221 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8222 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8223 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8224 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8225 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8226 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8227 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8229 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8230 ) ) ; +cby_1__1_ cby_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8231 } ) , + .chany_bottom_in ( sb_1__1__24_chany_top_out ) , + .chany_top_in ( sb_1__1__25_chany_bottom_out ) , + .ccff_head ( grid_clb_27_ccff_tail ) , + .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) , + .chany_top_out ( cby_1__1__27_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__27_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8232 ) , + .Test_en_E_in ( Test_enWires[96] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8233 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8234 ) , + .Test_en_W_out ( Test_enWires[93] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8235 ) , + .pReset_S_in ( pResetWires[171] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8236 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8237 ) , + .Reset_E_in ( ResetWires[96] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8238 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8239 ) , + .Reset_W_out ( ResetWires[93] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8240 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[111] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[112] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8241 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[40] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8242 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8243 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8244 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8245 ) , + .clk_2_N_in ( clk_2_wires[40] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8246 ) , + .clk_2_S_out ( clk_2_wires[41] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8247 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8248 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8249 ) ) ; +cby_1__1_ cby_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8250 } ) , + .chany_bottom_in ( sb_1__1__25_chany_top_out ) , + .chany_top_in ( sb_1__1__26_chany_bottom_out ) , + .ccff_head ( grid_clb_28_ccff_tail ) , + .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) , + .chany_top_out ( cby_1__1__28_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__28_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8251 ) , + .Test_en_E_in ( Test_enWires[118] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8252 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8253 ) , + .Test_en_W_out ( Test_enWires[115] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8254 ) , + .pReset_S_in ( pResetWires[220] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8255 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8256 ) , + .Reset_E_in ( ResetWires[118] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8257 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8258 ) , + .Reset_W_out ( ResetWires[115] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8259 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[114] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[115] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8260 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8261 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8262 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8263 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8264 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8265 ) , + .clk_2_S_in ( clk_2_wires[38] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8266 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8267 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8268 ) ) ; +cby_1__1_ cby_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8269 } ) , + .chany_bottom_in ( sb_1__1__26_chany_top_out ) , + .chany_top_in ( sb_1__1__27_chany_bottom_out ) , + .ccff_head ( grid_clb_29_ccff_tail ) , + .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) , + .chany_top_out ( cby_1__1__29_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__29_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8270 ) , + .Test_en_E_in ( Test_enWires[140] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8271 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8272 ) , + .Test_en_W_out ( Test_enWires[137] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8273 ) , + .pReset_S_in ( pResetWires[269] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8274 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8275 ) , + .Reset_E_in ( ResetWires[140] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8276 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8277 ) , + .Reset_W_out ( ResetWires[137] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8278 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8279 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8280 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8281 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8282 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8283 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8284 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8286 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8287 ) ) ; +cby_1__1_ cby_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8288 } ) , + .chany_bottom_in ( sb_1__1__27_chany_top_out ) , + .chany_top_in ( sb_1__1__28_chany_bottom_out ) , + .ccff_head ( grid_clb_30_ccff_tail ) , + .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) , + .chany_top_out ( cby_1__1__30_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__30_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8289 ) , + .Test_en_E_in ( Test_enWires[162] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8290 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8291 ) , + .Test_en_W_out ( Test_enWires[159] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8292 ) , + .pReset_S_in ( pResetWires[318] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8293 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8294 ) , + .Reset_E_in ( ResetWires[162] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8295 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8296 ) , + .Reset_W_out ( ResetWires[159] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8297 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8298 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8299 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8300 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8301 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8302 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8303 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8305 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8306 ) ) ; +cby_1__1_ cby_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8307 } ) , + .chany_bottom_in ( sb_1__1__28_chany_top_out ) , + .chany_top_in ( sb_1__1__29_chany_bottom_out ) , + .ccff_head ( grid_clb_31_ccff_tail ) , + .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) , + .chany_top_out ( cby_1__1__31_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__31_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8308 ) , + .Test_en_E_in ( Test_enWires[184] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8309 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8310 ) , + .Test_en_W_out ( Test_enWires[181] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8311 ) , + .pReset_S_in ( pResetWires[367] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8312 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8313 ) , + .Reset_E_in ( ResetWires[184] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8314 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8315 ) , + .Reset_W_out ( ResetWires[181] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8316 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[123] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[124] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8317 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[53] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8318 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8319 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8320 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8321 ) , + .clk_2_N_in ( clk_2_wires[53] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8322 ) , + .clk_2_S_out ( clk_2_wires[54] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8323 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8324 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8325 ) ) ; +cby_1__1_ cby_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8326 } ) , + .chany_bottom_in ( sb_1__1__29_chany_top_out ) , + .chany_top_in ( sb_1__1__30_chany_bottom_out ) , + .ccff_head ( grid_clb_32_ccff_tail ) , + .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) , + .chany_top_out ( cby_1__1__32_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__32_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8327 ) , + .Test_en_E_in ( Test_enWires[206] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8328 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8329 ) , + .Test_en_W_out ( Test_enWires[203] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8330 ) , + .pReset_S_in ( pResetWires[416] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8331 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8332 ) , + .Reset_E_in ( ResetWires[206] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8333 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8334 ) , + .Reset_W_out ( ResetWires[203] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8335 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[126] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[127] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8336 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8337 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8338 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8339 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8340 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8341 ) , + .clk_2_S_in ( clk_2_wires[51] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8342 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8343 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8344 ) ) ; +cby_1__1_ cby_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8345 } ) , + .chany_bottom_in ( sb_1__1__30_chany_top_out ) , + .chany_top_in ( sb_1__1__31_chany_bottom_out ) , + .ccff_head ( grid_clb_33_ccff_tail ) , + .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) , + .chany_top_out ( cby_1__1__33_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__33_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8346 ) , + .Test_en_E_in ( Test_enWires[228] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8347 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8348 ) , + .Test_en_W_out ( Test_enWires[225] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8349 ) , + .pReset_S_in ( pResetWires[465] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8350 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8351 ) , + .Reset_E_in ( ResetWires[228] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8352 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8353 ) , + .Reset_W_out ( ResetWires[225] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8354 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8355 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8356 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8357 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8358 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8359 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8360 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8362 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8363 ) ) ; +cby_1__1_ cby_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8364 } ) , + .chany_bottom_in ( sb_1__1__31_chany_top_out ) , + .chany_top_in ( sb_1__1__32_chany_bottom_out ) , + .ccff_head ( grid_clb_34_ccff_tail ) , + .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) , + .chany_top_out ( cby_1__1__34_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__34_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8365 ) , + .Test_en_E_in ( Test_enWires[250] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8366 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8367 ) , + .Test_en_W_out ( Test_enWires[247] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8368 ) , + .pReset_S_in ( pResetWires[514] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8369 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8370 ) , + .Reset_E_in ( ResetWires[250] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8371 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8372 ) , + .Reset_W_out ( ResetWires[247] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8373 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[132] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[133] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8374 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8375 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8376 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8377 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8378 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8379 ) , + .clk_2_S_in ( clk_2_wires[64] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8380 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8381 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8382 ) ) ; +cby_1__1_ cby_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8383 } ) , + .chany_bottom_in ( sb_1__1__32_chany_top_out ) , + .chany_top_in ( sb_1__12__2_chany_bottom_out ) , + .ccff_head ( grid_clb_35_ccff_tail ) , + .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) , + .chany_top_out ( cby_1__1__35_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__35_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8384 ) , + .Test_en_E_in ( Test_enWires[272] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8385 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8386 ) , + .Test_en_W_out ( Test_enWires[269] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8387 ) , + .pReset_S_in ( pResetWires[563] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8388 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8389 ) , + .Reset_E_in ( ResetWires[272] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8390 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8391 ) , + .Reset_W_out ( ResetWires[269] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8392 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8393 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8394 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8395 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8396 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8397 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8399 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8400 ) ) ; +cby_1__1_ cby_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8401 } ) , + .chany_bottom_in ( sb_1__0__3_chany_top_out ) , + .chany_top_in ( sb_1__1__33_chany_bottom_out ) , + .ccff_head ( grid_clb_36_ccff_tail ) , + .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) , + .chany_top_out ( cby_1__1__36_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__36_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8402 ) , + .Test_en_E_in ( Test_enWires[32] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8403 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8404 ) , + .Test_en_W_out ( Test_enWires[29] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8405 ) , + .pReset_S_in ( pResetWires[36] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8406 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8407 ) , + .Reset_E_in ( ResetWires[32] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8408 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8409 ) , + .Reset_W_out ( ResetWires[29] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8410 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8411 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8412 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8413 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8414 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8415 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8416 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8419 ) ) ; +cby_1__1_ cby_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8420 } ) , + .chany_bottom_in ( sb_1__1__33_chany_top_out ) , + .chany_top_in ( sb_1__1__34_chany_bottom_out ) , + .ccff_head ( grid_clb_37_ccff_tail ) , + .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) , + .chany_top_out ( cby_1__1__37_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__37_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8421 ) , + .Test_en_E_in ( Test_enWires[54] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8422 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8423 ) , + .Test_en_W_out ( Test_enWires[51] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8424 ) , + .pReset_S_in ( pResetWires[77] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8425 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8426 ) , + .Reset_E_in ( ResetWires[54] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8427 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8428 ) , + .Reset_W_out ( ResetWires[51] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8429 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8430 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8431 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8433 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8434 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8435 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8437 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8438 ) ) ; +cby_1__1_ cby_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8439 } ) , + .chany_bottom_in ( sb_1__1__34_chany_top_out ) , + .chany_top_in ( sb_1__1__35_chany_bottom_out ) , + .ccff_head ( grid_clb_38_ccff_tail ) , + .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) , + .chany_top_out ( cby_1__1__38_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__38_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8440 ) , + .Test_en_E_in ( Test_enWires[76] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8441 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8442 ) , + .Test_en_W_out ( Test_enWires[73] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8443 ) , + .pReset_S_in ( pResetWires[126] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8444 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8445 ) , + .Reset_E_in ( ResetWires[76] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8446 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8447 ) , + .Reset_W_out ( ResetWires[73] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8448 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8449 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8450 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8451 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8452 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8453 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8454 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8455 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8456 ) , + .clk_3_N_in ( clk_3_wires[24] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8457 ) , + .clk_3_S_out ( clk_3_wires[25] ) ) ; +cby_1__1_ cby_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8458 } ) , + .chany_bottom_in ( sb_1__1__35_chany_top_out ) , + .chany_top_in ( sb_1__1__36_chany_bottom_out ) , + .ccff_head ( grid_clb_39_ccff_tail ) , + .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) , + .chany_top_out ( cby_1__1__39_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__39_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8459 ) , + .Test_en_E_in ( Test_enWires[98] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8460 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8461 ) , + .Test_en_W_out ( Test_enWires[95] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8462 ) , + .pReset_S_in ( pResetWires[175] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8463 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8464 ) , + .Reset_E_in ( ResetWires[98] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8465 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8466 ) , + .Reset_W_out ( ResetWires[95] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8467 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8468 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8469 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8470 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8471 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8472 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8473 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8474 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8475 ) , + .clk_3_N_in ( clk_3_wires[20] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8476 ) , + .clk_3_S_out ( clk_3_wires[21] ) ) ; +cby_1__1_ cby_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8477 } ) , + .chany_bottom_in ( sb_1__1__36_chany_top_out ) , + .chany_top_in ( sb_1__1__37_chany_bottom_out ) , + .ccff_head ( grid_clb_40_ccff_tail ) , + .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) , + .chany_top_out ( cby_1__1__40_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__40_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8478 ) , + .Test_en_E_in ( Test_enWires[120] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8479 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8480 ) , + .Test_en_W_out ( Test_enWires[117] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8481 ) , + .pReset_S_in ( pResetWires[224] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8482 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8483 ) , + .Reset_E_in ( ResetWires[120] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8484 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8485 ) , + .Reset_W_out ( ResetWires[117] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8486 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8487 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8488 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8489 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8490 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8491 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8492 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8493 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8494 ) , + .clk_3_N_in ( clk_3_wires[14] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8495 ) , + .clk_3_S_out ( clk_3_wires[15] ) ) ; +cby_1__1_ cby_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8496 } ) , + .chany_bottom_in ( sb_1__1__37_chany_top_out ) , + .chany_top_in ( sb_1__1__38_chany_bottom_out ) , + .ccff_head ( grid_clb_41_ccff_tail ) , + .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) , + .chany_top_out ( cby_1__1__41_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__41_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8497 ) , + .Test_en_E_in ( Test_enWires[142] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8498 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8499 ) , + .Test_en_W_out ( Test_enWires[139] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8500 ) , + .pReset_S_in ( pResetWires[273] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8501 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8502 ) , + .Reset_E_in ( ResetWires[142] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8503 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8504 ) , + .Reset_W_out ( ResetWires[139] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8505 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8506 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8507 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8508 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8509 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8510 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8511 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8512 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8513 ) , + .clk_3_N_in ( clk_3_wires[10] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8514 ) , + .clk_3_S_out ( clk_3_wires[11] ) ) ; +cby_1__1_ cby_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8515 } ) , + .chany_bottom_in ( sb_1__1__38_chany_top_out ) , + .chany_top_in ( sb_1__1__39_chany_bottom_out ) , + .ccff_head ( grid_clb_42_ccff_tail ) , + .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) , + .chany_top_out ( cby_1__1__42_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__42_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8516 ) , + .Test_en_E_in ( Test_enWires[164] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8517 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8518 ) , + .Test_en_W_out ( Test_enWires[161] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8519 ) , + .pReset_S_in ( pResetWires[322] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8520 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8521 ) , + .Reset_E_in ( ResetWires[164] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8522 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8523 ) , + .Reset_W_out ( ResetWires[161] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8524 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8525 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8526 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8527 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8528 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8529 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8530 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8531 ) , + .clk_3_S_in ( clk_3_wires[8] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8532 ) , + .clk_3_N_out ( clk_3_wires[9] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8533 ) ) ; +cby_1__1_ cby_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8534 } ) , + .chany_bottom_in ( sb_1__1__39_chany_top_out ) , + .chany_top_in ( sb_1__1__40_chany_bottom_out ) , + .ccff_head ( grid_clb_43_ccff_tail ) , + .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) , + .chany_top_out ( cby_1__1__43_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__43_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8535 ) , + .Test_en_E_in ( Test_enWires[186] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8536 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8537 ) , + .Test_en_W_out ( Test_enWires[183] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8538 ) , + .pReset_S_in ( pResetWires[371] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8539 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8540 ) , + .Reset_E_in ( ResetWires[186] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8541 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8542 ) , + .Reset_W_out ( ResetWires[183] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8543 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8544 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8545 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8546 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8547 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8548 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8549 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8550 ) , + .clk_3_S_in ( clk_3_wires[12] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8551 ) , + .clk_3_N_out ( clk_3_wires[13] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8552 ) ) ; +cby_1__1_ cby_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8553 } ) , + .chany_bottom_in ( sb_1__1__40_chany_top_out ) , + .chany_top_in ( sb_1__1__41_chany_bottom_out ) , + .ccff_head ( grid_clb_44_ccff_tail ) , + .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) , + .chany_top_out ( cby_1__1__44_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__44_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8554 ) , + .Test_en_E_in ( Test_enWires[208] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8555 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8556 ) , + .Test_en_W_out ( Test_enWires[205] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8557 ) , + .pReset_S_in ( pResetWires[420] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8558 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8559 ) , + .Reset_E_in ( ResetWires[208] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8560 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8561 ) , + .Reset_W_out ( ResetWires[205] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8562 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8563 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8564 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8565 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8566 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8567 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8568 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8569 ) , + .clk_3_S_in ( clk_3_wires[18] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8570 ) , + .clk_3_N_out ( clk_3_wires[19] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8571 ) ) ; +cby_1__1_ cby_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8572 } ) , + .chany_bottom_in ( sb_1__1__41_chany_top_out ) , + .chany_top_in ( sb_1__1__42_chany_bottom_out ) , + .ccff_head ( grid_clb_45_ccff_tail ) , + .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) , + .chany_top_out ( cby_1__1__45_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__45_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8573 ) , + .Test_en_E_in ( Test_enWires[230] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8574 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8575 ) , + .Test_en_W_out ( Test_enWires[227] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8576 ) , + .pReset_S_in ( pResetWires[469] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8577 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8578 ) , + .Reset_E_in ( ResetWires[230] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8579 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8580 ) , + .Reset_W_out ( ResetWires[227] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8581 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8582 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8583 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8584 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8585 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8586 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8587 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8588 ) , + .clk_3_S_in ( clk_3_wires[22] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8589 ) , + .clk_3_N_out ( clk_3_wires[23] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8590 ) ) ; +cby_1__1_ cby_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8591 } ) , + .chany_bottom_in ( sb_1__1__42_chany_top_out ) , + .chany_top_in ( sb_1__1__43_chany_bottom_out ) , + .ccff_head ( grid_clb_46_ccff_tail ) , + .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) , + .chany_top_out ( cby_1__1__46_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__46_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8592 ) , + .Test_en_E_in ( Test_enWires[252] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8593 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8594 ) , + .Test_en_W_out ( Test_enWires[249] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8595 ) , + .pReset_S_in ( pResetWires[518] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8596 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8597 ) , + .Reset_E_in ( ResetWires[252] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8598 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8599 ) , + .Reset_W_out ( ResetWires[249] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8600 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8601 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8602 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8604 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8605 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8606 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8608 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8609 ) ) ; +cby_1__1_ cby_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8610 } ) , + .chany_bottom_in ( sb_1__1__43_chany_top_out ) , + .chany_top_in ( sb_1__12__3_chany_bottom_out ) , + .ccff_head ( grid_clb_47_ccff_tail ) , + .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) , + .chany_top_out ( cby_1__1__47_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__47_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8611 ) , + .Test_en_E_in ( Test_enWires[274] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8612 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8613 ) , + .Test_en_W_out ( Test_enWires[271] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8614 ) , + .pReset_S_in ( pResetWires[567] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8615 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8616 ) , + .Reset_E_in ( ResetWires[274] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8617 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8618 ) , + .Reset_W_out ( ResetWires[271] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8619 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8620 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8621 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8622 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8623 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8624 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8626 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8627 ) ) ; +cby_1__1_ cby_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8628 } ) , + .chany_bottom_in ( sb_1__0__4_chany_top_out ) , + .chany_top_in ( sb_1__1__44_chany_bottom_out ) , + .ccff_head ( grid_clb_48_ccff_tail ) , + .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) , + .chany_top_out ( cby_1__1__48_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__48_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8629 ) , + .Test_en_E_in ( Test_enWires[34] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8630 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8631 ) , + .Test_en_W_out ( Test_enWires[31] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8632 ) , + .pReset_S_in ( pResetWires[39] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8633 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8634 ) , + .Reset_E_in ( ResetWires[34] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8635 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8636 ) , + .Reset_W_out ( ResetWires[31] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8637 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8638 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8639 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8640 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8641 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8642 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8643 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8645 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8646 ) ) ; +cby_1__1_ cby_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8647 } ) , + .chany_bottom_in ( sb_1__1__44_chany_top_out ) , + .chany_top_in ( sb_1__1__45_chany_bottom_out ) , + .ccff_head ( grid_clb_49_ccff_tail ) , + .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) , + .chany_top_out ( cby_1__1__49_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__49_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8648 ) , + .Test_en_E_in ( Test_enWires[56] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8649 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8650 ) , + .Test_en_W_out ( Test_enWires[53] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8651 ) , + .pReset_S_in ( pResetWires[81] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8652 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8653 ) , + .Reset_E_in ( ResetWires[56] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8654 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8655 ) , + .Reset_W_out ( ResetWires[53] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8656 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[181] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[182] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8657 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[31] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8658 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8659 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8660 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8661 ) , + .clk_2_N_in ( clk_2_wires[31] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8662 ) , + .clk_2_S_out ( clk_2_wires[32] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8663 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8664 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8665 ) ) ; +cby_1__1_ cby_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8666 } ) , + .chany_bottom_in ( sb_1__1__45_chany_top_out ) , + .chany_top_in ( sb_1__1__46_chany_bottom_out ) , + .ccff_head ( grid_clb_50_ccff_tail ) , + .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) , + .chany_top_out ( cby_1__1__50_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__50_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8667 ) , + .Test_en_E_in ( Test_enWires[78] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8668 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8669 ) , + .Test_en_W_out ( Test_enWires[75] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8670 ) , + .pReset_S_in ( pResetWires[130] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8671 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8672 ) , + .Reset_E_in ( ResetWires[78] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8673 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8674 ) , + .Reset_W_out ( ResetWires[75] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8675 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8676 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8677 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8678 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8679 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8680 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8681 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8683 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8684 ) ) ; +cby_1__1_ cby_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8685 } ) , + .chany_bottom_in ( sb_1__1__46_chany_top_out ) , + .chany_top_in ( sb_1__1__47_chany_bottom_out ) , + .ccff_head ( grid_clb_51_ccff_tail ) , + .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) , + .chany_top_out ( cby_1__1__51_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__51_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8686 ) , + .Test_en_E_in ( Test_enWires[100] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8687 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8688 ) , + .Test_en_W_out ( Test_enWires[97] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8689 ) , + .pReset_S_in ( pResetWires[179] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8690 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8691 ) , + .Reset_E_in ( ResetWires[100] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8692 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8693 ) , + .Reset_W_out ( ResetWires[97] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8694 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[187] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[188] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8695 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[44] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8696 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8697 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8698 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8699 ) , + .clk_2_N_in ( clk_2_wires[44] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8700 ) , + .clk_2_S_out ( clk_2_wires[45] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8701 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8702 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8703 ) ) ; +cby_1__1_ cby_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8704 } ) , + .chany_bottom_in ( sb_1__1__47_chany_top_out ) , + .chany_top_in ( sb_1__1__48_chany_bottom_out ) , + .ccff_head ( grid_clb_52_ccff_tail ) , + .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) , + .chany_top_out ( cby_1__1__52_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__52_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8705 ) , + .Test_en_E_in ( Test_enWires[122] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8706 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8707 ) , + .Test_en_W_out ( Test_enWires[119] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8708 ) , + .pReset_S_in ( pResetWires[228] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8709 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8710 ) , + .Reset_E_in ( ResetWires[122] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8711 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8712 ) , + .Reset_W_out ( ResetWires[119] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8713 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[190] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[191] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8714 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8715 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8716 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8717 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8718 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8719 ) , + .clk_2_S_in ( clk_2_wires[42] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8720 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8721 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8722 ) ) ; +cby_1__1_ cby_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8723 } ) , + .chany_bottom_in ( sb_1__1__48_chany_top_out ) , + .chany_top_in ( sb_1__1__49_chany_bottom_out ) , + .ccff_head ( grid_clb_53_ccff_tail ) , + .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) , + .chany_top_out ( cby_1__1__53_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__53_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8724 ) , + .Test_en_E_in ( Test_enWires[144] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8725 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8726 ) , + .Test_en_W_out ( Test_enWires[141] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8727 ) , + .pReset_S_in ( pResetWires[277] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8728 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8729 ) , + .Reset_E_in ( ResetWires[144] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8730 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8731 ) , + .Reset_W_out ( ResetWires[141] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8732 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8733 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8734 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8735 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8736 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8737 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8738 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8740 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8741 ) ) ; +cby_1__1_ cby_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8742 } ) , + .chany_bottom_in ( sb_1__1__49_chany_top_out ) , + .chany_top_in ( sb_1__1__50_chany_bottom_out ) , + .ccff_head ( grid_clb_54_ccff_tail ) , + .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) , + .chany_top_out ( cby_1__1__54_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__54_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8743 ) , + .Test_en_E_in ( Test_enWires[166] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8744 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8745 ) , + .Test_en_W_out ( Test_enWires[163] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8746 ) , + .pReset_S_in ( pResetWires[326] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8747 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8748 ) , + .Reset_E_in ( ResetWires[166] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8749 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8750 ) , + .Reset_W_out ( ResetWires[163] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8751 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8752 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8753 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8754 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8755 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8756 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8757 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8759 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8760 ) ) ; +cby_1__1_ cby_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8761 } ) , + .chany_bottom_in ( sb_1__1__50_chany_top_out ) , + .chany_top_in ( sb_1__1__51_chany_bottom_out ) , + .ccff_head ( grid_clb_55_ccff_tail ) , + .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) , + .chany_top_out ( cby_1__1__55_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__55_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8762 ) , + .Test_en_E_in ( Test_enWires[188] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8763 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8764 ) , + .Test_en_W_out ( Test_enWires[185] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8765 ) , + .pReset_S_in ( pResetWires[375] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8766 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8767 ) , + .Reset_E_in ( ResetWires[188] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8768 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8769 ) , + .Reset_W_out ( ResetWires[185] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8770 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[199] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[200] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8771 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[57] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8772 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8773 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8774 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8775 ) , + .clk_2_N_in ( clk_2_wires[57] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8776 ) , + .clk_2_S_out ( clk_2_wires[58] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8777 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8778 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8779 ) ) ; +cby_1__1_ cby_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8780 } ) , + .chany_bottom_in ( sb_1__1__51_chany_top_out ) , + .chany_top_in ( sb_1__1__52_chany_bottom_out ) , + .ccff_head ( grid_clb_56_ccff_tail ) , + .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) , + .chany_top_out ( cby_1__1__56_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__56_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8781 ) , + .Test_en_E_in ( Test_enWires[210] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8782 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8783 ) , + .Test_en_W_out ( Test_enWires[207] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8784 ) , + .pReset_S_in ( pResetWires[424] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8785 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8786 ) , + .Reset_E_in ( ResetWires[210] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8787 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8788 ) , + .Reset_W_out ( ResetWires[207] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8789 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[202] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[203] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8790 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8791 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8792 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8793 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8794 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8795 ) , + .clk_2_S_in ( clk_2_wires[55] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8796 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8797 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8798 ) ) ; +cby_1__1_ cby_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8799 } ) , + .chany_bottom_in ( sb_1__1__52_chany_top_out ) , + .chany_top_in ( sb_1__1__53_chany_bottom_out ) , + .ccff_head ( grid_clb_57_ccff_tail ) , + .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) , + .chany_top_out ( cby_1__1__57_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__57_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8800 ) , + .Test_en_E_in ( Test_enWires[232] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8801 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8802 ) , + .Test_en_W_out ( Test_enWires[229] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8803 ) , + .pReset_S_in ( pResetWires[473] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8804 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8805 ) , + .Reset_E_in ( ResetWires[232] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8806 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8807 ) , + .Reset_W_out ( ResetWires[229] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8808 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8809 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8810 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8811 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8812 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8813 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8814 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8816 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8817 ) ) ; +cby_1__1_ cby_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8818 } ) , + .chany_bottom_in ( sb_1__1__53_chany_top_out ) , + .chany_top_in ( sb_1__1__54_chany_bottom_out ) , + .ccff_head ( grid_clb_58_ccff_tail ) , + .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) , + .chany_top_out ( cby_1__1__58_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__58_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8819 ) , + .Test_en_E_in ( Test_enWires[254] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8820 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8821 ) , + .Test_en_W_out ( Test_enWires[251] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8822 ) , + .pReset_S_in ( pResetWires[522] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8823 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8824 ) , + .Reset_E_in ( ResetWires[254] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8825 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8826 ) , + .Reset_W_out ( ResetWires[251] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8827 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[208] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[209] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8828 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8829 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8830 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8831 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8832 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8833 ) , + .clk_2_S_in ( clk_2_wires[66] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8834 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8835 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8836 ) ) ; +cby_1__1_ cby_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8837 } ) , + .chany_bottom_in ( sb_1__1__54_chany_top_out ) , + .chany_top_in ( sb_1__12__4_chany_bottom_out ) , + .ccff_head ( grid_clb_59_ccff_tail ) , + .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) , + .chany_top_out ( cby_1__1__59_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__59_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8838 ) , + .Test_en_E_in ( Test_enWires[276] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8839 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8840 ) , + .Test_en_W_out ( Test_enWires[273] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8841 ) , + .pReset_S_in ( pResetWires[571] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8842 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8843 ) , + .Reset_E_in ( ResetWires[276] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8844 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8845 ) , + .Reset_W_out ( ResetWires[273] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8846 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8847 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8848 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8849 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8850 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8853 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8854 ) ) ; +cby_1__1_ cby_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8855 } ) , + .chany_bottom_in ( sb_1__0__5_chany_top_out ) , + .chany_top_in ( sb_1__1__55_chany_bottom_out ) , + .ccff_head ( grid_clb_60_ccff_tail ) , + .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) , + .chany_top_out ( cby_1__1__60_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__60_ccff_tail ) , + .Test_en_S_in ( Test_enWires[1] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8856 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8857 ) , + .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) , + .Test_en_E_out ( Test_enWires[35] ) , .pReset_S_in ( pResetWires[42] ) , + .pReset_N_out ( pResetWires[2] ) , .Reset_S_in ( ResetWires[1] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8858 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8859 ) , + .Reset_N_out ( ResetWires[2] ) , .Reset_W_out ( ResetWires[33] ) , + .Reset_E_out ( ResetWires[35] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8860 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8861 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8862 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8863 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8864 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8865 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8866 ) , + .clk_3_S_in ( clk_3_wires[90] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8867 ) , + .clk_3_N_out ( clk_3_wires[89] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8868 ) ) ; +cby_1__1_ cby_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8869 } ) , + .chany_bottom_in ( sb_1__1__55_chany_top_out ) , + .chany_top_in ( sb_1__1__56_chany_bottom_out ) , + .ccff_head ( grid_clb_61_ccff_tail ) , + .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) , + .chany_top_out ( cby_1__1__61_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__61_ccff_tail ) , + .Test_en_S_in ( Test_enWires[3] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8870 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8871 ) , + .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) , + .Test_en_E_out ( Test_enWires[57] ) , .pReset_S_in ( pResetWires[85] ) , + .pReset_N_out ( pResetWires[4] ) , .Reset_S_in ( ResetWires[3] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8872 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8873 ) , + .Reset_N_out ( ResetWires[4] ) , .Reset_W_out ( ResetWires[55] ) , + .Reset_E_out ( ResetWires[57] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8874 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8875 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8876 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8877 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8878 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8879 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8880 ) , + .clk_3_S_in ( clk_3_wires[92] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8881 ) , + .clk_3_N_out ( clk_3_wires[91] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8882 ) ) ; +cby_1__1_ cby_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8883 } ) , + .chany_bottom_in ( sb_1__1__56_chany_top_out ) , + .chany_top_in ( sb_1__1__57_chany_bottom_out ) , + .ccff_head ( grid_clb_62_ccff_tail ) , + .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) , + .chany_top_out ( cby_1__1__62_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__62_ccff_tail ) , + .Test_en_S_in ( Test_enWires[5] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8884 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8885 ) , + .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) , + .Test_en_E_out ( Test_enWires[79] ) , .pReset_S_in ( pResetWires[134] ) , + .pReset_N_out ( pResetWires[6] ) , .Reset_S_in ( ResetWires[5] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8886 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8887 ) , + .Reset_N_out ( ResetWires[6] ) , .Reset_W_out ( ResetWires[77] ) , + .Reset_E_out ( ResetWires[79] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8888 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8889 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8891 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8892 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8893 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8894 ) , + .clk_3_S_in ( clk_3_wires[94] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8895 ) , + .clk_3_N_out ( clk_3_wires[93] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8896 ) ) ; +cby_1__1_ cby_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8897 } ) , + .chany_bottom_in ( sb_1__1__57_chany_top_out ) , + .chany_top_in ( sb_1__1__58_chany_bottom_out ) , + .ccff_head ( grid_clb_63_ccff_tail ) , + .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) , + .chany_top_out ( cby_1__1__63_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__63_ccff_tail ) , + .Test_en_S_in ( Test_enWires[7] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8898 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8899 ) , + .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) , + .Test_en_E_out ( Test_enWires[101] ) , .pReset_S_in ( pResetWires[183] ) , + .pReset_N_out ( pResetWires[8] ) , .Reset_S_in ( ResetWires[7] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8900 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8901 ) , + .Reset_N_out ( ResetWires[8] ) , .Reset_W_out ( ResetWires[99] ) , + .Reset_E_out ( ResetWires[101] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8902 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8903 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8904 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8905 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8906 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8907 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8908 ) , + .clk_3_S_in ( clk_3_wires[96] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8909 ) , + .clk_3_N_out ( clk_3_wires[95] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8910 ) ) ; +cby_1__1_ cby_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8911 } ) , + .chany_bottom_in ( sb_1__1__58_chany_top_out ) , + .chany_top_in ( sb_1__1__59_chany_bottom_out ) , + .ccff_head ( grid_clb_64_ccff_tail ) , + .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) , + .chany_top_out ( cby_1__1__64_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__64_ccff_tail ) , + .Test_en_S_in ( Test_enWires[9] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8912 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8913 ) , + .Test_en_N_out ( Test_enWires[10] ) , + .Test_en_W_out ( Test_enWires[121] ) , + .Test_en_E_out ( Test_enWires[123] ) , .pReset_S_in ( pResetWires[232] ) , + .pReset_N_out ( pResetWires[10] ) , .Reset_S_in ( ResetWires[9] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8914 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8915 ) , + .Reset_N_out ( ResetWires[10] ) , .Reset_W_out ( ResetWires[121] ) , + .Reset_E_out ( ResetWires[123] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8916 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8917 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8918 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8919 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8920 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8921 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8922 ) , + .clk_3_S_in ( clk_3_wires[98] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8923 ) , + .clk_3_N_out ( clk_3_wires[97] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8924 ) ) ; +cby_1__1_ cby_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8925 } ) , + .chany_bottom_in ( sb_1__1__59_chany_top_out ) , + .chany_top_in ( sb_1__1__60_chany_bottom_out ) , + .ccff_head ( grid_clb_65_ccff_tail ) , + .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) , + .chany_top_out ( cby_1__1__65_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__65_ccff_tail ) , + .Test_en_S_in ( Test_enWires[11] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8926 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8927 ) , + .Test_en_N_out ( Test_enWires[12] ) , + .Test_en_W_out ( Test_enWires[143] ) , + .Test_en_E_out ( Test_enWires[145] ) , .pReset_S_in ( pResetWires[281] ) , + .pReset_N_out ( pResetWires[12] ) , .Reset_S_in ( ResetWires[11] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8928 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8929 ) , + .Reset_N_out ( ResetWires[12] ) , .Reset_W_out ( ResetWires[143] ) , + .Reset_E_out ( ResetWires[145] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8930 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8931 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8932 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8933 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8934 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8935 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8936 ) , + .clk_3_S_in ( clk_3_wires[100] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8937 ) , + .clk_3_N_out ( clk_3_wires[99] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8938 ) ) ; +cby_1__1_ cby_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8939 } ) , + .chany_bottom_in ( sb_1__1__60_chany_top_out ) , + .chany_top_in ( sb_1__1__61_chany_bottom_out ) , + .ccff_head ( grid_clb_66_ccff_tail ) , + .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) , + .chany_top_out ( cby_1__1__66_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__66_ccff_tail ) , + .Test_en_S_in ( Test_enWires[13] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8940 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8941 ) , + .Test_en_N_out ( Test_enWires[14] ) , + .Test_en_W_out ( Test_enWires[165] ) , + .Test_en_E_out ( Test_enWires[167] ) , .pReset_S_in ( pResetWires[330] ) , + .pReset_N_out ( pResetWires[14] ) , .Reset_S_in ( ResetWires[13] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8942 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8943 ) , + .Reset_N_out ( ResetWires[14] ) , .Reset_W_out ( ResetWires[165] ) , + .Reset_E_out ( ResetWires[167] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8944 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8945 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8946 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8947 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8948 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8949 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8951 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8952 ) ) ; +cby_1__1_ cby_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8953 } ) , + .chany_bottom_in ( sb_1__1__61_chany_top_out ) , + .chany_top_in ( sb_1__1__62_chany_bottom_out ) , + .ccff_head ( grid_clb_67_ccff_tail ) , + .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) , + .chany_top_out ( cby_1__1__67_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__67_ccff_tail ) , + .Test_en_S_in ( Test_enWires[15] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8954 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8955 ) , + .Test_en_N_out ( Test_enWires[16] ) , + .Test_en_W_out ( Test_enWires[187] ) , + .Test_en_E_out ( Test_enWires[189] ) , .pReset_S_in ( pResetWires[379] ) , + .pReset_N_out ( pResetWires[16] ) , .Reset_S_in ( ResetWires[15] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8956 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8957 ) , + .Reset_N_out ( ResetWires[16] ) , .Reset_W_out ( ResetWires[187] ) , + .Reset_E_out ( ResetWires[189] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8958 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8959 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8960 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8961 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8962 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8963 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8965 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8966 ) ) ; +cby_1__1_ cby_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8967 } ) , + .chany_bottom_in ( sb_1__1__62_chany_top_out ) , + .chany_top_in ( sb_1__1__63_chany_bottom_out ) , + .ccff_head ( grid_clb_68_ccff_tail ) , + .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) , + .chany_top_out ( cby_1__1__68_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__68_ccff_tail ) , + .Test_en_S_in ( Test_enWires[17] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8968 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8969 ) , + .Test_en_N_out ( Test_enWires[18] ) , + .Test_en_W_out ( Test_enWires[209] ) , + .Test_en_E_out ( Test_enWires[211] ) , .pReset_S_in ( pResetWires[428] ) , + .pReset_N_out ( pResetWires[18] ) , .Reset_S_in ( ResetWires[17] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8970 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8971 ) , + .Reset_N_out ( ResetWires[18] ) , .Reset_W_out ( ResetWires[209] ) , + .Reset_E_out ( ResetWires[211] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8972 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8973 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8974 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8975 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8976 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8977 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8979 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8980 ) ) ; +cby_1__1_ cby_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8981 } ) , + .chany_bottom_in ( sb_1__1__63_chany_top_out ) , + .chany_top_in ( sb_1__1__64_chany_bottom_out ) , + .ccff_head ( grid_clb_69_ccff_tail ) , + .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) , + .chany_top_out ( cby_1__1__69_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__69_ccff_tail ) , + .Test_en_S_in ( Test_enWires[19] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8982 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8983 ) , + .Test_en_N_out ( Test_enWires[20] ) , + .Test_en_W_out ( Test_enWires[231] ) , + .Test_en_E_out ( Test_enWires[233] ) , .pReset_S_in ( pResetWires[477] ) , + .pReset_N_out ( pResetWires[20] ) , .Reset_S_in ( ResetWires[19] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8984 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8985 ) , + .Reset_N_out ( ResetWires[20] ) , .Reset_W_out ( ResetWires[231] ) , + .Reset_E_out ( ResetWires[233] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8986 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8987 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8988 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8989 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8990 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8991 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8993 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8994 ) ) ; +cby_1__1_ cby_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8995 } ) , + .chany_bottom_in ( sb_1__1__64_chany_top_out ) , + .chany_top_in ( sb_1__1__65_chany_bottom_out ) , + .ccff_head ( grid_clb_70_ccff_tail ) , + .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) , + .chany_top_out ( cby_1__1__70_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__70_ccff_tail ) , + .Test_en_S_in ( Test_enWires[21] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8996 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8997 ) , + .Test_en_N_out ( Test_enWires[22] ) , + .Test_en_W_out ( Test_enWires[253] ) , + .Test_en_E_out ( Test_enWires[255] ) , .pReset_S_in ( pResetWires[526] ) , + .pReset_N_out ( pResetWires[22] ) , .Reset_S_in ( ResetWires[21] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8998 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8999 ) , + .Reset_N_out ( ResetWires[22] ) , .Reset_W_out ( ResetWires[253] ) , + .Reset_E_out ( ResetWires[255] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9000 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9001 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9002 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9003 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9004 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9005 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9007 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9008 ) ) ; +cby_1__1_ cby_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9009 } ) , + .chany_bottom_in ( sb_1__1__65_chany_top_out ) , + .chany_top_in ( sb_1__12__5_chany_bottom_out ) , + .ccff_head ( grid_clb_71_ccff_tail ) , + .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) , + .chany_top_out ( cby_1__1__71_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__71_ccff_tail ) , + .Test_en_S_in ( Test_enWires[23] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9010 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9011 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9012 ) , + .Test_en_W_out ( Test_enWires[275] ) , + .Test_en_E_out ( Test_enWires[277] ) , .pReset_S_in ( pResetWires[575] ) , + .pReset_N_out ( pResetWires[24] ) , .Reset_S_in ( ResetWires[23] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9013 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_9014 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9015 ) , + .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9016 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9017 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9018 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9019 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9020 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9022 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9023 ) ) ; +cby_1__1_ cby_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9024 } ) , + .chany_bottom_in ( sb_1__0__6_chany_top_out ) , + .chany_top_in ( sb_1__1__66_chany_bottom_out ) , + .ccff_head ( grid_clb_72_ccff_tail ) , + .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) , + .chany_top_out ( cby_1__1__72_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__72_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9025 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9026 ) , + .Test_en_W_in ( Test_enWires[36] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9027 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9028 ) , + .Test_en_E_out ( Test_enWires[37] ) , .pReset_S_in ( pResetWires[45] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9029 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9030 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9031 ) , + .Reset_W_in ( ResetWires[36] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9032 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9033 ) , + .Reset_E_out ( ResetWires[37] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9034 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9035 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9036 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9037 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9038 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9039 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9041 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9042 ) ) ; +cby_1__1_ cby_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9043 } ) , + .chany_bottom_in ( sb_1__1__66_chany_top_out ) , + .chany_top_in ( sb_1__1__67_chany_bottom_out ) , + .ccff_head ( grid_clb_73_ccff_tail ) , + .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) , + .chany_top_out ( cby_1__1__73_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__73_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9044 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9045 ) , + .Test_en_W_in ( Test_enWires[58] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9046 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9047 ) , + .Test_en_E_out ( Test_enWires[59] ) , .pReset_S_in ( pResetWires[89] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9048 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9049 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9050 ) , + .Reset_W_in ( ResetWires[58] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9051 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9052 ) , + .Reset_E_out ( ResetWires[59] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[257] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[258] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9053 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[73] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9054 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9055 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9056 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9057 ) , + .clk_2_N_in ( clk_2_wires[73] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9058 ) , + .clk_2_S_out ( clk_2_wires[74] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9059 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9060 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9061 ) ) ; +cby_1__1_ cby_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9062 } ) , + .chany_bottom_in ( sb_1__1__67_chany_top_out ) , + .chany_top_in ( sb_1__1__68_chany_bottom_out ) , + .ccff_head ( grid_clb_74_ccff_tail ) , + .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) , + .chany_top_out ( cby_1__1__74_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__74_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9063 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9064 ) , + .Test_en_W_in ( Test_enWires[80] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9065 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9066 ) , + .Test_en_E_out ( Test_enWires[81] ) , .pReset_S_in ( pResetWires[138] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9067 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9068 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9069 ) , + .Reset_W_in ( ResetWires[80] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9070 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9071 ) , + .Reset_E_out ( ResetWires[81] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9072 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9073 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9074 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9075 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9076 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9077 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9079 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9080 ) ) ; +cby_1__1_ cby_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9081 } ) , + .chany_bottom_in ( sb_1__1__68_chany_top_out ) , + .chany_top_in ( sb_1__1__69_chany_bottom_out ) , + .ccff_head ( grid_clb_75_ccff_tail ) , + .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) , + .chany_top_out ( cby_1__1__75_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__75_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9082 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9083 ) , + .Test_en_W_in ( Test_enWires[102] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9084 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9085 ) , + .Test_en_E_out ( Test_enWires[103] ) , .pReset_S_in ( pResetWires[187] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9086 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9087 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9088 ) , + .Reset_W_in ( ResetWires[102] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9089 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9090 ) , + .Reset_E_out ( ResetWires[103] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[263] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[264] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9091 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[84] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9092 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9093 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9094 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9095 ) , + .clk_2_N_in ( clk_2_wires[84] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9096 ) , + .clk_2_S_out ( clk_2_wires[85] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9097 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9098 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9099 ) ) ; +cby_1__1_ cby_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9100 } ) , + .chany_bottom_in ( sb_1__1__69_chany_top_out ) , + .chany_top_in ( sb_1__1__70_chany_bottom_out ) , + .ccff_head ( grid_clb_76_ccff_tail ) , + .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) , + .chany_top_out ( cby_1__1__76_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__76_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9101 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9102 ) , + .Test_en_W_in ( Test_enWires[124] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9103 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9104 ) , + .Test_en_E_out ( Test_enWires[125] ) , .pReset_S_in ( pResetWires[236] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9105 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9106 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9107 ) , + .Reset_W_in ( ResetWires[124] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9108 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9109 ) , + .Reset_E_out ( ResetWires[125] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[266] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[267] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9110 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9111 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9112 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9113 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9115 ) , + .clk_2_S_in ( clk_2_wires[82] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9116 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9117 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9118 ) ) ; +cby_1__1_ cby_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9119 } ) , + .chany_bottom_in ( sb_1__1__70_chany_top_out ) , + .chany_top_in ( sb_1__1__71_chany_bottom_out ) , + .ccff_head ( grid_clb_77_ccff_tail ) , + .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) , + .chany_top_out ( cby_1__1__77_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__77_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9120 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9121 ) , + .Test_en_W_in ( Test_enWires[146] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9122 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9123 ) , + .Test_en_E_out ( Test_enWires[147] ) , .pReset_S_in ( pResetWires[285] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9124 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9125 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9126 ) , + .Reset_W_in ( ResetWires[146] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9127 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9128 ) , + .Reset_E_out ( ResetWires[147] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9129 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9130 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9131 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9132 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9133 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9134 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9136 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9137 ) ) ; +cby_1__1_ cby_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9138 } ) , + .chany_bottom_in ( sb_1__1__71_chany_top_out ) , + .chany_top_in ( sb_1__1__72_chany_bottom_out ) , + .ccff_head ( grid_clb_78_ccff_tail ) , + .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) , + .chany_top_out ( cby_1__1__78_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__78_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9139 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9140 ) , + .Test_en_W_in ( Test_enWires[168] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9141 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9142 ) , + .Test_en_E_out ( Test_enWires[169] ) , .pReset_S_in ( pResetWires[334] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9143 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9144 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9145 ) , + .Reset_W_in ( ResetWires[168] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9146 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9147 ) , + .Reset_E_out ( ResetWires[169] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9148 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9149 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9150 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9151 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9152 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9153 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9155 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9156 ) ) ; +cby_1__1_ cby_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9157 } ) , + .chany_bottom_in ( sb_1__1__72_chany_top_out ) , + .chany_top_in ( sb_1__1__73_chany_bottom_out ) , + .ccff_head ( grid_clb_79_ccff_tail ) , + .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) , + .chany_top_out ( cby_1__1__79_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__79_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9158 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9159 ) , + .Test_en_W_in ( Test_enWires[190] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9160 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9161 ) , + .Test_en_E_out ( Test_enWires[191] ) , .pReset_S_in ( pResetWires[383] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9162 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9163 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9164 ) , + .Reset_W_in ( ResetWires[190] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9165 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9166 ) , + .Reset_E_out ( ResetWires[191] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[275] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[276] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9167 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[97] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9168 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9169 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9170 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9171 ) , + .clk_2_N_in ( clk_2_wires[97] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9172 ) , + .clk_2_S_out ( clk_2_wires[98] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9173 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9174 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9175 ) ) ; +cby_1__1_ cby_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9176 } ) , + .chany_bottom_in ( sb_1__1__73_chany_top_out ) , + .chany_top_in ( sb_1__1__74_chany_bottom_out ) , + .ccff_head ( grid_clb_80_ccff_tail ) , + .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) , + .chany_top_out ( cby_1__1__80_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__80_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9177 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9178 ) , + .Test_en_W_in ( Test_enWires[212] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9179 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9180 ) , + .Test_en_E_out ( Test_enWires[213] ) , .pReset_S_in ( pResetWires[432] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9181 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9182 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9183 ) , + .Reset_W_in ( ResetWires[212] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9184 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9185 ) , + .Reset_E_out ( ResetWires[213] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[278] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[279] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9186 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9187 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9188 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9189 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9191 ) , + .clk_2_S_in ( clk_2_wires[95] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9192 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9193 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9194 ) ) ; +cby_1__1_ cby_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9195 } ) , + .chany_bottom_in ( sb_1__1__74_chany_top_out ) , + .chany_top_in ( sb_1__1__75_chany_bottom_out ) , + .ccff_head ( grid_clb_81_ccff_tail ) , + .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) , + .chany_top_out ( cby_1__1__81_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__81_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9196 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9197 ) , + .Test_en_W_in ( Test_enWires[234] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9198 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9199 ) , + .Test_en_E_out ( Test_enWires[235] ) , .pReset_S_in ( pResetWires[481] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9200 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9201 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9202 ) , + .Reset_W_in ( ResetWires[234] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9203 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9204 ) , + .Reset_E_out ( ResetWires[235] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9205 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9206 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9207 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9208 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9209 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9210 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9212 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9213 ) ) ; +cby_1__1_ cby_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9214 } ) , + .chany_bottom_in ( sb_1__1__75_chany_top_out ) , + .chany_top_in ( sb_1__1__76_chany_bottom_out ) , + .ccff_head ( grid_clb_82_ccff_tail ) , + .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) , + .chany_top_out ( cby_1__1__82_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__82_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9215 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9216 ) , + .Test_en_W_in ( Test_enWires[256] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9217 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9218 ) , + .Test_en_E_out ( Test_enWires[257] ) , .pReset_S_in ( pResetWires[530] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9219 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9220 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9221 ) , + .Reset_W_in ( ResetWires[256] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9222 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9223 ) , + .Reset_E_out ( ResetWires[257] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[284] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[285] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9224 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9225 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9226 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9227 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9229 ) , + .clk_2_S_in ( clk_2_wires[108] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9230 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9231 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9232 ) ) ; +cby_1__1_ cby_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9233 } ) , + .chany_bottom_in ( sb_1__1__76_chany_top_out ) , + .chany_top_in ( sb_1__12__6_chany_bottom_out ) , + .ccff_head ( grid_clb_83_ccff_tail ) , + .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) , + .chany_top_out ( cby_1__1__83_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__83_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9234 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9235 ) , + .Test_en_W_in ( Test_enWires[278] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9236 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9237 ) , + .Test_en_E_out ( Test_enWires[279] ) , .pReset_S_in ( pResetWires[579] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9238 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9239 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9240 ) , + .Reset_W_in ( ResetWires[278] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9241 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9242 ) , + .Reset_E_out ( ResetWires[279] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9243 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9244 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9245 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9246 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9247 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9249 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9250 ) ) ; +cby_1__1_ cby_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9251 } ) , + .chany_bottom_in ( sb_1__0__7_chany_top_out ) , + .chany_top_in ( sb_1__1__77_chany_bottom_out ) , + .ccff_head ( grid_clb_84_ccff_tail ) , + .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) , + .chany_top_out ( cby_1__1__84_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__84_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9252 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9253 ) , + .Test_en_W_in ( Test_enWires[38] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9254 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9255 ) , + .Test_en_E_out ( Test_enWires[39] ) , .pReset_S_in ( pResetWires[48] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9256 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9257 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9258 ) , + .Reset_W_in ( ResetWires[38] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9259 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9260 ) , + .Reset_E_out ( ResetWires[39] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9261 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9262 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9264 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9265 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9266 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9268 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9269 ) ) ; +cby_1__1_ cby_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9270 } ) , + .chany_bottom_in ( sb_1__1__77_chany_top_out ) , + .chany_top_in ( sb_1__1__78_chany_bottom_out ) , + .ccff_head ( grid_clb_85_ccff_tail ) , + .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) , + .chany_top_out ( cby_1__1__85_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__85_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9272 ) , + .Test_en_W_in ( Test_enWires[60] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9273 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9274 ) , + .Test_en_E_out ( Test_enWires[61] ) , .pReset_S_in ( pResetWires[93] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9275 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9276 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9277 ) , + .Reset_W_in ( ResetWires[60] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9278 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9279 ) , + .Reset_E_out ( ResetWires[61] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9280 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9281 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9282 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9283 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9284 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9285 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9287 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9288 ) ) ; +cby_1__1_ cby_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9289 } ) , + .chany_bottom_in ( sb_1__1__78_chany_top_out ) , + .chany_top_in ( sb_1__1__79_chany_bottom_out ) , + .ccff_head ( grid_clb_86_ccff_tail ) , + .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) , + .chany_top_out ( cby_1__1__86_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__86_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9290 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9291 ) , + .Test_en_W_in ( Test_enWires[82] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9292 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9293 ) , + .Test_en_E_out ( Test_enWires[83] ) , .pReset_S_in ( pResetWires[142] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9294 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9295 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9296 ) , + .Reset_W_in ( ResetWires[82] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9297 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9298 ) , + .Reset_E_out ( ResetWires[83] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9299 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9300 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9301 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9302 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9303 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9304 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9305 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9306 ) , + .clk_3_N_in ( clk_3_wires[42] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , + .clk_3_S_out ( clk_3_wires[43] ) ) ; +cby_1__1_ cby_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9308 } ) , + .chany_bottom_in ( sb_1__1__79_chany_top_out ) , + .chany_top_in ( sb_1__1__80_chany_bottom_out ) , + .ccff_head ( grid_clb_87_ccff_tail ) , + .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) , + .chany_top_out ( cby_1__1__87_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__87_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9309 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9310 ) , + .Test_en_W_in ( Test_enWires[104] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9311 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9312 ) , + .Test_en_E_out ( Test_enWires[105] ) , .pReset_S_in ( pResetWires[191] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9313 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9314 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9315 ) , + .Reset_W_in ( ResetWires[104] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9316 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9317 ) , + .Reset_E_out ( ResetWires[105] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9318 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9319 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9321 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9322 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9323 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9324 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9325 ) , + .clk_3_N_in ( clk_3_wires[38] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9326 ) , + .clk_3_S_out ( clk_3_wires[39] ) ) ; +cby_1__1_ cby_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9327 } ) , + .chany_bottom_in ( sb_1__1__80_chany_top_out ) , + .chany_top_in ( sb_1__1__81_chany_bottom_out ) , + .ccff_head ( grid_clb_88_ccff_tail ) , + .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) , + .chany_top_out ( cby_1__1__88_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__88_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9328 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9329 ) , + .Test_en_W_in ( Test_enWires[126] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9330 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9331 ) , + .Test_en_E_out ( Test_enWires[127] ) , .pReset_S_in ( pResetWires[240] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9332 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9333 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9334 ) , + .Reset_W_in ( ResetWires[126] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9335 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9336 ) , + .Reset_E_out ( ResetWires[127] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9337 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9338 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9339 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9340 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9342 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9344 ) , + .clk_3_N_in ( clk_3_wires[32] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9345 ) , + .clk_3_S_out ( clk_3_wires[33] ) ) ; +cby_1__1_ cby_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9346 } ) , + .chany_bottom_in ( sb_1__1__81_chany_top_out ) , + .chany_top_in ( sb_1__1__82_chany_bottom_out ) , + .ccff_head ( grid_clb_89_ccff_tail ) , + .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) , + .chany_top_out ( cby_1__1__89_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__89_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9347 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9348 ) , + .Test_en_W_in ( Test_enWires[148] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9349 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9350 ) , + .Test_en_E_out ( Test_enWires[149] ) , .pReset_S_in ( pResetWires[289] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9351 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9352 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9353 ) , + .Reset_W_in ( ResetWires[148] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9354 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9355 ) , + .Reset_E_out ( ResetWires[149] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9356 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9357 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9359 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9361 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9362 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9363 ) , + .clk_3_N_in ( clk_3_wires[28] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , + .clk_3_S_out ( clk_3_wires[29] ) ) ; +cby_1__1_ cby_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9365 } ) , + .chany_bottom_in ( sb_1__1__82_chany_top_out ) , + .chany_top_in ( sb_1__1__83_chany_bottom_out ) , + .ccff_head ( grid_clb_90_ccff_tail ) , + .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) , + .chany_top_out ( cby_1__1__90_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__90_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9366 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9367 ) , + .Test_en_W_in ( Test_enWires[170] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9368 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9369 ) , + .Test_en_E_out ( Test_enWires[171] ) , .pReset_S_in ( pResetWires[338] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9370 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9371 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9372 ) , + .Reset_W_in ( ResetWires[170] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9373 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9374 ) , + .Reset_E_out ( ResetWires[171] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9375 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9376 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9378 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9379 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9380 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9381 ) , + .clk_3_S_in ( clk_3_wires[26] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9382 ) , + .clk_3_N_out ( clk_3_wires[27] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9383 ) ) ; +cby_1__1_ cby_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9384 } ) , + .chany_bottom_in ( sb_1__1__83_chany_top_out ) , + .chany_top_in ( sb_1__1__84_chany_bottom_out ) , + .ccff_head ( grid_clb_91_ccff_tail ) , + .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) , + .chany_top_out ( cby_1__1__91_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__91_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9385 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9386 ) , + .Test_en_W_in ( Test_enWires[192] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9387 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9388 ) , + .Test_en_E_out ( Test_enWires[193] ) , .pReset_S_in ( pResetWires[387] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9389 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9390 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9391 ) , + .Reset_W_in ( ResetWires[192] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9392 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9393 ) , + .Reset_E_out ( ResetWires[193] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9394 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9395 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9396 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9397 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9398 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9399 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9400 ) , + .clk_3_S_in ( clk_3_wires[30] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9401 ) , + .clk_3_N_out ( clk_3_wires[31] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9402 ) ) ; +cby_1__1_ cby_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9403 } ) , + .chany_bottom_in ( sb_1__1__84_chany_top_out ) , + .chany_top_in ( sb_1__1__85_chany_bottom_out ) , + .ccff_head ( grid_clb_92_ccff_tail ) , + .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) , + .chany_top_out ( cby_1__1__92_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__92_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9404 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9405 ) , + .Test_en_W_in ( Test_enWires[214] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9406 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9407 ) , + .Test_en_E_out ( Test_enWires[215] ) , .pReset_S_in ( pResetWires[436] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9408 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9409 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9410 ) , + .Reset_W_in ( ResetWires[214] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9411 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9412 ) , + .Reset_E_out ( ResetWires[215] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9413 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9414 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9416 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9417 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9418 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9419 ) , + .clk_3_S_in ( clk_3_wires[36] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9420 ) , + .clk_3_N_out ( clk_3_wires[37] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9421 ) ) ; +cby_1__1_ cby_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9422 } ) , + .chany_bottom_in ( sb_1__1__85_chany_top_out ) , + .chany_top_in ( sb_1__1__86_chany_bottom_out ) , + .ccff_head ( grid_clb_93_ccff_tail ) , + .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) , + .chany_top_out ( cby_1__1__93_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__93_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9423 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9424 ) , + .Test_en_W_in ( Test_enWires[236] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9425 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9426 ) , + .Test_en_E_out ( Test_enWires[237] ) , .pReset_S_in ( pResetWires[485] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9427 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9428 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9429 ) , + .Reset_W_in ( ResetWires[236] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9430 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9431 ) , + .Reset_E_out ( ResetWires[237] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9432 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9433 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9434 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9435 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9436 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9438 ) , + .clk_3_S_in ( clk_3_wires[40] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9439 ) , + .clk_3_N_out ( clk_3_wires[41] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9440 ) ) ; +cby_1__1_ cby_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9441 } ) , + .chany_bottom_in ( sb_1__1__86_chany_top_out ) , + .chany_top_in ( sb_1__1__87_chany_bottom_out ) , + .ccff_head ( grid_clb_94_ccff_tail ) , + .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) , + .chany_top_out ( cby_1__1__94_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__94_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9442 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9443 ) , + .Test_en_W_in ( Test_enWires[258] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9444 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9445 ) , + .Test_en_E_out ( Test_enWires[259] ) , .pReset_S_in ( pResetWires[534] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9446 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9447 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9448 ) , + .Reset_W_in ( ResetWires[258] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9449 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9450 ) , + .Reset_E_out ( ResetWires[259] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9451 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9452 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9453 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9454 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9455 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9456 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9458 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9459 ) ) ; +cby_1__1_ cby_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9460 } ) , + .chany_bottom_in ( sb_1__1__87_chany_top_out ) , + .chany_top_in ( sb_1__12__7_chany_bottom_out ) , + .ccff_head ( grid_clb_95_ccff_tail ) , + .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) , + .chany_top_out ( cby_1__1__95_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__95_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9461 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9462 ) , + .Test_en_W_in ( Test_enWires[280] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9463 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9464 ) , + .Test_en_E_out ( Test_enWires[281] ) , .pReset_S_in ( pResetWires[583] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9465 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9466 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9467 ) , + .Reset_W_in ( ResetWires[280] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9468 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9469 ) , + .Reset_E_out ( ResetWires[281] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9470 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9471 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9472 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9473 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9474 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9476 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9477 ) ) ; +cby_1__1_ cby_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9478 } ) , + .chany_bottom_in ( sb_1__0__8_chany_top_out ) , + .chany_top_in ( sb_1__1__88_chany_bottom_out ) , + .ccff_head ( grid_clb_96_ccff_tail ) , + .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) , + .chany_top_out ( cby_1__1__96_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__96_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9479 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9480 ) , + .Test_en_W_in ( Test_enWires[40] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9481 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9482 ) , + .Test_en_E_out ( Test_enWires[41] ) , .pReset_S_in ( pResetWires[51] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9483 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9484 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9485 ) , + .Reset_W_in ( ResetWires[40] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9486 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9487 ) , + .Reset_E_out ( ResetWires[41] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9488 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9489 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9490 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9491 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9492 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9493 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9495 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9496 ) ) ; +cby_1__1_ cby_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9497 } ) , + .chany_bottom_in ( sb_1__1__88_chany_top_out ) , + .chany_top_in ( sb_1__1__89_chany_bottom_out ) , + .ccff_head ( grid_clb_97_ccff_tail ) , + .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) , + .chany_top_out ( cby_1__1__97_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__97_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9498 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9499 ) , + .Test_en_W_in ( Test_enWires[62] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9500 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9501 ) , + .Test_en_E_out ( Test_enWires[63] ) , .pReset_S_in ( pResetWires[97] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9502 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9503 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9504 ) , + .Reset_W_in ( ResetWires[62] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9505 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9506 ) , + .Reset_E_out ( ResetWires[63] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[333] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[334] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9507 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[75] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9508 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9509 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9510 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9511 ) , + .clk_2_N_in ( clk_2_wires[75] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9512 ) , + .clk_2_S_out ( clk_2_wires[76] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9513 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9514 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9515 ) ) ; +cby_1__1_ cby_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9516 } ) , + .chany_bottom_in ( sb_1__1__89_chany_top_out ) , + .chany_top_in ( sb_1__1__90_chany_bottom_out ) , + .ccff_head ( grid_clb_98_ccff_tail ) , + .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) , + .chany_top_out ( cby_1__1__98_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__98_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9517 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9518 ) , + .Test_en_W_in ( Test_enWires[84] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9519 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9520 ) , + .Test_en_E_out ( Test_enWires[85] ) , .pReset_S_in ( pResetWires[146] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9521 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9522 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9523 ) , + .Reset_W_in ( ResetWires[84] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9524 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9525 ) , + .Reset_E_out ( ResetWires[85] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9526 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9527 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9528 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9529 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9530 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9531 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9534 ) ) ; +cby_1__1_ cby_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9535 } ) , + .chany_bottom_in ( sb_1__1__90_chany_top_out ) , + .chany_top_in ( sb_1__1__91_chany_bottom_out ) , + .ccff_head ( grid_clb_99_ccff_tail ) , + .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) , + .chany_top_out ( cby_1__1__99_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__99_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9536 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9537 ) , + .Test_en_W_in ( Test_enWires[106] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9538 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9539 ) , + .Test_en_E_out ( Test_enWires[107] ) , .pReset_S_in ( pResetWires[195] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9540 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9541 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9542 ) , + .Reset_W_in ( ResetWires[106] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9543 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9544 ) , + .Reset_E_out ( ResetWires[107] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[339] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[340] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9545 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[88] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9546 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9547 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9548 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9549 ) , + .clk_2_N_in ( clk_2_wires[88] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9550 ) , + .clk_2_S_out ( clk_2_wires[89] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9551 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9552 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9553 ) ) ; +cby_1__1_ cby_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9554 } ) , + .chany_bottom_in ( sb_1__1__91_chany_top_out ) , + .chany_top_in ( sb_1__1__92_chany_bottom_out ) , + .ccff_head ( grid_clb_100_ccff_tail ) , + .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) , + .chany_top_out ( cby_1__1__100_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__100_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9555 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9556 ) , + .Test_en_W_in ( Test_enWires[128] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9557 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9558 ) , + .Test_en_E_out ( Test_enWires[129] ) , .pReset_S_in ( pResetWires[244] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9559 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9560 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9561 ) , + .Reset_W_in ( ResetWires[128] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9562 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9563 ) , + .Reset_E_out ( ResetWires[129] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[342] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[343] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9564 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9565 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9566 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9567 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9568 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9569 ) , + .clk_2_S_in ( clk_2_wires[86] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9570 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9571 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9572 ) ) ; +cby_1__1_ cby_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9573 } ) , + .chany_bottom_in ( sb_1__1__92_chany_top_out ) , + .chany_top_in ( sb_1__1__93_chany_bottom_out ) , + .ccff_head ( grid_clb_101_ccff_tail ) , + .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) , + .chany_top_out ( cby_1__1__101_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__101_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9574 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9575 ) , + .Test_en_W_in ( Test_enWires[150] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9576 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9577 ) , + .Test_en_E_out ( Test_enWires[151] ) , .pReset_S_in ( pResetWires[293] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9578 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9579 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9580 ) , + .Reset_W_in ( ResetWires[150] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9581 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9582 ) , + .Reset_E_out ( ResetWires[151] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9583 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9584 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9585 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9586 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9587 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9588 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9590 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9591 ) ) ; +cby_1__1_ cby_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9592 } ) , + .chany_bottom_in ( sb_1__1__93_chany_top_out ) , + .chany_top_in ( sb_1__1__94_chany_bottom_out ) , + .ccff_head ( grid_clb_102_ccff_tail ) , + .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) , + .chany_top_out ( cby_1__1__102_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__102_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9593 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9594 ) , + .Test_en_W_in ( Test_enWires[172] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9595 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9596 ) , + .Test_en_E_out ( Test_enWires[173] ) , .pReset_S_in ( pResetWires[342] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9597 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9598 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9599 ) , + .Reset_W_in ( ResetWires[172] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9600 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9601 ) , + .Reset_E_out ( ResetWires[173] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9602 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9603 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9604 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9605 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9606 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9607 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9609 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9610 ) ) ; +cby_1__1_ cby_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9611 } ) , + .chany_bottom_in ( sb_1__1__94_chany_top_out ) , + .chany_top_in ( sb_1__1__95_chany_bottom_out ) , + .ccff_head ( grid_clb_103_ccff_tail ) , + .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) , + .chany_top_out ( cby_1__1__103_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__103_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9612 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9613 ) , + .Test_en_W_in ( Test_enWires[194] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9614 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9615 ) , + .Test_en_E_out ( Test_enWires[195] ) , .pReset_S_in ( pResetWires[391] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9616 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9617 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9618 ) , + .Reset_W_in ( ResetWires[194] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9619 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9620 ) , + .Reset_E_out ( ResetWires[195] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[351] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[352] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9621 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[101] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9622 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9623 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9624 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9625 ) , + .clk_2_N_in ( clk_2_wires[101] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9626 ) , + .clk_2_S_out ( clk_2_wires[102] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9627 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9628 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9629 ) ) ; +cby_1__1_ cby_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9630 } ) , + .chany_bottom_in ( sb_1__1__95_chany_top_out ) , + .chany_top_in ( sb_1__1__96_chany_bottom_out ) , + .ccff_head ( grid_clb_104_ccff_tail ) , + .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) , + .chany_top_out ( cby_1__1__104_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__104_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9631 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9632 ) , + .Test_en_W_in ( Test_enWires[216] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9633 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9634 ) , + .Test_en_E_out ( Test_enWires[217] ) , .pReset_S_in ( pResetWires[440] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9635 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9636 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9637 ) , + .Reset_W_in ( ResetWires[216] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9638 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9639 ) , + .Reset_E_out ( ResetWires[217] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[354] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[355] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9640 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9641 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9642 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9643 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9644 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9645 ) , + .clk_2_S_in ( clk_2_wires[99] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9646 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9647 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9648 ) ) ; +cby_1__1_ cby_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9649 } ) , + .chany_bottom_in ( sb_1__1__96_chany_top_out ) , + .chany_top_in ( sb_1__1__97_chany_bottom_out ) , + .ccff_head ( grid_clb_105_ccff_tail ) , + .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) , + .chany_top_out ( cby_1__1__105_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__105_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9650 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9651 ) , + .Test_en_W_in ( Test_enWires[238] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9652 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9653 ) , + .Test_en_E_out ( Test_enWires[239] ) , .pReset_S_in ( pResetWires[489] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9654 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9655 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9656 ) , + .Reset_W_in ( ResetWires[238] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9657 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9658 ) , + .Reset_E_out ( ResetWires[239] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9659 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9660 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9661 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9662 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9663 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9664 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9666 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9667 ) ) ; +cby_1__1_ cby_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9668 } ) , + .chany_bottom_in ( sb_1__1__97_chany_top_out ) , + .chany_top_in ( sb_1__1__98_chany_bottom_out ) , + .ccff_head ( grid_clb_106_ccff_tail ) , + .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) , + .chany_top_out ( cby_1__1__106_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__106_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9669 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9670 ) , + .Test_en_W_in ( Test_enWires[260] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9671 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9672 ) , + .Test_en_E_out ( Test_enWires[261] ) , .pReset_S_in ( pResetWires[538] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9673 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9674 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9675 ) , + .Reset_W_in ( ResetWires[260] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9676 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9677 ) , + .Reset_E_out ( ResetWires[261] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[360] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[361] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9678 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9679 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9680 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9682 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9683 ) , + .clk_2_S_in ( clk_2_wires[110] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9684 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9685 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9686 ) ) ; +cby_1__1_ cby_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9687 } ) , + .chany_bottom_in ( sb_1__1__98_chany_top_out ) , + .chany_top_in ( sb_1__12__8_chany_bottom_out ) , + .ccff_head ( grid_clb_107_ccff_tail ) , + .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) , + .chany_top_out ( cby_1__1__107_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__107_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9688 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9689 ) , + .Test_en_W_in ( Test_enWires[282] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9690 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9691 ) , + .Test_en_E_out ( Test_enWires[283] ) , .pReset_S_in ( pResetWires[587] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9692 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9693 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9694 ) , + .Reset_W_in ( ResetWires[282] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9695 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9696 ) , + .Reset_E_out ( ResetWires[283] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9697 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9698 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9699 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9700 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9701 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9704 ) ) ; +cby_1__1_ cby_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9705 } ) , + .chany_bottom_in ( sb_1__0__9_chany_top_out ) , + .chany_top_in ( sb_1__1__99_chany_bottom_out ) , + .ccff_head ( grid_clb_108_ccff_tail ) , + .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) , + .chany_top_out ( cby_1__1__108_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__108_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9706 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9707 ) , + .Test_en_W_in ( Test_enWires[42] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9708 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9709 ) , + .Test_en_E_out ( Test_enWires[43] ) , .pReset_S_in ( pResetWires[54] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9710 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9711 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9712 ) , + .Reset_W_in ( ResetWires[42] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9713 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9714 ) , + .Reset_E_out ( ResetWires[43] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9715 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9716 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9717 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9719 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9720 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9722 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9723 ) ) ; +cby_1__1_ cby_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9724 } ) , + .chany_bottom_in ( sb_1__1__99_chany_top_out ) , + .chany_top_in ( sb_1__1__100_chany_bottom_out ) , + .ccff_head ( grid_clb_109_ccff_tail ) , + .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) , + .chany_top_out ( cby_1__1__109_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__109_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9725 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9726 ) , + .Test_en_W_in ( Test_enWires[64] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9727 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9728 ) , + .Test_en_E_out ( Test_enWires[65] ) , .pReset_S_in ( pResetWires[101] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9729 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9730 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9731 ) , + .Reset_W_in ( ResetWires[64] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9732 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9733 ) , + .Reset_E_out ( ResetWires[65] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9734 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9735 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9736 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9737 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9738 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9739 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9741 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9742 ) ) ; +cby_1__1_ cby_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9743 } ) , + .chany_bottom_in ( sb_1__1__100_chany_top_out ) , + .chany_top_in ( sb_1__1__101_chany_bottom_out ) , + .ccff_head ( grid_clb_110_ccff_tail ) , + .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) , + .chany_top_out ( cby_1__1__110_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__110_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9744 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9745 ) , + .Test_en_W_in ( Test_enWires[86] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9746 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9747 ) , + .Test_en_E_out ( Test_enWires[87] ) , .pReset_S_in ( pResetWires[150] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9748 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9749 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9750 ) , + .Reset_W_in ( ResetWires[86] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9751 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9752 ) , + .Reset_E_out ( ResetWires[87] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9753 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9754 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9755 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9756 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9757 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9758 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9759 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9760 ) , + .clk_3_N_in ( clk_3_wires[86] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9761 ) , + .clk_3_S_out ( clk_3_wires[87] ) ) ; +cby_1__1_ cby_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9762 } ) , + .chany_bottom_in ( sb_1__1__101_chany_top_out ) , + .chany_top_in ( sb_1__1__102_chany_bottom_out ) , + .ccff_head ( grid_clb_111_ccff_tail ) , + .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) , + .chany_top_out ( cby_1__1__111_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__111_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9763 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9764 ) , + .Test_en_W_in ( Test_enWires[108] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9765 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9766 ) , + .Test_en_E_out ( Test_enWires[109] ) , .pReset_S_in ( pResetWires[199] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9767 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9768 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9769 ) , + .Reset_W_in ( ResetWires[108] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9770 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9771 ) , + .Reset_E_out ( ResetWires[109] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9772 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9773 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9775 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9776 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9777 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9778 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9779 ) , + .clk_3_N_in ( clk_3_wires[82] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9780 ) , + .clk_3_S_out ( clk_3_wires[83] ) ) ; +cby_1__1_ cby_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9781 } ) , + .chany_bottom_in ( sb_1__1__102_chany_top_out ) , + .chany_top_in ( sb_1__1__103_chany_bottom_out ) , + .ccff_head ( grid_clb_112_ccff_tail ) , + .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) , + .chany_top_out ( cby_1__1__112_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__112_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9782 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9783 ) , + .Test_en_W_in ( Test_enWires[130] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9784 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9785 ) , + .Test_en_E_out ( Test_enWires[131] ) , .pReset_S_in ( pResetWires[248] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9786 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9787 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9788 ) , + .Reset_W_in ( ResetWires[130] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9789 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9790 ) , + .Reset_E_out ( ResetWires[131] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9791 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9792 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9794 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9797 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9798 ) , + .clk_3_N_in ( clk_3_wires[76] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9799 ) , + .clk_3_S_out ( clk_3_wires[77] ) ) ; +cby_1__1_ cby_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9800 } ) , + .chany_bottom_in ( sb_1__1__103_chany_top_out ) , + .chany_top_in ( sb_1__1__104_chany_bottom_out ) , + .ccff_head ( grid_clb_113_ccff_tail ) , + .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) , + .chany_top_out ( cby_1__1__113_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__113_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9801 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9802 ) , + .Test_en_W_in ( Test_enWires[152] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9803 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9804 ) , + .Test_en_E_out ( Test_enWires[153] ) , .pReset_S_in ( pResetWires[297] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9805 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9806 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9807 ) , + .Reset_W_in ( ResetWires[152] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9808 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9809 ) , + .Reset_E_out ( ResetWires[153] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9810 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9811 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9813 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9814 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9815 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9816 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9817 ) , + .clk_3_N_in ( clk_3_wires[72] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9818 ) , + .clk_3_S_out ( clk_3_wires[73] ) ) ; +cby_1__1_ cby_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9819 } ) , + .chany_bottom_in ( sb_1__1__104_chany_top_out ) , + .chany_top_in ( sb_1__1__105_chany_bottom_out ) , + .ccff_head ( grid_clb_114_ccff_tail ) , + .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) , + .chany_top_out ( cby_1__1__114_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__114_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9820 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9821 ) , + .Test_en_W_in ( Test_enWires[174] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9822 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9823 ) , + .Test_en_E_out ( Test_enWires[175] ) , .pReset_S_in ( pResetWires[346] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9824 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9825 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9826 ) , + .Reset_W_in ( ResetWires[174] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9827 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9828 ) , + .Reset_E_out ( ResetWires[175] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9829 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9830 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9831 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9832 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9833 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9834 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9835 ) , + .clk_3_S_in ( clk_3_wires[70] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9836 ) , + .clk_3_N_out ( clk_3_wires[71] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9837 ) ) ; +cby_1__1_ cby_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9838 } ) , + .chany_bottom_in ( sb_1__1__105_chany_top_out ) , + .chany_top_in ( sb_1__1__106_chany_bottom_out ) , + .ccff_head ( grid_clb_115_ccff_tail ) , + .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) , + .chany_top_out ( cby_1__1__115_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__115_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9839 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9840 ) , + .Test_en_W_in ( Test_enWires[196] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9841 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9842 ) , + .Test_en_E_out ( Test_enWires[197] ) , .pReset_S_in ( pResetWires[395] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9843 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9844 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9845 ) , + .Reset_W_in ( ResetWires[196] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9846 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9847 ) , + .Reset_E_out ( ResetWires[197] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9848 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9849 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9850 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9851 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9852 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9854 ) , + .clk_3_S_in ( clk_3_wires[74] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9855 ) , + .clk_3_N_out ( clk_3_wires[75] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9856 ) ) ; +cby_1__1_ cby_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9857 } ) , + .chany_bottom_in ( sb_1__1__106_chany_top_out ) , + .chany_top_in ( sb_1__1__107_chany_bottom_out ) , + .ccff_head ( grid_clb_116_ccff_tail ) , + .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) , + .chany_top_out ( cby_1__1__116_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__116_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9858 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9859 ) , + .Test_en_W_in ( Test_enWires[218] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9860 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9861 ) , + .Test_en_E_out ( Test_enWires[219] ) , .pReset_S_in ( pResetWires[444] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9862 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9863 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9864 ) , + .Reset_W_in ( ResetWires[218] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9865 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9866 ) , + .Reset_E_out ( ResetWires[219] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9867 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9869 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9870 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9871 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9872 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9873 ) , + .clk_3_S_in ( clk_3_wires[80] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9874 ) , + .clk_3_N_out ( clk_3_wires[81] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9875 ) ) ; +cby_1__1_ cby_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9876 } ) , + .chany_bottom_in ( sb_1__1__107_chany_top_out ) , + .chany_top_in ( sb_1__1__108_chany_bottom_out ) , + .ccff_head ( grid_clb_117_ccff_tail ) , + .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) , + .chany_top_out ( cby_1__1__117_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__117_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9877 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9878 ) , + .Test_en_W_in ( Test_enWires[240] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9879 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9880 ) , + .Test_en_E_out ( Test_enWires[241] ) , .pReset_S_in ( pResetWires[493] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9881 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9882 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9883 ) , + .Reset_W_in ( ResetWires[240] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9884 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9885 ) , + .Reset_E_out ( ResetWires[241] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9886 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9887 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9888 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9889 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9890 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9891 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9892 ) , + .clk_3_S_in ( clk_3_wires[84] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9893 ) , + .clk_3_N_out ( clk_3_wires[85] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9894 ) ) ; +cby_1__1_ cby_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9895 } ) , + .chany_bottom_in ( sb_1__1__108_chany_top_out ) , + .chany_top_in ( sb_1__1__109_chany_bottom_out ) , + .ccff_head ( grid_clb_118_ccff_tail ) , + .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) , + .chany_top_out ( cby_1__1__118_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__118_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9896 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9897 ) , + .Test_en_W_in ( Test_enWires[262] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9898 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9899 ) , + .Test_en_E_out ( Test_enWires[263] ) , .pReset_S_in ( pResetWires[542] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9900 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9901 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9902 ) , + .Reset_W_in ( ResetWires[262] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9903 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9904 ) , + .Reset_E_out ( ResetWires[263] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9905 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9906 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9907 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9908 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9909 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9910 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9913 ) ) ; +cby_1__1_ cby_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9914 } ) , + .chany_bottom_in ( sb_1__1__109_chany_top_out ) , + .chany_top_in ( sb_1__12__9_chany_bottom_out ) , + .ccff_head ( grid_clb_119_ccff_tail ) , + .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) , + .chany_top_out ( cby_1__1__119_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__119_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9915 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9916 ) , + .Test_en_W_in ( Test_enWires[284] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9917 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9918 ) , + .Test_en_E_out ( Test_enWires[285] ) , .pReset_S_in ( pResetWires[591] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9919 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9920 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9921 ) , + .Reset_W_in ( ResetWires[284] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9922 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9923 ) , + .Reset_E_out ( ResetWires[285] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9924 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9925 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9926 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9927 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9928 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9930 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9931 ) ) ; +cby_1__1_ cby_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9932 } ) , + .chany_bottom_in ( sb_1__0__10_chany_top_out ) , + .chany_top_in ( sb_1__1__110_chany_bottom_out ) , + .ccff_head ( grid_clb_120_ccff_tail ) , + .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) , + .chany_top_out ( cby_1__1__120_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__120_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9933 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9934 ) , + .Test_en_W_in ( Test_enWires[44] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9935 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9936 ) , + .Test_en_E_out ( Test_enWires[45] ) , .pReset_S_in ( pResetWires[57] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9937 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9938 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9939 ) , + .Reset_W_in ( ResetWires[44] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9940 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9941 ) , + .Reset_E_out ( ResetWires[45] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9942 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9943 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9944 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9945 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9946 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9947 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9949 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9950 ) ) ; +cby_1__1_ cby_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9951 } ) , + .chany_bottom_in ( sb_1__1__110_chany_top_out ) , + .chany_top_in ( sb_1__1__111_chany_bottom_out ) , + .ccff_head ( grid_clb_121_ccff_tail ) , + .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) , + .chany_top_out ( cby_1__1__121_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__121_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9952 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9953 ) , + .Test_en_W_in ( Test_enWires[66] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9954 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9955 ) , + .Test_en_E_out ( Test_enWires[67] ) , .pReset_S_in ( pResetWires[105] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9956 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9957 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9958 ) , + .Reset_W_in ( ResetWires[66] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9959 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9960 ) , + .Reset_E_out ( ResetWires[67] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[409] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[410] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9961 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[115] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9962 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9963 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9964 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9965 ) , + .clk_2_N_in ( clk_2_wires[115] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9966 ) , + .clk_2_S_out ( clk_2_wires[116] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9967 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9968 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9969 ) ) ; +cby_1__1_ cby_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9970 } ) , + .chany_bottom_in ( sb_1__1__111_chany_top_out ) , + .chany_top_in ( sb_1__1__112_chany_bottom_out ) , + .ccff_head ( grid_clb_122_ccff_tail ) , + .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) , + .chany_top_out ( cby_1__1__122_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__122_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9971 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9972 ) , + .Test_en_W_in ( Test_enWires[88] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9973 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9974 ) , + .Test_en_E_out ( Test_enWires[89] ) , .pReset_S_in ( pResetWires[154] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9975 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9976 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9977 ) , + .Reset_W_in ( ResetWires[88] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9978 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9979 ) , + .Reset_E_out ( ResetWires[89] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9980 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9981 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9982 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9983 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9984 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9985 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9988 ) ) ; +cby_1__1_ cby_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9989 } ) , + .chany_bottom_in ( sb_1__1__112_chany_top_out ) , + .chany_top_in ( sb_1__1__113_chany_bottom_out ) , + .ccff_head ( grid_clb_123_ccff_tail ) , + .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) , + .chany_top_out ( cby_1__1__123_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__123_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9990 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9991 ) , + .Test_en_W_in ( Test_enWires[110] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9992 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9993 ) , + .Test_en_E_out ( Test_enWires[111] ) , .pReset_S_in ( pResetWires[203] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9994 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9995 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9996 ) , + .Reset_W_in ( ResetWires[110] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9997 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9998 ) , + .Reset_E_out ( ResetWires[111] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[415] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[416] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9999 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[122] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10000 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10001 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10002 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10003 ) , + .clk_2_N_in ( clk_2_wires[122] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10004 ) , + .clk_2_S_out ( clk_2_wires[123] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10005 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10006 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10007 ) ) ; +cby_1__1_ cby_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10008 } ) , + .chany_bottom_in ( sb_1__1__113_chany_top_out ) , + .chany_top_in ( sb_1__1__114_chany_bottom_out ) , + .ccff_head ( grid_clb_124_ccff_tail ) , + .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) , + .chany_top_out ( cby_1__1__124_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__124_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10009 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10010 ) , + .Test_en_W_in ( Test_enWires[132] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10011 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10012 ) , + .Test_en_E_out ( Test_enWires[133] ) , .pReset_S_in ( pResetWires[252] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10013 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10014 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10015 ) , + .Reset_W_in ( ResetWires[132] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10016 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10017 ) , + .Reset_E_out ( ResetWires[133] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[418] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[419] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10018 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10019 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10020 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10021 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10022 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10023 ) , + .clk_2_S_in ( clk_2_wires[120] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10024 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10025 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10026 ) ) ; +cby_1__1_ cby_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10027 } ) , + .chany_bottom_in ( sb_1__1__114_chany_top_out ) , + .chany_top_in ( sb_1__1__115_chany_bottom_out ) , + .ccff_head ( grid_clb_125_ccff_tail ) , + .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) , + .chany_top_out ( cby_1__1__125_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__125_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10028 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10029 ) , + .Test_en_W_in ( Test_enWires[154] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10030 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10031 ) , + .Test_en_E_out ( Test_enWires[155] ) , .pReset_S_in ( pResetWires[301] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10032 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10033 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10034 ) , + .Reset_W_in ( ResetWires[154] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10035 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10036 ) , + .Reset_E_out ( ResetWires[155] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10037 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10038 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10039 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10040 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10041 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10042 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10044 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10045 ) ) ; +cby_1__1_ cby_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10046 } ) , + .chany_bottom_in ( sb_1__1__115_chany_top_out ) , + .chany_top_in ( sb_1__1__116_chany_bottom_out ) , + .ccff_head ( grid_clb_126_ccff_tail ) , + .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) , + .chany_top_out ( cby_1__1__126_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__126_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10047 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10048 ) , + .Test_en_W_in ( Test_enWires[176] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10049 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10050 ) , + .Test_en_E_out ( Test_enWires[177] ) , .pReset_S_in ( pResetWires[350] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10051 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10052 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10053 ) , + .Reset_W_in ( ResetWires[176] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10054 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10055 ) , + .Reset_E_out ( ResetWires[177] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10056 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10057 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10058 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10059 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10060 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10061 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10063 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10064 ) ) ; +cby_1__1_ cby_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10065 } ) , + .chany_bottom_in ( sb_1__1__116_chany_top_out ) , + .chany_top_in ( sb_1__1__117_chany_bottom_out ) , + .ccff_head ( grid_clb_127_ccff_tail ) , + .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) , + .chany_top_out ( cby_1__1__127_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__127_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10066 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10067 ) , + .Test_en_W_in ( Test_enWires[198] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10068 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10069 ) , + .Test_en_E_out ( Test_enWires[199] ) , .pReset_S_in ( pResetWires[399] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10070 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10071 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10072 ) , + .Reset_W_in ( ResetWires[198] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10073 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10074 ) , + .Reset_E_out ( ResetWires[199] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[427] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[428] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10075 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[129] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10076 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10077 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10078 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10079 ) , + .clk_2_N_in ( clk_2_wires[129] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10080 ) , + .clk_2_S_out ( clk_2_wires[130] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10081 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10082 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10083 ) ) ; +cby_1__1_ cby_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10084 } ) , + .chany_bottom_in ( sb_1__1__117_chany_top_out ) , + .chany_top_in ( sb_1__1__118_chany_bottom_out ) , + .ccff_head ( grid_clb_128_ccff_tail ) , + .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) , + .chany_top_out ( cby_1__1__128_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__128_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10085 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10086 ) , + .Test_en_W_in ( Test_enWires[220] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10087 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10088 ) , + .Test_en_E_out ( Test_enWires[221] ) , .pReset_S_in ( pResetWires[448] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10089 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10090 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10091 ) , + .Reset_W_in ( ResetWires[220] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10092 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10093 ) , + .Reset_E_out ( ResetWires[221] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[430] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[431] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10094 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10095 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10096 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10097 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10098 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10099 ) , + .clk_2_S_in ( clk_2_wires[127] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10100 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10101 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10102 ) ) ; +cby_1__1_ cby_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10103 } ) , + .chany_bottom_in ( sb_1__1__118_chany_top_out ) , + .chany_top_in ( sb_1__1__119_chany_bottom_out ) , + .ccff_head ( grid_clb_129_ccff_tail ) , + .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) , + .chany_top_out ( cby_1__1__129_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__129_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10104 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10105 ) , + .Test_en_W_in ( Test_enWires[242] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10106 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10107 ) , + .Test_en_E_out ( Test_enWires[243] ) , .pReset_S_in ( pResetWires[497] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10108 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10109 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10110 ) , + .Reset_W_in ( ResetWires[242] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10111 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10112 ) , + .Reset_E_out ( ResetWires[243] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10113 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10114 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10115 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10117 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10118 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10120 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10121 ) ) ; +cby_1__1_ cby_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10122 } ) , + .chany_bottom_in ( sb_1__1__119_chany_top_out ) , + .chany_top_in ( sb_1__1__120_chany_bottom_out ) , + .ccff_head ( grid_clb_130_ccff_tail ) , + .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) , + .chany_top_out ( cby_1__1__130_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__130_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10123 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10124 ) , + .Test_en_W_in ( Test_enWires[264] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10125 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10126 ) , + .Test_en_E_out ( Test_enWires[265] ) , .pReset_S_in ( pResetWires[546] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10127 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10128 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10129 ) , + .Reset_W_in ( ResetWires[264] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10130 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10131 ) , + .Reset_E_out ( ResetWires[265] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[436] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[437] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10132 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10133 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10134 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10136 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10137 ) , + .clk_2_S_in ( clk_2_wires[134] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10138 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10139 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10140 ) ) ; +cby_1__1_ cby_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10141 } ) , + .chany_bottom_in ( sb_1__1__120_chany_top_out ) , + .chany_top_in ( sb_1__12__10_chany_bottom_out ) , + .ccff_head ( grid_clb_131_ccff_tail ) , + .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) , + .chany_top_out ( cby_1__1__131_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__131_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10142 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10143 ) , + .Test_en_W_in ( Test_enWires[286] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10144 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10145 ) , + .Test_en_E_out ( Test_enWires[287] ) , .pReset_S_in ( pResetWires[595] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10146 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10147 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10148 ) , + .Reset_W_in ( ResetWires[286] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10149 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10150 ) , + .Reset_E_out ( ResetWires[287] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10151 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10152 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10154 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10155 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10157 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10158 ) ) ; +cby_2__1_ cby_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10159 } ) , + .chany_bottom_in ( sb_12__0__0_chany_top_out ) , + .chany_top_in ( sb_12__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_132_ccff_tail ) , + .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) , + .chany_top_out ( cby_12__1__0_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[60] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[444] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[445] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ; +cby_2__1_ cby_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) , + .chany_bottom_in ( sb_12__1__0_chany_top_out ) , + .chany_top_in ( sb_12__1__1_chany_bottom_out ) , + .ccff_head ( grid_clb_133_ccff_tail ) , + .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) , + .chany_top_out ( cby_12__1__1_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[109] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[447] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[448] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) ) ; +cby_2__1_ cby_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10163 } ) , + .chany_bottom_in ( sb_12__1__1_chany_top_out ) , + .chany_top_in ( sb_12__1__2_chany_bottom_out ) , + .ccff_head ( grid_clb_134_ccff_tail ) , + .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) , + .chany_top_out ( cby_12__1__2_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[158] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[450] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[451] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) ) ; +cby_2__1_ cby_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10165 } ) , + .chany_bottom_in ( sb_12__1__2_chany_top_out ) , + .chany_top_in ( sb_12__1__3_chany_bottom_out ) , + .ccff_head ( grid_clb_135_ccff_tail ) , + .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) , + .chany_top_out ( cby_12__1__3_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[207] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[453] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[454] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) ) ; +cby_2__1_ cby_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10167 } ) , + .chany_bottom_in ( sb_12__1__3_chany_top_out ) , + .chany_top_in ( sb_12__1__4_chany_bottom_out ) , + .ccff_head ( grid_clb_136_ccff_tail ) , + .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) , + .chany_top_out ( cby_12__1__4_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[256] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[456] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[457] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) ) ; +cby_2__1_ cby_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10169 } ) , + .chany_bottom_in ( sb_12__1__4_chany_top_out ) , + .chany_top_in ( sb_12__1__5_chany_bottom_out ) , + .ccff_head ( grid_clb_137_ccff_tail ) , + .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) , + .chany_top_out ( cby_12__1__5_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[305] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[459] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[460] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) ) ; +cby_2__1_ cby_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10171 } ) , + .chany_bottom_in ( sb_12__1__5_chany_top_out ) , + .chany_top_in ( sb_12__1__6_chany_bottom_out ) , + .ccff_head ( grid_clb_138_ccff_tail ) , + .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) , + .chany_top_out ( cby_12__1__6_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[354] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[462] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[463] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) ) ; +cby_2__1_ cby_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10173 } ) , + .chany_bottom_in ( sb_12__1__6_chany_top_out ) , + .chany_top_in ( sb_12__1__7_chany_bottom_out ) , + .ccff_head ( grid_clb_139_ccff_tail ) , + .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) , + .chany_top_out ( cby_12__1__7_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[403] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[465] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[466] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) ) ; +cby_2__1_ cby_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10175 } ) , + .chany_bottom_in ( sb_12__1__7_chany_top_out ) , + .chany_top_in ( sb_12__1__8_chany_bottom_out ) , + .ccff_head ( grid_clb_140_ccff_tail ) , + .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) , + .chany_top_out ( cby_12__1__8_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[452] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[468] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[469] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) ) ; +cby_2__1_ cby_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10177 } ) , + .chany_bottom_in ( sb_12__1__8_chany_top_out ) , + .chany_top_in ( sb_12__1__9_chany_bottom_out ) , + .ccff_head ( grid_clb_141_ccff_tail ) , + .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) , + .chany_top_out ( cby_12__1__9_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[501] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[471] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[472] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) ) ; +cby_2__1_ cby_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10179 } ) , + .chany_bottom_in ( sb_12__1__9_chany_top_out ) , + .chany_top_in ( sb_12__1__10_chany_bottom_out ) , + .ccff_head ( grid_clb_142_ccff_tail ) , + .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) , + .chany_top_out ( cby_12__1__10_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[550] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[474] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[475] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) ) ; +cby_2__1_ cby_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10181 } ) , + .chany_bottom_in ( sb_12__1__10_chany_top_out ) , + .chany_top_in ( sb_12__12__0_chany_bottom_out ) , + .ccff_head ( grid_clb_143_ccff_tail ) , + .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) , + .chany_top_out ( cby_12__1__11_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[599] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[477] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[478] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[480] ) ) ; +endmodule + + +module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , + vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , + wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , + la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ , + analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ , + analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ , + analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ , + analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ , + analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , + analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , + analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , + analog_io_9_ , user_clock2 ) ; +inout vdda1 ; +inout vdda2 ; +inout vssa1 ; +inout vssa2 ; +inout vccd1 ; +inout vccd2 ; +inout vssd1 ; +inout vssd2 ; +input wb_clk_i ; +input wb_rst_i ; +input wbs_stb_i ; +input wbs_cyc_i ; +input wbs_we_i ; +input [3:0] wbs_sel_i ; +input [31:0] wbs_dat_i ; +input [31:0] wbs_adr_i ; +output wbs_ack_o ; +output [31:0] wbs_dat_o ; +input [127:0] la_data_in ; +output [127:0] la_data_out ; +input [127:0] la_oen ; +input [37:0] io_in ; +output [37:0] io_out ; +output [37:0] io_oeb ; +inout analog_io_0_ ; +inout analog_io_10_ ; +inout analog_io_11_ ; +inout analog_io_12_ ; +inout analog_io_13_ ; +inout analog_io_14_ ; +inout analog_io_15_ ; +inout analog_io_16_ ; +inout analog_io_17_ ; +inout analog_io_18_ ; +inout analog_io_19_ ; +inout analog_io_1_ ; +inout analog_io_20_ ; +inout analog_io_21_ ; +inout analog_io_22_ ; +inout analog_io_23_ ; +inout analog_io_24_ ; +inout analog_io_25_ ; +inout analog_io_26_ ; +inout analog_io_27_ ; +inout analog_io_28_ ; +inout analog_io_29_ ; +inout analog_io_2_ ; +inout analog_io_30_ ; +inout analog_io_3_ ; +inout analog_io_4_ ; +inout analog_io_5_ ; +inout analog_io_6_ ; +inout analog_io_7_ ; +inout analog_io_8_ ; +inout analog_io_9_ ; +input user_clock2 ; + +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +wire ccff_head ; +wire sc_tail ; +wire pReset ; +wire Reset ; +wire IO_ISOL_N ; +wire Test_en ; +wire prog_clk ; +wire clk ; +wire ccff_tail ; +wire sc_head ; +wire wb_la_switch ; + +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ; +assign ccff_head = io_in[12] ; +assign sc_tail = io_out[11] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ; +assign pReset = io_in[3] ; +assign Reset = io_in[2] ; +assign IO_ISOL_N = io_in[1] ; +assign Test_en = io_in[0] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ; +assign prog_clk = io_in[37] ; +assign clk = io_in[36] ; +assign ccff_tail = io_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ; +assign sc_head = io_in[26] ; +assign wb_la_switch = io_in[25] ; + +sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) , + .Y ( wb_la_switch_b ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[0] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[116] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[1] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[115] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[2] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[114] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[3] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[113] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[4] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[112] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[5] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[111] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[6] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[110] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[7] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[109] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[8] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[108] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[9] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[107] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[10] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[106] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[11] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[105] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[12] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[104] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[13] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[103] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[14] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[102] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[15] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[101] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[16] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[100] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[17] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[99] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[18] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[98] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[19] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[97] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[20] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[96] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[21] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[95] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[22] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[94] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[23] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[93] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[24] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[92] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[25] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[91] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[26] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[90] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[27] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[89] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[28] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[88] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[29] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[87] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[30] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[86] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[31] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[85] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) , + .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) , + .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) , + .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) , + .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) , + .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) , + .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) , + .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) , + .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) , + .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) , + .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) , + .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) , + .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) , + .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) , + .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) , + .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) , + .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) , + .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) , + .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) , + .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) , + .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) , + .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) , + .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) , + .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) , + .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) , + .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) , + .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) , + .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) , + .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) , + .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) , + .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) , + .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) , + .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) , + .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) , + .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) , + .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) , + .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) , + .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) , + .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) , + .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) , + .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) , + .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) , + .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) , + .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) , + .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) , + .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) , + .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) , + .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) , + .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) , + .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) , + .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) , + .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) , + .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) , + .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) , + .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) , + .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) , + .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) , + .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) , + .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) , + .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) , + .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) , + .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) , + .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) , + .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) , + .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) , + .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) , + .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) , + .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) , + .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) , + .A1 ( wbs_we_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) , + .A1 ( wbs_stb_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) , + .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_ack_o ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[13] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) , + .A1 ( wb_rst_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) , + .A1 ( wb_clk_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ; +fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , + .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) , + .Reset ( io_in[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] , + io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] , + io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] , + io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] , + la_data_in[127] , la_data_in[126] , la_data_in[125] , + la_data_in[124] , la_data_in[123] , la_data_in[122] , + la_data_in[121] , la_data_in[120] , la_data_in[119] , + la_data_in[118] , la_data_in[117] , la_data_in[116] , + la_data_in[115] , la_data_in[114] , la_data_in[113] , + la_data_in[112] , la_data_in[111] , la_data_in[110] , + la_data_in[109] , la_data_in[108] , la_data_in[107] , + la_data_in[106] , la_data_in[105] , la_data_in[104] , + la_data_in[103] , la_data_in[102] , la_data_in[101] , + la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] , + la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] , + la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] , + la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] , + io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] , + io_in[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] , + io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] , + io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] , + io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] , + io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] , + la_data_out[125] , la_data_out[124] , la_data_out[123] , + la_data_out[122] , la_data_out[121] , la_data_out[120] , + la_data_out[119] , la_data_out[118] , la_data_out[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] , + la_data_out[83] , la_data_out[82] , la_data_out[81] , + la_data_out[80] , la_data_out[79] , la_data_out[78] , + la_data_out[77] , la_data_out[76] , la_data_out[75] , + la_data_out[74] , la_data_out[73] , la_data_out[72] , + la_data_out[71] , la_data_out[70] , la_data_out[69] , + la_data_out[68] , la_data_out[67] , la_data_out[66] , + la_data_out[65] , la_data_out[64] , la_data_out[63] , + la_data_out[62] , la_data_out[61] , la_data_out[60] , + la_data_out[59] , la_data_out[58] , la_data_out[57] , + la_data_out[56] , la_data_out[55] , la_data_out[54] , + la_data_out[53] , la_data_out[52] , la_data_out[51] , + la_data_out[50] , la_data_out[49] , la_data_out[48] , + la_data_out[47] , la_data_out[46] , la_data_out[45] , + la_data_out[44] , la_data_out[43] , la_data_out[42] , + la_data_out[41] , la_data_out[40] , la_data_out[39] , + la_data_out[38] , la_data_out[37] , la_data_out[36] , + la_data_out[35] , la_data_out[34] , la_data_out[33] , + la_data_out[32] , la_data_out[31] , la_data_out[30] , + la_data_out[29] , la_data_out[28] , la_data_out[27] , + la_data_out[26] , la_data_out[25] , la_data_out[24] , + la_data_out[23] , la_data_out[22] , la_data_out[21] , + la_data_out[20] , la_data_out[19] , la_data_out[18] , + la_data_out[17] , la_data_out[16] , la_data_out[15] , + la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] , + la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] , + io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] , + io_out[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] , + io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] , + io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] , + io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] , + io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] , + io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] , + io_oeb[27] } ) , + .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) , + .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , .h_incr0 ( 1'b0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( io_oeb[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( io_oeb[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( io_oeb[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( io_oeb[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( io_oeb[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( io_oeb[25] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( io_oeb[26] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( io_oeb[36] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , + .HI ( io_oeb[37] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) , + .HI ( SYNOPSYS_UNCONNECTED_10 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) , + .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) , + .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) , + .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) , + .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) , + .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) , + .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) , + .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) , + .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) , + .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , + .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ; +endmodule + + diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz new file mode 100644 index 0000000..3a0959f Binary files /dev/null and b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz differ diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lef b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lef new file mode 100644 index 0000000..bc1a90d --- /dev/null +++ b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lef @@ -0,0 +1,352 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; + +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +MANUFACTURINGGRID 0.005 ; + +LAYER li1 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.17 ; +END li1 + +LAYER mcon + TYPE CUT ; +END mcon + +LAYER met1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.34 ; + WIDTH 0.14 ; +END met1 + +LAYER via + TYPE CUT ; +END via + +LAYER met2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.46 ; + WIDTH 0.14 ; +END met2 + +LAYER via2 + TYPE CUT ; +END via2 + +LAYER met3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 0.68 ; + WIDTH 0.3 ; +END met3 + +LAYER via3 + TYPE CUT ; +END via3 + +LAYER met4 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 0.92 ; + WIDTH 0.3 ; +END met4 + +LAYER via4 + TYPE CUT ; +END via4 + +LAYER met5 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3.4 ; + WIDTH 1.6 ; +END met5 + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER pwell + TYPE MASTERSLICE ; +END pwell + +VIA L1M1_PR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR + +VIA L1M1_PR_R + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_R + +VIA L1M1_PR_M + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.115 -0.145 0.115 0.145 ; +END L1M1_PR_M + +VIA L1M1_PR_MR + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.115 0.145 0.115 ; +END L1M1_PR_MR + +VIA L1M1_PR_C + LAYER li1 ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER mcon ; + RECT -0.085 -0.085 0.085 0.085 ; + LAYER met1 ; + RECT -0.145 -0.145 0.145 0.145 ; +END L1M1_PR_C + +VIA M1M2_PR + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR + +VIA M1M2_PR_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_Enc + +VIA M1M2_PR_R + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_R + +VIA M1M2_PR_R_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_R_Enc + +VIA M1M2_PR_M + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_M + +VIA M1M2_PR_M_Enc + LAYER met1 ; + RECT -0.16 -0.13 0.16 0.13 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_M_Enc + +VIA M1M2_PR_MR + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.13 -0.16 0.13 0.16 ; +END M1M2_PR_MR + +VIA M1M2_PR_MR_Enc + LAYER met1 ; + RECT -0.13 -0.16 0.13 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.13 0.16 0.13 ; +END M1M2_PR_MR_Enc + +VIA M1M2_PR_C + LAYER met1 ; + RECT -0.16 -0.16 0.16 0.16 ; + LAYER via ; + RECT -0.075 -0.075 0.075 0.075 ; + LAYER met2 ; + RECT -0.16 -0.16 0.16 0.16 ; +END M1M2_PR_C + +VIA M2M3_PR + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR + +VIA M2M3_PR_R + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_R + +VIA M2M3_PR_M + LAYER met2 ; + RECT -0.14 -0.185 0.14 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_M + +VIA M2M3_PR_MR + LAYER met2 ; + RECT -0.185 -0.14 0.185 0.14 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_MR + +VIA M2M3_PR_C + LAYER met2 ; + RECT -0.185 -0.185 0.185 0.185 ; + LAYER via2 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met3 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M2M3_PR_C + +VIA M3M4_PR + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR + +VIA M3M4_PR_R + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_R + +VIA M3M4_PR_M + LAYER met3 ; + RECT -0.19 -0.16 0.19 0.16 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_M + +VIA M3M4_PR_MR + LAYER met3 ; + RECT -0.16 -0.19 0.16 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_MR + +VIA M3M4_PR_C + LAYER met3 ; + RECT -0.19 -0.19 0.19 0.19 ; + LAYER via3 ; + RECT -0.1 -0.1 0.1 0.1 ; + LAYER met4 ; + RECT -0.165 -0.165 0.165 0.165 ; +END M3M4_PR_C + +VIA M4M5_PR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR + +VIA M4M5_PR_R + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_R + +VIA M4M5_PR_M + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_M + +VIA M4M5_PR_MR + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_MR + +VIA M4M5_PR_C + LAYER met4 ; + RECT -0.59 -0.59 0.59 0.59 ; + LAYER via4 ; + RECT -0.4 -0.4 0.4 0.4 ; + LAYER met5 ; + RECT -0.71 -0.71 0.71 0.71 ; +END M4M5_PR_C + +SITE unit + CLASS CORE ; + SYMMETRY Y ; + SIZE 0.46 BY 2.72 ; +END unit + +SITE unithddbl + CLASS CORE ; + SIZE 0.46 BY 5.44 ; +END unithddbl + +END LIBRARY diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lvs.v new file mode 100644 index 0000000..308323c --- /dev/null +++ b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lvs.v @@ -0,0 +1,107740 @@ +// +// +// +// +// +// +module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_103 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1347 ( .A ( ropt_net_114 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_106 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_103 ) , + .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_104 ) , + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_113 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ccff_head[0] ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_98 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_101 ) , + .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1345 ( .A ( ropt_net_111 ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( ropt_net_112 ) , + .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_295 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591232 ( .A ( ctsbuf_net_194 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641237 ( .A ( ctsbuf_net_295 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( mem_out[3] ) , + .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_130 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) , + .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) , + .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , + .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( copt_net_123 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign Test_en_S_in = Test_en_E_in ; +assign Test_en_W_in = Test_en_E_in ; +assign Reset_S_in = Reset_E_in ; +assign Reset_W_in = Reset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_N_in = prog_clk_2_S_in ; +assign prog_clk_3_S_in = prog_clk_3_N_in ; +assign clk_2_N_in = clk_2_S_in ; +assign clk_3_S_in = clk_3_N_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_12 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_78 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_78 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_78 ) , + .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , + .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , + .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) , + .X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , + .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , + .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_70 ) , + .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_71 ) , + .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in , + VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_134 ; +wire ropt_net_128 ; +wire ropt_net_129 ; +wire ropt_net_133 ; +wire ropt_net_127 ; +wire ropt_net_122 ; +wire ropt_net_124 ; +wire ropt_net_132 ; +wire ropt_net_123 ; +wire ropt_net_120 ; +wire ropt_net_138 ; +wire ropt_net_125 ; +wire ropt_net_137 ; +wire ropt_net_121 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_120 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_108 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_107 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_101 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1327 ( .A ( ccff_head[0] ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1329 ( .A ( copt_net_102 ) , + .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1333 ( .A ( copt_net_103 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_106 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_104 ) , + .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_105 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; +input VDD ; +input VSS ; + +wire ropt_net_130 ; +wire ropt_net_121 ; +wire ropt_net_132 ; +wire ropt_net_124 ; +wire ropt_net_125 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_W_in = prog_clk_1_E_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_W_in = prog_clk_3_E_in ; +assign clk_1_W_in = clk_1_E_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_W_in = clk_3_E_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_96 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_94 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_108 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_88 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( ZBUF_39_0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_124 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( clk_1_S_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1345 ( .A ( ZBUF_39_0 ) , + .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531232 ( .A ( ctsbuf_net_198 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( ropt_net_133 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1356 ( .A ( copt_net_108 ) , + .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_110 ) , + .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( ropt_net_135 ) , + .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_125 ) , + .X ( COUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1377 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1379 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1380 ( .A ( copt_net_113 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1381 ( .A ( copt_net_112 ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1382 ( .A ( ropt_net_134 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_113 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) , + .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_898_f_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; +input ZBUF_898_f_0 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , + ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_898_f_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_898_f_0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_208_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; +input ZBUF_208_0 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , + ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_208_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_208_0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS , ZBUF_217_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; +input ZBUF_217_0 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , + ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_217_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input ZBUF_217_0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) , + .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) , + .X ( copt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) , + .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) , + .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_12 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_172 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_172 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_172 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_150 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_207 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_166 ) , + .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( ccff_head[0] ) , + .X ( copt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_161 ) , + .X ( copt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_162 ) , + .X ( copt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_163 ) , + .X ( copt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_164 ) , + .X ( copt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1378 ( .A ( copt_net_165 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_205 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( ropt_net_203 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_204 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1382 ( .A ( ropt_net_206 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_144 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; +input VDD ; +input VSS ; + +wire ropt_net_182 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_124 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_125 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_126 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_166 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) , + .X ( copt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) , + .X ( copt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , + .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_168 ) , + .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1337 ( .A ( copt_net_150 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( copt_net_158 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1339 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_164 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_164 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_142 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_148 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_140 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_138 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_136 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_146 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_132 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_128 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_126 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_124 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_156 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_158 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( ccff_head[0] ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( ropt_net_192 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_157 ) , + .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1393 ( .A ( ropt_net_196 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1394 ( .A ( copt_net_159 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_194 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1397 ( .A ( ropt_net_195 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_122 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_144 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; +input VDD ; +input VSS ; + +wire ropt_net_174 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( pReset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( pReset_W_in ) , .Y ( BUF_net_121 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1337 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_147 ) , + .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_150 ) , + .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_148 ) , + .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_149 ) , + .X ( copt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_151 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_182 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_183 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_184 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +input VDD ; +input VSS ; + +wire ropt_net_167 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_145 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , + chanx_right_out[17] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( net_net_139 ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1349 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , + .X ( copt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_172 ) , + .X ( copt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ropt_net_179 ) , + .X ( copt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_173 ) , + .X ( copt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , + .X ( copt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ccff_head[0] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; +input VDD ; +input VSS ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_E_in ; +assign prog_clk_2_S_out = prog_clk_2_E_in ; +assign prog_clk_2_N_out = prog_clk_2_E_in ; +assign prog_clk_2_E_out = prog_clk_2_E_in ; +assign prog_clk_3_E_out = prog_clk_3_E_in ; +assign prog_clk_3_W_out = prog_clk_3_E_in ; +assign prog_clk_3_N_out = prog_clk_3_E_in ; +assign prog_clk_3_S_out = prog_clk_3_E_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_E_in ; +assign clk_2_S_out = clk_2_E_in ; +assign clk_2_N_out = clk_2_E_in ; +assign clk_2_E_out = clk_2_E_in ; +assign clk_3_E_out = clk_3_E_in ; +assign clk_3_W_out = clk_3_E_in ; +assign clk_3_N_out = clk_3_E_in ; +assign clk_3_S_out = clk_3_E_in ; +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_N_in = prog_clk_1_S_in ; +assign prog_clk_2_N_in = prog_clk_2_E_in ; +assign prog_clk_2_S_in = prog_clk_2_E_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_W_in = prog_clk_3_E_in ; +assign prog_clk_3_S_in = prog_clk_3_E_in ; +assign prog_clk_3_N_in = prog_clk_3_E_in ; +assign clk_1_N_in = clk_1_S_in ; +assign clk_2_N_in = clk_2_E_in ; +assign clk_2_S_in = clk_2_E_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_W_in = clk_3_E_in ; +assign clk_3_S_in = clk_3_E_in ; +assign clk_3_N_in = clk_3_E_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( { ropt_net_180 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( { copt_net_170 } ) , + .mem_out ( mux_tree_tapbuf_size6_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 copt_h_inst_1358 ( .A ( copt_net_170 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_155 ) , + .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_157 ) , + .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_152 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( ccff_head[0] ) , + .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_153 ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( copt_net_154 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_156 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_184 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_182 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_183 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; +input VDD ; +input VSS ; + +wire ropt_net_170 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign pReset_S_in = pReset_E_in ; +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_170 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , + .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( Test_en_S_in ) , .Y ( BUF_net_133 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( pReset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( Reset_S_in ) , .Y ( BUF_net_137 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , + .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( clk_3_N_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_170 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_102 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_101 ) , + .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_103 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_99 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_95 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_129 ; +wire ropt_net_127 ; +wire ropt_net_137 ; +wire ropt_net_128 ; +wire ropt_net_134 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_143 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +wire copt_net_164 ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_164 ) , + .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( ccff_head[0] ) , + .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1347 ( .A ( copt_net_158 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1348 ( .A ( ropt_net_177 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1349 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1350 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_168 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , ropt_net_168 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + ropt_net_168 } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1340 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_116 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( mem_out[1] ) , + .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_114 ) , + .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_115 ) , + .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_194 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( ccff_head[0] ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_112 ) , + .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_110 ) , + .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_109 ) , + .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( copt_net_111 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_192 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1358 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in , VDD , VSS ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; +input VDD ; +input VSS ; + +wire ropt_net_139 ; +wire ropt_net_140 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1614 ( .A ( copt_net_198 ) , + .X ( copt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1615 ( .A ( copt_net_195 ) , + .X ( copt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1616 ( .A ( copt_net_199 ) , + .X ( copt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1617 ( .A ( copt_net_197 ) , + .X ( copt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1618 ( .A ( mem_out[1] ) , + .X ( copt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_46 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_45 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_44 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_46 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_45 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_44 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_520_ ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS , p_abuf0 , + p_abuf1 ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_43 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_42 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_43 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_42 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb22 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_43 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_45 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_46 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( p_abuf1 ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , + .p_abuf3 ( p_abuf2 ) , .p0 ( p1 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_41 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_40 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_39 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_38 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_41 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_39 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_37 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_36 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_36 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb19 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_37 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p0 ( p1 ) ) ; +grid_clb_mux_tree_size2_40 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_39 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_40 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_41 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; +input p3 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_35 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_32 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_31 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb16 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p3 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_31 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p0 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_32 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_33 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_34 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_35 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p3 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p0 ; +input p2 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_25 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p2 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_27 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_28 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_29 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p2 ; +input p3 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , + .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_19 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_20 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_21 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_22 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_23 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; +input p4 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_13 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p2 ; +input p4 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_14 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_17 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_15 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_16 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_17 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p2 ; +input p4 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p2 ( p2 ) , + .p4 ( p4 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb4 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_7 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p0 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_9 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_11 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , VDD , VSS , + p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X , VDD , + VSS ) ; +input A0 ; +input A1 ; +input S ; +output X ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout , VDD , VSS ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1607 ( .A ( ccff_head[0] ) , + .X ( copt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1608 ( .A ( copt_net_191 ) , + .X ( copt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1609 ( .A ( copt_net_192 ) , + .X ( copt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1610 ( .A ( copt_net_190 ) , + .X ( copt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1611 ( .A ( copt_net_188 ) , + .X ( copt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1612 ( .A ( copt_net_189 ) , + .X ( copt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1619 ( .A ( copt_net_193 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out , VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p1 ; +input p4 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_1 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , + p_abuf0 , p_abuf1 , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p4 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_2 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_5 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_3 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_4 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_5 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p4 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_clb_ ( pReset , prog_clk , Test_en , + clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , + clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , + clb_I7 , clb_I7i , clb_reg_in , clb_sc_in , clb_cin , clb_reset , + clb_clk , ccff_head , clb_O , clb_reg_out , clb_sc_out , clb_cout , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , + p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , + p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , + p4 , p5 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:1] clb_I0 ; +input [0:1] clb_I0i ; +input [0:1] clb_I1 ; +input [0:1] clb_I1i ; +input [0:1] clb_I2 ; +input [0:1] clb_I2i ; +input [0:1] clb_I3 ; +input [0:1] clb_I3i ; +input [0:1] clb_I4 ; +input [0:1] clb_I4i ; +input [0:1] clb_I5 ; +input [0:1] clb_I5i ; +input [0:1] clb_I6 ; +input [0:1] clb_I6i ; +input [0:1] clb_I7 ; +input [0:1] clb_I7i ; +input [0:0] clb_reg_in ; +input [0:0] clb_sc_in ; +input [0:0] clb_cin ; +input [0:0] clb_reset ; +input [0:0] clb_clk ; +input [0:0] ccff_head ; +output [0:15] clb_O ; +output [0:0] clb_reg_out ; +output [0:0] clb_sc_out ; +output [0:0] clb_cout ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; +output p_abuf7 ; +output p_abuf8 ; +output p_abuf9 ; +output p_abuf10 ; +output p_abuf11 ; +output p_abuf12 ; +output p_abuf13 ; +output p_abuf14 ; +output p_abuf15 ; +output p_abuf16 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; +input p4 ; +input p5 ; + +wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_86_out ; +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) , + .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( ccff_head ) , + .fle_out ( { clb_O[1] , clb_O[0] } ) , + .fle_reg_out ( direct_interc_32_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , + .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , + .fle_reg_in ( direct_interc_32_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , + .fle_reg_out ( direct_interc_41_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , + .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , + .fle_reg_in ( direct_interc_41_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .fle_out ( { clb_O[5] , clb_O[4] } ) , + .fle_reg_out ( direct_interc_50_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf5 ) , + .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , + .fle_reg_in ( direct_interc_50_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { clb_O[7] , clb_O[6] } ) , + .fle_reg_out ( direct_interc_59_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf7 ) , + .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , + .fle_reg_in ( direct_interc_59_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .fle_out ( { clb_O[9] , clb_O[8] } ) , + .fle_reg_out ( direct_interc_68_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf9 ) , + .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , + .fle_reg_in ( direct_interc_68_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .fle_out ( { clb_O[11] , clb_O[10] } ) , + .fle_reg_out ( direct_interc_77_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , + .p_abuf1 ( p_abuf12 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , + .fle_reg_in ( direct_interc_77_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .fle_out ( { clb_O[13] , clb_O[12] } ) , + .fle_reg_out ( direct_interc_86_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf13 ) , + .p_abuf1 ( p_abuf14 ) , .p0 ( p0 ) , .p1 ( p1 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , + .fle_reg_in ( direct_interc_86_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , + .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf15 ) , + .p_abuf2 ( p_abuf16 ) , .p1 ( p1 ) ) ; +endmodule + + +module grid_clb ( pReset , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , + top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , + top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , + top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , + top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , top_width_0_height_0__pin_34_ , + right_width_0_height_0__pin_16_ , right_width_0_height_0__pin_17_ , + right_width_0_height_0__pin_18_ , right_width_0_height_0__pin_19_ , + right_width_0_height_0__pin_20_ , right_width_0_height_0__pin_21_ , + right_width_0_height_0__pin_22_ , right_width_0_height_0__pin_23_ , + right_width_0_height_0__pin_24_ , right_width_0_height_0__pin_25_ , + right_width_0_height_0__pin_26_ , right_width_0_height_0__pin_27_ , + right_width_0_height_0__pin_28_ , right_width_0_height_0__pin_29_ , + right_width_0_height_0__pin_30_ , right_width_0_height_0__pin_31_ , + Reset , ccff_head , top_width_0_height_0__pin_36_upper , + top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , + top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , + top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , + top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , + top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , + top_width_0_height_0__pin_41_lower , top_width_0_height_0__pin_42_upper , + top_width_0_height_0__pin_42_lower , top_width_0_height_0__pin_43_upper , + top_width_0_height_0__pin_43_lower , + right_width_0_height_0__pin_44_upper , + right_width_0_height_0__pin_44_lower , + right_width_0_height_0__pin_45_upper , + right_width_0_height_0__pin_45_lower , + right_width_0_height_0__pin_46_upper , + right_width_0_height_0__pin_46_lower , + right_width_0_height_0__pin_47_upper , + right_width_0_height_0__pin_47_lower , + right_width_0_height_0__pin_48_upper , + right_width_0_height_0__pin_48_lower , + right_width_0_height_0__pin_49_upper , + right_width_0_height_0__pin_49_lower , + right_width_0_height_0__pin_50_upper , + right_width_0_height_0__pin_50_lower , + right_width_0_height_0__pin_51_upper , + right_width_0_height_0__pin_51_lower , bottom_width_0_height_0__pin_52_ , + bottom_width_0_height_0__pin_53_ , bottom_width_0_height_0__pin_54_ , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + Test_en_E_in , Test_en_W_in , Test_en_W_out , Test_en_E_out , + pReset_N_in , Reset_E_in , Reset_W_in , Reset_W_out , Reset_E_out , + prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out , prog_clk_0_E_out , + prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in , VDD , + VSS ) ; +input [0:0] pReset ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_1_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_3_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_5_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_7_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_9_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_11_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_13_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_15_ ; +input [0:0] top_width_0_height_0__pin_32_ ; +input [0:0] top_width_0_height_0__pin_33_ ; +input [0:0] top_width_0_height_0__pin_34_ ; +input [0:0] right_width_0_height_0__pin_16_ ; +input [0:0] right_width_0_height_0__pin_17_ ; +input [0:0] right_width_0_height_0__pin_18_ ; +input [0:0] right_width_0_height_0__pin_19_ ; +input [0:0] right_width_0_height_0__pin_20_ ; +input [0:0] right_width_0_height_0__pin_21_ ; +input [0:0] right_width_0_height_0__pin_22_ ; +input [0:0] right_width_0_height_0__pin_23_ ; +input [0:0] right_width_0_height_0__pin_24_ ; +input [0:0] right_width_0_height_0__pin_25_ ; +input [0:0] right_width_0_height_0__pin_26_ ; +input [0:0] right_width_0_height_0__pin_27_ ; +input [0:0] right_width_0_height_0__pin_28_ ; +input [0:0] right_width_0_height_0__pin_29_ ; +input [0:0] right_width_0_height_0__pin_30_ ; +input [0:0] right_width_0_height_0__pin_31_ ; +input [0:0] Reset ; +input [0:0] ccff_head ; +output [0:0] top_width_0_height_0__pin_36_upper ; +output [0:0] top_width_0_height_0__pin_36_lower ; +output [0:0] top_width_0_height_0__pin_37_upper ; +output [0:0] top_width_0_height_0__pin_37_lower ; +output [0:0] top_width_0_height_0__pin_38_upper ; +output [0:0] top_width_0_height_0__pin_38_lower ; +output [0:0] top_width_0_height_0__pin_39_upper ; +output [0:0] top_width_0_height_0__pin_39_lower ; +output [0:0] top_width_0_height_0__pin_40_upper ; +output [0:0] top_width_0_height_0__pin_40_lower ; +output [0:0] top_width_0_height_0__pin_41_upper ; +output [0:0] top_width_0_height_0__pin_41_lower ; +output [0:0] top_width_0_height_0__pin_42_upper ; +output [0:0] top_width_0_height_0__pin_42_lower ; +output [0:0] top_width_0_height_0__pin_43_upper ; +output [0:0] top_width_0_height_0__pin_43_lower ; +output [0:0] right_width_0_height_0__pin_44_upper ; +output [0:0] right_width_0_height_0__pin_44_lower ; +output [0:0] right_width_0_height_0__pin_45_upper ; +output [0:0] right_width_0_height_0__pin_45_lower ; +output [0:0] right_width_0_height_0__pin_46_upper ; +output [0:0] right_width_0_height_0__pin_46_lower ; +output [0:0] right_width_0_height_0__pin_47_upper ; +output [0:0] right_width_0_height_0__pin_47_lower ; +output [0:0] right_width_0_height_0__pin_48_upper ; +output [0:0] right_width_0_height_0__pin_48_lower ; +output [0:0] right_width_0_height_0__pin_49_upper ; +output [0:0] right_width_0_height_0__pin_49_lower ; +output [0:0] right_width_0_height_0__pin_50_upper ; +output [0:0] right_width_0_height_0__pin_50_lower ; +output [0:0] right_width_0_height_0__pin_51_upper ; +output [0:0] right_width_0_height_0__pin_51_lower ; +output [0:0] bottom_width_0_height_0__pin_52_ ; +output [0:0] bottom_width_0_height_0__pin_53_ ; +output [0:0] bottom_width_0_height_0__pin_54_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_N_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_N_in ; +input prog_clk_0_S_in ; +output prog_clk_0_S_out ; +output prog_clk_0_E_out ; +output prog_clk_0_W_out ; +output prog_clk_0_N_out ; +input clk_0_N_in ; +input clk_0_S_in ; +input VDD ; +input VSS ; + +wire p_abuf12 ; +wire p_abuf11 ; +wire p_abuf16 ; +wire prog_clk_0 ; +wire [0:0] prog_clk ; +wire [0:0] clk ; +wire clk_0 ; +wire [0:0] Test_en ; +supply1 VDD ; +supply0 VSS ; + +assign SC_IN_TOP = SC_IN_BOT ; +assign Test_en_E_in = Test_en_W_in ; +assign Reset_E_in = Reset_W_in ; +assign prog_clk[0] = prog_clk_0 ; +assign prog_clk_0_N_in = prog_clk_0_S_in ; +assign clk_0 = clk[0] ; +assign clk_0_N_in = clk_0_S_in ; + +grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .pReset ( pReset ) , + .prog_clk ( { prog_clk_0 } ) , + .Test_en ( Test_en ) , + .clb_I0 ( { top_width_0_height_0__pin_0_[0] , + top_width_0_height_0__pin_1_[0] } ) , + .clb_I0i ( { top_width_0_height_0__pin_2_[0] , + top_width_0_height_0__pin_3_[0] } ) , + .clb_I1 ( { top_width_0_height_0__pin_4_[0] , + top_width_0_height_0__pin_5_[0] } ) , + .clb_I1i ( { top_width_0_height_0__pin_6_[0] , + top_width_0_height_0__pin_7_[0] } ) , + .clb_I2 ( { top_width_0_height_0__pin_8_[0] , + top_width_0_height_0__pin_9_[0] } ) , + .clb_I2i ( { top_width_0_height_0__pin_10_[0] , + top_width_0_height_0__pin_11_[0] } ) , + .clb_I3 ( { top_width_0_height_0__pin_12_[0] , + top_width_0_height_0__pin_13_[0] } ) , + .clb_I3i ( { top_width_0_height_0__pin_14_[0] , + top_width_0_height_0__pin_15_[0] } ) , + .clb_I4 ( { right_width_0_height_0__pin_16_[0] , + right_width_0_height_0__pin_17_[0] } ) , + .clb_I4i ( { right_width_0_height_0__pin_18_[0] , + right_width_0_height_0__pin_19_[0] } ) , + .clb_I5 ( { right_width_0_height_0__pin_20_[0] , + right_width_0_height_0__pin_21_[0] } ) , + .clb_I5i ( { right_width_0_height_0__pin_22_[0] , + right_width_0_height_0__pin_23_[0] } ) , + .clb_I6 ( { right_width_0_height_0__pin_24_[0] , + right_width_0_height_0__pin_25_[0] } ) , + .clb_I6i ( { right_width_0_height_0__pin_26_[0] , + right_width_0_height_0__pin_27_[0] } ) , + .clb_I7 ( { right_width_0_height_0__pin_28_[0] , + right_width_0_height_0__pin_29_[0] } ) , + .clb_I7i ( { right_width_0_height_0__pin_30_[0] , + right_width_0_height_0__pin_31_[0] } ) , + .clb_reg_in ( top_width_0_height_0__pin_32_ ) , + .clb_sc_in ( { SC_IN_BOT } ) , + .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_522_ , aps_rename_523_ , aps_rename_524_ , + aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , + aps_rename_528_ , aps_rename_529_ , aps_rename_530_ , + aps_rename_531_ , right_width_0_height_0__pin_46_lower[0] , + right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , + aps_rename_535_ , right_width_0_height_0__pin_50_lower[0] , + aps_rename_537_ } ) , + .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , + .clb_sc_out ( { aps_rename_538_ } ) , + .clb_cout ( bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( SC_OUT_BOT ) , + .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , + .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , + .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , + .p_abuf4 ( top_width_0_height_0__pin_38_lower[0] ) , + .p_abuf5 ( top_width_0_height_0__pin_41_lower[0] ) , + .p_abuf6 ( top_width_0_height_0__pin_40_lower[0] ) , + .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) , + .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) , + .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) , + .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) , + .p_abuf11 ( p_abuf11 ) , .p_abuf12 ( p_abuf12 ) , + .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , + .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , + .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_178 ) , .p1 ( optlc_net_179 ) , + .p2 ( optlc_net_180 ) , .p3 ( optlc_net_181 ) , .p4 ( optlc_net_182 ) , + .p5 ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , + .X ( Test_en[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_539_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_540_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_541_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_542_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_4187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , + .X ( top_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_523_ ) , + .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_524_ ) , + .X ( top_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_525_ ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_526_ ) , + .X ( top_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_527_ ) , + .X ( top_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_528_ ) , + .X ( top_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_529_ ) , + .X ( top_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_530_ ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_531_ ) , + .X ( right_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , + .X ( right_width_0_height_0__pin_46_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_534_ ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_535_ ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) , + .X ( right_width_0_height_0__pin_50_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , + .X ( right_width_0_height_0__pin_51_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , + .Y ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_539_ ) , + .Y ( BUF_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , + .Y ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_W_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_542_ ) , + .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3981324 ( .A ( ctsbuf_net_1184 ) , + .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_4031329 ( .A ( ctsbuf_net_2185 ) , + .X ( prog_clk_0_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_4081334 ( .A ( ctsbuf_net_3186 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_4131339 ( .A ( ctsbuf_net_4187 ) , + .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head , + sc_tail , VDD , VSS , h_incr0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] IO_ISOL_N ; +input [0:0] clk ; +input [0:0] Reset ; +input [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +input sc_head ; +output sc_tail ; +input VDD ; +input VSS ; +input h_incr0 ; + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:29] cbx_1__0__0_chanx_left_out ; +wire [0:29] cbx_1__0__0_chanx_right_out ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__10_ccff_tail ; +wire [0:29] cbx_1__0__10_chanx_left_out ; +wire [0:29] cbx_1__0__10_chanx_right_out ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__11_ccff_tail ; +wire [0:29] cbx_1__0__11_chanx_left_out ; +wire [0:29] cbx_1__0__11_chanx_right_out ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:29] cbx_1__0__1_chanx_left_out ; +wire [0:29] cbx_1__0__1_chanx_right_out ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__2_ccff_tail ; +wire [0:29] cbx_1__0__2_chanx_left_out ; +wire [0:29] cbx_1__0__2_chanx_right_out ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__3_ccff_tail ; +wire [0:29] cbx_1__0__3_chanx_left_out ; +wire [0:29] cbx_1__0__3_chanx_right_out ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__4_ccff_tail ; +wire [0:29] cbx_1__0__4_chanx_left_out ; +wire [0:29] cbx_1__0__4_chanx_right_out ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__5_ccff_tail ; +wire [0:29] cbx_1__0__5_chanx_left_out ; +wire [0:29] cbx_1__0__5_chanx_right_out ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__6_ccff_tail ; +wire [0:29] cbx_1__0__6_chanx_left_out ; +wire [0:29] cbx_1__0__6_chanx_right_out ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__7_ccff_tail ; +wire [0:29] cbx_1__0__7_chanx_left_out ; +wire [0:29] cbx_1__0__7_chanx_right_out ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__8_ccff_tail ; +wire [0:29] cbx_1__0__8_chanx_left_out ; +wire [0:29] cbx_1__0__8_chanx_right_out ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__9_ccff_tail ; +wire [0:29] cbx_1__0__9_chanx_left_out ; +wire [0:29] cbx_1__0__9_chanx_right_out ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__0_ccff_tail ; +wire [0:29] cbx_1__12__0_chanx_left_out ; +wire [0:29] cbx_1__12__0_chanx_right_out ; +wire [0:0] cbx_1__12__0_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__10_ccff_tail ; +wire [0:29] cbx_1__12__10_chanx_left_out ; +wire [0:29] cbx_1__12__10_chanx_right_out ; +wire [0:0] cbx_1__12__10_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__11_ccff_tail ; +wire [0:29] cbx_1__12__11_chanx_left_out ; +wire [0:29] cbx_1__12__11_chanx_right_out ; +wire [0:0] cbx_1__12__11_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__1_ccff_tail ; +wire [0:29] cbx_1__12__1_chanx_left_out ; +wire [0:29] cbx_1__12__1_chanx_right_out ; +wire [0:0] cbx_1__12__1_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__2_ccff_tail ; +wire [0:29] cbx_1__12__2_chanx_left_out ; +wire [0:29] cbx_1__12__2_chanx_right_out ; +wire [0:0] cbx_1__12__2_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__3_ccff_tail ; +wire [0:29] cbx_1__12__3_chanx_left_out ; +wire [0:29] cbx_1__12__3_chanx_right_out ; +wire [0:0] cbx_1__12__3_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__4_ccff_tail ; +wire [0:29] cbx_1__12__4_chanx_left_out ; +wire [0:29] cbx_1__12__4_chanx_right_out ; +wire [0:0] cbx_1__12__4_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__5_ccff_tail ; +wire [0:29] cbx_1__12__5_chanx_left_out ; +wire [0:29] cbx_1__12__5_chanx_right_out ; +wire [0:0] cbx_1__12__5_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__6_ccff_tail ; +wire [0:29] cbx_1__12__6_chanx_left_out ; +wire [0:29] cbx_1__12__6_chanx_right_out ; +wire [0:0] cbx_1__12__6_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__7_ccff_tail ; +wire [0:29] cbx_1__12__7_chanx_left_out ; +wire [0:29] cbx_1__12__7_chanx_right_out ; +wire [0:0] cbx_1__12__7_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__8_ccff_tail ; +wire [0:29] cbx_1__12__8_chanx_left_out ; +wire [0:29] cbx_1__12__8_chanx_right_out ; +wire [0:0] cbx_1__12__8_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__9_ccff_tail ; +wire [0:29] cbx_1__12__9_chanx_left_out ; +wire [0:29] cbx_1__12__9_chanx_right_out ; +wire [0:0] cbx_1__12__9_top_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__0_ccff_tail ; +wire [0:29] cbx_1__1__0_chanx_left_out ; +wire [0:29] cbx_1__1__0_chanx_right_out ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__100_ccff_tail ; +wire [0:29] cbx_1__1__100_chanx_left_out ; +wire [0:29] cbx_1__1__100_chanx_right_out ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__101_ccff_tail ; +wire [0:29] cbx_1__1__101_chanx_left_out ; +wire [0:29] cbx_1__1__101_chanx_right_out ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__102_ccff_tail ; +wire [0:29] cbx_1__1__102_chanx_left_out ; +wire [0:29] cbx_1__1__102_chanx_right_out ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__103_ccff_tail ; +wire [0:29] cbx_1__1__103_chanx_left_out ; +wire [0:29] cbx_1__1__103_chanx_right_out ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__104_ccff_tail ; +wire [0:29] cbx_1__1__104_chanx_left_out ; +wire [0:29] cbx_1__1__104_chanx_right_out ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__105_ccff_tail ; +wire [0:29] cbx_1__1__105_chanx_left_out ; +wire [0:29] cbx_1__1__105_chanx_right_out ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__106_ccff_tail ; +wire [0:29] cbx_1__1__106_chanx_left_out ; +wire [0:29] cbx_1__1__106_chanx_right_out ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__107_ccff_tail ; +wire [0:29] cbx_1__1__107_chanx_left_out ; +wire [0:29] cbx_1__1__107_chanx_right_out ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__108_ccff_tail ; +wire [0:29] cbx_1__1__108_chanx_left_out ; +wire [0:29] cbx_1__1__108_chanx_right_out ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__109_ccff_tail ; +wire [0:29] cbx_1__1__109_chanx_left_out ; +wire [0:29] cbx_1__1__109_chanx_right_out ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__10_ccff_tail ; +wire [0:29] cbx_1__1__10_chanx_left_out ; +wire [0:29] cbx_1__1__10_chanx_right_out ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__110_ccff_tail ; +wire [0:29] cbx_1__1__110_chanx_left_out ; +wire [0:29] cbx_1__1__110_chanx_right_out ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__111_ccff_tail ; +wire [0:29] cbx_1__1__111_chanx_left_out ; +wire [0:29] cbx_1__1__111_chanx_right_out ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__112_ccff_tail ; +wire [0:29] cbx_1__1__112_chanx_left_out ; +wire [0:29] cbx_1__1__112_chanx_right_out ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__113_ccff_tail ; +wire [0:29] cbx_1__1__113_chanx_left_out ; +wire [0:29] cbx_1__1__113_chanx_right_out ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__114_ccff_tail ; +wire [0:29] cbx_1__1__114_chanx_left_out ; +wire [0:29] cbx_1__1__114_chanx_right_out ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__115_ccff_tail ; +wire [0:29] cbx_1__1__115_chanx_left_out ; +wire [0:29] cbx_1__1__115_chanx_right_out ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__116_ccff_tail ; +wire [0:29] cbx_1__1__116_chanx_left_out ; +wire [0:29] cbx_1__1__116_chanx_right_out ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__117_ccff_tail ; +wire [0:29] cbx_1__1__117_chanx_left_out ; +wire [0:29] cbx_1__1__117_chanx_right_out ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__118_ccff_tail ; +wire [0:29] cbx_1__1__118_chanx_left_out ; +wire [0:29] cbx_1__1__118_chanx_right_out ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__119_ccff_tail ; +wire [0:29] cbx_1__1__119_chanx_left_out ; +wire [0:29] cbx_1__1__119_chanx_right_out ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__11_ccff_tail ; +wire [0:29] cbx_1__1__11_chanx_left_out ; +wire [0:29] cbx_1__1__11_chanx_right_out ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__120_ccff_tail ; +wire [0:29] cbx_1__1__120_chanx_left_out ; +wire [0:29] cbx_1__1__120_chanx_right_out ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__121_ccff_tail ; +wire [0:29] cbx_1__1__121_chanx_left_out ; +wire [0:29] cbx_1__1__121_chanx_right_out ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__122_ccff_tail ; +wire [0:29] cbx_1__1__122_chanx_left_out ; +wire [0:29] cbx_1__1__122_chanx_right_out ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__123_ccff_tail ; +wire [0:29] cbx_1__1__123_chanx_left_out ; +wire [0:29] cbx_1__1__123_chanx_right_out ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__124_ccff_tail ; +wire [0:29] cbx_1__1__124_chanx_left_out ; +wire [0:29] cbx_1__1__124_chanx_right_out ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__125_ccff_tail ; +wire [0:29] cbx_1__1__125_chanx_left_out ; +wire [0:29] cbx_1__1__125_chanx_right_out ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__126_ccff_tail ; +wire [0:29] cbx_1__1__126_chanx_left_out ; +wire [0:29] cbx_1__1__126_chanx_right_out ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__127_ccff_tail ; +wire [0:29] cbx_1__1__127_chanx_left_out ; +wire [0:29] cbx_1__1__127_chanx_right_out ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__128_ccff_tail ; +wire [0:29] cbx_1__1__128_chanx_left_out ; +wire [0:29] cbx_1__1__128_chanx_right_out ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__129_ccff_tail ; +wire [0:29] cbx_1__1__129_chanx_left_out ; +wire [0:29] cbx_1__1__129_chanx_right_out ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__12_ccff_tail ; +wire [0:29] cbx_1__1__12_chanx_left_out ; +wire [0:29] cbx_1__1__12_chanx_right_out ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__130_ccff_tail ; +wire [0:29] cbx_1__1__130_chanx_left_out ; +wire [0:29] cbx_1__1__130_chanx_right_out ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__131_ccff_tail ; +wire [0:29] cbx_1__1__131_chanx_left_out ; +wire [0:29] cbx_1__1__131_chanx_right_out ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__13_ccff_tail ; +wire [0:29] cbx_1__1__13_chanx_left_out ; +wire [0:29] cbx_1__1__13_chanx_right_out ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__14_ccff_tail ; +wire [0:29] cbx_1__1__14_chanx_left_out ; +wire [0:29] cbx_1__1__14_chanx_right_out ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__15_ccff_tail ; +wire [0:29] cbx_1__1__15_chanx_left_out ; +wire [0:29] cbx_1__1__15_chanx_right_out ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__16_ccff_tail ; +wire [0:29] cbx_1__1__16_chanx_left_out ; +wire [0:29] cbx_1__1__16_chanx_right_out ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__17_ccff_tail ; +wire [0:29] cbx_1__1__17_chanx_left_out ; +wire [0:29] cbx_1__1__17_chanx_right_out ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__18_ccff_tail ; +wire [0:29] cbx_1__1__18_chanx_left_out ; +wire [0:29] cbx_1__1__18_chanx_right_out ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__19_ccff_tail ; +wire [0:29] cbx_1__1__19_chanx_left_out ; +wire [0:29] cbx_1__1__19_chanx_right_out ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__1_ccff_tail ; +wire [0:29] cbx_1__1__1_chanx_left_out ; +wire [0:29] cbx_1__1__1_chanx_right_out ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__20_ccff_tail ; +wire [0:29] cbx_1__1__20_chanx_left_out ; +wire [0:29] cbx_1__1__20_chanx_right_out ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__21_ccff_tail ; +wire [0:29] cbx_1__1__21_chanx_left_out ; +wire [0:29] cbx_1__1__21_chanx_right_out ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__22_ccff_tail ; +wire [0:29] cbx_1__1__22_chanx_left_out ; +wire [0:29] cbx_1__1__22_chanx_right_out ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__23_ccff_tail ; +wire [0:29] cbx_1__1__23_chanx_left_out ; +wire [0:29] cbx_1__1__23_chanx_right_out ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__24_ccff_tail ; +wire [0:29] cbx_1__1__24_chanx_left_out ; +wire [0:29] cbx_1__1__24_chanx_right_out ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__25_ccff_tail ; +wire [0:29] cbx_1__1__25_chanx_left_out ; +wire [0:29] cbx_1__1__25_chanx_right_out ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__26_ccff_tail ; +wire [0:29] cbx_1__1__26_chanx_left_out ; +wire [0:29] cbx_1__1__26_chanx_right_out ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__27_ccff_tail ; +wire [0:29] cbx_1__1__27_chanx_left_out ; +wire [0:29] cbx_1__1__27_chanx_right_out ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__28_ccff_tail ; +wire [0:29] cbx_1__1__28_chanx_left_out ; +wire [0:29] cbx_1__1__28_chanx_right_out ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__29_ccff_tail ; +wire [0:29] cbx_1__1__29_chanx_left_out ; +wire [0:29] cbx_1__1__29_chanx_right_out ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__2_ccff_tail ; +wire [0:29] cbx_1__1__2_chanx_left_out ; +wire [0:29] cbx_1__1__2_chanx_right_out ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__30_ccff_tail ; +wire [0:29] cbx_1__1__30_chanx_left_out ; +wire [0:29] cbx_1__1__30_chanx_right_out ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__31_ccff_tail ; +wire [0:29] cbx_1__1__31_chanx_left_out ; +wire [0:29] cbx_1__1__31_chanx_right_out ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__32_ccff_tail ; +wire [0:29] cbx_1__1__32_chanx_left_out ; +wire [0:29] cbx_1__1__32_chanx_right_out ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__33_ccff_tail ; +wire [0:29] cbx_1__1__33_chanx_left_out ; +wire [0:29] cbx_1__1__33_chanx_right_out ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__34_ccff_tail ; +wire [0:29] cbx_1__1__34_chanx_left_out ; +wire [0:29] cbx_1__1__34_chanx_right_out ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__35_ccff_tail ; +wire [0:29] cbx_1__1__35_chanx_left_out ; +wire [0:29] cbx_1__1__35_chanx_right_out ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__36_ccff_tail ; +wire [0:29] cbx_1__1__36_chanx_left_out ; +wire [0:29] cbx_1__1__36_chanx_right_out ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__37_ccff_tail ; +wire [0:29] cbx_1__1__37_chanx_left_out ; +wire [0:29] cbx_1__1__37_chanx_right_out ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__38_ccff_tail ; +wire [0:29] cbx_1__1__38_chanx_left_out ; +wire [0:29] cbx_1__1__38_chanx_right_out ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__39_ccff_tail ; +wire [0:29] cbx_1__1__39_chanx_left_out ; +wire [0:29] cbx_1__1__39_chanx_right_out ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__3_ccff_tail ; +wire [0:29] cbx_1__1__3_chanx_left_out ; +wire [0:29] cbx_1__1__3_chanx_right_out ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__40_ccff_tail ; +wire [0:29] cbx_1__1__40_chanx_left_out ; +wire [0:29] cbx_1__1__40_chanx_right_out ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__41_ccff_tail ; +wire [0:29] cbx_1__1__41_chanx_left_out ; +wire [0:29] cbx_1__1__41_chanx_right_out ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__42_ccff_tail ; +wire [0:29] cbx_1__1__42_chanx_left_out ; +wire [0:29] cbx_1__1__42_chanx_right_out ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__43_ccff_tail ; +wire [0:29] cbx_1__1__43_chanx_left_out ; +wire [0:29] cbx_1__1__43_chanx_right_out ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__44_ccff_tail ; +wire [0:29] cbx_1__1__44_chanx_left_out ; +wire [0:29] cbx_1__1__44_chanx_right_out ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__45_ccff_tail ; +wire [0:29] cbx_1__1__45_chanx_left_out ; +wire [0:29] cbx_1__1__45_chanx_right_out ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__46_ccff_tail ; +wire [0:29] cbx_1__1__46_chanx_left_out ; +wire [0:29] cbx_1__1__46_chanx_right_out ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__47_ccff_tail ; +wire [0:29] cbx_1__1__47_chanx_left_out ; +wire [0:29] cbx_1__1__47_chanx_right_out ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__48_ccff_tail ; +wire [0:29] cbx_1__1__48_chanx_left_out ; +wire [0:29] cbx_1__1__48_chanx_right_out ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__49_ccff_tail ; +wire [0:29] cbx_1__1__49_chanx_left_out ; +wire [0:29] cbx_1__1__49_chanx_right_out ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__4_ccff_tail ; +wire [0:29] cbx_1__1__4_chanx_left_out ; +wire [0:29] cbx_1__1__4_chanx_right_out ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__50_ccff_tail ; +wire [0:29] cbx_1__1__50_chanx_left_out ; +wire [0:29] cbx_1__1__50_chanx_right_out ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__51_ccff_tail ; +wire [0:29] cbx_1__1__51_chanx_left_out ; +wire [0:29] cbx_1__1__51_chanx_right_out ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__52_ccff_tail ; +wire [0:29] cbx_1__1__52_chanx_left_out ; +wire [0:29] cbx_1__1__52_chanx_right_out ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__53_ccff_tail ; +wire [0:29] cbx_1__1__53_chanx_left_out ; +wire [0:29] cbx_1__1__53_chanx_right_out ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__54_ccff_tail ; +wire [0:29] cbx_1__1__54_chanx_left_out ; +wire [0:29] cbx_1__1__54_chanx_right_out ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__55_ccff_tail ; +wire [0:29] cbx_1__1__55_chanx_left_out ; +wire [0:29] cbx_1__1__55_chanx_right_out ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__56_ccff_tail ; +wire [0:29] cbx_1__1__56_chanx_left_out ; +wire [0:29] cbx_1__1__56_chanx_right_out ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__57_ccff_tail ; +wire [0:29] cbx_1__1__57_chanx_left_out ; +wire [0:29] cbx_1__1__57_chanx_right_out ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__58_ccff_tail ; +wire [0:29] cbx_1__1__58_chanx_left_out ; +wire [0:29] cbx_1__1__58_chanx_right_out ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__59_ccff_tail ; +wire [0:29] cbx_1__1__59_chanx_left_out ; +wire [0:29] cbx_1__1__59_chanx_right_out ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__5_ccff_tail ; +wire [0:29] cbx_1__1__5_chanx_left_out ; +wire [0:29] cbx_1__1__5_chanx_right_out ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__60_ccff_tail ; +wire [0:29] cbx_1__1__60_chanx_left_out ; +wire [0:29] cbx_1__1__60_chanx_right_out ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__61_ccff_tail ; +wire [0:29] cbx_1__1__61_chanx_left_out ; +wire [0:29] cbx_1__1__61_chanx_right_out ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__62_ccff_tail ; +wire [0:29] cbx_1__1__62_chanx_left_out ; +wire [0:29] cbx_1__1__62_chanx_right_out ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__63_ccff_tail ; +wire [0:29] cbx_1__1__63_chanx_left_out ; +wire [0:29] cbx_1__1__63_chanx_right_out ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__64_ccff_tail ; +wire [0:29] cbx_1__1__64_chanx_left_out ; +wire [0:29] cbx_1__1__64_chanx_right_out ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__65_ccff_tail ; +wire [0:29] cbx_1__1__65_chanx_left_out ; +wire [0:29] cbx_1__1__65_chanx_right_out ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__66_ccff_tail ; +wire [0:29] cbx_1__1__66_chanx_left_out ; +wire [0:29] cbx_1__1__66_chanx_right_out ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__67_ccff_tail ; +wire [0:29] cbx_1__1__67_chanx_left_out ; +wire [0:29] cbx_1__1__67_chanx_right_out ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__68_ccff_tail ; +wire [0:29] cbx_1__1__68_chanx_left_out ; +wire [0:29] cbx_1__1__68_chanx_right_out ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__69_ccff_tail ; +wire [0:29] cbx_1__1__69_chanx_left_out ; +wire [0:29] cbx_1__1__69_chanx_right_out ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__6_ccff_tail ; +wire [0:29] cbx_1__1__6_chanx_left_out ; +wire [0:29] cbx_1__1__6_chanx_right_out ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__70_ccff_tail ; +wire [0:29] cbx_1__1__70_chanx_left_out ; +wire [0:29] cbx_1__1__70_chanx_right_out ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__71_ccff_tail ; +wire [0:29] cbx_1__1__71_chanx_left_out ; +wire [0:29] cbx_1__1__71_chanx_right_out ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__72_ccff_tail ; +wire [0:29] cbx_1__1__72_chanx_left_out ; +wire [0:29] cbx_1__1__72_chanx_right_out ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__73_ccff_tail ; +wire [0:29] cbx_1__1__73_chanx_left_out ; +wire [0:29] cbx_1__1__73_chanx_right_out ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__74_ccff_tail ; +wire [0:29] cbx_1__1__74_chanx_left_out ; +wire [0:29] cbx_1__1__74_chanx_right_out ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__75_ccff_tail ; +wire [0:29] cbx_1__1__75_chanx_left_out ; +wire [0:29] cbx_1__1__75_chanx_right_out ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__76_ccff_tail ; +wire [0:29] cbx_1__1__76_chanx_left_out ; +wire [0:29] cbx_1__1__76_chanx_right_out ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__77_ccff_tail ; +wire [0:29] cbx_1__1__77_chanx_left_out ; +wire [0:29] cbx_1__1__77_chanx_right_out ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__78_ccff_tail ; +wire [0:29] cbx_1__1__78_chanx_left_out ; +wire [0:29] cbx_1__1__78_chanx_right_out ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__79_ccff_tail ; +wire [0:29] cbx_1__1__79_chanx_left_out ; +wire [0:29] cbx_1__1__79_chanx_right_out ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__7_ccff_tail ; +wire [0:29] cbx_1__1__7_chanx_left_out ; +wire [0:29] cbx_1__1__7_chanx_right_out ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__80_ccff_tail ; +wire [0:29] cbx_1__1__80_chanx_left_out ; +wire [0:29] cbx_1__1__80_chanx_right_out ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__81_ccff_tail ; +wire [0:29] cbx_1__1__81_chanx_left_out ; +wire [0:29] cbx_1__1__81_chanx_right_out ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__82_ccff_tail ; +wire [0:29] cbx_1__1__82_chanx_left_out ; +wire [0:29] cbx_1__1__82_chanx_right_out ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__83_ccff_tail ; +wire [0:29] cbx_1__1__83_chanx_left_out ; +wire [0:29] cbx_1__1__83_chanx_right_out ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__84_ccff_tail ; +wire [0:29] cbx_1__1__84_chanx_left_out ; +wire [0:29] cbx_1__1__84_chanx_right_out ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__85_ccff_tail ; +wire [0:29] cbx_1__1__85_chanx_left_out ; +wire [0:29] cbx_1__1__85_chanx_right_out ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__86_ccff_tail ; +wire [0:29] cbx_1__1__86_chanx_left_out ; +wire [0:29] cbx_1__1__86_chanx_right_out ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__87_ccff_tail ; +wire [0:29] cbx_1__1__87_chanx_left_out ; +wire [0:29] cbx_1__1__87_chanx_right_out ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__88_ccff_tail ; +wire [0:29] cbx_1__1__88_chanx_left_out ; +wire [0:29] cbx_1__1__88_chanx_right_out ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__89_ccff_tail ; +wire [0:29] cbx_1__1__89_chanx_left_out ; +wire [0:29] cbx_1__1__89_chanx_right_out ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__8_ccff_tail ; +wire [0:29] cbx_1__1__8_chanx_left_out ; +wire [0:29] cbx_1__1__8_chanx_right_out ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__90_ccff_tail ; +wire [0:29] cbx_1__1__90_chanx_left_out ; +wire [0:29] cbx_1__1__90_chanx_right_out ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__91_ccff_tail ; +wire [0:29] cbx_1__1__91_chanx_left_out ; +wire [0:29] cbx_1__1__91_chanx_right_out ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__92_ccff_tail ; +wire [0:29] cbx_1__1__92_chanx_left_out ; +wire [0:29] cbx_1__1__92_chanx_right_out ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__93_ccff_tail ; +wire [0:29] cbx_1__1__93_chanx_left_out ; +wire [0:29] cbx_1__1__93_chanx_right_out ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__94_ccff_tail ; +wire [0:29] cbx_1__1__94_chanx_left_out ; +wire [0:29] cbx_1__1__94_chanx_right_out ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__95_ccff_tail ; +wire [0:29] cbx_1__1__95_chanx_left_out ; +wire [0:29] cbx_1__1__95_chanx_right_out ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__96_ccff_tail ; +wire [0:29] cbx_1__1__96_chanx_left_out ; +wire [0:29] cbx_1__1__96_chanx_right_out ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__97_ccff_tail ; +wire [0:29] cbx_1__1__97_chanx_left_out ; +wire [0:29] cbx_1__1__97_chanx_right_out ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__98_ccff_tail ; +wire [0:29] cbx_1__1__98_chanx_left_out ; +wire [0:29] cbx_1__1__98_chanx_right_out ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__99_ccff_tail ; +wire [0:29] cbx_1__1__99_chanx_left_out ; +wire [0:29] cbx_1__1__99_chanx_right_out ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__9_ccff_tail ; +wire [0:29] cbx_1__1__9_chanx_left_out ; +wire [0:29] cbx_1__1__9_chanx_right_out ; +wire [0:0] cby_0__1__0_ccff_tail ; +wire [0:29] cby_0__1__0_chany_bottom_out ; +wire [0:29] cby_0__1__0_chany_top_out ; +wire [0:0] cby_0__1__0_left_grid_pin_0_ ; +wire [0:0] cby_0__1__10_ccff_tail ; +wire [0:29] cby_0__1__10_chany_bottom_out ; +wire [0:29] cby_0__1__10_chany_top_out ; +wire [0:0] cby_0__1__10_left_grid_pin_0_ ; +wire [0:0] cby_0__1__11_ccff_tail ; +wire [0:29] cby_0__1__11_chany_bottom_out ; +wire [0:29] cby_0__1__11_chany_top_out ; +wire [0:0] cby_0__1__11_left_grid_pin_0_ ; +wire [0:0] cby_0__1__1_ccff_tail ; +wire [0:29] cby_0__1__1_chany_bottom_out ; +wire [0:29] cby_0__1__1_chany_top_out ; +wire [0:0] cby_0__1__1_left_grid_pin_0_ ; +wire [0:0] cby_0__1__2_ccff_tail ; +wire [0:29] cby_0__1__2_chany_bottom_out ; +wire [0:29] cby_0__1__2_chany_top_out ; +wire [0:0] cby_0__1__2_left_grid_pin_0_ ; +wire [0:0] cby_0__1__3_ccff_tail ; +wire [0:29] cby_0__1__3_chany_bottom_out ; +wire [0:29] cby_0__1__3_chany_top_out ; +wire [0:0] cby_0__1__3_left_grid_pin_0_ ; +wire [0:0] cby_0__1__4_ccff_tail ; +wire [0:29] cby_0__1__4_chany_bottom_out ; +wire [0:29] cby_0__1__4_chany_top_out ; +wire [0:0] cby_0__1__4_left_grid_pin_0_ ; +wire [0:0] cby_0__1__5_ccff_tail ; +wire [0:29] cby_0__1__5_chany_bottom_out ; +wire [0:29] cby_0__1__5_chany_top_out ; +wire [0:0] cby_0__1__5_left_grid_pin_0_ ; +wire [0:0] cby_0__1__6_ccff_tail ; +wire [0:29] cby_0__1__6_chany_bottom_out ; +wire [0:29] cby_0__1__6_chany_top_out ; +wire [0:0] cby_0__1__6_left_grid_pin_0_ ; +wire [0:0] cby_0__1__7_ccff_tail ; +wire [0:29] cby_0__1__7_chany_bottom_out ; +wire [0:29] cby_0__1__7_chany_top_out ; +wire [0:0] cby_0__1__7_left_grid_pin_0_ ; +wire [0:0] cby_0__1__8_ccff_tail ; +wire [0:29] cby_0__1__8_chany_bottom_out ; +wire [0:29] cby_0__1__8_chany_top_out ; +wire [0:0] cby_0__1__8_left_grid_pin_0_ ; +wire [0:0] cby_0__1__9_ccff_tail ; +wire [0:29] cby_0__1__9_chany_bottom_out ; +wire [0:29] cby_0__1__9_chany_top_out ; +wire [0:0] cby_0__1__9_left_grid_pin_0_ ; +wire [0:0] cby_12__1__0_ccff_tail ; +wire [0:29] cby_12__1__0_chany_bottom_out ; +wire [0:29] cby_12__1__0_chany_top_out ; +wire [0:0] cby_12__1__0_left_grid_pin_16_ ; +wire [0:0] cby_12__1__0_left_grid_pin_17_ ; +wire [0:0] cby_12__1__0_left_grid_pin_18_ ; +wire [0:0] cby_12__1__0_left_grid_pin_19_ ; +wire [0:0] cby_12__1__0_left_grid_pin_20_ ; +wire [0:0] cby_12__1__0_left_grid_pin_21_ ; +wire [0:0] cby_12__1__0_left_grid_pin_22_ ; +wire [0:0] cby_12__1__0_left_grid_pin_23_ ; +wire [0:0] cby_12__1__0_left_grid_pin_24_ ; +wire [0:0] cby_12__1__0_left_grid_pin_25_ ; +wire [0:0] cby_12__1__0_left_grid_pin_26_ ; +wire [0:0] cby_12__1__0_left_grid_pin_27_ ; +wire [0:0] cby_12__1__0_left_grid_pin_28_ ; +wire [0:0] cby_12__1__0_left_grid_pin_29_ ; +wire [0:0] cby_12__1__0_left_grid_pin_30_ ; +wire [0:0] cby_12__1__0_left_grid_pin_31_ ; +wire [0:0] cby_12__1__0_right_grid_pin_0_ ; +wire [0:0] cby_12__1__10_ccff_tail ; +wire [0:29] cby_12__1__10_chany_bottom_out ; +wire [0:29] cby_12__1__10_chany_top_out ; +wire [0:0] cby_12__1__10_left_grid_pin_16_ ; +wire [0:0] cby_12__1__10_left_grid_pin_17_ ; +wire [0:0] cby_12__1__10_left_grid_pin_18_ ; +wire [0:0] cby_12__1__10_left_grid_pin_19_ ; +wire [0:0] cby_12__1__10_left_grid_pin_20_ ; +wire [0:0] cby_12__1__10_left_grid_pin_21_ ; +wire [0:0] cby_12__1__10_left_grid_pin_22_ ; +wire [0:0] cby_12__1__10_left_grid_pin_23_ ; +wire [0:0] cby_12__1__10_left_grid_pin_24_ ; +wire [0:0] cby_12__1__10_left_grid_pin_25_ ; +wire [0:0] cby_12__1__10_left_grid_pin_26_ ; +wire [0:0] cby_12__1__10_left_grid_pin_27_ ; +wire [0:0] cby_12__1__10_left_grid_pin_28_ ; +wire [0:0] cby_12__1__10_left_grid_pin_29_ ; +wire [0:0] cby_12__1__10_left_grid_pin_30_ ; +wire [0:0] cby_12__1__10_left_grid_pin_31_ ; +wire [0:0] cby_12__1__10_right_grid_pin_0_ ; +wire [0:0] cby_12__1__11_ccff_tail ; +wire [0:29] cby_12__1__11_chany_bottom_out ; +wire [0:29] cby_12__1__11_chany_top_out ; +wire [0:0] cby_12__1__11_left_grid_pin_16_ ; +wire [0:0] cby_12__1__11_left_grid_pin_17_ ; +wire [0:0] cby_12__1__11_left_grid_pin_18_ ; +wire [0:0] cby_12__1__11_left_grid_pin_19_ ; +wire [0:0] cby_12__1__11_left_grid_pin_20_ ; +wire [0:0] cby_12__1__11_left_grid_pin_21_ ; +wire [0:0] cby_12__1__11_left_grid_pin_22_ ; +wire [0:0] cby_12__1__11_left_grid_pin_23_ ; +wire [0:0] cby_12__1__11_left_grid_pin_24_ ; +wire [0:0] cby_12__1__11_left_grid_pin_25_ ; +wire [0:0] cby_12__1__11_left_grid_pin_26_ ; +wire [0:0] cby_12__1__11_left_grid_pin_27_ ; +wire [0:0] cby_12__1__11_left_grid_pin_28_ ; +wire [0:0] cby_12__1__11_left_grid_pin_29_ ; +wire [0:0] cby_12__1__11_left_grid_pin_30_ ; +wire [0:0] cby_12__1__11_left_grid_pin_31_ ; +wire [0:0] cby_12__1__11_right_grid_pin_0_ ; +wire [0:0] cby_12__1__1_ccff_tail ; +wire [0:29] cby_12__1__1_chany_bottom_out ; +wire [0:29] cby_12__1__1_chany_top_out ; +wire [0:0] cby_12__1__1_left_grid_pin_16_ ; +wire [0:0] cby_12__1__1_left_grid_pin_17_ ; +wire [0:0] cby_12__1__1_left_grid_pin_18_ ; +wire [0:0] cby_12__1__1_left_grid_pin_19_ ; +wire [0:0] cby_12__1__1_left_grid_pin_20_ ; +wire [0:0] cby_12__1__1_left_grid_pin_21_ ; +wire [0:0] cby_12__1__1_left_grid_pin_22_ ; +wire [0:0] cby_12__1__1_left_grid_pin_23_ ; +wire [0:0] cby_12__1__1_left_grid_pin_24_ ; +wire [0:0] cby_12__1__1_left_grid_pin_25_ ; +wire [0:0] cby_12__1__1_left_grid_pin_26_ ; +wire [0:0] cby_12__1__1_left_grid_pin_27_ ; +wire [0:0] cby_12__1__1_left_grid_pin_28_ ; +wire [0:0] cby_12__1__1_left_grid_pin_29_ ; +wire [0:0] cby_12__1__1_left_grid_pin_30_ ; +wire [0:0] cby_12__1__1_left_grid_pin_31_ ; +wire [0:0] cby_12__1__1_right_grid_pin_0_ ; +wire [0:0] cby_12__1__2_ccff_tail ; +wire [0:29] cby_12__1__2_chany_bottom_out ; +wire [0:29] cby_12__1__2_chany_top_out ; +wire [0:0] cby_12__1__2_left_grid_pin_16_ ; +wire [0:0] cby_12__1__2_left_grid_pin_17_ ; +wire [0:0] cby_12__1__2_left_grid_pin_18_ ; +wire [0:0] cby_12__1__2_left_grid_pin_19_ ; +wire [0:0] cby_12__1__2_left_grid_pin_20_ ; +wire [0:0] cby_12__1__2_left_grid_pin_21_ ; +wire [0:0] cby_12__1__2_left_grid_pin_22_ ; +wire [0:0] cby_12__1__2_left_grid_pin_23_ ; +wire [0:0] cby_12__1__2_left_grid_pin_24_ ; +wire [0:0] cby_12__1__2_left_grid_pin_25_ ; +wire [0:0] cby_12__1__2_left_grid_pin_26_ ; +wire [0:0] cby_12__1__2_left_grid_pin_27_ ; +wire [0:0] cby_12__1__2_left_grid_pin_28_ ; +wire [0:0] cby_12__1__2_left_grid_pin_29_ ; +wire [0:0] cby_12__1__2_left_grid_pin_30_ ; +wire [0:0] cby_12__1__2_left_grid_pin_31_ ; +wire [0:0] cby_12__1__2_right_grid_pin_0_ ; +wire [0:0] cby_12__1__3_ccff_tail ; +wire [0:29] cby_12__1__3_chany_bottom_out ; +wire [0:29] cby_12__1__3_chany_top_out ; +wire [0:0] cby_12__1__3_left_grid_pin_16_ ; +wire [0:0] cby_12__1__3_left_grid_pin_17_ ; +wire [0:0] cby_12__1__3_left_grid_pin_18_ ; +wire [0:0] cby_12__1__3_left_grid_pin_19_ ; +wire [0:0] cby_12__1__3_left_grid_pin_20_ ; +wire [0:0] cby_12__1__3_left_grid_pin_21_ ; +wire [0:0] cby_12__1__3_left_grid_pin_22_ ; +wire [0:0] cby_12__1__3_left_grid_pin_23_ ; +wire [0:0] cby_12__1__3_left_grid_pin_24_ ; +wire [0:0] cby_12__1__3_left_grid_pin_25_ ; +wire [0:0] cby_12__1__3_left_grid_pin_26_ ; +wire [0:0] cby_12__1__3_left_grid_pin_27_ ; +wire [0:0] cby_12__1__3_left_grid_pin_28_ ; +wire [0:0] cby_12__1__3_left_grid_pin_29_ ; +wire [0:0] cby_12__1__3_left_grid_pin_30_ ; +wire [0:0] cby_12__1__3_left_grid_pin_31_ ; +wire [0:0] cby_12__1__3_right_grid_pin_0_ ; +wire [0:0] cby_12__1__4_ccff_tail ; +wire [0:29] cby_12__1__4_chany_bottom_out ; +wire [0:29] cby_12__1__4_chany_top_out ; +wire [0:0] cby_12__1__4_left_grid_pin_16_ ; +wire [0:0] cby_12__1__4_left_grid_pin_17_ ; +wire [0:0] cby_12__1__4_left_grid_pin_18_ ; +wire [0:0] cby_12__1__4_left_grid_pin_19_ ; +wire [0:0] cby_12__1__4_left_grid_pin_20_ ; +wire [0:0] cby_12__1__4_left_grid_pin_21_ ; +wire [0:0] cby_12__1__4_left_grid_pin_22_ ; +wire [0:0] cby_12__1__4_left_grid_pin_23_ ; +wire [0:0] cby_12__1__4_left_grid_pin_24_ ; +wire [0:0] cby_12__1__4_left_grid_pin_25_ ; +wire [0:0] cby_12__1__4_left_grid_pin_26_ ; +wire [0:0] cby_12__1__4_left_grid_pin_27_ ; +wire [0:0] cby_12__1__4_left_grid_pin_28_ ; +wire [0:0] cby_12__1__4_left_grid_pin_29_ ; +wire [0:0] cby_12__1__4_left_grid_pin_30_ ; +wire [0:0] cby_12__1__4_left_grid_pin_31_ ; +wire [0:0] cby_12__1__4_right_grid_pin_0_ ; +wire [0:0] cby_12__1__5_ccff_tail ; +wire [0:29] cby_12__1__5_chany_bottom_out ; +wire [0:29] cby_12__1__5_chany_top_out ; +wire [0:0] cby_12__1__5_left_grid_pin_16_ ; +wire [0:0] cby_12__1__5_left_grid_pin_17_ ; +wire [0:0] cby_12__1__5_left_grid_pin_18_ ; +wire [0:0] cby_12__1__5_left_grid_pin_19_ ; +wire [0:0] cby_12__1__5_left_grid_pin_20_ ; +wire [0:0] cby_12__1__5_left_grid_pin_21_ ; +wire [0:0] cby_12__1__5_left_grid_pin_22_ ; +wire [0:0] cby_12__1__5_left_grid_pin_23_ ; +wire [0:0] cby_12__1__5_left_grid_pin_24_ ; +wire [0:0] cby_12__1__5_left_grid_pin_25_ ; +wire [0:0] cby_12__1__5_left_grid_pin_26_ ; +wire [0:0] cby_12__1__5_left_grid_pin_27_ ; +wire [0:0] cby_12__1__5_left_grid_pin_28_ ; +wire [0:0] cby_12__1__5_left_grid_pin_29_ ; +wire [0:0] cby_12__1__5_left_grid_pin_30_ ; +wire [0:0] cby_12__1__5_left_grid_pin_31_ ; +wire [0:0] cby_12__1__5_right_grid_pin_0_ ; +wire [0:0] cby_12__1__6_ccff_tail ; +wire [0:29] cby_12__1__6_chany_bottom_out ; +wire [0:29] cby_12__1__6_chany_top_out ; +wire [0:0] cby_12__1__6_left_grid_pin_16_ ; +wire [0:0] cby_12__1__6_left_grid_pin_17_ ; +wire [0:0] cby_12__1__6_left_grid_pin_18_ ; +wire [0:0] cby_12__1__6_left_grid_pin_19_ ; +wire [0:0] cby_12__1__6_left_grid_pin_20_ ; +wire [0:0] cby_12__1__6_left_grid_pin_21_ ; +wire [0:0] cby_12__1__6_left_grid_pin_22_ ; +wire [0:0] cby_12__1__6_left_grid_pin_23_ ; +wire [0:0] cby_12__1__6_left_grid_pin_24_ ; +wire [0:0] cby_12__1__6_left_grid_pin_25_ ; +wire [0:0] cby_12__1__6_left_grid_pin_26_ ; +wire [0:0] cby_12__1__6_left_grid_pin_27_ ; +wire [0:0] cby_12__1__6_left_grid_pin_28_ ; +wire [0:0] cby_12__1__6_left_grid_pin_29_ ; +wire [0:0] cby_12__1__6_left_grid_pin_30_ ; +wire [0:0] cby_12__1__6_left_grid_pin_31_ ; +wire [0:0] cby_12__1__6_right_grid_pin_0_ ; +wire [0:0] cby_12__1__7_ccff_tail ; +wire [0:29] cby_12__1__7_chany_bottom_out ; +wire [0:29] cby_12__1__7_chany_top_out ; +wire [0:0] cby_12__1__7_left_grid_pin_16_ ; +wire [0:0] cby_12__1__7_left_grid_pin_17_ ; +wire [0:0] cby_12__1__7_left_grid_pin_18_ ; +wire [0:0] cby_12__1__7_left_grid_pin_19_ ; +wire [0:0] cby_12__1__7_left_grid_pin_20_ ; +wire [0:0] cby_12__1__7_left_grid_pin_21_ ; +wire [0:0] cby_12__1__7_left_grid_pin_22_ ; +wire [0:0] cby_12__1__7_left_grid_pin_23_ ; +wire [0:0] cby_12__1__7_left_grid_pin_24_ ; +wire [0:0] cby_12__1__7_left_grid_pin_25_ ; +wire [0:0] cby_12__1__7_left_grid_pin_26_ ; +wire [0:0] cby_12__1__7_left_grid_pin_27_ ; +wire [0:0] cby_12__1__7_left_grid_pin_28_ ; +wire [0:0] cby_12__1__7_left_grid_pin_29_ ; +wire [0:0] cby_12__1__7_left_grid_pin_30_ ; +wire [0:0] cby_12__1__7_left_grid_pin_31_ ; +wire [0:0] cby_12__1__7_right_grid_pin_0_ ; +wire [0:0] cby_12__1__8_ccff_tail ; +wire [0:29] cby_12__1__8_chany_bottom_out ; +wire [0:29] cby_12__1__8_chany_top_out ; +wire [0:0] cby_12__1__8_left_grid_pin_16_ ; +wire [0:0] cby_12__1__8_left_grid_pin_17_ ; +wire [0:0] cby_12__1__8_left_grid_pin_18_ ; +wire [0:0] cby_12__1__8_left_grid_pin_19_ ; +wire [0:0] cby_12__1__8_left_grid_pin_20_ ; +wire [0:0] cby_12__1__8_left_grid_pin_21_ ; +wire [0:0] cby_12__1__8_left_grid_pin_22_ ; +wire [0:0] cby_12__1__8_left_grid_pin_23_ ; +wire [0:0] cby_12__1__8_left_grid_pin_24_ ; +wire [0:0] cby_12__1__8_left_grid_pin_25_ ; +wire [0:0] cby_12__1__8_left_grid_pin_26_ ; +wire [0:0] cby_12__1__8_left_grid_pin_27_ ; +wire [0:0] cby_12__1__8_left_grid_pin_28_ ; +wire [0:0] cby_12__1__8_left_grid_pin_29_ ; +wire [0:0] cby_12__1__8_left_grid_pin_30_ ; +wire [0:0] cby_12__1__8_left_grid_pin_31_ ; +wire [0:0] cby_12__1__8_right_grid_pin_0_ ; +wire [0:0] cby_12__1__9_ccff_tail ; +wire [0:29] cby_12__1__9_chany_bottom_out ; +wire [0:29] cby_12__1__9_chany_top_out ; +wire [0:0] cby_12__1__9_left_grid_pin_16_ ; +wire [0:0] cby_12__1__9_left_grid_pin_17_ ; +wire [0:0] cby_12__1__9_left_grid_pin_18_ ; +wire [0:0] cby_12__1__9_left_grid_pin_19_ ; +wire [0:0] cby_12__1__9_left_grid_pin_20_ ; +wire [0:0] cby_12__1__9_left_grid_pin_21_ ; +wire [0:0] cby_12__1__9_left_grid_pin_22_ ; +wire [0:0] cby_12__1__9_left_grid_pin_23_ ; +wire [0:0] cby_12__1__9_left_grid_pin_24_ ; +wire [0:0] cby_12__1__9_left_grid_pin_25_ ; +wire [0:0] cby_12__1__9_left_grid_pin_26_ ; +wire [0:0] cby_12__1__9_left_grid_pin_27_ ; +wire [0:0] cby_12__1__9_left_grid_pin_28_ ; +wire [0:0] cby_12__1__9_left_grid_pin_29_ ; +wire [0:0] cby_12__1__9_left_grid_pin_30_ ; +wire [0:0] cby_12__1__9_left_grid_pin_31_ ; +wire [0:0] cby_12__1__9_right_grid_pin_0_ ; +wire [0:0] cby_1__1__0_ccff_tail ; +wire [0:29] cby_1__1__0_chany_bottom_out ; +wire [0:29] cby_1__1__0_chany_top_out ; +wire [0:0] cby_1__1__0_left_grid_pin_16_ ; +wire [0:0] cby_1__1__0_left_grid_pin_17_ ; +wire [0:0] cby_1__1__0_left_grid_pin_18_ ; +wire [0:0] cby_1__1__0_left_grid_pin_19_ ; +wire [0:0] cby_1__1__0_left_grid_pin_20_ ; +wire [0:0] cby_1__1__0_left_grid_pin_21_ ; +wire [0:0] cby_1__1__0_left_grid_pin_22_ ; +wire [0:0] cby_1__1__0_left_grid_pin_23_ ; +wire [0:0] cby_1__1__0_left_grid_pin_24_ ; +wire [0:0] cby_1__1__0_left_grid_pin_25_ ; +wire [0:0] cby_1__1__0_left_grid_pin_26_ ; +wire [0:0] cby_1__1__0_left_grid_pin_27_ ; +wire [0:0] cby_1__1__0_left_grid_pin_28_ ; +wire [0:0] cby_1__1__0_left_grid_pin_29_ ; +wire [0:0] cby_1__1__0_left_grid_pin_30_ ; +wire [0:0] cby_1__1__0_left_grid_pin_31_ ; +wire [0:0] cby_1__1__100_ccff_tail ; +wire [0:29] cby_1__1__100_chany_bottom_out ; +wire [0:29] cby_1__1__100_chany_top_out ; +wire [0:0] cby_1__1__100_left_grid_pin_16_ ; +wire [0:0] cby_1__1__100_left_grid_pin_17_ ; +wire [0:0] cby_1__1__100_left_grid_pin_18_ ; +wire [0:0] cby_1__1__100_left_grid_pin_19_ ; +wire [0:0] cby_1__1__100_left_grid_pin_20_ ; +wire [0:0] cby_1__1__100_left_grid_pin_21_ ; +wire [0:0] cby_1__1__100_left_grid_pin_22_ ; +wire [0:0] cby_1__1__100_left_grid_pin_23_ ; +wire [0:0] cby_1__1__100_left_grid_pin_24_ ; +wire [0:0] cby_1__1__100_left_grid_pin_25_ ; +wire [0:0] cby_1__1__100_left_grid_pin_26_ ; +wire [0:0] cby_1__1__100_left_grid_pin_27_ ; +wire [0:0] cby_1__1__100_left_grid_pin_28_ ; +wire [0:0] cby_1__1__100_left_grid_pin_29_ ; +wire [0:0] cby_1__1__100_left_grid_pin_30_ ; +wire [0:0] cby_1__1__100_left_grid_pin_31_ ; +wire [0:0] cby_1__1__101_ccff_tail ; +wire [0:29] cby_1__1__101_chany_bottom_out ; +wire [0:29] cby_1__1__101_chany_top_out ; +wire [0:0] cby_1__1__101_left_grid_pin_16_ ; +wire [0:0] cby_1__1__101_left_grid_pin_17_ ; +wire [0:0] cby_1__1__101_left_grid_pin_18_ ; +wire [0:0] cby_1__1__101_left_grid_pin_19_ ; +wire [0:0] cby_1__1__101_left_grid_pin_20_ ; +wire [0:0] cby_1__1__101_left_grid_pin_21_ ; +wire [0:0] cby_1__1__101_left_grid_pin_22_ ; +wire [0:0] cby_1__1__101_left_grid_pin_23_ ; +wire [0:0] cby_1__1__101_left_grid_pin_24_ ; +wire [0:0] cby_1__1__101_left_grid_pin_25_ ; +wire [0:0] cby_1__1__101_left_grid_pin_26_ ; +wire [0:0] cby_1__1__101_left_grid_pin_27_ ; +wire [0:0] cby_1__1__101_left_grid_pin_28_ ; +wire [0:0] cby_1__1__101_left_grid_pin_29_ ; +wire [0:0] cby_1__1__101_left_grid_pin_30_ ; +wire [0:0] cby_1__1__101_left_grid_pin_31_ ; +wire [0:0] cby_1__1__102_ccff_tail ; +wire [0:29] cby_1__1__102_chany_bottom_out ; +wire [0:29] cby_1__1__102_chany_top_out ; +wire [0:0] cby_1__1__102_left_grid_pin_16_ ; +wire [0:0] cby_1__1__102_left_grid_pin_17_ ; +wire [0:0] cby_1__1__102_left_grid_pin_18_ ; +wire [0:0] cby_1__1__102_left_grid_pin_19_ ; +wire [0:0] cby_1__1__102_left_grid_pin_20_ ; +wire [0:0] cby_1__1__102_left_grid_pin_21_ ; +wire [0:0] cby_1__1__102_left_grid_pin_22_ ; +wire [0:0] cby_1__1__102_left_grid_pin_23_ ; +wire [0:0] cby_1__1__102_left_grid_pin_24_ ; +wire [0:0] cby_1__1__102_left_grid_pin_25_ ; +wire [0:0] cby_1__1__102_left_grid_pin_26_ ; +wire [0:0] cby_1__1__102_left_grid_pin_27_ ; +wire [0:0] cby_1__1__102_left_grid_pin_28_ ; +wire [0:0] cby_1__1__102_left_grid_pin_29_ ; +wire [0:0] cby_1__1__102_left_grid_pin_30_ ; +wire [0:0] cby_1__1__102_left_grid_pin_31_ ; +wire [0:0] cby_1__1__103_ccff_tail ; +wire [0:29] cby_1__1__103_chany_bottom_out ; +wire [0:29] cby_1__1__103_chany_top_out ; +wire [0:0] cby_1__1__103_left_grid_pin_16_ ; +wire [0:0] cby_1__1__103_left_grid_pin_17_ ; +wire [0:0] cby_1__1__103_left_grid_pin_18_ ; +wire [0:0] cby_1__1__103_left_grid_pin_19_ ; +wire [0:0] cby_1__1__103_left_grid_pin_20_ ; +wire [0:0] cby_1__1__103_left_grid_pin_21_ ; +wire [0:0] cby_1__1__103_left_grid_pin_22_ ; +wire [0:0] cby_1__1__103_left_grid_pin_23_ ; +wire [0:0] cby_1__1__103_left_grid_pin_24_ ; +wire [0:0] cby_1__1__103_left_grid_pin_25_ ; +wire [0:0] cby_1__1__103_left_grid_pin_26_ ; +wire [0:0] cby_1__1__103_left_grid_pin_27_ ; +wire [0:0] cby_1__1__103_left_grid_pin_28_ ; +wire [0:0] cby_1__1__103_left_grid_pin_29_ ; +wire [0:0] cby_1__1__103_left_grid_pin_30_ ; +wire [0:0] cby_1__1__103_left_grid_pin_31_ ; +wire [0:0] cby_1__1__104_ccff_tail ; +wire [0:29] cby_1__1__104_chany_bottom_out ; +wire [0:29] cby_1__1__104_chany_top_out ; +wire [0:0] cby_1__1__104_left_grid_pin_16_ ; +wire [0:0] cby_1__1__104_left_grid_pin_17_ ; +wire [0:0] cby_1__1__104_left_grid_pin_18_ ; +wire [0:0] cby_1__1__104_left_grid_pin_19_ ; +wire [0:0] cby_1__1__104_left_grid_pin_20_ ; +wire [0:0] cby_1__1__104_left_grid_pin_21_ ; +wire [0:0] cby_1__1__104_left_grid_pin_22_ ; +wire [0:0] cby_1__1__104_left_grid_pin_23_ ; +wire [0:0] cby_1__1__104_left_grid_pin_24_ ; +wire [0:0] cby_1__1__104_left_grid_pin_25_ ; +wire [0:0] cby_1__1__104_left_grid_pin_26_ ; +wire [0:0] cby_1__1__104_left_grid_pin_27_ ; +wire [0:0] cby_1__1__104_left_grid_pin_28_ ; +wire [0:0] cby_1__1__104_left_grid_pin_29_ ; +wire [0:0] cby_1__1__104_left_grid_pin_30_ ; +wire [0:0] cby_1__1__104_left_grid_pin_31_ ; +wire [0:0] cby_1__1__105_ccff_tail ; +wire [0:29] cby_1__1__105_chany_bottom_out ; +wire [0:29] cby_1__1__105_chany_top_out ; +wire [0:0] cby_1__1__105_left_grid_pin_16_ ; +wire [0:0] cby_1__1__105_left_grid_pin_17_ ; +wire [0:0] cby_1__1__105_left_grid_pin_18_ ; +wire [0:0] cby_1__1__105_left_grid_pin_19_ ; +wire [0:0] cby_1__1__105_left_grid_pin_20_ ; +wire [0:0] cby_1__1__105_left_grid_pin_21_ ; +wire [0:0] cby_1__1__105_left_grid_pin_22_ ; +wire [0:0] cby_1__1__105_left_grid_pin_23_ ; +wire [0:0] cby_1__1__105_left_grid_pin_24_ ; +wire [0:0] cby_1__1__105_left_grid_pin_25_ ; +wire [0:0] cby_1__1__105_left_grid_pin_26_ ; +wire [0:0] cby_1__1__105_left_grid_pin_27_ ; +wire [0:0] cby_1__1__105_left_grid_pin_28_ ; +wire [0:0] cby_1__1__105_left_grid_pin_29_ ; +wire [0:0] cby_1__1__105_left_grid_pin_30_ ; +wire [0:0] cby_1__1__105_left_grid_pin_31_ ; +wire [0:0] cby_1__1__106_ccff_tail ; +wire [0:29] cby_1__1__106_chany_bottom_out ; +wire [0:29] cby_1__1__106_chany_top_out ; +wire [0:0] cby_1__1__106_left_grid_pin_16_ ; +wire [0:0] cby_1__1__106_left_grid_pin_17_ ; +wire [0:0] cby_1__1__106_left_grid_pin_18_ ; +wire [0:0] cby_1__1__106_left_grid_pin_19_ ; +wire [0:0] cby_1__1__106_left_grid_pin_20_ ; +wire [0:0] cby_1__1__106_left_grid_pin_21_ ; +wire [0:0] cby_1__1__106_left_grid_pin_22_ ; +wire [0:0] cby_1__1__106_left_grid_pin_23_ ; +wire [0:0] cby_1__1__106_left_grid_pin_24_ ; +wire [0:0] cby_1__1__106_left_grid_pin_25_ ; +wire [0:0] cby_1__1__106_left_grid_pin_26_ ; +wire [0:0] cby_1__1__106_left_grid_pin_27_ ; +wire [0:0] cby_1__1__106_left_grid_pin_28_ ; +wire [0:0] cby_1__1__106_left_grid_pin_29_ ; +wire [0:0] cby_1__1__106_left_grid_pin_30_ ; +wire [0:0] cby_1__1__106_left_grid_pin_31_ ; +wire [0:0] cby_1__1__107_ccff_tail ; +wire [0:29] cby_1__1__107_chany_bottom_out ; +wire [0:29] cby_1__1__107_chany_top_out ; +wire [0:0] cby_1__1__107_left_grid_pin_16_ ; +wire [0:0] cby_1__1__107_left_grid_pin_17_ ; +wire [0:0] cby_1__1__107_left_grid_pin_18_ ; +wire [0:0] cby_1__1__107_left_grid_pin_19_ ; +wire [0:0] cby_1__1__107_left_grid_pin_20_ ; +wire [0:0] cby_1__1__107_left_grid_pin_21_ ; +wire [0:0] cby_1__1__107_left_grid_pin_22_ ; +wire [0:0] cby_1__1__107_left_grid_pin_23_ ; +wire [0:0] cby_1__1__107_left_grid_pin_24_ ; +wire [0:0] cby_1__1__107_left_grid_pin_25_ ; +wire [0:0] cby_1__1__107_left_grid_pin_26_ ; +wire [0:0] cby_1__1__107_left_grid_pin_27_ ; +wire [0:0] cby_1__1__107_left_grid_pin_28_ ; +wire [0:0] cby_1__1__107_left_grid_pin_29_ ; +wire [0:0] cby_1__1__107_left_grid_pin_30_ ; +wire [0:0] cby_1__1__107_left_grid_pin_31_ ; +wire [0:0] cby_1__1__108_ccff_tail ; +wire [0:29] cby_1__1__108_chany_bottom_out ; +wire [0:29] cby_1__1__108_chany_top_out ; +wire [0:0] cby_1__1__108_left_grid_pin_16_ ; +wire [0:0] cby_1__1__108_left_grid_pin_17_ ; +wire [0:0] cby_1__1__108_left_grid_pin_18_ ; +wire [0:0] cby_1__1__108_left_grid_pin_19_ ; +wire [0:0] cby_1__1__108_left_grid_pin_20_ ; +wire [0:0] cby_1__1__108_left_grid_pin_21_ ; +wire [0:0] cby_1__1__108_left_grid_pin_22_ ; +wire [0:0] cby_1__1__108_left_grid_pin_23_ ; +wire [0:0] cby_1__1__108_left_grid_pin_24_ ; +wire [0:0] cby_1__1__108_left_grid_pin_25_ ; +wire [0:0] cby_1__1__108_left_grid_pin_26_ ; +wire [0:0] cby_1__1__108_left_grid_pin_27_ ; +wire [0:0] cby_1__1__108_left_grid_pin_28_ ; +wire [0:0] cby_1__1__108_left_grid_pin_29_ ; +wire [0:0] cby_1__1__108_left_grid_pin_30_ ; +wire [0:0] cby_1__1__108_left_grid_pin_31_ ; +wire [0:0] cby_1__1__109_ccff_tail ; +wire [0:29] cby_1__1__109_chany_bottom_out ; +wire [0:29] cby_1__1__109_chany_top_out ; +wire [0:0] cby_1__1__109_left_grid_pin_16_ ; +wire [0:0] cby_1__1__109_left_grid_pin_17_ ; +wire [0:0] cby_1__1__109_left_grid_pin_18_ ; +wire [0:0] cby_1__1__109_left_grid_pin_19_ ; +wire [0:0] cby_1__1__109_left_grid_pin_20_ ; +wire [0:0] cby_1__1__109_left_grid_pin_21_ ; +wire [0:0] cby_1__1__109_left_grid_pin_22_ ; +wire [0:0] cby_1__1__109_left_grid_pin_23_ ; +wire [0:0] cby_1__1__109_left_grid_pin_24_ ; +wire [0:0] cby_1__1__109_left_grid_pin_25_ ; +wire [0:0] cby_1__1__109_left_grid_pin_26_ ; +wire [0:0] cby_1__1__109_left_grid_pin_27_ ; +wire [0:0] cby_1__1__109_left_grid_pin_28_ ; +wire [0:0] cby_1__1__109_left_grid_pin_29_ ; +wire [0:0] cby_1__1__109_left_grid_pin_30_ ; +wire [0:0] cby_1__1__109_left_grid_pin_31_ ; +wire [0:0] cby_1__1__10_ccff_tail ; +wire [0:29] cby_1__1__10_chany_bottom_out ; +wire [0:29] cby_1__1__10_chany_top_out ; +wire [0:0] cby_1__1__10_left_grid_pin_16_ ; +wire [0:0] cby_1__1__10_left_grid_pin_17_ ; +wire [0:0] cby_1__1__10_left_grid_pin_18_ ; +wire [0:0] cby_1__1__10_left_grid_pin_19_ ; +wire [0:0] cby_1__1__10_left_grid_pin_20_ ; +wire [0:0] cby_1__1__10_left_grid_pin_21_ ; +wire [0:0] cby_1__1__10_left_grid_pin_22_ ; +wire [0:0] cby_1__1__10_left_grid_pin_23_ ; +wire [0:0] cby_1__1__10_left_grid_pin_24_ ; +wire [0:0] cby_1__1__10_left_grid_pin_25_ ; +wire [0:0] cby_1__1__10_left_grid_pin_26_ ; +wire [0:0] cby_1__1__10_left_grid_pin_27_ ; +wire [0:0] cby_1__1__10_left_grid_pin_28_ ; +wire [0:0] cby_1__1__10_left_grid_pin_29_ ; +wire [0:0] cby_1__1__10_left_grid_pin_30_ ; +wire [0:0] cby_1__1__10_left_grid_pin_31_ ; +wire [0:0] cby_1__1__110_ccff_tail ; +wire [0:29] cby_1__1__110_chany_bottom_out ; +wire [0:29] cby_1__1__110_chany_top_out ; +wire [0:0] cby_1__1__110_left_grid_pin_16_ ; +wire [0:0] cby_1__1__110_left_grid_pin_17_ ; +wire [0:0] cby_1__1__110_left_grid_pin_18_ ; +wire [0:0] cby_1__1__110_left_grid_pin_19_ ; +wire [0:0] cby_1__1__110_left_grid_pin_20_ ; +wire [0:0] cby_1__1__110_left_grid_pin_21_ ; +wire [0:0] cby_1__1__110_left_grid_pin_22_ ; +wire [0:0] cby_1__1__110_left_grid_pin_23_ ; +wire [0:0] cby_1__1__110_left_grid_pin_24_ ; +wire [0:0] cby_1__1__110_left_grid_pin_25_ ; +wire [0:0] cby_1__1__110_left_grid_pin_26_ ; +wire [0:0] cby_1__1__110_left_grid_pin_27_ ; +wire [0:0] cby_1__1__110_left_grid_pin_28_ ; +wire [0:0] cby_1__1__110_left_grid_pin_29_ ; +wire [0:0] cby_1__1__110_left_grid_pin_30_ ; +wire [0:0] cby_1__1__110_left_grid_pin_31_ ; +wire [0:0] cby_1__1__111_ccff_tail ; +wire [0:29] cby_1__1__111_chany_bottom_out ; +wire [0:29] cby_1__1__111_chany_top_out ; +wire [0:0] cby_1__1__111_left_grid_pin_16_ ; +wire [0:0] cby_1__1__111_left_grid_pin_17_ ; +wire [0:0] cby_1__1__111_left_grid_pin_18_ ; +wire [0:0] cby_1__1__111_left_grid_pin_19_ ; +wire [0:0] cby_1__1__111_left_grid_pin_20_ ; +wire [0:0] cby_1__1__111_left_grid_pin_21_ ; +wire [0:0] cby_1__1__111_left_grid_pin_22_ ; +wire [0:0] cby_1__1__111_left_grid_pin_23_ ; +wire [0:0] cby_1__1__111_left_grid_pin_24_ ; +wire [0:0] cby_1__1__111_left_grid_pin_25_ ; +wire [0:0] cby_1__1__111_left_grid_pin_26_ ; +wire [0:0] cby_1__1__111_left_grid_pin_27_ ; +wire [0:0] cby_1__1__111_left_grid_pin_28_ ; +wire [0:0] cby_1__1__111_left_grid_pin_29_ ; +wire [0:0] cby_1__1__111_left_grid_pin_30_ ; +wire [0:0] cby_1__1__111_left_grid_pin_31_ ; +wire [0:0] cby_1__1__112_ccff_tail ; +wire [0:29] cby_1__1__112_chany_bottom_out ; +wire [0:29] cby_1__1__112_chany_top_out ; +wire [0:0] cby_1__1__112_left_grid_pin_16_ ; +wire [0:0] cby_1__1__112_left_grid_pin_17_ ; +wire [0:0] cby_1__1__112_left_grid_pin_18_ ; +wire [0:0] cby_1__1__112_left_grid_pin_19_ ; +wire [0:0] cby_1__1__112_left_grid_pin_20_ ; +wire [0:0] cby_1__1__112_left_grid_pin_21_ ; +wire [0:0] cby_1__1__112_left_grid_pin_22_ ; +wire [0:0] cby_1__1__112_left_grid_pin_23_ ; +wire [0:0] cby_1__1__112_left_grid_pin_24_ ; +wire [0:0] cby_1__1__112_left_grid_pin_25_ ; +wire [0:0] cby_1__1__112_left_grid_pin_26_ ; +wire [0:0] cby_1__1__112_left_grid_pin_27_ ; +wire [0:0] cby_1__1__112_left_grid_pin_28_ ; +wire [0:0] cby_1__1__112_left_grid_pin_29_ ; +wire [0:0] cby_1__1__112_left_grid_pin_30_ ; +wire [0:0] cby_1__1__112_left_grid_pin_31_ ; +wire [0:0] cby_1__1__113_ccff_tail ; +wire [0:29] cby_1__1__113_chany_bottom_out ; +wire [0:29] cby_1__1__113_chany_top_out ; +wire [0:0] cby_1__1__113_left_grid_pin_16_ ; +wire [0:0] cby_1__1__113_left_grid_pin_17_ ; +wire [0:0] cby_1__1__113_left_grid_pin_18_ ; +wire [0:0] cby_1__1__113_left_grid_pin_19_ ; +wire [0:0] cby_1__1__113_left_grid_pin_20_ ; +wire [0:0] cby_1__1__113_left_grid_pin_21_ ; +wire [0:0] cby_1__1__113_left_grid_pin_22_ ; +wire [0:0] cby_1__1__113_left_grid_pin_23_ ; +wire [0:0] cby_1__1__113_left_grid_pin_24_ ; +wire [0:0] cby_1__1__113_left_grid_pin_25_ ; +wire [0:0] cby_1__1__113_left_grid_pin_26_ ; +wire [0:0] cby_1__1__113_left_grid_pin_27_ ; +wire [0:0] cby_1__1__113_left_grid_pin_28_ ; +wire [0:0] cby_1__1__113_left_grid_pin_29_ ; +wire [0:0] cby_1__1__113_left_grid_pin_30_ ; +wire [0:0] cby_1__1__113_left_grid_pin_31_ ; +wire [0:0] cby_1__1__114_ccff_tail ; +wire [0:29] cby_1__1__114_chany_bottom_out ; +wire [0:29] cby_1__1__114_chany_top_out ; +wire [0:0] cby_1__1__114_left_grid_pin_16_ ; +wire [0:0] cby_1__1__114_left_grid_pin_17_ ; +wire [0:0] cby_1__1__114_left_grid_pin_18_ ; +wire [0:0] cby_1__1__114_left_grid_pin_19_ ; +wire [0:0] cby_1__1__114_left_grid_pin_20_ ; +wire [0:0] cby_1__1__114_left_grid_pin_21_ ; +wire [0:0] cby_1__1__114_left_grid_pin_22_ ; +wire [0:0] cby_1__1__114_left_grid_pin_23_ ; +wire [0:0] cby_1__1__114_left_grid_pin_24_ ; +wire [0:0] cby_1__1__114_left_grid_pin_25_ ; +wire [0:0] cby_1__1__114_left_grid_pin_26_ ; +wire [0:0] cby_1__1__114_left_grid_pin_27_ ; +wire [0:0] cby_1__1__114_left_grid_pin_28_ ; +wire [0:0] cby_1__1__114_left_grid_pin_29_ ; +wire [0:0] cby_1__1__114_left_grid_pin_30_ ; +wire [0:0] cby_1__1__114_left_grid_pin_31_ ; +wire [0:0] cby_1__1__115_ccff_tail ; +wire [0:29] cby_1__1__115_chany_bottom_out ; +wire [0:29] cby_1__1__115_chany_top_out ; +wire [0:0] cby_1__1__115_left_grid_pin_16_ ; +wire [0:0] cby_1__1__115_left_grid_pin_17_ ; +wire [0:0] cby_1__1__115_left_grid_pin_18_ ; +wire [0:0] cby_1__1__115_left_grid_pin_19_ ; +wire [0:0] cby_1__1__115_left_grid_pin_20_ ; +wire [0:0] cby_1__1__115_left_grid_pin_21_ ; +wire [0:0] cby_1__1__115_left_grid_pin_22_ ; +wire [0:0] cby_1__1__115_left_grid_pin_23_ ; +wire [0:0] cby_1__1__115_left_grid_pin_24_ ; +wire [0:0] cby_1__1__115_left_grid_pin_25_ ; +wire [0:0] cby_1__1__115_left_grid_pin_26_ ; +wire [0:0] cby_1__1__115_left_grid_pin_27_ ; +wire [0:0] cby_1__1__115_left_grid_pin_28_ ; +wire [0:0] cby_1__1__115_left_grid_pin_29_ ; +wire [0:0] cby_1__1__115_left_grid_pin_30_ ; +wire [0:0] cby_1__1__115_left_grid_pin_31_ ; +wire [0:0] cby_1__1__116_ccff_tail ; +wire [0:29] cby_1__1__116_chany_bottom_out ; +wire [0:29] cby_1__1__116_chany_top_out ; +wire [0:0] cby_1__1__116_left_grid_pin_16_ ; +wire [0:0] cby_1__1__116_left_grid_pin_17_ ; +wire [0:0] cby_1__1__116_left_grid_pin_18_ ; +wire [0:0] cby_1__1__116_left_grid_pin_19_ ; +wire [0:0] cby_1__1__116_left_grid_pin_20_ ; +wire [0:0] cby_1__1__116_left_grid_pin_21_ ; +wire [0:0] cby_1__1__116_left_grid_pin_22_ ; +wire [0:0] cby_1__1__116_left_grid_pin_23_ ; +wire [0:0] cby_1__1__116_left_grid_pin_24_ ; +wire [0:0] cby_1__1__116_left_grid_pin_25_ ; +wire [0:0] cby_1__1__116_left_grid_pin_26_ ; +wire [0:0] cby_1__1__116_left_grid_pin_27_ ; +wire [0:0] cby_1__1__116_left_grid_pin_28_ ; +wire [0:0] cby_1__1__116_left_grid_pin_29_ ; +wire [0:0] cby_1__1__116_left_grid_pin_30_ ; +wire [0:0] cby_1__1__116_left_grid_pin_31_ ; +wire [0:0] cby_1__1__117_ccff_tail ; +wire [0:29] cby_1__1__117_chany_bottom_out ; +wire [0:29] cby_1__1__117_chany_top_out ; +wire [0:0] cby_1__1__117_left_grid_pin_16_ ; +wire [0:0] cby_1__1__117_left_grid_pin_17_ ; +wire [0:0] cby_1__1__117_left_grid_pin_18_ ; +wire [0:0] cby_1__1__117_left_grid_pin_19_ ; +wire [0:0] cby_1__1__117_left_grid_pin_20_ ; +wire [0:0] cby_1__1__117_left_grid_pin_21_ ; +wire [0:0] cby_1__1__117_left_grid_pin_22_ ; +wire [0:0] cby_1__1__117_left_grid_pin_23_ ; +wire [0:0] cby_1__1__117_left_grid_pin_24_ ; +wire [0:0] cby_1__1__117_left_grid_pin_25_ ; +wire [0:0] cby_1__1__117_left_grid_pin_26_ ; +wire [0:0] cby_1__1__117_left_grid_pin_27_ ; +wire [0:0] cby_1__1__117_left_grid_pin_28_ ; +wire [0:0] cby_1__1__117_left_grid_pin_29_ ; +wire [0:0] cby_1__1__117_left_grid_pin_30_ ; +wire [0:0] cby_1__1__117_left_grid_pin_31_ ; +wire [0:0] cby_1__1__118_ccff_tail ; +wire [0:29] cby_1__1__118_chany_bottom_out ; +wire [0:29] cby_1__1__118_chany_top_out ; +wire [0:0] cby_1__1__118_left_grid_pin_16_ ; +wire [0:0] cby_1__1__118_left_grid_pin_17_ ; +wire [0:0] cby_1__1__118_left_grid_pin_18_ ; +wire [0:0] cby_1__1__118_left_grid_pin_19_ ; +wire [0:0] cby_1__1__118_left_grid_pin_20_ ; +wire [0:0] cby_1__1__118_left_grid_pin_21_ ; +wire [0:0] cby_1__1__118_left_grid_pin_22_ ; +wire [0:0] cby_1__1__118_left_grid_pin_23_ ; +wire [0:0] cby_1__1__118_left_grid_pin_24_ ; +wire [0:0] cby_1__1__118_left_grid_pin_25_ ; +wire [0:0] cby_1__1__118_left_grid_pin_26_ ; +wire [0:0] cby_1__1__118_left_grid_pin_27_ ; +wire [0:0] cby_1__1__118_left_grid_pin_28_ ; +wire [0:0] cby_1__1__118_left_grid_pin_29_ ; +wire [0:0] cby_1__1__118_left_grid_pin_30_ ; +wire [0:0] cby_1__1__118_left_grid_pin_31_ ; +wire [0:0] cby_1__1__119_ccff_tail ; +wire [0:29] cby_1__1__119_chany_bottom_out ; +wire [0:29] cby_1__1__119_chany_top_out ; +wire [0:0] cby_1__1__119_left_grid_pin_16_ ; +wire [0:0] cby_1__1__119_left_grid_pin_17_ ; +wire [0:0] cby_1__1__119_left_grid_pin_18_ ; +wire [0:0] cby_1__1__119_left_grid_pin_19_ ; +wire [0:0] cby_1__1__119_left_grid_pin_20_ ; +wire [0:0] cby_1__1__119_left_grid_pin_21_ ; +wire [0:0] cby_1__1__119_left_grid_pin_22_ ; +wire [0:0] cby_1__1__119_left_grid_pin_23_ ; +wire [0:0] cby_1__1__119_left_grid_pin_24_ ; +wire [0:0] cby_1__1__119_left_grid_pin_25_ ; +wire [0:0] cby_1__1__119_left_grid_pin_26_ ; +wire [0:0] cby_1__1__119_left_grid_pin_27_ ; +wire [0:0] cby_1__1__119_left_grid_pin_28_ ; +wire [0:0] cby_1__1__119_left_grid_pin_29_ ; +wire [0:0] cby_1__1__119_left_grid_pin_30_ ; +wire [0:0] cby_1__1__119_left_grid_pin_31_ ; +wire [0:0] cby_1__1__11_ccff_tail ; +wire [0:29] cby_1__1__11_chany_bottom_out ; +wire [0:29] cby_1__1__11_chany_top_out ; +wire [0:0] cby_1__1__11_left_grid_pin_16_ ; +wire [0:0] cby_1__1__11_left_grid_pin_17_ ; +wire [0:0] cby_1__1__11_left_grid_pin_18_ ; +wire [0:0] cby_1__1__11_left_grid_pin_19_ ; +wire [0:0] cby_1__1__11_left_grid_pin_20_ ; +wire [0:0] cby_1__1__11_left_grid_pin_21_ ; +wire [0:0] cby_1__1__11_left_grid_pin_22_ ; +wire [0:0] cby_1__1__11_left_grid_pin_23_ ; +wire [0:0] cby_1__1__11_left_grid_pin_24_ ; +wire [0:0] cby_1__1__11_left_grid_pin_25_ ; +wire [0:0] cby_1__1__11_left_grid_pin_26_ ; +wire [0:0] cby_1__1__11_left_grid_pin_27_ ; +wire [0:0] cby_1__1__11_left_grid_pin_28_ ; +wire [0:0] cby_1__1__11_left_grid_pin_29_ ; +wire [0:0] cby_1__1__11_left_grid_pin_30_ ; +wire [0:0] cby_1__1__11_left_grid_pin_31_ ; +wire [0:0] cby_1__1__120_ccff_tail ; +wire [0:29] cby_1__1__120_chany_bottom_out ; +wire [0:29] cby_1__1__120_chany_top_out ; +wire [0:0] cby_1__1__120_left_grid_pin_16_ ; +wire [0:0] cby_1__1__120_left_grid_pin_17_ ; +wire [0:0] cby_1__1__120_left_grid_pin_18_ ; +wire [0:0] cby_1__1__120_left_grid_pin_19_ ; +wire [0:0] cby_1__1__120_left_grid_pin_20_ ; +wire [0:0] cby_1__1__120_left_grid_pin_21_ ; +wire [0:0] cby_1__1__120_left_grid_pin_22_ ; +wire [0:0] cby_1__1__120_left_grid_pin_23_ ; +wire [0:0] cby_1__1__120_left_grid_pin_24_ ; +wire [0:0] cby_1__1__120_left_grid_pin_25_ ; +wire [0:0] cby_1__1__120_left_grid_pin_26_ ; +wire [0:0] cby_1__1__120_left_grid_pin_27_ ; +wire [0:0] cby_1__1__120_left_grid_pin_28_ ; +wire [0:0] cby_1__1__120_left_grid_pin_29_ ; +wire [0:0] cby_1__1__120_left_grid_pin_30_ ; +wire [0:0] cby_1__1__120_left_grid_pin_31_ ; +wire [0:0] cby_1__1__121_ccff_tail ; +wire [0:29] cby_1__1__121_chany_bottom_out ; +wire [0:29] cby_1__1__121_chany_top_out ; +wire [0:0] cby_1__1__121_left_grid_pin_16_ ; +wire [0:0] cby_1__1__121_left_grid_pin_17_ ; +wire [0:0] cby_1__1__121_left_grid_pin_18_ ; +wire [0:0] cby_1__1__121_left_grid_pin_19_ ; +wire [0:0] cby_1__1__121_left_grid_pin_20_ ; +wire [0:0] cby_1__1__121_left_grid_pin_21_ ; +wire [0:0] cby_1__1__121_left_grid_pin_22_ ; +wire [0:0] cby_1__1__121_left_grid_pin_23_ ; +wire [0:0] cby_1__1__121_left_grid_pin_24_ ; +wire [0:0] cby_1__1__121_left_grid_pin_25_ ; +wire [0:0] cby_1__1__121_left_grid_pin_26_ ; +wire [0:0] cby_1__1__121_left_grid_pin_27_ ; +wire [0:0] cby_1__1__121_left_grid_pin_28_ ; +wire [0:0] cby_1__1__121_left_grid_pin_29_ ; +wire [0:0] cby_1__1__121_left_grid_pin_30_ ; +wire [0:0] cby_1__1__121_left_grid_pin_31_ ; +wire [0:0] cby_1__1__122_ccff_tail ; +wire [0:29] cby_1__1__122_chany_bottom_out ; +wire [0:29] cby_1__1__122_chany_top_out ; +wire [0:0] cby_1__1__122_left_grid_pin_16_ ; +wire [0:0] cby_1__1__122_left_grid_pin_17_ ; +wire [0:0] cby_1__1__122_left_grid_pin_18_ ; +wire [0:0] cby_1__1__122_left_grid_pin_19_ ; +wire [0:0] cby_1__1__122_left_grid_pin_20_ ; +wire [0:0] cby_1__1__122_left_grid_pin_21_ ; +wire [0:0] cby_1__1__122_left_grid_pin_22_ ; +wire [0:0] cby_1__1__122_left_grid_pin_23_ ; +wire [0:0] cby_1__1__122_left_grid_pin_24_ ; +wire [0:0] cby_1__1__122_left_grid_pin_25_ ; +wire [0:0] cby_1__1__122_left_grid_pin_26_ ; +wire [0:0] cby_1__1__122_left_grid_pin_27_ ; +wire [0:0] cby_1__1__122_left_grid_pin_28_ ; +wire [0:0] cby_1__1__122_left_grid_pin_29_ ; +wire [0:0] cby_1__1__122_left_grid_pin_30_ ; +wire [0:0] cby_1__1__122_left_grid_pin_31_ ; +wire [0:0] cby_1__1__123_ccff_tail ; +wire [0:29] cby_1__1__123_chany_bottom_out ; +wire [0:29] cby_1__1__123_chany_top_out ; +wire [0:0] cby_1__1__123_left_grid_pin_16_ ; +wire [0:0] cby_1__1__123_left_grid_pin_17_ ; +wire [0:0] cby_1__1__123_left_grid_pin_18_ ; +wire [0:0] cby_1__1__123_left_grid_pin_19_ ; +wire [0:0] cby_1__1__123_left_grid_pin_20_ ; +wire [0:0] cby_1__1__123_left_grid_pin_21_ ; +wire [0:0] cby_1__1__123_left_grid_pin_22_ ; +wire [0:0] cby_1__1__123_left_grid_pin_23_ ; +wire [0:0] cby_1__1__123_left_grid_pin_24_ ; +wire [0:0] cby_1__1__123_left_grid_pin_25_ ; +wire [0:0] cby_1__1__123_left_grid_pin_26_ ; +wire [0:0] cby_1__1__123_left_grid_pin_27_ ; +wire [0:0] cby_1__1__123_left_grid_pin_28_ ; +wire [0:0] cby_1__1__123_left_grid_pin_29_ ; +wire [0:0] cby_1__1__123_left_grid_pin_30_ ; +wire [0:0] cby_1__1__123_left_grid_pin_31_ ; +wire [0:0] cby_1__1__124_ccff_tail ; +wire [0:29] cby_1__1__124_chany_bottom_out ; +wire [0:29] cby_1__1__124_chany_top_out ; +wire [0:0] cby_1__1__124_left_grid_pin_16_ ; +wire [0:0] cby_1__1__124_left_grid_pin_17_ ; +wire [0:0] cby_1__1__124_left_grid_pin_18_ ; +wire [0:0] cby_1__1__124_left_grid_pin_19_ ; +wire [0:0] cby_1__1__124_left_grid_pin_20_ ; +wire [0:0] cby_1__1__124_left_grid_pin_21_ ; +wire [0:0] cby_1__1__124_left_grid_pin_22_ ; +wire [0:0] cby_1__1__124_left_grid_pin_23_ ; +wire [0:0] cby_1__1__124_left_grid_pin_24_ ; +wire [0:0] cby_1__1__124_left_grid_pin_25_ ; +wire [0:0] cby_1__1__124_left_grid_pin_26_ ; +wire [0:0] cby_1__1__124_left_grid_pin_27_ ; +wire [0:0] cby_1__1__124_left_grid_pin_28_ ; +wire [0:0] cby_1__1__124_left_grid_pin_29_ ; +wire [0:0] cby_1__1__124_left_grid_pin_30_ ; +wire [0:0] cby_1__1__124_left_grid_pin_31_ ; +wire [0:0] cby_1__1__125_ccff_tail ; +wire [0:29] cby_1__1__125_chany_bottom_out ; +wire [0:29] cby_1__1__125_chany_top_out ; +wire [0:0] cby_1__1__125_left_grid_pin_16_ ; +wire [0:0] cby_1__1__125_left_grid_pin_17_ ; +wire [0:0] cby_1__1__125_left_grid_pin_18_ ; +wire [0:0] cby_1__1__125_left_grid_pin_19_ ; +wire [0:0] cby_1__1__125_left_grid_pin_20_ ; +wire [0:0] cby_1__1__125_left_grid_pin_21_ ; +wire [0:0] cby_1__1__125_left_grid_pin_22_ ; +wire [0:0] cby_1__1__125_left_grid_pin_23_ ; +wire [0:0] cby_1__1__125_left_grid_pin_24_ ; +wire [0:0] cby_1__1__125_left_grid_pin_25_ ; +wire [0:0] cby_1__1__125_left_grid_pin_26_ ; +wire [0:0] cby_1__1__125_left_grid_pin_27_ ; +wire [0:0] cby_1__1__125_left_grid_pin_28_ ; +wire [0:0] cby_1__1__125_left_grid_pin_29_ ; +wire [0:0] cby_1__1__125_left_grid_pin_30_ ; +wire [0:0] cby_1__1__125_left_grid_pin_31_ ; +wire [0:0] cby_1__1__126_ccff_tail ; +wire [0:29] cby_1__1__126_chany_bottom_out ; +wire [0:29] cby_1__1__126_chany_top_out ; +wire [0:0] cby_1__1__126_left_grid_pin_16_ ; +wire [0:0] cby_1__1__126_left_grid_pin_17_ ; +wire [0:0] cby_1__1__126_left_grid_pin_18_ ; +wire [0:0] cby_1__1__126_left_grid_pin_19_ ; +wire [0:0] cby_1__1__126_left_grid_pin_20_ ; +wire [0:0] cby_1__1__126_left_grid_pin_21_ ; +wire [0:0] cby_1__1__126_left_grid_pin_22_ ; +wire [0:0] cby_1__1__126_left_grid_pin_23_ ; +wire [0:0] cby_1__1__126_left_grid_pin_24_ ; +wire [0:0] cby_1__1__126_left_grid_pin_25_ ; +wire [0:0] cby_1__1__126_left_grid_pin_26_ ; +wire [0:0] cby_1__1__126_left_grid_pin_27_ ; +wire [0:0] cby_1__1__126_left_grid_pin_28_ ; +wire [0:0] cby_1__1__126_left_grid_pin_29_ ; +wire [0:0] cby_1__1__126_left_grid_pin_30_ ; +wire [0:0] cby_1__1__126_left_grid_pin_31_ ; +wire [0:0] cby_1__1__127_ccff_tail ; +wire [0:29] cby_1__1__127_chany_bottom_out ; +wire [0:29] cby_1__1__127_chany_top_out ; +wire [0:0] cby_1__1__127_left_grid_pin_16_ ; +wire [0:0] cby_1__1__127_left_grid_pin_17_ ; +wire [0:0] cby_1__1__127_left_grid_pin_18_ ; +wire [0:0] cby_1__1__127_left_grid_pin_19_ ; +wire [0:0] cby_1__1__127_left_grid_pin_20_ ; +wire [0:0] cby_1__1__127_left_grid_pin_21_ ; +wire [0:0] cby_1__1__127_left_grid_pin_22_ ; +wire [0:0] cby_1__1__127_left_grid_pin_23_ ; +wire [0:0] cby_1__1__127_left_grid_pin_24_ ; +wire [0:0] cby_1__1__127_left_grid_pin_25_ ; +wire [0:0] cby_1__1__127_left_grid_pin_26_ ; +wire [0:0] cby_1__1__127_left_grid_pin_27_ ; +wire [0:0] cby_1__1__127_left_grid_pin_28_ ; +wire [0:0] cby_1__1__127_left_grid_pin_29_ ; +wire [0:0] cby_1__1__127_left_grid_pin_30_ ; +wire [0:0] cby_1__1__127_left_grid_pin_31_ ; +wire [0:0] cby_1__1__128_ccff_tail ; +wire [0:29] cby_1__1__128_chany_bottom_out ; +wire [0:29] cby_1__1__128_chany_top_out ; +wire [0:0] cby_1__1__128_left_grid_pin_16_ ; +wire [0:0] cby_1__1__128_left_grid_pin_17_ ; +wire [0:0] cby_1__1__128_left_grid_pin_18_ ; +wire [0:0] cby_1__1__128_left_grid_pin_19_ ; +wire [0:0] cby_1__1__128_left_grid_pin_20_ ; +wire [0:0] cby_1__1__128_left_grid_pin_21_ ; +wire [0:0] cby_1__1__128_left_grid_pin_22_ ; +wire [0:0] cby_1__1__128_left_grid_pin_23_ ; +wire [0:0] cby_1__1__128_left_grid_pin_24_ ; +wire [0:0] cby_1__1__128_left_grid_pin_25_ ; +wire [0:0] cby_1__1__128_left_grid_pin_26_ ; +wire [0:0] cby_1__1__128_left_grid_pin_27_ ; +wire [0:0] cby_1__1__128_left_grid_pin_28_ ; +wire [0:0] cby_1__1__128_left_grid_pin_29_ ; +wire [0:0] cby_1__1__128_left_grid_pin_30_ ; +wire [0:0] cby_1__1__128_left_grid_pin_31_ ; +wire [0:0] cby_1__1__129_ccff_tail ; +wire [0:29] cby_1__1__129_chany_bottom_out ; +wire [0:29] cby_1__1__129_chany_top_out ; +wire [0:0] cby_1__1__129_left_grid_pin_16_ ; +wire [0:0] cby_1__1__129_left_grid_pin_17_ ; +wire [0:0] cby_1__1__129_left_grid_pin_18_ ; +wire [0:0] cby_1__1__129_left_grid_pin_19_ ; +wire [0:0] cby_1__1__129_left_grid_pin_20_ ; +wire [0:0] cby_1__1__129_left_grid_pin_21_ ; +wire [0:0] cby_1__1__129_left_grid_pin_22_ ; +wire [0:0] cby_1__1__129_left_grid_pin_23_ ; +wire [0:0] cby_1__1__129_left_grid_pin_24_ ; +wire [0:0] cby_1__1__129_left_grid_pin_25_ ; +wire [0:0] cby_1__1__129_left_grid_pin_26_ ; +wire [0:0] cby_1__1__129_left_grid_pin_27_ ; +wire [0:0] cby_1__1__129_left_grid_pin_28_ ; +wire [0:0] cby_1__1__129_left_grid_pin_29_ ; +wire [0:0] cby_1__1__129_left_grid_pin_30_ ; +wire [0:0] cby_1__1__129_left_grid_pin_31_ ; +wire [0:0] cby_1__1__12_ccff_tail ; +wire [0:29] cby_1__1__12_chany_bottom_out ; +wire [0:29] cby_1__1__12_chany_top_out ; +wire [0:0] cby_1__1__12_left_grid_pin_16_ ; +wire [0:0] cby_1__1__12_left_grid_pin_17_ ; +wire [0:0] cby_1__1__12_left_grid_pin_18_ ; +wire [0:0] cby_1__1__12_left_grid_pin_19_ ; +wire [0:0] cby_1__1__12_left_grid_pin_20_ ; +wire [0:0] cby_1__1__12_left_grid_pin_21_ ; +wire [0:0] cby_1__1__12_left_grid_pin_22_ ; +wire [0:0] cby_1__1__12_left_grid_pin_23_ ; +wire [0:0] cby_1__1__12_left_grid_pin_24_ ; +wire [0:0] cby_1__1__12_left_grid_pin_25_ ; +wire [0:0] cby_1__1__12_left_grid_pin_26_ ; +wire [0:0] cby_1__1__12_left_grid_pin_27_ ; +wire [0:0] cby_1__1__12_left_grid_pin_28_ ; +wire [0:0] cby_1__1__12_left_grid_pin_29_ ; +wire [0:0] cby_1__1__12_left_grid_pin_30_ ; +wire [0:0] cby_1__1__12_left_grid_pin_31_ ; +wire [0:0] cby_1__1__130_ccff_tail ; +wire [0:29] cby_1__1__130_chany_bottom_out ; +wire [0:29] cby_1__1__130_chany_top_out ; +wire [0:0] cby_1__1__130_left_grid_pin_16_ ; +wire [0:0] cby_1__1__130_left_grid_pin_17_ ; +wire [0:0] cby_1__1__130_left_grid_pin_18_ ; +wire [0:0] cby_1__1__130_left_grid_pin_19_ ; +wire [0:0] cby_1__1__130_left_grid_pin_20_ ; +wire [0:0] cby_1__1__130_left_grid_pin_21_ ; +wire [0:0] cby_1__1__130_left_grid_pin_22_ ; +wire [0:0] cby_1__1__130_left_grid_pin_23_ ; +wire [0:0] cby_1__1__130_left_grid_pin_24_ ; +wire [0:0] cby_1__1__130_left_grid_pin_25_ ; +wire [0:0] cby_1__1__130_left_grid_pin_26_ ; +wire [0:0] cby_1__1__130_left_grid_pin_27_ ; +wire [0:0] cby_1__1__130_left_grid_pin_28_ ; +wire [0:0] cby_1__1__130_left_grid_pin_29_ ; +wire [0:0] cby_1__1__130_left_grid_pin_30_ ; +wire [0:0] cby_1__1__130_left_grid_pin_31_ ; +wire [0:0] cby_1__1__131_ccff_tail ; +wire [0:29] cby_1__1__131_chany_bottom_out ; +wire [0:29] cby_1__1__131_chany_top_out ; +wire [0:0] cby_1__1__131_left_grid_pin_16_ ; +wire [0:0] cby_1__1__131_left_grid_pin_17_ ; +wire [0:0] cby_1__1__131_left_grid_pin_18_ ; +wire [0:0] cby_1__1__131_left_grid_pin_19_ ; +wire [0:0] cby_1__1__131_left_grid_pin_20_ ; +wire [0:0] cby_1__1__131_left_grid_pin_21_ ; +wire [0:0] cby_1__1__131_left_grid_pin_22_ ; +wire [0:0] cby_1__1__131_left_grid_pin_23_ ; +wire [0:0] cby_1__1__131_left_grid_pin_24_ ; +wire [0:0] cby_1__1__131_left_grid_pin_25_ ; +wire [0:0] cby_1__1__131_left_grid_pin_26_ ; +wire [0:0] cby_1__1__131_left_grid_pin_27_ ; +wire [0:0] cby_1__1__131_left_grid_pin_28_ ; +wire [0:0] cby_1__1__131_left_grid_pin_29_ ; +wire [0:0] cby_1__1__131_left_grid_pin_30_ ; +wire [0:0] cby_1__1__131_left_grid_pin_31_ ; +wire [0:0] cby_1__1__13_ccff_tail ; +wire [0:29] cby_1__1__13_chany_bottom_out ; +wire [0:29] cby_1__1__13_chany_top_out ; +wire [0:0] cby_1__1__13_left_grid_pin_16_ ; +wire [0:0] cby_1__1__13_left_grid_pin_17_ ; +wire [0:0] cby_1__1__13_left_grid_pin_18_ ; +wire [0:0] cby_1__1__13_left_grid_pin_19_ ; +wire [0:0] cby_1__1__13_left_grid_pin_20_ ; +wire [0:0] cby_1__1__13_left_grid_pin_21_ ; +wire [0:0] cby_1__1__13_left_grid_pin_22_ ; +wire [0:0] cby_1__1__13_left_grid_pin_23_ ; +wire [0:0] cby_1__1__13_left_grid_pin_24_ ; +wire [0:0] cby_1__1__13_left_grid_pin_25_ ; +wire [0:0] cby_1__1__13_left_grid_pin_26_ ; +wire [0:0] cby_1__1__13_left_grid_pin_27_ ; +wire [0:0] cby_1__1__13_left_grid_pin_28_ ; +wire [0:0] cby_1__1__13_left_grid_pin_29_ ; +wire [0:0] cby_1__1__13_left_grid_pin_30_ ; +wire [0:0] cby_1__1__13_left_grid_pin_31_ ; +wire [0:0] cby_1__1__14_ccff_tail ; +wire [0:29] cby_1__1__14_chany_bottom_out ; +wire [0:29] cby_1__1__14_chany_top_out ; +wire [0:0] cby_1__1__14_left_grid_pin_16_ ; +wire [0:0] cby_1__1__14_left_grid_pin_17_ ; +wire [0:0] cby_1__1__14_left_grid_pin_18_ ; +wire [0:0] cby_1__1__14_left_grid_pin_19_ ; +wire [0:0] cby_1__1__14_left_grid_pin_20_ ; +wire [0:0] cby_1__1__14_left_grid_pin_21_ ; +wire [0:0] cby_1__1__14_left_grid_pin_22_ ; +wire [0:0] cby_1__1__14_left_grid_pin_23_ ; +wire [0:0] cby_1__1__14_left_grid_pin_24_ ; +wire [0:0] cby_1__1__14_left_grid_pin_25_ ; +wire [0:0] cby_1__1__14_left_grid_pin_26_ ; +wire [0:0] cby_1__1__14_left_grid_pin_27_ ; +wire [0:0] cby_1__1__14_left_grid_pin_28_ ; +wire [0:0] cby_1__1__14_left_grid_pin_29_ ; +wire [0:0] cby_1__1__14_left_grid_pin_30_ ; +wire [0:0] cby_1__1__14_left_grid_pin_31_ ; +wire [0:0] cby_1__1__15_ccff_tail ; +wire [0:29] cby_1__1__15_chany_bottom_out ; +wire [0:29] cby_1__1__15_chany_top_out ; +wire [0:0] cby_1__1__15_left_grid_pin_16_ ; +wire [0:0] cby_1__1__15_left_grid_pin_17_ ; +wire [0:0] cby_1__1__15_left_grid_pin_18_ ; +wire [0:0] cby_1__1__15_left_grid_pin_19_ ; +wire [0:0] cby_1__1__15_left_grid_pin_20_ ; +wire [0:0] cby_1__1__15_left_grid_pin_21_ ; +wire [0:0] cby_1__1__15_left_grid_pin_22_ ; +wire [0:0] cby_1__1__15_left_grid_pin_23_ ; +wire [0:0] cby_1__1__15_left_grid_pin_24_ ; +wire [0:0] cby_1__1__15_left_grid_pin_25_ ; +wire [0:0] cby_1__1__15_left_grid_pin_26_ ; +wire [0:0] cby_1__1__15_left_grid_pin_27_ ; +wire [0:0] cby_1__1__15_left_grid_pin_28_ ; +wire [0:0] cby_1__1__15_left_grid_pin_29_ ; +wire [0:0] cby_1__1__15_left_grid_pin_30_ ; +wire [0:0] cby_1__1__15_left_grid_pin_31_ ; +wire [0:0] cby_1__1__16_ccff_tail ; +wire [0:29] cby_1__1__16_chany_bottom_out ; +wire [0:29] cby_1__1__16_chany_top_out ; +wire [0:0] cby_1__1__16_left_grid_pin_16_ ; +wire [0:0] cby_1__1__16_left_grid_pin_17_ ; +wire [0:0] cby_1__1__16_left_grid_pin_18_ ; +wire [0:0] cby_1__1__16_left_grid_pin_19_ ; +wire [0:0] cby_1__1__16_left_grid_pin_20_ ; +wire [0:0] cby_1__1__16_left_grid_pin_21_ ; +wire [0:0] cby_1__1__16_left_grid_pin_22_ ; +wire [0:0] cby_1__1__16_left_grid_pin_23_ ; +wire [0:0] cby_1__1__16_left_grid_pin_24_ ; +wire [0:0] cby_1__1__16_left_grid_pin_25_ ; +wire [0:0] cby_1__1__16_left_grid_pin_26_ ; +wire [0:0] cby_1__1__16_left_grid_pin_27_ ; +wire [0:0] cby_1__1__16_left_grid_pin_28_ ; +wire [0:0] cby_1__1__16_left_grid_pin_29_ ; +wire [0:0] cby_1__1__16_left_grid_pin_30_ ; +wire [0:0] cby_1__1__16_left_grid_pin_31_ ; +wire [0:0] cby_1__1__17_ccff_tail ; +wire [0:29] cby_1__1__17_chany_bottom_out ; +wire [0:29] cby_1__1__17_chany_top_out ; +wire [0:0] cby_1__1__17_left_grid_pin_16_ ; +wire [0:0] cby_1__1__17_left_grid_pin_17_ ; +wire [0:0] cby_1__1__17_left_grid_pin_18_ ; +wire [0:0] cby_1__1__17_left_grid_pin_19_ ; +wire [0:0] cby_1__1__17_left_grid_pin_20_ ; +wire [0:0] cby_1__1__17_left_grid_pin_21_ ; +wire [0:0] cby_1__1__17_left_grid_pin_22_ ; +wire [0:0] cby_1__1__17_left_grid_pin_23_ ; +wire [0:0] cby_1__1__17_left_grid_pin_24_ ; +wire [0:0] cby_1__1__17_left_grid_pin_25_ ; +wire [0:0] cby_1__1__17_left_grid_pin_26_ ; +wire [0:0] cby_1__1__17_left_grid_pin_27_ ; +wire [0:0] cby_1__1__17_left_grid_pin_28_ ; +wire [0:0] cby_1__1__17_left_grid_pin_29_ ; +wire [0:0] cby_1__1__17_left_grid_pin_30_ ; +wire [0:0] cby_1__1__17_left_grid_pin_31_ ; +wire [0:0] cby_1__1__18_ccff_tail ; +wire [0:29] cby_1__1__18_chany_bottom_out ; +wire [0:29] cby_1__1__18_chany_top_out ; +wire [0:0] cby_1__1__18_left_grid_pin_16_ ; +wire [0:0] cby_1__1__18_left_grid_pin_17_ ; +wire [0:0] cby_1__1__18_left_grid_pin_18_ ; +wire [0:0] cby_1__1__18_left_grid_pin_19_ ; +wire [0:0] cby_1__1__18_left_grid_pin_20_ ; +wire [0:0] cby_1__1__18_left_grid_pin_21_ ; +wire [0:0] cby_1__1__18_left_grid_pin_22_ ; +wire [0:0] cby_1__1__18_left_grid_pin_23_ ; +wire [0:0] cby_1__1__18_left_grid_pin_24_ ; +wire [0:0] cby_1__1__18_left_grid_pin_25_ ; +wire [0:0] cby_1__1__18_left_grid_pin_26_ ; +wire [0:0] cby_1__1__18_left_grid_pin_27_ ; +wire [0:0] cby_1__1__18_left_grid_pin_28_ ; +wire [0:0] cby_1__1__18_left_grid_pin_29_ ; +wire [0:0] cby_1__1__18_left_grid_pin_30_ ; +wire [0:0] cby_1__1__18_left_grid_pin_31_ ; +wire [0:0] cby_1__1__19_ccff_tail ; +wire [0:29] cby_1__1__19_chany_bottom_out ; +wire [0:29] cby_1__1__19_chany_top_out ; +wire [0:0] cby_1__1__19_left_grid_pin_16_ ; +wire [0:0] cby_1__1__19_left_grid_pin_17_ ; +wire [0:0] cby_1__1__19_left_grid_pin_18_ ; +wire [0:0] cby_1__1__19_left_grid_pin_19_ ; +wire [0:0] cby_1__1__19_left_grid_pin_20_ ; +wire [0:0] cby_1__1__19_left_grid_pin_21_ ; +wire [0:0] cby_1__1__19_left_grid_pin_22_ ; +wire [0:0] cby_1__1__19_left_grid_pin_23_ ; +wire [0:0] cby_1__1__19_left_grid_pin_24_ ; +wire [0:0] cby_1__1__19_left_grid_pin_25_ ; +wire [0:0] cby_1__1__19_left_grid_pin_26_ ; +wire [0:0] cby_1__1__19_left_grid_pin_27_ ; +wire [0:0] cby_1__1__19_left_grid_pin_28_ ; +wire [0:0] cby_1__1__19_left_grid_pin_29_ ; +wire [0:0] cby_1__1__19_left_grid_pin_30_ ; +wire [0:0] cby_1__1__19_left_grid_pin_31_ ; +wire [0:0] cby_1__1__1_ccff_tail ; +wire [0:29] cby_1__1__1_chany_bottom_out ; +wire [0:29] cby_1__1__1_chany_top_out ; +wire [0:0] cby_1__1__1_left_grid_pin_16_ ; +wire [0:0] cby_1__1__1_left_grid_pin_17_ ; +wire [0:0] cby_1__1__1_left_grid_pin_18_ ; +wire [0:0] cby_1__1__1_left_grid_pin_19_ ; +wire [0:0] cby_1__1__1_left_grid_pin_20_ ; +wire [0:0] cby_1__1__1_left_grid_pin_21_ ; +wire [0:0] cby_1__1__1_left_grid_pin_22_ ; +wire [0:0] cby_1__1__1_left_grid_pin_23_ ; +wire [0:0] cby_1__1__1_left_grid_pin_24_ ; +wire [0:0] cby_1__1__1_left_grid_pin_25_ ; +wire [0:0] cby_1__1__1_left_grid_pin_26_ ; +wire [0:0] cby_1__1__1_left_grid_pin_27_ ; +wire [0:0] cby_1__1__1_left_grid_pin_28_ ; +wire [0:0] cby_1__1__1_left_grid_pin_29_ ; +wire [0:0] cby_1__1__1_left_grid_pin_30_ ; +wire [0:0] cby_1__1__1_left_grid_pin_31_ ; +wire [0:0] cby_1__1__20_ccff_tail ; +wire [0:29] cby_1__1__20_chany_bottom_out ; +wire [0:29] cby_1__1__20_chany_top_out ; +wire [0:0] cby_1__1__20_left_grid_pin_16_ ; +wire [0:0] cby_1__1__20_left_grid_pin_17_ ; +wire [0:0] cby_1__1__20_left_grid_pin_18_ ; +wire [0:0] cby_1__1__20_left_grid_pin_19_ ; +wire [0:0] cby_1__1__20_left_grid_pin_20_ ; +wire [0:0] cby_1__1__20_left_grid_pin_21_ ; +wire [0:0] cby_1__1__20_left_grid_pin_22_ ; +wire [0:0] cby_1__1__20_left_grid_pin_23_ ; +wire [0:0] cby_1__1__20_left_grid_pin_24_ ; +wire [0:0] cby_1__1__20_left_grid_pin_25_ ; +wire [0:0] cby_1__1__20_left_grid_pin_26_ ; +wire [0:0] cby_1__1__20_left_grid_pin_27_ ; +wire [0:0] cby_1__1__20_left_grid_pin_28_ ; +wire [0:0] cby_1__1__20_left_grid_pin_29_ ; +wire [0:0] cby_1__1__20_left_grid_pin_30_ ; +wire [0:0] cby_1__1__20_left_grid_pin_31_ ; +wire [0:0] cby_1__1__21_ccff_tail ; +wire [0:29] cby_1__1__21_chany_bottom_out ; +wire [0:29] cby_1__1__21_chany_top_out ; +wire [0:0] cby_1__1__21_left_grid_pin_16_ ; +wire [0:0] cby_1__1__21_left_grid_pin_17_ ; +wire [0:0] cby_1__1__21_left_grid_pin_18_ ; +wire [0:0] cby_1__1__21_left_grid_pin_19_ ; +wire [0:0] cby_1__1__21_left_grid_pin_20_ ; +wire [0:0] cby_1__1__21_left_grid_pin_21_ ; +wire [0:0] cby_1__1__21_left_grid_pin_22_ ; +wire [0:0] cby_1__1__21_left_grid_pin_23_ ; +wire [0:0] cby_1__1__21_left_grid_pin_24_ ; +wire [0:0] cby_1__1__21_left_grid_pin_25_ ; +wire [0:0] cby_1__1__21_left_grid_pin_26_ ; +wire [0:0] cby_1__1__21_left_grid_pin_27_ ; +wire [0:0] cby_1__1__21_left_grid_pin_28_ ; +wire [0:0] cby_1__1__21_left_grid_pin_29_ ; +wire [0:0] cby_1__1__21_left_grid_pin_30_ ; +wire [0:0] cby_1__1__21_left_grid_pin_31_ ; +wire [0:0] cby_1__1__22_ccff_tail ; +wire [0:29] cby_1__1__22_chany_bottom_out ; +wire [0:29] cby_1__1__22_chany_top_out ; +wire [0:0] cby_1__1__22_left_grid_pin_16_ ; +wire [0:0] cby_1__1__22_left_grid_pin_17_ ; +wire [0:0] cby_1__1__22_left_grid_pin_18_ ; +wire [0:0] cby_1__1__22_left_grid_pin_19_ ; +wire [0:0] cby_1__1__22_left_grid_pin_20_ ; +wire [0:0] cby_1__1__22_left_grid_pin_21_ ; +wire [0:0] cby_1__1__22_left_grid_pin_22_ ; +wire [0:0] cby_1__1__22_left_grid_pin_23_ ; +wire [0:0] cby_1__1__22_left_grid_pin_24_ ; +wire [0:0] cby_1__1__22_left_grid_pin_25_ ; +wire [0:0] cby_1__1__22_left_grid_pin_26_ ; +wire [0:0] cby_1__1__22_left_grid_pin_27_ ; +wire [0:0] cby_1__1__22_left_grid_pin_28_ ; +wire [0:0] cby_1__1__22_left_grid_pin_29_ ; +wire [0:0] cby_1__1__22_left_grid_pin_30_ ; +wire [0:0] cby_1__1__22_left_grid_pin_31_ ; +wire [0:0] cby_1__1__23_ccff_tail ; +wire [0:29] cby_1__1__23_chany_bottom_out ; +wire [0:29] cby_1__1__23_chany_top_out ; +wire [0:0] cby_1__1__23_left_grid_pin_16_ ; +wire [0:0] cby_1__1__23_left_grid_pin_17_ ; +wire [0:0] cby_1__1__23_left_grid_pin_18_ ; +wire [0:0] cby_1__1__23_left_grid_pin_19_ ; +wire [0:0] cby_1__1__23_left_grid_pin_20_ ; +wire [0:0] cby_1__1__23_left_grid_pin_21_ ; +wire [0:0] cby_1__1__23_left_grid_pin_22_ ; +wire [0:0] cby_1__1__23_left_grid_pin_23_ ; +wire [0:0] cby_1__1__23_left_grid_pin_24_ ; +wire [0:0] cby_1__1__23_left_grid_pin_25_ ; +wire [0:0] cby_1__1__23_left_grid_pin_26_ ; +wire [0:0] cby_1__1__23_left_grid_pin_27_ ; +wire [0:0] cby_1__1__23_left_grid_pin_28_ ; +wire [0:0] cby_1__1__23_left_grid_pin_29_ ; +wire [0:0] cby_1__1__23_left_grid_pin_30_ ; +wire [0:0] cby_1__1__23_left_grid_pin_31_ ; +wire [0:0] cby_1__1__24_ccff_tail ; +wire [0:29] cby_1__1__24_chany_bottom_out ; +wire [0:29] cby_1__1__24_chany_top_out ; +wire [0:0] cby_1__1__24_left_grid_pin_16_ ; +wire [0:0] cby_1__1__24_left_grid_pin_17_ ; +wire [0:0] cby_1__1__24_left_grid_pin_18_ ; +wire [0:0] cby_1__1__24_left_grid_pin_19_ ; +wire [0:0] cby_1__1__24_left_grid_pin_20_ ; +wire [0:0] cby_1__1__24_left_grid_pin_21_ ; +wire [0:0] cby_1__1__24_left_grid_pin_22_ ; +wire [0:0] cby_1__1__24_left_grid_pin_23_ ; +wire [0:0] cby_1__1__24_left_grid_pin_24_ ; +wire [0:0] cby_1__1__24_left_grid_pin_25_ ; +wire [0:0] cby_1__1__24_left_grid_pin_26_ ; +wire [0:0] cby_1__1__24_left_grid_pin_27_ ; +wire [0:0] cby_1__1__24_left_grid_pin_28_ ; +wire [0:0] cby_1__1__24_left_grid_pin_29_ ; +wire [0:0] cby_1__1__24_left_grid_pin_30_ ; +wire [0:0] cby_1__1__24_left_grid_pin_31_ ; +wire [0:0] cby_1__1__25_ccff_tail ; +wire [0:29] cby_1__1__25_chany_bottom_out ; +wire [0:29] cby_1__1__25_chany_top_out ; +wire [0:0] cby_1__1__25_left_grid_pin_16_ ; +wire [0:0] cby_1__1__25_left_grid_pin_17_ ; +wire [0:0] cby_1__1__25_left_grid_pin_18_ ; +wire [0:0] cby_1__1__25_left_grid_pin_19_ ; +wire [0:0] cby_1__1__25_left_grid_pin_20_ ; +wire [0:0] cby_1__1__25_left_grid_pin_21_ ; +wire [0:0] cby_1__1__25_left_grid_pin_22_ ; +wire [0:0] cby_1__1__25_left_grid_pin_23_ ; +wire [0:0] cby_1__1__25_left_grid_pin_24_ ; +wire [0:0] cby_1__1__25_left_grid_pin_25_ ; +wire [0:0] cby_1__1__25_left_grid_pin_26_ ; +wire [0:0] cby_1__1__25_left_grid_pin_27_ ; +wire [0:0] cby_1__1__25_left_grid_pin_28_ ; +wire [0:0] cby_1__1__25_left_grid_pin_29_ ; +wire [0:0] cby_1__1__25_left_grid_pin_30_ ; +wire [0:0] cby_1__1__25_left_grid_pin_31_ ; +wire [0:0] cby_1__1__26_ccff_tail ; +wire [0:29] cby_1__1__26_chany_bottom_out ; +wire [0:29] cby_1__1__26_chany_top_out ; +wire [0:0] cby_1__1__26_left_grid_pin_16_ ; +wire [0:0] cby_1__1__26_left_grid_pin_17_ ; +wire [0:0] cby_1__1__26_left_grid_pin_18_ ; +wire [0:0] cby_1__1__26_left_grid_pin_19_ ; +wire [0:0] cby_1__1__26_left_grid_pin_20_ ; +wire [0:0] cby_1__1__26_left_grid_pin_21_ ; +wire [0:0] cby_1__1__26_left_grid_pin_22_ ; +wire [0:0] cby_1__1__26_left_grid_pin_23_ ; +wire [0:0] cby_1__1__26_left_grid_pin_24_ ; +wire [0:0] cby_1__1__26_left_grid_pin_25_ ; +wire [0:0] cby_1__1__26_left_grid_pin_26_ ; +wire [0:0] cby_1__1__26_left_grid_pin_27_ ; +wire [0:0] cby_1__1__26_left_grid_pin_28_ ; +wire [0:0] cby_1__1__26_left_grid_pin_29_ ; +wire [0:0] cby_1__1__26_left_grid_pin_30_ ; +wire [0:0] cby_1__1__26_left_grid_pin_31_ ; +wire [0:0] cby_1__1__27_ccff_tail ; +wire [0:29] cby_1__1__27_chany_bottom_out ; +wire [0:29] cby_1__1__27_chany_top_out ; +wire [0:0] cby_1__1__27_left_grid_pin_16_ ; +wire [0:0] cby_1__1__27_left_grid_pin_17_ ; +wire [0:0] cby_1__1__27_left_grid_pin_18_ ; +wire [0:0] cby_1__1__27_left_grid_pin_19_ ; +wire [0:0] cby_1__1__27_left_grid_pin_20_ ; +wire [0:0] cby_1__1__27_left_grid_pin_21_ ; +wire [0:0] cby_1__1__27_left_grid_pin_22_ ; +wire [0:0] cby_1__1__27_left_grid_pin_23_ ; +wire [0:0] cby_1__1__27_left_grid_pin_24_ ; +wire [0:0] cby_1__1__27_left_grid_pin_25_ ; +wire [0:0] cby_1__1__27_left_grid_pin_26_ ; +wire [0:0] cby_1__1__27_left_grid_pin_27_ ; +wire [0:0] cby_1__1__27_left_grid_pin_28_ ; +wire [0:0] cby_1__1__27_left_grid_pin_29_ ; +wire [0:0] cby_1__1__27_left_grid_pin_30_ ; +wire [0:0] cby_1__1__27_left_grid_pin_31_ ; +wire [0:0] cby_1__1__28_ccff_tail ; +wire [0:29] cby_1__1__28_chany_bottom_out ; +wire [0:29] cby_1__1__28_chany_top_out ; +wire [0:0] cby_1__1__28_left_grid_pin_16_ ; +wire [0:0] cby_1__1__28_left_grid_pin_17_ ; +wire [0:0] cby_1__1__28_left_grid_pin_18_ ; +wire [0:0] cby_1__1__28_left_grid_pin_19_ ; +wire [0:0] cby_1__1__28_left_grid_pin_20_ ; +wire [0:0] cby_1__1__28_left_grid_pin_21_ ; +wire [0:0] cby_1__1__28_left_grid_pin_22_ ; +wire [0:0] cby_1__1__28_left_grid_pin_23_ ; +wire [0:0] cby_1__1__28_left_grid_pin_24_ ; +wire [0:0] cby_1__1__28_left_grid_pin_25_ ; +wire [0:0] cby_1__1__28_left_grid_pin_26_ ; +wire [0:0] cby_1__1__28_left_grid_pin_27_ ; +wire [0:0] cby_1__1__28_left_grid_pin_28_ ; +wire [0:0] cby_1__1__28_left_grid_pin_29_ ; +wire [0:0] cby_1__1__28_left_grid_pin_30_ ; +wire [0:0] cby_1__1__28_left_grid_pin_31_ ; +wire [0:0] cby_1__1__29_ccff_tail ; +wire [0:29] cby_1__1__29_chany_bottom_out ; +wire [0:29] cby_1__1__29_chany_top_out ; +wire [0:0] cby_1__1__29_left_grid_pin_16_ ; +wire [0:0] cby_1__1__29_left_grid_pin_17_ ; +wire [0:0] cby_1__1__29_left_grid_pin_18_ ; +wire [0:0] cby_1__1__29_left_grid_pin_19_ ; +wire [0:0] cby_1__1__29_left_grid_pin_20_ ; +wire [0:0] cby_1__1__29_left_grid_pin_21_ ; +wire [0:0] cby_1__1__29_left_grid_pin_22_ ; +wire [0:0] cby_1__1__29_left_grid_pin_23_ ; +wire [0:0] cby_1__1__29_left_grid_pin_24_ ; +wire [0:0] cby_1__1__29_left_grid_pin_25_ ; +wire [0:0] cby_1__1__29_left_grid_pin_26_ ; +wire [0:0] cby_1__1__29_left_grid_pin_27_ ; +wire [0:0] cby_1__1__29_left_grid_pin_28_ ; +wire [0:0] cby_1__1__29_left_grid_pin_29_ ; +wire [0:0] cby_1__1__29_left_grid_pin_30_ ; +wire [0:0] cby_1__1__29_left_grid_pin_31_ ; +wire [0:0] cby_1__1__2_ccff_tail ; +wire [0:29] cby_1__1__2_chany_bottom_out ; +wire [0:29] cby_1__1__2_chany_top_out ; +wire [0:0] cby_1__1__2_left_grid_pin_16_ ; +wire [0:0] cby_1__1__2_left_grid_pin_17_ ; +wire [0:0] cby_1__1__2_left_grid_pin_18_ ; +wire [0:0] cby_1__1__2_left_grid_pin_19_ ; +wire [0:0] cby_1__1__2_left_grid_pin_20_ ; +wire [0:0] cby_1__1__2_left_grid_pin_21_ ; +wire [0:0] cby_1__1__2_left_grid_pin_22_ ; +wire [0:0] cby_1__1__2_left_grid_pin_23_ ; +wire [0:0] cby_1__1__2_left_grid_pin_24_ ; +wire [0:0] cby_1__1__2_left_grid_pin_25_ ; +wire [0:0] cby_1__1__2_left_grid_pin_26_ ; +wire [0:0] cby_1__1__2_left_grid_pin_27_ ; +wire [0:0] cby_1__1__2_left_grid_pin_28_ ; +wire [0:0] cby_1__1__2_left_grid_pin_29_ ; +wire [0:0] cby_1__1__2_left_grid_pin_30_ ; +wire [0:0] cby_1__1__2_left_grid_pin_31_ ; +wire [0:0] cby_1__1__30_ccff_tail ; +wire [0:29] cby_1__1__30_chany_bottom_out ; +wire [0:29] cby_1__1__30_chany_top_out ; +wire [0:0] cby_1__1__30_left_grid_pin_16_ ; +wire [0:0] cby_1__1__30_left_grid_pin_17_ ; +wire [0:0] cby_1__1__30_left_grid_pin_18_ ; +wire [0:0] cby_1__1__30_left_grid_pin_19_ ; +wire [0:0] cby_1__1__30_left_grid_pin_20_ ; +wire [0:0] cby_1__1__30_left_grid_pin_21_ ; +wire [0:0] cby_1__1__30_left_grid_pin_22_ ; +wire [0:0] cby_1__1__30_left_grid_pin_23_ ; +wire [0:0] cby_1__1__30_left_grid_pin_24_ ; +wire [0:0] cby_1__1__30_left_grid_pin_25_ ; +wire [0:0] cby_1__1__30_left_grid_pin_26_ ; +wire [0:0] cby_1__1__30_left_grid_pin_27_ ; +wire [0:0] cby_1__1__30_left_grid_pin_28_ ; +wire [0:0] cby_1__1__30_left_grid_pin_29_ ; +wire [0:0] cby_1__1__30_left_grid_pin_30_ ; +wire [0:0] cby_1__1__30_left_grid_pin_31_ ; +wire [0:0] cby_1__1__31_ccff_tail ; +wire [0:29] cby_1__1__31_chany_bottom_out ; +wire [0:29] cby_1__1__31_chany_top_out ; +wire [0:0] cby_1__1__31_left_grid_pin_16_ ; +wire [0:0] cby_1__1__31_left_grid_pin_17_ ; +wire [0:0] cby_1__1__31_left_grid_pin_18_ ; +wire [0:0] cby_1__1__31_left_grid_pin_19_ ; +wire [0:0] cby_1__1__31_left_grid_pin_20_ ; +wire [0:0] cby_1__1__31_left_grid_pin_21_ ; +wire [0:0] cby_1__1__31_left_grid_pin_22_ ; +wire [0:0] cby_1__1__31_left_grid_pin_23_ ; +wire [0:0] cby_1__1__31_left_grid_pin_24_ ; +wire [0:0] cby_1__1__31_left_grid_pin_25_ ; +wire [0:0] cby_1__1__31_left_grid_pin_26_ ; +wire [0:0] cby_1__1__31_left_grid_pin_27_ ; +wire [0:0] cby_1__1__31_left_grid_pin_28_ ; +wire [0:0] cby_1__1__31_left_grid_pin_29_ ; +wire [0:0] cby_1__1__31_left_grid_pin_30_ ; +wire [0:0] cby_1__1__31_left_grid_pin_31_ ; +wire [0:0] cby_1__1__32_ccff_tail ; +wire [0:29] cby_1__1__32_chany_bottom_out ; +wire [0:29] cby_1__1__32_chany_top_out ; +wire [0:0] cby_1__1__32_left_grid_pin_16_ ; +wire [0:0] cby_1__1__32_left_grid_pin_17_ ; +wire [0:0] cby_1__1__32_left_grid_pin_18_ ; +wire [0:0] cby_1__1__32_left_grid_pin_19_ ; +wire [0:0] cby_1__1__32_left_grid_pin_20_ ; +wire [0:0] cby_1__1__32_left_grid_pin_21_ ; +wire [0:0] cby_1__1__32_left_grid_pin_22_ ; +wire [0:0] cby_1__1__32_left_grid_pin_23_ ; +wire [0:0] cby_1__1__32_left_grid_pin_24_ ; +wire [0:0] cby_1__1__32_left_grid_pin_25_ ; +wire [0:0] cby_1__1__32_left_grid_pin_26_ ; +wire [0:0] cby_1__1__32_left_grid_pin_27_ ; +wire [0:0] cby_1__1__32_left_grid_pin_28_ ; +wire [0:0] cby_1__1__32_left_grid_pin_29_ ; +wire [0:0] cby_1__1__32_left_grid_pin_30_ ; +wire [0:0] cby_1__1__32_left_grid_pin_31_ ; +wire [0:0] cby_1__1__33_ccff_tail ; +wire [0:29] cby_1__1__33_chany_bottom_out ; +wire [0:29] cby_1__1__33_chany_top_out ; +wire [0:0] cby_1__1__33_left_grid_pin_16_ ; +wire [0:0] cby_1__1__33_left_grid_pin_17_ ; +wire [0:0] cby_1__1__33_left_grid_pin_18_ ; +wire [0:0] cby_1__1__33_left_grid_pin_19_ ; +wire [0:0] cby_1__1__33_left_grid_pin_20_ ; +wire [0:0] cby_1__1__33_left_grid_pin_21_ ; +wire [0:0] cby_1__1__33_left_grid_pin_22_ ; +wire [0:0] cby_1__1__33_left_grid_pin_23_ ; +wire [0:0] cby_1__1__33_left_grid_pin_24_ ; +wire [0:0] cby_1__1__33_left_grid_pin_25_ ; +wire [0:0] cby_1__1__33_left_grid_pin_26_ ; +wire [0:0] cby_1__1__33_left_grid_pin_27_ ; +wire [0:0] cby_1__1__33_left_grid_pin_28_ ; +wire [0:0] cby_1__1__33_left_grid_pin_29_ ; +wire [0:0] cby_1__1__33_left_grid_pin_30_ ; +wire [0:0] cby_1__1__33_left_grid_pin_31_ ; +wire [0:0] cby_1__1__34_ccff_tail ; +wire [0:29] cby_1__1__34_chany_bottom_out ; +wire [0:29] cby_1__1__34_chany_top_out ; +wire [0:0] cby_1__1__34_left_grid_pin_16_ ; +wire [0:0] cby_1__1__34_left_grid_pin_17_ ; +wire [0:0] cby_1__1__34_left_grid_pin_18_ ; +wire [0:0] cby_1__1__34_left_grid_pin_19_ ; +wire [0:0] cby_1__1__34_left_grid_pin_20_ ; +wire [0:0] cby_1__1__34_left_grid_pin_21_ ; +wire [0:0] cby_1__1__34_left_grid_pin_22_ ; +wire [0:0] cby_1__1__34_left_grid_pin_23_ ; +wire [0:0] cby_1__1__34_left_grid_pin_24_ ; +wire [0:0] cby_1__1__34_left_grid_pin_25_ ; +wire [0:0] cby_1__1__34_left_grid_pin_26_ ; +wire [0:0] cby_1__1__34_left_grid_pin_27_ ; +wire [0:0] cby_1__1__34_left_grid_pin_28_ ; +wire [0:0] cby_1__1__34_left_grid_pin_29_ ; +wire [0:0] cby_1__1__34_left_grid_pin_30_ ; +wire [0:0] cby_1__1__34_left_grid_pin_31_ ; +wire [0:0] cby_1__1__35_ccff_tail ; +wire [0:29] cby_1__1__35_chany_bottom_out ; +wire [0:29] cby_1__1__35_chany_top_out ; +wire [0:0] cby_1__1__35_left_grid_pin_16_ ; +wire [0:0] cby_1__1__35_left_grid_pin_17_ ; +wire [0:0] cby_1__1__35_left_grid_pin_18_ ; +wire [0:0] cby_1__1__35_left_grid_pin_19_ ; +wire [0:0] cby_1__1__35_left_grid_pin_20_ ; +wire [0:0] cby_1__1__35_left_grid_pin_21_ ; +wire [0:0] cby_1__1__35_left_grid_pin_22_ ; +wire [0:0] cby_1__1__35_left_grid_pin_23_ ; +wire [0:0] cby_1__1__35_left_grid_pin_24_ ; +wire [0:0] cby_1__1__35_left_grid_pin_25_ ; +wire [0:0] cby_1__1__35_left_grid_pin_26_ ; +wire [0:0] cby_1__1__35_left_grid_pin_27_ ; +wire [0:0] cby_1__1__35_left_grid_pin_28_ ; +wire [0:0] cby_1__1__35_left_grid_pin_29_ ; +wire [0:0] cby_1__1__35_left_grid_pin_30_ ; +wire [0:0] cby_1__1__35_left_grid_pin_31_ ; +wire [0:0] cby_1__1__36_ccff_tail ; +wire [0:29] cby_1__1__36_chany_bottom_out ; +wire [0:29] cby_1__1__36_chany_top_out ; +wire [0:0] cby_1__1__36_left_grid_pin_16_ ; +wire [0:0] cby_1__1__36_left_grid_pin_17_ ; +wire [0:0] cby_1__1__36_left_grid_pin_18_ ; +wire [0:0] cby_1__1__36_left_grid_pin_19_ ; +wire [0:0] cby_1__1__36_left_grid_pin_20_ ; +wire [0:0] cby_1__1__36_left_grid_pin_21_ ; +wire [0:0] cby_1__1__36_left_grid_pin_22_ ; +wire [0:0] cby_1__1__36_left_grid_pin_23_ ; +wire [0:0] cby_1__1__36_left_grid_pin_24_ ; +wire [0:0] cby_1__1__36_left_grid_pin_25_ ; +wire [0:0] cby_1__1__36_left_grid_pin_26_ ; +wire [0:0] cby_1__1__36_left_grid_pin_27_ ; +wire [0:0] cby_1__1__36_left_grid_pin_28_ ; +wire [0:0] cby_1__1__36_left_grid_pin_29_ ; +wire [0:0] cby_1__1__36_left_grid_pin_30_ ; +wire [0:0] cby_1__1__36_left_grid_pin_31_ ; +wire [0:0] cby_1__1__37_ccff_tail ; +wire [0:29] cby_1__1__37_chany_bottom_out ; +wire [0:29] cby_1__1__37_chany_top_out ; +wire [0:0] cby_1__1__37_left_grid_pin_16_ ; +wire [0:0] cby_1__1__37_left_grid_pin_17_ ; +wire [0:0] cby_1__1__37_left_grid_pin_18_ ; +wire [0:0] cby_1__1__37_left_grid_pin_19_ ; +wire [0:0] cby_1__1__37_left_grid_pin_20_ ; +wire [0:0] cby_1__1__37_left_grid_pin_21_ ; +wire [0:0] cby_1__1__37_left_grid_pin_22_ ; +wire [0:0] cby_1__1__37_left_grid_pin_23_ ; +wire [0:0] cby_1__1__37_left_grid_pin_24_ ; +wire [0:0] cby_1__1__37_left_grid_pin_25_ ; +wire [0:0] cby_1__1__37_left_grid_pin_26_ ; +wire [0:0] cby_1__1__37_left_grid_pin_27_ ; +wire [0:0] cby_1__1__37_left_grid_pin_28_ ; +wire [0:0] cby_1__1__37_left_grid_pin_29_ ; +wire [0:0] cby_1__1__37_left_grid_pin_30_ ; +wire [0:0] cby_1__1__37_left_grid_pin_31_ ; +wire [0:0] cby_1__1__38_ccff_tail ; +wire [0:29] cby_1__1__38_chany_bottom_out ; +wire [0:29] cby_1__1__38_chany_top_out ; +wire [0:0] cby_1__1__38_left_grid_pin_16_ ; +wire [0:0] cby_1__1__38_left_grid_pin_17_ ; +wire [0:0] cby_1__1__38_left_grid_pin_18_ ; +wire [0:0] cby_1__1__38_left_grid_pin_19_ ; +wire [0:0] cby_1__1__38_left_grid_pin_20_ ; +wire [0:0] cby_1__1__38_left_grid_pin_21_ ; +wire [0:0] cby_1__1__38_left_grid_pin_22_ ; +wire [0:0] cby_1__1__38_left_grid_pin_23_ ; +wire [0:0] cby_1__1__38_left_grid_pin_24_ ; +wire [0:0] cby_1__1__38_left_grid_pin_25_ ; +wire [0:0] cby_1__1__38_left_grid_pin_26_ ; +wire [0:0] cby_1__1__38_left_grid_pin_27_ ; +wire [0:0] cby_1__1__38_left_grid_pin_28_ ; +wire [0:0] cby_1__1__38_left_grid_pin_29_ ; +wire [0:0] cby_1__1__38_left_grid_pin_30_ ; +wire [0:0] cby_1__1__38_left_grid_pin_31_ ; +wire [0:0] cby_1__1__39_ccff_tail ; +wire [0:29] cby_1__1__39_chany_bottom_out ; +wire [0:29] cby_1__1__39_chany_top_out ; +wire [0:0] cby_1__1__39_left_grid_pin_16_ ; +wire [0:0] cby_1__1__39_left_grid_pin_17_ ; +wire [0:0] cby_1__1__39_left_grid_pin_18_ ; +wire [0:0] cby_1__1__39_left_grid_pin_19_ ; +wire [0:0] cby_1__1__39_left_grid_pin_20_ ; +wire [0:0] cby_1__1__39_left_grid_pin_21_ ; +wire [0:0] cby_1__1__39_left_grid_pin_22_ ; +wire [0:0] cby_1__1__39_left_grid_pin_23_ ; +wire [0:0] cby_1__1__39_left_grid_pin_24_ ; +wire [0:0] cby_1__1__39_left_grid_pin_25_ ; +wire [0:0] cby_1__1__39_left_grid_pin_26_ ; +wire [0:0] cby_1__1__39_left_grid_pin_27_ ; +wire [0:0] cby_1__1__39_left_grid_pin_28_ ; +wire [0:0] cby_1__1__39_left_grid_pin_29_ ; +wire [0:0] cby_1__1__39_left_grid_pin_30_ ; +wire [0:0] cby_1__1__39_left_grid_pin_31_ ; +wire [0:0] cby_1__1__3_ccff_tail ; +wire [0:29] cby_1__1__3_chany_bottom_out ; +wire [0:29] cby_1__1__3_chany_top_out ; +wire [0:0] cby_1__1__3_left_grid_pin_16_ ; +wire [0:0] cby_1__1__3_left_grid_pin_17_ ; +wire [0:0] cby_1__1__3_left_grid_pin_18_ ; +wire [0:0] cby_1__1__3_left_grid_pin_19_ ; +wire [0:0] cby_1__1__3_left_grid_pin_20_ ; +wire [0:0] cby_1__1__3_left_grid_pin_21_ ; +wire [0:0] cby_1__1__3_left_grid_pin_22_ ; +wire [0:0] cby_1__1__3_left_grid_pin_23_ ; +wire [0:0] cby_1__1__3_left_grid_pin_24_ ; +wire [0:0] cby_1__1__3_left_grid_pin_25_ ; +wire [0:0] cby_1__1__3_left_grid_pin_26_ ; +wire [0:0] cby_1__1__3_left_grid_pin_27_ ; +wire [0:0] cby_1__1__3_left_grid_pin_28_ ; +wire [0:0] cby_1__1__3_left_grid_pin_29_ ; +wire [0:0] cby_1__1__3_left_grid_pin_30_ ; +wire [0:0] cby_1__1__3_left_grid_pin_31_ ; +wire [0:0] cby_1__1__40_ccff_tail ; +wire [0:29] cby_1__1__40_chany_bottom_out ; +wire [0:29] cby_1__1__40_chany_top_out ; +wire [0:0] cby_1__1__40_left_grid_pin_16_ ; +wire [0:0] cby_1__1__40_left_grid_pin_17_ ; +wire [0:0] cby_1__1__40_left_grid_pin_18_ ; +wire [0:0] cby_1__1__40_left_grid_pin_19_ ; +wire [0:0] cby_1__1__40_left_grid_pin_20_ ; +wire [0:0] cby_1__1__40_left_grid_pin_21_ ; +wire [0:0] cby_1__1__40_left_grid_pin_22_ ; +wire [0:0] cby_1__1__40_left_grid_pin_23_ ; +wire [0:0] cby_1__1__40_left_grid_pin_24_ ; +wire [0:0] cby_1__1__40_left_grid_pin_25_ ; +wire [0:0] cby_1__1__40_left_grid_pin_26_ ; +wire [0:0] cby_1__1__40_left_grid_pin_27_ ; +wire [0:0] cby_1__1__40_left_grid_pin_28_ ; +wire [0:0] cby_1__1__40_left_grid_pin_29_ ; +wire [0:0] cby_1__1__40_left_grid_pin_30_ ; +wire [0:0] cby_1__1__40_left_grid_pin_31_ ; +wire [0:0] cby_1__1__41_ccff_tail ; +wire [0:29] cby_1__1__41_chany_bottom_out ; +wire [0:29] cby_1__1__41_chany_top_out ; +wire [0:0] cby_1__1__41_left_grid_pin_16_ ; +wire [0:0] cby_1__1__41_left_grid_pin_17_ ; +wire [0:0] cby_1__1__41_left_grid_pin_18_ ; +wire [0:0] cby_1__1__41_left_grid_pin_19_ ; +wire [0:0] cby_1__1__41_left_grid_pin_20_ ; +wire [0:0] cby_1__1__41_left_grid_pin_21_ ; +wire [0:0] cby_1__1__41_left_grid_pin_22_ ; +wire [0:0] cby_1__1__41_left_grid_pin_23_ ; +wire [0:0] cby_1__1__41_left_grid_pin_24_ ; +wire [0:0] cby_1__1__41_left_grid_pin_25_ ; +wire [0:0] cby_1__1__41_left_grid_pin_26_ ; +wire [0:0] cby_1__1__41_left_grid_pin_27_ ; +wire [0:0] cby_1__1__41_left_grid_pin_28_ ; +wire [0:0] cby_1__1__41_left_grid_pin_29_ ; +wire [0:0] cby_1__1__41_left_grid_pin_30_ ; +wire [0:0] cby_1__1__41_left_grid_pin_31_ ; +wire [0:0] cby_1__1__42_ccff_tail ; +wire [0:29] cby_1__1__42_chany_bottom_out ; +wire [0:29] cby_1__1__42_chany_top_out ; +wire [0:0] cby_1__1__42_left_grid_pin_16_ ; +wire [0:0] cby_1__1__42_left_grid_pin_17_ ; +wire [0:0] cby_1__1__42_left_grid_pin_18_ ; +wire [0:0] cby_1__1__42_left_grid_pin_19_ ; +wire [0:0] cby_1__1__42_left_grid_pin_20_ ; +wire [0:0] cby_1__1__42_left_grid_pin_21_ ; +wire [0:0] cby_1__1__42_left_grid_pin_22_ ; +wire [0:0] cby_1__1__42_left_grid_pin_23_ ; +wire [0:0] cby_1__1__42_left_grid_pin_24_ ; +wire [0:0] cby_1__1__42_left_grid_pin_25_ ; +wire [0:0] cby_1__1__42_left_grid_pin_26_ ; +wire [0:0] cby_1__1__42_left_grid_pin_27_ ; +wire [0:0] cby_1__1__42_left_grid_pin_28_ ; +wire [0:0] cby_1__1__42_left_grid_pin_29_ ; +wire [0:0] cby_1__1__42_left_grid_pin_30_ ; +wire [0:0] cby_1__1__42_left_grid_pin_31_ ; +wire [0:0] cby_1__1__43_ccff_tail ; +wire [0:29] cby_1__1__43_chany_bottom_out ; +wire [0:29] cby_1__1__43_chany_top_out ; +wire [0:0] cby_1__1__43_left_grid_pin_16_ ; +wire [0:0] cby_1__1__43_left_grid_pin_17_ ; +wire [0:0] cby_1__1__43_left_grid_pin_18_ ; +wire [0:0] cby_1__1__43_left_grid_pin_19_ ; +wire [0:0] cby_1__1__43_left_grid_pin_20_ ; +wire [0:0] cby_1__1__43_left_grid_pin_21_ ; +wire [0:0] cby_1__1__43_left_grid_pin_22_ ; +wire [0:0] cby_1__1__43_left_grid_pin_23_ ; +wire [0:0] cby_1__1__43_left_grid_pin_24_ ; +wire [0:0] cby_1__1__43_left_grid_pin_25_ ; +wire [0:0] cby_1__1__43_left_grid_pin_26_ ; +wire [0:0] cby_1__1__43_left_grid_pin_27_ ; +wire [0:0] cby_1__1__43_left_grid_pin_28_ ; +wire [0:0] cby_1__1__43_left_grid_pin_29_ ; +wire [0:0] cby_1__1__43_left_grid_pin_30_ ; +wire [0:0] cby_1__1__43_left_grid_pin_31_ ; +wire [0:0] cby_1__1__44_ccff_tail ; +wire [0:29] cby_1__1__44_chany_bottom_out ; +wire [0:29] cby_1__1__44_chany_top_out ; +wire [0:0] cby_1__1__44_left_grid_pin_16_ ; +wire [0:0] cby_1__1__44_left_grid_pin_17_ ; +wire [0:0] cby_1__1__44_left_grid_pin_18_ ; +wire [0:0] cby_1__1__44_left_grid_pin_19_ ; +wire [0:0] cby_1__1__44_left_grid_pin_20_ ; +wire [0:0] cby_1__1__44_left_grid_pin_21_ ; +wire [0:0] cby_1__1__44_left_grid_pin_22_ ; +wire [0:0] cby_1__1__44_left_grid_pin_23_ ; +wire [0:0] cby_1__1__44_left_grid_pin_24_ ; +wire [0:0] cby_1__1__44_left_grid_pin_25_ ; +wire [0:0] cby_1__1__44_left_grid_pin_26_ ; +wire [0:0] cby_1__1__44_left_grid_pin_27_ ; +wire [0:0] cby_1__1__44_left_grid_pin_28_ ; +wire [0:0] cby_1__1__44_left_grid_pin_29_ ; +wire [0:0] cby_1__1__44_left_grid_pin_30_ ; +wire [0:0] cby_1__1__44_left_grid_pin_31_ ; +wire [0:0] cby_1__1__45_ccff_tail ; +wire [0:29] cby_1__1__45_chany_bottom_out ; +wire [0:29] cby_1__1__45_chany_top_out ; +wire [0:0] cby_1__1__45_left_grid_pin_16_ ; +wire [0:0] cby_1__1__45_left_grid_pin_17_ ; +wire [0:0] cby_1__1__45_left_grid_pin_18_ ; +wire [0:0] cby_1__1__45_left_grid_pin_19_ ; +wire [0:0] cby_1__1__45_left_grid_pin_20_ ; +wire [0:0] cby_1__1__45_left_grid_pin_21_ ; +wire [0:0] cby_1__1__45_left_grid_pin_22_ ; +wire [0:0] cby_1__1__45_left_grid_pin_23_ ; +wire [0:0] cby_1__1__45_left_grid_pin_24_ ; +wire [0:0] cby_1__1__45_left_grid_pin_25_ ; +wire [0:0] cby_1__1__45_left_grid_pin_26_ ; +wire [0:0] cby_1__1__45_left_grid_pin_27_ ; +wire [0:0] cby_1__1__45_left_grid_pin_28_ ; +wire [0:0] cby_1__1__45_left_grid_pin_29_ ; +wire [0:0] cby_1__1__45_left_grid_pin_30_ ; +wire [0:0] cby_1__1__45_left_grid_pin_31_ ; +wire [0:0] cby_1__1__46_ccff_tail ; +wire [0:29] cby_1__1__46_chany_bottom_out ; +wire [0:29] cby_1__1__46_chany_top_out ; +wire [0:0] cby_1__1__46_left_grid_pin_16_ ; +wire [0:0] cby_1__1__46_left_grid_pin_17_ ; +wire [0:0] cby_1__1__46_left_grid_pin_18_ ; +wire [0:0] cby_1__1__46_left_grid_pin_19_ ; +wire [0:0] cby_1__1__46_left_grid_pin_20_ ; +wire [0:0] cby_1__1__46_left_grid_pin_21_ ; +wire [0:0] cby_1__1__46_left_grid_pin_22_ ; +wire [0:0] cby_1__1__46_left_grid_pin_23_ ; +wire [0:0] cby_1__1__46_left_grid_pin_24_ ; +wire [0:0] cby_1__1__46_left_grid_pin_25_ ; +wire [0:0] cby_1__1__46_left_grid_pin_26_ ; +wire [0:0] cby_1__1__46_left_grid_pin_27_ ; +wire [0:0] cby_1__1__46_left_grid_pin_28_ ; +wire [0:0] cby_1__1__46_left_grid_pin_29_ ; +wire [0:0] cby_1__1__46_left_grid_pin_30_ ; +wire [0:0] cby_1__1__46_left_grid_pin_31_ ; +wire [0:0] cby_1__1__47_ccff_tail ; +wire [0:29] cby_1__1__47_chany_bottom_out ; +wire [0:29] cby_1__1__47_chany_top_out ; +wire [0:0] cby_1__1__47_left_grid_pin_16_ ; +wire [0:0] cby_1__1__47_left_grid_pin_17_ ; +wire [0:0] cby_1__1__47_left_grid_pin_18_ ; +wire [0:0] cby_1__1__47_left_grid_pin_19_ ; +wire [0:0] cby_1__1__47_left_grid_pin_20_ ; +wire [0:0] cby_1__1__47_left_grid_pin_21_ ; +wire [0:0] cby_1__1__47_left_grid_pin_22_ ; +wire [0:0] cby_1__1__47_left_grid_pin_23_ ; +wire [0:0] cby_1__1__47_left_grid_pin_24_ ; +wire [0:0] cby_1__1__47_left_grid_pin_25_ ; +wire [0:0] cby_1__1__47_left_grid_pin_26_ ; +wire [0:0] cby_1__1__47_left_grid_pin_27_ ; +wire [0:0] cby_1__1__47_left_grid_pin_28_ ; +wire [0:0] cby_1__1__47_left_grid_pin_29_ ; +wire [0:0] cby_1__1__47_left_grid_pin_30_ ; +wire [0:0] cby_1__1__47_left_grid_pin_31_ ; +wire [0:0] cby_1__1__48_ccff_tail ; +wire [0:29] cby_1__1__48_chany_bottom_out ; +wire [0:29] cby_1__1__48_chany_top_out ; +wire [0:0] cby_1__1__48_left_grid_pin_16_ ; +wire [0:0] cby_1__1__48_left_grid_pin_17_ ; +wire [0:0] cby_1__1__48_left_grid_pin_18_ ; +wire [0:0] cby_1__1__48_left_grid_pin_19_ ; +wire [0:0] cby_1__1__48_left_grid_pin_20_ ; +wire [0:0] cby_1__1__48_left_grid_pin_21_ ; +wire [0:0] cby_1__1__48_left_grid_pin_22_ ; +wire [0:0] cby_1__1__48_left_grid_pin_23_ ; +wire [0:0] cby_1__1__48_left_grid_pin_24_ ; +wire [0:0] cby_1__1__48_left_grid_pin_25_ ; +wire [0:0] cby_1__1__48_left_grid_pin_26_ ; +wire [0:0] cby_1__1__48_left_grid_pin_27_ ; +wire [0:0] cby_1__1__48_left_grid_pin_28_ ; +wire [0:0] cby_1__1__48_left_grid_pin_29_ ; +wire [0:0] cby_1__1__48_left_grid_pin_30_ ; +wire [0:0] cby_1__1__48_left_grid_pin_31_ ; +wire [0:0] cby_1__1__49_ccff_tail ; +wire [0:29] cby_1__1__49_chany_bottom_out ; +wire [0:29] cby_1__1__49_chany_top_out ; +wire [0:0] cby_1__1__49_left_grid_pin_16_ ; +wire [0:0] cby_1__1__49_left_grid_pin_17_ ; +wire [0:0] cby_1__1__49_left_grid_pin_18_ ; +wire [0:0] cby_1__1__49_left_grid_pin_19_ ; +wire [0:0] cby_1__1__49_left_grid_pin_20_ ; +wire [0:0] cby_1__1__49_left_grid_pin_21_ ; +wire [0:0] cby_1__1__49_left_grid_pin_22_ ; +wire [0:0] cby_1__1__49_left_grid_pin_23_ ; +wire [0:0] cby_1__1__49_left_grid_pin_24_ ; +wire [0:0] cby_1__1__49_left_grid_pin_25_ ; +wire [0:0] cby_1__1__49_left_grid_pin_26_ ; +wire [0:0] cby_1__1__49_left_grid_pin_27_ ; +wire [0:0] cby_1__1__49_left_grid_pin_28_ ; +wire [0:0] cby_1__1__49_left_grid_pin_29_ ; +wire [0:0] cby_1__1__49_left_grid_pin_30_ ; +wire [0:0] cby_1__1__49_left_grid_pin_31_ ; +wire [0:0] cby_1__1__4_ccff_tail ; +wire [0:29] cby_1__1__4_chany_bottom_out ; +wire [0:29] cby_1__1__4_chany_top_out ; +wire [0:0] cby_1__1__4_left_grid_pin_16_ ; +wire [0:0] cby_1__1__4_left_grid_pin_17_ ; +wire [0:0] cby_1__1__4_left_grid_pin_18_ ; +wire [0:0] cby_1__1__4_left_grid_pin_19_ ; +wire [0:0] cby_1__1__4_left_grid_pin_20_ ; +wire [0:0] cby_1__1__4_left_grid_pin_21_ ; +wire [0:0] cby_1__1__4_left_grid_pin_22_ ; +wire [0:0] cby_1__1__4_left_grid_pin_23_ ; +wire [0:0] cby_1__1__4_left_grid_pin_24_ ; +wire [0:0] cby_1__1__4_left_grid_pin_25_ ; +wire [0:0] cby_1__1__4_left_grid_pin_26_ ; +wire [0:0] cby_1__1__4_left_grid_pin_27_ ; +wire [0:0] cby_1__1__4_left_grid_pin_28_ ; +wire [0:0] cby_1__1__4_left_grid_pin_29_ ; +wire [0:0] cby_1__1__4_left_grid_pin_30_ ; +wire [0:0] cby_1__1__4_left_grid_pin_31_ ; +wire [0:0] cby_1__1__50_ccff_tail ; +wire [0:29] cby_1__1__50_chany_bottom_out ; +wire [0:29] cby_1__1__50_chany_top_out ; +wire [0:0] cby_1__1__50_left_grid_pin_16_ ; +wire [0:0] cby_1__1__50_left_grid_pin_17_ ; +wire [0:0] cby_1__1__50_left_grid_pin_18_ ; +wire [0:0] cby_1__1__50_left_grid_pin_19_ ; +wire [0:0] cby_1__1__50_left_grid_pin_20_ ; +wire [0:0] cby_1__1__50_left_grid_pin_21_ ; +wire [0:0] cby_1__1__50_left_grid_pin_22_ ; +wire [0:0] cby_1__1__50_left_grid_pin_23_ ; +wire [0:0] cby_1__1__50_left_grid_pin_24_ ; +wire [0:0] cby_1__1__50_left_grid_pin_25_ ; +wire [0:0] cby_1__1__50_left_grid_pin_26_ ; +wire [0:0] cby_1__1__50_left_grid_pin_27_ ; +wire [0:0] cby_1__1__50_left_grid_pin_28_ ; +wire [0:0] cby_1__1__50_left_grid_pin_29_ ; +wire [0:0] cby_1__1__50_left_grid_pin_30_ ; +wire [0:0] cby_1__1__50_left_grid_pin_31_ ; +wire [0:0] cby_1__1__51_ccff_tail ; +wire [0:29] cby_1__1__51_chany_bottom_out ; +wire [0:29] cby_1__1__51_chany_top_out ; +wire [0:0] cby_1__1__51_left_grid_pin_16_ ; +wire [0:0] cby_1__1__51_left_grid_pin_17_ ; +wire [0:0] cby_1__1__51_left_grid_pin_18_ ; +wire [0:0] cby_1__1__51_left_grid_pin_19_ ; +wire [0:0] cby_1__1__51_left_grid_pin_20_ ; +wire [0:0] cby_1__1__51_left_grid_pin_21_ ; +wire [0:0] cby_1__1__51_left_grid_pin_22_ ; +wire [0:0] cby_1__1__51_left_grid_pin_23_ ; +wire [0:0] cby_1__1__51_left_grid_pin_24_ ; +wire [0:0] cby_1__1__51_left_grid_pin_25_ ; +wire [0:0] cby_1__1__51_left_grid_pin_26_ ; +wire [0:0] cby_1__1__51_left_grid_pin_27_ ; +wire [0:0] cby_1__1__51_left_grid_pin_28_ ; +wire [0:0] cby_1__1__51_left_grid_pin_29_ ; +wire [0:0] cby_1__1__51_left_grid_pin_30_ ; +wire [0:0] cby_1__1__51_left_grid_pin_31_ ; +wire [0:0] cby_1__1__52_ccff_tail ; +wire [0:29] cby_1__1__52_chany_bottom_out ; +wire [0:29] cby_1__1__52_chany_top_out ; +wire [0:0] cby_1__1__52_left_grid_pin_16_ ; +wire [0:0] cby_1__1__52_left_grid_pin_17_ ; +wire [0:0] cby_1__1__52_left_grid_pin_18_ ; +wire [0:0] cby_1__1__52_left_grid_pin_19_ ; +wire [0:0] cby_1__1__52_left_grid_pin_20_ ; +wire [0:0] cby_1__1__52_left_grid_pin_21_ ; +wire [0:0] cby_1__1__52_left_grid_pin_22_ ; +wire [0:0] cby_1__1__52_left_grid_pin_23_ ; +wire [0:0] cby_1__1__52_left_grid_pin_24_ ; +wire [0:0] cby_1__1__52_left_grid_pin_25_ ; +wire [0:0] cby_1__1__52_left_grid_pin_26_ ; +wire [0:0] cby_1__1__52_left_grid_pin_27_ ; +wire [0:0] cby_1__1__52_left_grid_pin_28_ ; +wire [0:0] cby_1__1__52_left_grid_pin_29_ ; +wire [0:0] cby_1__1__52_left_grid_pin_30_ ; +wire [0:0] cby_1__1__52_left_grid_pin_31_ ; +wire [0:0] cby_1__1__53_ccff_tail ; +wire [0:29] cby_1__1__53_chany_bottom_out ; +wire [0:29] cby_1__1__53_chany_top_out ; +wire [0:0] cby_1__1__53_left_grid_pin_16_ ; +wire [0:0] cby_1__1__53_left_grid_pin_17_ ; +wire [0:0] cby_1__1__53_left_grid_pin_18_ ; +wire [0:0] cby_1__1__53_left_grid_pin_19_ ; +wire [0:0] cby_1__1__53_left_grid_pin_20_ ; +wire [0:0] cby_1__1__53_left_grid_pin_21_ ; +wire [0:0] cby_1__1__53_left_grid_pin_22_ ; +wire [0:0] cby_1__1__53_left_grid_pin_23_ ; +wire [0:0] cby_1__1__53_left_grid_pin_24_ ; +wire [0:0] cby_1__1__53_left_grid_pin_25_ ; +wire [0:0] cby_1__1__53_left_grid_pin_26_ ; +wire [0:0] cby_1__1__53_left_grid_pin_27_ ; +wire [0:0] cby_1__1__53_left_grid_pin_28_ ; +wire [0:0] cby_1__1__53_left_grid_pin_29_ ; +wire [0:0] cby_1__1__53_left_grid_pin_30_ ; +wire [0:0] cby_1__1__53_left_grid_pin_31_ ; +wire [0:0] cby_1__1__54_ccff_tail ; +wire [0:29] cby_1__1__54_chany_bottom_out ; +wire [0:29] cby_1__1__54_chany_top_out ; +wire [0:0] cby_1__1__54_left_grid_pin_16_ ; +wire [0:0] cby_1__1__54_left_grid_pin_17_ ; +wire [0:0] cby_1__1__54_left_grid_pin_18_ ; +wire [0:0] cby_1__1__54_left_grid_pin_19_ ; +wire [0:0] cby_1__1__54_left_grid_pin_20_ ; +wire [0:0] cby_1__1__54_left_grid_pin_21_ ; +wire [0:0] cby_1__1__54_left_grid_pin_22_ ; +wire [0:0] cby_1__1__54_left_grid_pin_23_ ; +wire [0:0] cby_1__1__54_left_grid_pin_24_ ; +wire [0:0] cby_1__1__54_left_grid_pin_25_ ; +wire [0:0] cby_1__1__54_left_grid_pin_26_ ; +wire [0:0] cby_1__1__54_left_grid_pin_27_ ; +wire [0:0] cby_1__1__54_left_grid_pin_28_ ; +wire [0:0] cby_1__1__54_left_grid_pin_29_ ; +wire [0:0] cby_1__1__54_left_grid_pin_30_ ; +wire [0:0] cby_1__1__54_left_grid_pin_31_ ; +wire [0:0] cby_1__1__55_ccff_tail ; +wire [0:29] cby_1__1__55_chany_bottom_out ; +wire [0:29] cby_1__1__55_chany_top_out ; +wire [0:0] cby_1__1__55_left_grid_pin_16_ ; +wire [0:0] cby_1__1__55_left_grid_pin_17_ ; +wire [0:0] cby_1__1__55_left_grid_pin_18_ ; +wire [0:0] cby_1__1__55_left_grid_pin_19_ ; +wire [0:0] cby_1__1__55_left_grid_pin_20_ ; +wire [0:0] cby_1__1__55_left_grid_pin_21_ ; +wire [0:0] cby_1__1__55_left_grid_pin_22_ ; +wire [0:0] cby_1__1__55_left_grid_pin_23_ ; +wire [0:0] cby_1__1__55_left_grid_pin_24_ ; +wire [0:0] cby_1__1__55_left_grid_pin_25_ ; +wire [0:0] cby_1__1__55_left_grid_pin_26_ ; +wire [0:0] cby_1__1__55_left_grid_pin_27_ ; +wire [0:0] cby_1__1__55_left_grid_pin_28_ ; +wire [0:0] cby_1__1__55_left_grid_pin_29_ ; +wire [0:0] cby_1__1__55_left_grid_pin_30_ ; +wire [0:0] cby_1__1__55_left_grid_pin_31_ ; +wire [0:0] cby_1__1__56_ccff_tail ; +wire [0:29] cby_1__1__56_chany_bottom_out ; +wire [0:29] cby_1__1__56_chany_top_out ; +wire [0:0] cby_1__1__56_left_grid_pin_16_ ; +wire [0:0] cby_1__1__56_left_grid_pin_17_ ; +wire [0:0] cby_1__1__56_left_grid_pin_18_ ; +wire [0:0] cby_1__1__56_left_grid_pin_19_ ; +wire [0:0] cby_1__1__56_left_grid_pin_20_ ; +wire [0:0] cby_1__1__56_left_grid_pin_21_ ; +wire [0:0] cby_1__1__56_left_grid_pin_22_ ; +wire [0:0] cby_1__1__56_left_grid_pin_23_ ; +wire [0:0] cby_1__1__56_left_grid_pin_24_ ; +wire [0:0] cby_1__1__56_left_grid_pin_25_ ; +wire [0:0] cby_1__1__56_left_grid_pin_26_ ; +wire [0:0] cby_1__1__56_left_grid_pin_27_ ; +wire [0:0] cby_1__1__56_left_grid_pin_28_ ; +wire [0:0] cby_1__1__56_left_grid_pin_29_ ; +wire [0:0] cby_1__1__56_left_grid_pin_30_ ; +wire [0:0] cby_1__1__56_left_grid_pin_31_ ; +wire [0:0] cby_1__1__57_ccff_tail ; +wire [0:29] cby_1__1__57_chany_bottom_out ; +wire [0:29] cby_1__1__57_chany_top_out ; +wire [0:0] cby_1__1__57_left_grid_pin_16_ ; +wire [0:0] cby_1__1__57_left_grid_pin_17_ ; +wire [0:0] cby_1__1__57_left_grid_pin_18_ ; +wire [0:0] cby_1__1__57_left_grid_pin_19_ ; +wire [0:0] cby_1__1__57_left_grid_pin_20_ ; +wire [0:0] cby_1__1__57_left_grid_pin_21_ ; +wire [0:0] cby_1__1__57_left_grid_pin_22_ ; +wire [0:0] cby_1__1__57_left_grid_pin_23_ ; +wire [0:0] cby_1__1__57_left_grid_pin_24_ ; +wire [0:0] cby_1__1__57_left_grid_pin_25_ ; +wire [0:0] cby_1__1__57_left_grid_pin_26_ ; +wire [0:0] cby_1__1__57_left_grid_pin_27_ ; +wire [0:0] cby_1__1__57_left_grid_pin_28_ ; +wire [0:0] cby_1__1__57_left_grid_pin_29_ ; +wire [0:0] cby_1__1__57_left_grid_pin_30_ ; +wire [0:0] cby_1__1__57_left_grid_pin_31_ ; +wire [0:0] cby_1__1__58_ccff_tail ; +wire [0:29] cby_1__1__58_chany_bottom_out ; +wire [0:29] cby_1__1__58_chany_top_out ; +wire [0:0] cby_1__1__58_left_grid_pin_16_ ; +wire [0:0] cby_1__1__58_left_grid_pin_17_ ; +wire [0:0] cby_1__1__58_left_grid_pin_18_ ; +wire [0:0] cby_1__1__58_left_grid_pin_19_ ; +wire [0:0] cby_1__1__58_left_grid_pin_20_ ; +wire [0:0] cby_1__1__58_left_grid_pin_21_ ; +wire [0:0] cby_1__1__58_left_grid_pin_22_ ; +wire [0:0] cby_1__1__58_left_grid_pin_23_ ; +wire [0:0] cby_1__1__58_left_grid_pin_24_ ; +wire [0:0] cby_1__1__58_left_grid_pin_25_ ; +wire [0:0] cby_1__1__58_left_grid_pin_26_ ; +wire [0:0] cby_1__1__58_left_grid_pin_27_ ; +wire [0:0] cby_1__1__58_left_grid_pin_28_ ; +wire [0:0] cby_1__1__58_left_grid_pin_29_ ; +wire [0:0] cby_1__1__58_left_grid_pin_30_ ; +wire [0:0] cby_1__1__58_left_grid_pin_31_ ; +wire [0:0] cby_1__1__59_ccff_tail ; +wire [0:29] cby_1__1__59_chany_bottom_out ; +wire [0:29] cby_1__1__59_chany_top_out ; +wire [0:0] cby_1__1__59_left_grid_pin_16_ ; +wire [0:0] cby_1__1__59_left_grid_pin_17_ ; +wire [0:0] cby_1__1__59_left_grid_pin_18_ ; +wire [0:0] cby_1__1__59_left_grid_pin_19_ ; +wire [0:0] cby_1__1__59_left_grid_pin_20_ ; +wire [0:0] cby_1__1__59_left_grid_pin_21_ ; +wire [0:0] cby_1__1__59_left_grid_pin_22_ ; +wire [0:0] cby_1__1__59_left_grid_pin_23_ ; +wire [0:0] cby_1__1__59_left_grid_pin_24_ ; +wire [0:0] cby_1__1__59_left_grid_pin_25_ ; +wire [0:0] cby_1__1__59_left_grid_pin_26_ ; +wire [0:0] cby_1__1__59_left_grid_pin_27_ ; +wire [0:0] cby_1__1__59_left_grid_pin_28_ ; +wire [0:0] cby_1__1__59_left_grid_pin_29_ ; +wire [0:0] cby_1__1__59_left_grid_pin_30_ ; +wire [0:0] cby_1__1__59_left_grid_pin_31_ ; +wire [0:0] cby_1__1__5_ccff_tail ; +wire [0:29] cby_1__1__5_chany_bottom_out ; +wire [0:29] cby_1__1__5_chany_top_out ; +wire [0:0] cby_1__1__5_left_grid_pin_16_ ; +wire [0:0] cby_1__1__5_left_grid_pin_17_ ; +wire [0:0] cby_1__1__5_left_grid_pin_18_ ; +wire [0:0] cby_1__1__5_left_grid_pin_19_ ; +wire [0:0] cby_1__1__5_left_grid_pin_20_ ; +wire [0:0] cby_1__1__5_left_grid_pin_21_ ; +wire [0:0] cby_1__1__5_left_grid_pin_22_ ; +wire [0:0] cby_1__1__5_left_grid_pin_23_ ; +wire [0:0] cby_1__1__5_left_grid_pin_24_ ; +wire [0:0] cby_1__1__5_left_grid_pin_25_ ; +wire [0:0] cby_1__1__5_left_grid_pin_26_ ; +wire [0:0] cby_1__1__5_left_grid_pin_27_ ; +wire [0:0] cby_1__1__5_left_grid_pin_28_ ; +wire [0:0] cby_1__1__5_left_grid_pin_29_ ; +wire [0:0] cby_1__1__5_left_grid_pin_30_ ; +wire [0:0] cby_1__1__5_left_grid_pin_31_ ; +wire [0:0] cby_1__1__60_ccff_tail ; +wire [0:29] cby_1__1__60_chany_bottom_out ; +wire [0:29] cby_1__1__60_chany_top_out ; +wire [0:0] cby_1__1__60_left_grid_pin_16_ ; +wire [0:0] cby_1__1__60_left_grid_pin_17_ ; +wire [0:0] cby_1__1__60_left_grid_pin_18_ ; +wire [0:0] cby_1__1__60_left_grid_pin_19_ ; +wire [0:0] cby_1__1__60_left_grid_pin_20_ ; +wire [0:0] cby_1__1__60_left_grid_pin_21_ ; +wire [0:0] cby_1__1__60_left_grid_pin_22_ ; +wire [0:0] cby_1__1__60_left_grid_pin_23_ ; +wire [0:0] cby_1__1__60_left_grid_pin_24_ ; +wire [0:0] cby_1__1__60_left_grid_pin_25_ ; +wire [0:0] cby_1__1__60_left_grid_pin_26_ ; +wire [0:0] cby_1__1__60_left_grid_pin_27_ ; +wire [0:0] cby_1__1__60_left_grid_pin_28_ ; +wire [0:0] cby_1__1__60_left_grid_pin_29_ ; +wire [0:0] cby_1__1__60_left_grid_pin_30_ ; +wire [0:0] cby_1__1__60_left_grid_pin_31_ ; +wire [0:0] cby_1__1__61_ccff_tail ; +wire [0:29] cby_1__1__61_chany_bottom_out ; +wire [0:29] cby_1__1__61_chany_top_out ; +wire [0:0] cby_1__1__61_left_grid_pin_16_ ; +wire [0:0] cby_1__1__61_left_grid_pin_17_ ; +wire [0:0] cby_1__1__61_left_grid_pin_18_ ; +wire [0:0] cby_1__1__61_left_grid_pin_19_ ; +wire [0:0] cby_1__1__61_left_grid_pin_20_ ; +wire [0:0] cby_1__1__61_left_grid_pin_21_ ; +wire [0:0] cby_1__1__61_left_grid_pin_22_ ; +wire [0:0] cby_1__1__61_left_grid_pin_23_ ; +wire [0:0] cby_1__1__61_left_grid_pin_24_ ; +wire [0:0] cby_1__1__61_left_grid_pin_25_ ; +wire [0:0] cby_1__1__61_left_grid_pin_26_ ; +wire [0:0] cby_1__1__61_left_grid_pin_27_ ; +wire [0:0] cby_1__1__61_left_grid_pin_28_ ; +wire [0:0] cby_1__1__61_left_grid_pin_29_ ; +wire [0:0] cby_1__1__61_left_grid_pin_30_ ; +wire [0:0] cby_1__1__61_left_grid_pin_31_ ; +wire [0:0] cby_1__1__62_ccff_tail ; +wire [0:29] cby_1__1__62_chany_bottom_out ; +wire [0:29] cby_1__1__62_chany_top_out ; +wire [0:0] cby_1__1__62_left_grid_pin_16_ ; +wire [0:0] cby_1__1__62_left_grid_pin_17_ ; +wire [0:0] cby_1__1__62_left_grid_pin_18_ ; +wire [0:0] cby_1__1__62_left_grid_pin_19_ ; +wire [0:0] cby_1__1__62_left_grid_pin_20_ ; +wire [0:0] cby_1__1__62_left_grid_pin_21_ ; +wire [0:0] cby_1__1__62_left_grid_pin_22_ ; +wire [0:0] cby_1__1__62_left_grid_pin_23_ ; +wire [0:0] cby_1__1__62_left_grid_pin_24_ ; +wire [0:0] cby_1__1__62_left_grid_pin_25_ ; +wire [0:0] cby_1__1__62_left_grid_pin_26_ ; +wire [0:0] cby_1__1__62_left_grid_pin_27_ ; +wire [0:0] cby_1__1__62_left_grid_pin_28_ ; +wire [0:0] cby_1__1__62_left_grid_pin_29_ ; +wire [0:0] cby_1__1__62_left_grid_pin_30_ ; +wire [0:0] cby_1__1__62_left_grid_pin_31_ ; +wire [0:0] cby_1__1__63_ccff_tail ; +wire [0:29] cby_1__1__63_chany_bottom_out ; +wire [0:29] cby_1__1__63_chany_top_out ; +wire [0:0] cby_1__1__63_left_grid_pin_16_ ; +wire [0:0] cby_1__1__63_left_grid_pin_17_ ; +wire [0:0] cby_1__1__63_left_grid_pin_18_ ; +wire [0:0] cby_1__1__63_left_grid_pin_19_ ; +wire [0:0] cby_1__1__63_left_grid_pin_20_ ; +wire [0:0] cby_1__1__63_left_grid_pin_21_ ; +wire [0:0] cby_1__1__63_left_grid_pin_22_ ; +wire [0:0] cby_1__1__63_left_grid_pin_23_ ; +wire [0:0] cby_1__1__63_left_grid_pin_24_ ; +wire [0:0] cby_1__1__63_left_grid_pin_25_ ; +wire [0:0] cby_1__1__63_left_grid_pin_26_ ; +wire [0:0] cby_1__1__63_left_grid_pin_27_ ; +wire [0:0] cby_1__1__63_left_grid_pin_28_ ; +wire [0:0] cby_1__1__63_left_grid_pin_29_ ; +wire [0:0] cby_1__1__63_left_grid_pin_30_ ; +wire [0:0] cby_1__1__63_left_grid_pin_31_ ; +wire [0:0] cby_1__1__64_ccff_tail ; +wire [0:29] cby_1__1__64_chany_bottom_out ; +wire [0:29] cby_1__1__64_chany_top_out ; +wire [0:0] cby_1__1__64_left_grid_pin_16_ ; +wire [0:0] cby_1__1__64_left_grid_pin_17_ ; +wire [0:0] cby_1__1__64_left_grid_pin_18_ ; +wire [0:0] cby_1__1__64_left_grid_pin_19_ ; +wire [0:0] cby_1__1__64_left_grid_pin_20_ ; +wire [0:0] cby_1__1__64_left_grid_pin_21_ ; +wire [0:0] cby_1__1__64_left_grid_pin_22_ ; +wire [0:0] cby_1__1__64_left_grid_pin_23_ ; +wire [0:0] cby_1__1__64_left_grid_pin_24_ ; +wire [0:0] cby_1__1__64_left_grid_pin_25_ ; +wire [0:0] cby_1__1__64_left_grid_pin_26_ ; +wire [0:0] cby_1__1__64_left_grid_pin_27_ ; +wire [0:0] cby_1__1__64_left_grid_pin_28_ ; +wire [0:0] cby_1__1__64_left_grid_pin_29_ ; +wire [0:0] cby_1__1__64_left_grid_pin_30_ ; +wire [0:0] cby_1__1__64_left_grid_pin_31_ ; +wire [0:0] cby_1__1__65_ccff_tail ; +wire [0:29] cby_1__1__65_chany_bottom_out ; +wire [0:29] cby_1__1__65_chany_top_out ; +wire [0:0] cby_1__1__65_left_grid_pin_16_ ; +wire [0:0] cby_1__1__65_left_grid_pin_17_ ; +wire [0:0] cby_1__1__65_left_grid_pin_18_ ; +wire [0:0] cby_1__1__65_left_grid_pin_19_ ; +wire [0:0] cby_1__1__65_left_grid_pin_20_ ; +wire [0:0] cby_1__1__65_left_grid_pin_21_ ; +wire [0:0] cby_1__1__65_left_grid_pin_22_ ; +wire [0:0] cby_1__1__65_left_grid_pin_23_ ; +wire [0:0] cby_1__1__65_left_grid_pin_24_ ; +wire [0:0] cby_1__1__65_left_grid_pin_25_ ; +wire [0:0] cby_1__1__65_left_grid_pin_26_ ; +wire [0:0] cby_1__1__65_left_grid_pin_27_ ; +wire [0:0] cby_1__1__65_left_grid_pin_28_ ; +wire [0:0] cby_1__1__65_left_grid_pin_29_ ; +wire [0:0] cby_1__1__65_left_grid_pin_30_ ; +wire [0:0] cby_1__1__65_left_grid_pin_31_ ; +wire [0:0] cby_1__1__66_ccff_tail ; +wire [0:29] cby_1__1__66_chany_bottom_out ; +wire [0:29] cby_1__1__66_chany_top_out ; +wire [0:0] cby_1__1__66_left_grid_pin_16_ ; +wire [0:0] cby_1__1__66_left_grid_pin_17_ ; +wire [0:0] cby_1__1__66_left_grid_pin_18_ ; +wire [0:0] cby_1__1__66_left_grid_pin_19_ ; +wire [0:0] cby_1__1__66_left_grid_pin_20_ ; +wire [0:0] cby_1__1__66_left_grid_pin_21_ ; +wire [0:0] cby_1__1__66_left_grid_pin_22_ ; +wire [0:0] cby_1__1__66_left_grid_pin_23_ ; +wire [0:0] cby_1__1__66_left_grid_pin_24_ ; +wire [0:0] cby_1__1__66_left_grid_pin_25_ ; +wire [0:0] cby_1__1__66_left_grid_pin_26_ ; +wire [0:0] cby_1__1__66_left_grid_pin_27_ ; +wire [0:0] cby_1__1__66_left_grid_pin_28_ ; +wire [0:0] cby_1__1__66_left_grid_pin_29_ ; +wire [0:0] cby_1__1__66_left_grid_pin_30_ ; +wire [0:0] cby_1__1__66_left_grid_pin_31_ ; +wire [0:0] cby_1__1__67_ccff_tail ; +wire [0:29] cby_1__1__67_chany_bottom_out ; +wire [0:29] cby_1__1__67_chany_top_out ; +wire [0:0] cby_1__1__67_left_grid_pin_16_ ; +wire [0:0] cby_1__1__67_left_grid_pin_17_ ; +wire [0:0] cby_1__1__67_left_grid_pin_18_ ; +wire [0:0] cby_1__1__67_left_grid_pin_19_ ; +wire [0:0] cby_1__1__67_left_grid_pin_20_ ; +wire [0:0] cby_1__1__67_left_grid_pin_21_ ; +wire [0:0] cby_1__1__67_left_grid_pin_22_ ; +wire [0:0] cby_1__1__67_left_grid_pin_23_ ; +wire [0:0] cby_1__1__67_left_grid_pin_24_ ; +wire [0:0] cby_1__1__67_left_grid_pin_25_ ; +wire [0:0] cby_1__1__67_left_grid_pin_26_ ; +wire [0:0] cby_1__1__67_left_grid_pin_27_ ; +wire [0:0] cby_1__1__67_left_grid_pin_28_ ; +wire [0:0] cby_1__1__67_left_grid_pin_29_ ; +wire [0:0] cby_1__1__67_left_grid_pin_30_ ; +wire [0:0] cby_1__1__67_left_grid_pin_31_ ; +wire [0:0] cby_1__1__68_ccff_tail ; +wire [0:29] cby_1__1__68_chany_bottom_out ; +wire [0:29] cby_1__1__68_chany_top_out ; +wire [0:0] cby_1__1__68_left_grid_pin_16_ ; +wire [0:0] cby_1__1__68_left_grid_pin_17_ ; +wire [0:0] cby_1__1__68_left_grid_pin_18_ ; +wire [0:0] cby_1__1__68_left_grid_pin_19_ ; +wire [0:0] cby_1__1__68_left_grid_pin_20_ ; +wire [0:0] cby_1__1__68_left_grid_pin_21_ ; +wire [0:0] cby_1__1__68_left_grid_pin_22_ ; +wire [0:0] cby_1__1__68_left_grid_pin_23_ ; +wire [0:0] cby_1__1__68_left_grid_pin_24_ ; +wire [0:0] cby_1__1__68_left_grid_pin_25_ ; +wire [0:0] cby_1__1__68_left_grid_pin_26_ ; +wire [0:0] cby_1__1__68_left_grid_pin_27_ ; +wire [0:0] cby_1__1__68_left_grid_pin_28_ ; +wire [0:0] cby_1__1__68_left_grid_pin_29_ ; +wire [0:0] cby_1__1__68_left_grid_pin_30_ ; +wire [0:0] cby_1__1__68_left_grid_pin_31_ ; +wire [0:0] cby_1__1__69_ccff_tail ; +wire [0:29] cby_1__1__69_chany_bottom_out ; +wire [0:29] cby_1__1__69_chany_top_out ; +wire [0:0] cby_1__1__69_left_grid_pin_16_ ; +wire [0:0] cby_1__1__69_left_grid_pin_17_ ; +wire [0:0] cby_1__1__69_left_grid_pin_18_ ; +wire [0:0] cby_1__1__69_left_grid_pin_19_ ; +wire [0:0] cby_1__1__69_left_grid_pin_20_ ; +wire [0:0] cby_1__1__69_left_grid_pin_21_ ; +wire [0:0] cby_1__1__69_left_grid_pin_22_ ; +wire [0:0] cby_1__1__69_left_grid_pin_23_ ; +wire [0:0] cby_1__1__69_left_grid_pin_24_ ; +wire [0:0] cby_1__1__69_left_grid_pin_25_ ; +wire [0:0] cby_1__1__69_left_grid_pin_26_ ; +wire [0:0] cby_1__1__69_left_grid_pin_27_ ; +wire [0:0] cby_1__1__69_left_grid_pin_28_ ; +wire [0:0] cby_1__1__69_left_grid_pin_29_ ; +wire [0:0] cby_1__1__69_left_grid_pin_30_ ; +wire [0:0] cby_1__1__69_left_grid_pin_31_ ; +wire [0:0] cby_1__1__6_ccff_tail ; +wire [0:29] cby_1__1__6_chany_bottom_out ; +wire [0:29] cby_1__1__6_chany_top_out ; +wire [0:0] cby_1__1__6_left_grid_pin_16_ ; +wire [0:0] cby_1__1__6_left_grid_pin_17_ ; +wire [0:0] cby_1__1__6_left_grid_pin_18_ ; +wire [0:0] cby_1__1__6_left_grid_pin_19_ ; +wire [0:0] cby_1__1__6_left_grid_pin_20_ ; +wire [0:0] cby_1__1__6_left_grid_pin_21_ ; +wire [0:0] cby_1__1__6_left_grid_pin_22_ ; +wire [0:0] cby_1__1__6_left_grid_pin_23_ ; +wire [0:0] cby_1__1__6_left_grid_pin_24_ ; +wire [0:0] cby_1__1__6_left_grid_pin_25_ ; +wire [0:0] cby_1__1__6_left_grid_pin_26_ ; +wire [0:0] cby_1__1__6_left_grid_pin_27_ ; +wire [0:0] cby_1__1__6_left_grid_pin_28_ ; +wire [0:0] cby_1__1__6_left_grid_pin_29_ ; +wire [0:0] cby_1__1__6_left_grid_pin_30_ ; +wire [0:0] cby_1__1__6_left_grid_pin_31_ ; +wire [0:0] cby_1__1__70_ccff_tail ; +wire [0:29] cby_1__1__70_chany_bottom_out ; +wire [0:29] cby_1__1__70_chany_top_out ; +wire [0:0] cby_1__1__70_left_grid_pin_16_ ; +wire [0:0] cby_1__1__70_left_grid_pin_17_ ; +wire [0:0] cby_1__1__70_left_grid_pin_18_ ; +wire [0:0] cby_1__1__70_left_grid_pin_19_ ; +wire [0:0] cby_1__1__70_left_grid_pin_20_ ; +wire [0:0] cby_1__1__70_left_grid_pin_21_ ; +wire [0:0] cby_1__1__70_left_grid_pin_22_ ; +wire [0:0] cby_1__1__70_left_grid_pin_23_ ; +wire [0:0] cby_1__1__70_left_grid_pin_24_ ; +wire [0:0] cby_1__1__70_left_grid_pin_25_ ; +wire [0:0] cby_1__1__70_left_grid_pin_26_ ; +wire [0:0] cby_1__1__70_left_grid_pin_27_ ; +wire [0:0] cby_1__1__70_left_grid_pin_28_ ; +wire [0:0] cby_1__1__70_left_grid_pin_29_ ; +wire [0:0] cby_1__1__70_left_grid_pin_30_ ; +wire [0:0] cby_1__1__70_left_grid_pin_31_ ; +wire [0:0] cby_1__1__71_ccff_tail ; +wire [0:29] cby_1__1__71_chany_bottom_out ; +wire [0:29] cby_1__1__71_chany_top_out ; +wire [0:0] cby_1__1__71_left_grid_pin_16_ ; +wire [0:0] cby_1__1__71_left_grid_pin_17_ ; +wire [0:0] cby_1__1__71_left_grid_pin_18_ ; +wire [0:0] cby_1__1__71_left_grid_pin_19_ ; +wire [0:0] cby_1__1__71_left_grid_pin_20_ ; +wire [0:0] cby_1__1__71_left_grid_pin_21_ ; +wire [0:0] cby_1__1__71_left_grid_pin_22_ ; +wire [0:0] cby_1__1__71_left_grid_pin_23_ ; +wire [0:0] cby_1__1__71_left_grid_pin_24_ ; +wire [0:0] cby_1__1__71_left_grid_pin_25_ ; +wire [0:0] cby_1__1__71_left_grid_pin_26_ ; +wire [0:0] cby_1__1__71_left_grid_pin_27_ ; +wire [0:0] cby_1__1__71_left_grid_pin_28_ ; +wire [0:0] cby_1__1__71_left_grid_pin_29_ ; +wire [0:0] cby_1__1__71_left_grid_pin_30_ ; +wire [0:0] cby_1__1__71_left_grid_pin_31_ ; +wire [0:0] cby_1__1__72_ccff_tail ; +wire [0:29] cby_1__1__72_chany_bottom_out ; +wire [0:29] cby_1__1__72_chany_top_out ; +wire [0:0] cby_1__1__72_left_grid_pin_16_ ; +wire [0:0] cby_1__1__72_left_grid_pin_17_ ; +wire [0:0] cby_1__1__72_left_grid_pin_18_ ; +wire [0:0] cby_1__1__72_left_grid_pin_19_ ; +wire [0:0] cby_1__1__72_left_grid_pin_20_ ; +wire [0:0] cby_1__1__72_left_grid_pin_21_ ; +wire [0:0] cby_1__1__72_left_grid_pin_22_ ; +wire [0:0] cby_1__1__72_left_grid_pin_23_ ; +wire [0:0] cby_1__1__72_left_grid_pin_24_ ; +wire [0:0] cby_1__1__72_left_grid_pin_25_ ; +wire [0:0] cby_1__1__72_left_grid_pin_26_ ; +wire [0:0] cby_1__1__72_left_grid_pin_27_ ; +wire [0:0] cby_1__1__72_left_grid_pin_28_ ; +wire [0:0] cby_1__1__72_left_grid_pin_29_ ; +wire [0:0] cby_1__1__72_left_grid_pin_30_ ; +wire [0:0] cby_1__1__72_left_grid_pin_31_ ; +wire [0:0] cby_1__1__73_ccff_tail ; +wire [0:29] cby_1__1__73_chany_bottom_out ; +wire [0:29] cby_1__1__73_chany_top_out ; +wire [0:0] cby_1__1__73_left_grid_pin_16_ ; +wire [0:0] cby_1__1__73_left_grid_pin_17_ ; +wire [0:0] cby_1__1__73_left_grid_pin_18_ ; +wire [0:0] cby_1__1__73_left_grid_pin_19_ ; +wire [0:0] cby_1__1__73_left_grid_pin_20_ ; +wire [0:0] cby_1__1__73_left_grid_pin_21_ ; +wire [0:0] cby_1__1__73_left_grid_pin_22_ ; +wire [0:0] cby_1__1__73_left_grid_pin_23_ ; +wire [0:0] cby_1__1__73_left_grid_pin_24_ ; +wire [0:0] cby_1__1__73_left_grid_pin_25_ ; +wire [0:0] cby_1__1__73_left_grid_pin_26_ ; +wire [0:0] cby_1__1__73_left_grid_pin_27_ ; +wire [0:0] cby_1__1__73_left_grid_pin_28_ ; +wire [0:0] cby_1__1__73_left_grid_pin_29_ ; +wire [0:0] cby_1__1__73_left_grid_pin_30_ ; +wire [0:0] cby_1__1__73_left_grid_pin_31_ ; +wire [0:0] cby_1__1__74_ccff_tail ; +wire [0:29] cby_1__1__74_chany_bottom_out ; +wire [0:29] cby_1__1__74_chany_top_out ; +wire [0:0] cby_1__1__74_left_grid_pin_16_ ; +wire [0:0] cby_1__1__74_left_grid_pin_17_ ; +wire [0:0] cby_1__1__74_left_grid_pin_18_ ; +wire [0:0] cby_1__1__74_left_grid_pin_19_ ; +wire [0:0] cby_1__1__74_left_grid_pin_20_ ; +wire [0:0] cby_1__1__74_left_grid_pin_21_ ; +wire [0:0] cby_1__1__74_left_grid_pin_22_ ; +wire [0:0] cby_1__1__74_left_grid_pin_23_ ; +wire [0:0] cby_1__1__74_left_grid_pin_24_ ; +wire [0:0] cby_1__1__74_left_grid_pin_25_ ; +wire [0:0] cby_1__1__74_left_grid_pin_26_ ; +wire [0:0] cby_1__1__74_left_grid_pin_27_ ; +wire [0:0] cby_1__1__74_left_grid_pin_28_ ; +wire [0:0] cby_1__1__74_left_grid_pin_29_ ; +wire [0:0] cby_1__1__74_left_grid_pin_30_ ; +wire [0:0] cby_1__1__74_left_grid_pin_31_ ; +wire [0:0] cby_1__1__75_ccff_tail ; +wire [0:29] cby_1__1__75_chany_bottom_out ; +wire [0:29] cby_1__1__75_chany_top_out ; +wire [0:0] cby_1__1__75_left_grid_pin_16_ ; +wire [0:0] cby_1__1__75_left_grid_pin_17_ ; +wire [0:0] cby_1__1__75_left_grid_pin_18_ ; +wire [0:0] cby_1__1__75_left_grid_pin_19_ ; +wire [0:0] cby_1__1__75_left_grid_pin_20_ ; +wire [0:0] cby_1__1__75_left_grid_pin_21_ ; +wire [0:0] cby_1__1__75_left_grid_pin_22_ ; +wire [0:0] cby_1__1__75_left_grid_pin_23_ ; +wire [0:0] cby_1__1__75_left_grid_pin_24_ ; +wire [0:0] cby_1__1__75_left_grid_pin_25_ ; +wire [0:0] cby_1__1__75_left_grid_pin_26_ ; +wire [0:0] cby_1__1__75_left_grid_pin_27_ ; +wire [0:0] cby_1__1__75_left_grid_pin_28_ ; +wire [0:0] cby_1__1__75_left_grid_pin_29_ ; +wire [0:0] cby_1__1__75_left_grid_pin_30_ ; +wire [0:0] cby_1__1__75_left_grid_pin_31_ ; +wire [0:0] cby_1__1__76_ccff_tail ; +wire [0:29] cby_1__1__76_chany_bottom_out ; +wire [0:29] cby_1__1__76_chany_top_out ; +wire [0:0] cby_1__1__76_left_grid_pin_16_ ; +wire [0:0] cby_1__1__76_left_grid_pin_17_ ; +wire [0:0] cby_1__1__76_left_grid_pin_18_ ; +wire [0:0] cby_1__1__76_left_grid_pin_19_ ; +wire [0:0] cby_1__1__76_left_grid_pin_20_ ; +wire [0:0] cby_1__1__76_left_grid_pin_21_ ; +wire [0:0] cby_1__1__76_left_grid_pin_22_ ; +wire [0:0] cby_1__1__76_left_grid_pin_23_ ; +wire [0:0] cby_1__1__76_left_grid_pin_24_ ; +wire [0:0] cby_1__1__76_left_grid_pin_25_ ; +wire [0:0] cby_1__1__76_left_grid_pin_26_ ; +wire [0:0] cby_1__1__76_left_grid_pin_27_ ; +wire [0:0] cby_1__1__76_left_grid_pin_28_ ; +wire [0:0] cby_1__1__76_left_grid_pin_29_ ; +wire [0:0] cby_1__1__76_left_grid_pin_30_ ; +wire [0:0] cby_1__1__76_left_grid_pin_31_ ; +wire [0:0] cby_1__1__77_ccff_tail ; +wire [0:29] cby_1__1__77_chany_bottom_out ; +wire [0:29] cby_1__1__77_chany_top_out ; +wire [0:0] cby_1__1__77_left_grid_pin_16_ ; +wire [0:0] cby_1__1__77_left_grid_pin_17_ ; +wire [0:0] cby_1__1__77_left_grid_pin_18_ ; +wire [0:0] cby_1__1__77_left_grid_pin_19_ ; +wire [0:0] cby_1__1__77_left_grid_pin_20_ ; +wire [0:0] cby_1__1__77_left_grid_pin_21_ ; +wire [0:0] cby_1__1__77_left_grid_pin_22_ ; +wire [0:0] cby_1__1__77_left_grid_pin_23_ ; +wire [0:0] cby_1__1__77_left_grid_pin_24_ ; +wire [0:0] cby_1__1__77_left_grid_pin_25_ ; +wire [0:0] cby_1__1__77_left_grid_pin_26_ ; +wire [0:0] cby_1__1__77_left_grid_pin_27_ ; +wire [0:0] cby_1__1__77_left_grid_pin_28_ ; +wire [0:0] cby_1__1__77_left_grid_pin_29_ ; +wire [0:0] cby_1__1__77_left_grid_pin_30_ ; +wire [0:0] cby_1__1__77_left_grid_pin_31_ ; +wire [0:0] cby_1__1__78_ccff_tail ; +wire [0:29] cby_1__1__78_chany_bottom_out ; +wire [0:29] cby_1__1__78_chany_top_out ; +wire [0:0] cby_1__1__78_left_grid_pin_16_ ; +wire [0:0] cby_1__1__78_left_grid_pin_17_ ; +wire [0:0] cby_1__1__78_left_grid_pin_18_ ; +wire [0:0] cby_1__1__78_left_grid_pin_19_ ; +wire [0:0] cby_1__1__78_left_grid_pin_20_ ; +wire [0:0] cby_1__1__78_left_grid_pin_21_ ; +wire [0:0] cby_1__1__78_left_grid_pin_22_ ; +wire [0:0] cby_1__1__78_left_grid_pin_23_ ; +wire [0:0] cby_1__1__78_left_grid_pin_24_ ; +wire [0:0] cby_1__1__78_left_grid_pin_25_ ; +wire [0:0] cby_1__1__78_left_grid_pin_26_ ; +wire [0:0] cby_1__1__78_left_grid_pin_27_ ; +wire [0:0] cby_1__1__78_left_grid_pin_28_ ; +wire [0:0] cby_1__1__78_left_grid_pin_29_ ; +wire [0:0] cby_1__1__78_left_grid_pin_30_ ; +wire [0:0] cby_1__1__78_left_grid_pin_31_ ; +wire [0:0] cby_1__1__79_ccff_tail ; +wire [0:29] cby_1__1__79_chany_bottom_out ; +wire [0:29] cby_1__1__79_chany_top_out ; +wire [0:0] cby_1__1__79_left_grid_pin_16_ ; +wire [0:0] cby_1__1__79_left_grid_pin_17_ ; +wire [0:0] cby_1__1__79_left_grid_pin_18_ ; +wire [0:0] cby_1__1__79_left_grid_pin_19_ ; +wire [0:0] cby_1__1__79_left_grid_pin_20_ ; +wire [0:0] cby_1__1__79_left_grid_pin_21_ ; +wire [0:0] cby_1__1__79_left_grid_pin_22_ ; +wire [0:0] cby_1__1__79_left_grid_pin_23_ ; +wire [0:0] cby_1__1__79_left_grid_pin_24_ ; +wire [0:0] cby_1__1__79_left_grid_pin_25_ ; +wire [0:0] cby_1__1__79_left_grid_pin_26_ ; +wire [0:0] cby_1__1__79_left_grid_pin_27_ ; +wire [0:0] cby_1__1__79_left_grid_pin_28_ ; +wire [0:0] cby_1__1__79_left_grid_pin_29_ ; +wire [0:0] cby_1__1__79_left_grid_pin_30_ ; +wire [0:0] cby_1__1__79_left_grid_pin_31_ ; +wire [0:0] cby_1__1__7_ccff_tail ; +wire [0:29] cby_1__1__7_chany_bottom_out ; +wire [0:29] cby_1__1__7_chany_top_out ; +wire [0:0] cby_1__1__7_left_grid_pin_16_ ; +wire [0:0] cby_1__1__7_left_grid_pin_17_ ; +wire [0:0] cby_1__1__7_left_grid_pin_18_ ; +wire [0:0] cby_1__1__7_left_grid_pin_19_ ; +wire [0:0] cby_1__1__7_left_grid_pin_20_ ; +wire [0:0] cby_1__1__7_left_grid_pin_21_ ; +wire [0:0] cby_1__1__7_left_grid_pin_22_ ; +wire [0:0] cby_1__1__7_left_grid_pin_23_ ; +wire [0:0] cby_1__1__7_left_grid_pin_24_ ; +wire [0:0] cby_1__1__7_left_grid_pin_25_ ; +wire [0:0] cby_1__1__7_left_grid_pin_26_ ; +wire [0:0] cby_1__1__7_left_grid_pin_27_ ; +wire [0:0] cby_1__1__7_left_grid_pin_28_ ; +wire [0:0] cby_1__1__7_left_grid_pin_29_ ; +wire [0:0] cby_1__1__7_left_grid_pin_30_ ; +wire [0:0] cby_1__1__7_left_grid_pin_31_ ; +wire [0:0] cby_1__1__80_ccff_tail ; +wire [0:29] cby_1__1__80_chany_bottom_out ; +wire [0:29] cby_1__1__80_chany_top_out ; +wire [0:0] cby_1__1__80_left_grid_pin_16_ ; +wire [0:0] cby_1__1__80_left_grid_pin_17_ ; +wire [0:0] cby_1__1__80_left_grid_pin_18_ ; +wire [0:0] cby_1__1__80_left_grid_pin_19_ ; +wire [0:0] cby_1__1__80_left_grid_pin_20_ ; +wire [0:0] cby_1__1__80_left_grid_pin_21_ ; +wire [0:0] cby_1__1__80_left_grid_pin_22_ ; +wire [0:0] cby_1__1__80_left_grid_pin_23_ ; +wire [0:0] cby_1__1__80_left_grid_pin_24_ ; +wire [0:0] cby_1__1__80_left_grid_pin_25_ ; +wire [0:0] cby_1__1__80_left_grid_pin_26_ ; +wire [0:0] cby_1__1__80_left_grid_pin_27_ ; +wire [0:0] cby_1__1__80_left_grid_pin_28_ ; +wire [0:0] cby_1__1__80_left_grid_pin_29_ ; +wire [0:0] cby_1__1__80_left_grid_pin_30_ ; +wire [0:0] cby_1__1__80_left_grid_pin_31_ ; +wire [0:0] cby_1__1__81_ccff_tail ; +wire [0:29] cby_1__1__81_chany_bottom_out ; +wire [0:29] cby_1__1__81_chany_top_out ; +wire [0:0] cby_1__1__81_left_grid_pin_16_ ; +wire [0:0] cby_1__1__81_left_grid_pin_17_ ; +wire [0:0] cby_1__1__81_left_grid_pin_18_ ; +wire [0:0] cby_1__1__81_left_grid_pin_19_ ; +wire [0:0] cby_1__1__81_left_grid_pin_20_ ; +wire [0:0] cby_1__1__81_left_grid_pin_21_ ; +wire [0:0] cby_1__1__81_left_grid_pin_22_ ; +wire [0:0] cby_1__1__81_left_grid_pin_23_ ; +wire [0:0] cby_1__1__81_left_grid_pin_24_ ; +wire [0:0] cby_1__1__81_left_grid_pin_25_ ; +wire [0:0] cby_1__1__81_left_grid_pin_26_ ; +wire [0:0] cby_1__1__81_left_grid_pin_27_ ; +wire [0:0] cby_1__1__81_left_grid_pin_28_ ; +wire [0:0] cby_1__1__81_left_grid_pin_29_ ; +wire [0:0] cby_1__1__81_left_grid_pin_30_ ; +wire [0:0] cby_1__1__81_left_grid_pin_31_ ; +wire [0:0] cby_1__1__82_ccff_tail ; +wire [0:29] cby_1__1__82_chany_bottom_out ; +wire [0:29] cby_1__1__82_chany_top_out ; +wire [0:0] cby_1__1__82_left_grid_pin_16_ ; +wire [0:0] cby_1__1__82_left_grid_pin_17_ ; +wire [0:0] cby_1__1__82_left_grid_pin_18_ ; +wire [0:0] cby_1__1__82_left_grid_pin_19_ ; +wire [0:0] cby_1__1__82_left_grid_pin_20_ ; +wire [0:0] cby_1__1__82_left_grid_pin_21_ ; +wire [0:0] cby_1__1__82_left_grid_pin_22_ ; +wire [0:0] cby_1__1__82_left_grid_pin_23_ ; +wire [0:0] cby_1__1__82_left_grid_pin_24_ ; +wire [0:0] cby_1__1__82_left_grid_pin_25_ ; +wire [0:0] cby_1__1__82_left_grid_pin_26_ ; +wire [0:0] cby_1__1__82_left_grid_pin_27_ ; +wire [0:0] cby_1__1__82_left_grid_pin_28_ ; +wire [0:0] cby_1__1__82_left_grid_pin_29_ ; +wire [0:0] cby_1__1__82_left_grid_pin_30_ ; +wire [0:0] cby_1__1__82_left_grid_pin_31_ ; +wire [0:0] cby_1__1__83_ccff_tail ; +wire [0:29] cby_1__1__83_chany_bottom_out ; +wire [0:29] cby_1__1__83_chany_top_out ; +wire [0:0] cby_1__1__83_left_grid_pin_16_ ; +wire [0:0] cby_1__1__83_left_grid_pin_17_ ; +wire [0:0] cby_1__1__83_left_grid_pin_18_ ; +wire [0:0] cby_1__1__83_left_grid_pin_19_ ; +wire [0:0] cby_1__1__83_left_grid_pin_20_ ; +wire [0:0] cby_1__1__83_left_grid_pin_21_ ; +wire [0:0] cby_1__1__83_left_grid_pin_22_ ; +wire [0:0] cby_1__1__83_left_grid_pin_23_ ; +wire [0:0] cby_1__1__83_left_grid_pin_24_ ; +wire [0:0] cby_1__1__83_left_grid_pin_25_ ; +wire [0:0] cby_1__1__83_left_grid_pin_26_ ; +wire [0:0] cby_1__1__83_left_grid_pin_27_ ; +wire [0:0] cby_1__1__83_left_grid_pin_28_ ; +wire [0:0] cby_1__1__83_left_grid_pin_29_ ; +wire [0:0] cby_1__1__83_left_grid_pin_30_ ; +wire [0:0] cby_1__1__83_left_grid_pin_31_ ; +wire [0:0] cby_1__1__84_ccff_tail ; +wire [0:29] cby_1__1__84_chany_bottom_out ; +wire [0:29] cby_1__1__84_chany_top_out ; +wire [0:0] cby_1__1__84_left_grid_pin_16_ ; +wire [0:0] cby_1__1__84_left_grid_pin_17_ ; +wire [0:0] cby_1__1__84_left_grid_pin_18_ ; +wire [0:0] cby_1__1__84_left_grid_pin_19_ ; +wire [0:0] cby_1__1__84_left_grid_pin_20_ ; +wire [0:0] cby_1__1__84_left_grid_pin_21_ ; +wire [0:0] cby_1__1__84_left_grid_pin_22_ ; +wire [0:0] cby_1__1__84_left_grid_pin_23_ ; +wire [0:0] cby_1__1__84_left_grid_pin_24_ ; +wire [0:0] cby_1__1__84_left_grid_pin_25_ ; +wire [0:0] cby_1__1__84_left_grid_pin_26_ ; +wire [0:0] cby_1__1__84_left_grid_pin_27_ ; +wire [0:0] cby_1__1__84_left_grid_pin_28_ ; +wire [0:0] cby_1__1__84_left_grid_pin_29_ ; +wire [0:0] cby_1__1__84_left_grid_pin_30_ ; +wire [0:0] cby_1__1__84_left_grid_pin_31_ ; +wire [0:0] cby_1__1__85_ccff_tail ; +wire [0:29] cby_1__1__85_chany_bottom_out ; +wire [0:29] cby_1__1__85_chany_top_out ; +wire [0:0] cby_1__1__85_left_grid_pin_16_ ; +wire [0:0] cby_1__1__85_left_grid_pin_17_ ; +wire [0:0] cby_1__1__85_left_grid_pin_18_ ; +wire [0:0] cby_1__1__85_left_grid_pin_19_ ; +wire [0:0] cby_1__1__85_left_grid_pin_20_ ; +wire [0:0] cby_1__1__85_left_grid_pin_21_ ; +wire [0:0] cby_1__1__85_left_grid_pin_22_ ; +wire [0:0] cby_1__1__85_left_grid_pin_23_ ; +wire [0:0] cby_1__1__85_left_grid_pin_24_ ; +wire [0:0] cby_1__1__85_left_grid_pin_25_ ; +wire [0:0] cby_1__1__85_left_grid_pin_26_ ; +wire [0:0] cby_1__1__85_left_grid_pin_27_ ; +wire [0:0] cby_1__1__85_left_grid_pin_28_ ; +wire [0:0] cby_1__1__85_left_grid_pin_29_ ; +wire [0:0] cby_1__1__85_left_grid_pin_30_ ; +wire [0:0] cby_1__1__85_left_grid_pin_31_ ; +wire [0:0] cby_1__1__86_ccff_tail ; +wire [0:29] cby_1__1__86_chany_bottom_out ; +wire [0:29] cby_1__1__86_chany_top_out ; +wire [0:0] cby_1__1__86_left_grid_pin_16_ ; +wire [0:0] cby_1__1__86_left_grid_pin_17_ ; +wire [0:0] cby_1__1__86_left_grid_pin_18_ ; +wire [0:0] cby_1__1__86_left_grid_pin_19_ ; +wire [0:0] cby_1__1__86_left_grid_pin_20_ ; +wire [0:0] cby_1__1__86_left_grid_pin_21_ ; +wire [0:0] cby_1__1__86_left_grid_pin_22_ ; +wire [0:0] cby_1__1__86_left_grid_pin_23_ ; +wire [0:0] cby_1__1__86_left_grid_pin_24_ ; +wire [0:0] cby_1__1__86_left_grid_pin_25_ ; +wire [0:0] cby_1__1__86_left_grid_pin_26_ ; +wire [0:0] cby_1__1__86_left_grid_pin_27_ ; +wire [0:0] cby_1__1__86_left_grid_pin_28_ ; +wire [0:0] cby_1__1__86_left_grid_pin_29_ ; +wire [0:0] cby_1__1__86_left_grid_pin_30_ ; +wire [0:0] cby_1__1__86_left_grid_pin_31_ ; +wire [0:0] cby_1__1__87_ccff_tail ; +wire [0:29] cby_1__1__87_chany_bottom_out ; +wire [0:29] cby_1__1__87_chany_top_out ; +wire [0:0] cby_1__1__87_left_grid_pin_16_ ; +wire [0:0] cby_1__1__87_left_grid_pin_17_ ; +wire [0:0] cby_1__1__87_left_grid_pin_18_ ; +wire [0:0] cby_1__1__87_left_grid_pin_19_ ; +wire [0:0] cby_1__1__87_left_grid_pin_20_ ; +wire [0:0] cby_1__1__87_left_grid_pin_21_ ; +wire [0:0] cby_1__1__87_left_grid_pin_22_ ; +wire [0:0] cby_1__1__87_left_grid_pin_23_ ; +wire [0:0] cby_1__1__87_left_grid_pin_24_ ; +wire [0:0] cby_1__1__87_left_grid_pin_25_ ; +wire [0:0] cby_1__1__87_left_grid_pin_26_ ; +wire [0:0] cby_1__1__87_left_grid_pin_27_ ; +wire [0:0] cby_1__1__87_left_grid_pin_28_ ; +wire [0:0] cby_1__1__87_left_grid_pin_29_ ; +wire [0:0] cby_1__1__87_left_grid_pin_30_ ; +wire [0:0] cby_1__1__87_left_grid_pin_31_ ; +wire [0:0] cby_1__1__88_ccff_tail ; +wire [0:29] cby_1__1__88_chany_bottom_out ; +wire [0:29] cby_1__1__88_chany_top_out ; +wire [0:0] cby_1__1__88_left_grid_pin_16_ ; +wire [0:0] cby_1__1__88_left_grid_pin_17_ ; +wire [0:0] cby_1__1__88_left_grid_pin_18_ ; +wire [0:0] cby_1__1__88_left_grid_pin_19_ ; +wire [0:0] cby_1__1__88_left_grid_pin_20_ ; +wire [0:0] cby_1__1__88_left_grid_pin_21_ ; +wire [0:0] cby_1__1__88_left_grid_pin_22_ ; +wire [0:0] cby_1__1__88_left_grid_pin_23_ ; +wire [0:0] cby_1__1__88_left_grid_pin_24_ ; +wire [0:0] cby_1__1__88_left_grid_pin_25_ ; +wire [0:0] cby_1__1__88_left_grid_pin_26_ ; +wire [0:0] cby_1__1__88_left_grid_pin_27_ ; +wire [0:0] cby_1__1__88_left_grid_pin_28_ ; +wire [0:0] cby_1__1__88_left_grid_pin_29_ ; +wire [0:0] cby_1__1__88_left_grid_pin_30_ ; +wire [0:0] cby_1__1__88_left_grid_pin_31_ ; +wire [0:0] cby_1__1__89_ccff_tail ; +wire [0:29] cby_1__1__89_chany_bottom_out ; +wire [0:29] cby_1__1__89_chany_top_out ; +wire [0:0] cby_1__1__89_left_grid_pin_16_ ; +wire [0:0] cby_1__1__89_left_grid_pin_17_ ; +wire [0:0] cby_1__1__89_left_grid_pin_18_ ; +wire [0:0] cby_1__1__89_left_grid_pin_19_ ; +wire [0:0] cby_1__1__89_left_grid_pin_20_ ; +wire [0:0] cby_1__1__89_left_grid_pin_21_ ; +wire [0:0] cby_1__1__89_left_grid_pin_22_ ; +wire [0:0] cby_1__1__89_left_grid_pin_23_ ; +wire [0:0] cby_1__1__89_left_grid_pin_24_ ; +wire [0:0] cby_1__1__89_left_grid_pin_25_ ; +wire [0:0] cby_1__1__89_left_grid_pin_26_ ; +wire [0:0] cby_1__1__89_left_grid_pin_27_ ; +wire [0:0] cby_1__1__89_left_grid_pin_28_ ; +wire [0:0] cby_1__1__89_left_grid_pin_29_ ; +wire [0:0] cby_1__1__89_left_grid_pin_30_ ; +wire [0:0] cby_1__1__89_left_grid_pin_31_ ; +wire [0:0] cby_1__1__8_ccff_tail ; +wire [0:29] cby_1__1__8_chany_bottom_out ; +wire [0:29] cby_1__1__8_chany_top_out ; +wire [0:0] cby_1__1__8_left_grid_pin_16_ ; +wire [0:0] cby_1__1__8_left_grid_pin_17_ ; +wire [0:0] cby_1__1__8_left_grid_pin_18_ ; +wire [0:0] cby_1__1__8_left_grid_pin_19_ ; +wire [0:0] cby_1__1__8_left_grid_pin_20_ ; +wire [0:0] cby_1__1__8_left_grid_pin_21_ ; +wire [0:0] cby_1__1__8_left_grid_pin_22_ ; +wire [0:0] cby_1__1__8_left_grid_pin_23_ ; +wire [0:0] cby_1__1__8_left_grid_pin_24_ ; +wire [0:0] cby_1__1__8_left_grid_pin_25_ ; +wire [0:0] cby_1__1__8_left_grid_pin_26_ ; +wire [0:0] cby_1__1__8_left_grid_pin_27_ ; +wire [0:0] cby_1__1__8_left_grid_pin_28_ ; +wire [0:0] cby_1__1__8_left_grid_pin_29_ ; +wire [0:0] cby_1__1__8_left_grid_pin_30_ ; +wire [0:0] cby_1__1__8_left_grid_pin_31_ ; +wire [0:0] cby_1__1__90_ccff_tail ; +wire [0:29] cby_1__1__90_chany_bottom_out ; +wire [0:29] cby_1__1__90_chany_top_out ; +wire [0:0] cby_1__1__90_left_grid_pin_16_ ; +wire [0:0] cby_1__1__90_left_grid_pin_17_ ; +wire [0:0] cby_1__1__90_left_grid_pin_18_ ; +wire [0:0] cby_1__1__90_left_grid_pin_19_ ; +wire [0:0] cby_1__1__90_left_grid_pin_20_ ; +wire [0:0] cby_1__1__90_left_grid_pin_21_ ; +wire [0:0] cby_1__1__90_left_grid_pin_22_ ; +wire [0:0] cby_1__1__90_left_grid_pin_23_ ; +wire [0:0] cby_1__1__90_left_grid_pin_24_ ; +wire [0:0] cby_1__1__90_left_grid_pin_25_ ; +wire [0:0] cby_1__1__90_left_grid_pin_26_ ; +wire [0:0] cby_1__1__90_left_grid_pin_27_ ; +wire [0:0] cby_1__1__90_left_grid_pin_28_ ; +wire [0:0] cby_1__1__90_left_grid_pin_29_ ; +wire [0:0] cby_1__1__90_left_grid_pin_30_ ; +wire [0:0] cby_1__1__90_left_grid_pin_31_ ; +wire [0:0] cby_1__1__91_ccff_tail ; +wire [0:29] cby_1__1__91_chany_bottom_out ; +wire [0:29] cby_1__1__91_chany_top_out ; +wire [0:0] cby_1__1__91_left_grid_pin_16_ ; +wire [0:0] cby_1__1__91_left_grid_pin_17_ ; +wire [0:0] cby_1__1__91_left_grid_pin_18_ ; +wire [0:0] cby_1__1__91_left_grid_pin_19_ ; +wire [0:0] cby_1__1__91_left_grid_pin_20_ ; +wire [0:0] cby_1__1__91_left_grid_pin_21_ ; +wire [0:0] cby_1__1__91_left_grid_pin_22_ ; +wire [0:0] cby_1__1__91_left_grid_pin_23_ ; +wire [0:0] cby_1__1__91_left_grid_pin_24_ ; +wire [0:0] cby_1__1__91_left_grid_pin_25_ ; +wire [0:0] cby_1__1__91_left_grid_pin_26_ ; +wire [0:0] cby_1__1__91_left_grid_pin_27_ ; +wire [0:0] cby_1__1__91_left_grid_pin_28_ ; +wire [0:0] cby_1__1__91_left_grid_pin_29_ ; +wire [0:0] cby_1__1__91_left_grid_pin_30_ ; +wire [0:0] cby_1__1__91_left_grid_pin_31_ ; +wire [0:0] cby_1__1__92_ccff_tail ; +wire [0:29] cby_1__1__92_chany_bottom_out ; +wire [0:29] cby_1__1__92_chany_top_out ; +wire [0:0] cby_1__1__92_left_grid_pin_16_ ; +wire [0:0] cby_1__1__92_left_grid_pin_17_ ; +wire [0:0] cby_1__1__92_left_grid_pin_18_ ; +wire [0:0] cby_1__1__92_left_grid_pin_19_ ; +wire [0:0] cby_1__1__92_left_grid_pin_20_ ; +wire [0:0] cby_1__1__92_left_grid_pin_21_ ; +wire [0:0] cby_1__1__92_left_grid_pin_22_ ; +wire [0:0] cby_1__1__92_left_grid_pin_23_ ; +wire [0:0] cby_1__1__92_left_grid_pin_24_ ; +wire [0:0] cby_1__1__92_left_grid_pin_25_ ; +wire [0:0] cby_1__1__92_left_grid_pin_26_ ; +wire [0:0] cby_1__1__92_left_grid_pin_27_ ; +wire [0:0] cby_1__1__92_left_grid_pin_28_ ; +wire [0:0] cby_1__1__92_left_grid_pin_29_ ; +wire [0:0] cby_1__1__92_left_grid_pin_30_ ; +wire [0:0] cby_1__1__92_left_grid_pin_31_ ; +wire [0:0] cby_1__1__93_ccff_tail ; +wire [0:29] cby_1__1__93_chany_bottom_out ; +wire [0:29] cby_1__1__93_chany_top_out ; +wire [0:0] cby_1__1__93_left_grid_pin_16_ ; +wire [0:0] cby_1__1__93_left_grid_pin_17_ ; +wire [0:0] cby_1__1__93_left_grid_pin_18_ ; +wire [0:0] cby_1__1__93_left_grid_pin_19_ ; +wire [0:0] cby_1__1__93_left_grid_pin_20_ ; +wire [0:0] cby_1__1__93_left_grid_pin_21_ ; +wire [0:0] cby_1__1__93_left_grid_pin_22_ ; +wire [0:0] cby_1__1__93_left_grid_pin_23_ ; +wire [0:0] cby_1__1__93_left_grid_pin_24_ ; +wire [0:0] cby_1__1__93_left_grid_pin_25_ ; +wire [0:0] cby_1__1__93_left_grid_pin_26_ ; +wire [0:0] cby_1__1__93_left_grid_pin_27_ ; +wire [0:0] cby_1__1__93_left_grid_pin_28_ ; +wire [0:0] cby_1__1__93_left_grid_pin_29_ ; +wire [0:0] cby_1__1__93_left_grid_pin_30_ ; +wire [0:0] cby_1__1__93_left_grid_pin_31_ ; +wire [0:0] cby_1__1__94_ccff_tail ; +wire [0:29] cby_1__1__94_chany_bottom_out ; +wire [0:29] cby_1__1__94_chany_top_out ; +wire [0:0] cby_1__1__94_left_grid_pin_16_ ; +wire [0:0] cby_1__1__94_left_grid_pin_17_ ; +wire [0:0] cby_1__1__94_left_grid_pin_18_ ; +wire [0:0] cby_1__1__94_left_grid_pin_19_ ; +wire [0:0] cby_1__1__94_left_grid_pin_20_ ; +wire [0:0] cby_1__1__94_left_grid_pin_21_ ; +wire [0:0] cby_1__1__94_left_grid_pin_22_ ; +wire [0:0] cby_1__1__94_left_grid_pin_23_ ; +wire [0:0] cby_1__1__94_left_grid_pin_24_ ; +wire [0:0] cby_1__1__94_left_grid_pin_25_ ; +wire [0:0] cby_1__1__94_left_grid_pin_26_ ; +wire [0:0] cby_1__1__94_left_grid_pin_27_ ; +wire [0:0] cby_1__1__94_left_grid_pin_28_ ; +wire [0:0] cby_1__1__94_left_grid_pin_29_ ; +wire [0:0] cby_1__1__94_left_grid_pin_30_ ; +wire [0:0] cby_1__1__94_left_grid_pin_31_ ; +wire [0:0] cby_1__1__95_ccff_tail ; +wire [0:29] cby_1__1__95_chany_bottom_out ; +wire [0:29] cby_1__1__95_chany_top_out ; +wire [0:0] cby_1__1__95_left_grid_pin_16_ ; +wire [0:0] cby_1__1__95_left_grid_pin_17_ ; +wire [0:0] cby_1__1__95_left_grid_pin_18_ ; +wire [0:0] cby_1__1__95_left_grid_pin_19_ ; +wire [0:0] cby_1__1__95_left_grid_pin_20_ ; +wire [0:0] cby_1__1__95_left_grid_pin_21_ ; +wire [0:0] cby_1__1__95_left_grid_pin_22_ ; +wire [0:0] cby_1__1__95_left_grid_pin_23_ ; +wire [0:0] cby_1__1__95_left_grid_pin_24_ ; +wire [0:0] cby_1__1__95_left_grid_pin_25_ ; +wire [0:0] cby_1__1__95_left_grid_pin_26_ ; +wire [0:0] cby_1__1__95_left_grid_pin_27_ ; +wire [0:0] cby_1__1__95_left_grid_pin_28_ ; +wire [0:0] cby_1__1__95_left_grid_pin_29_ ; +wire [0:0] cby_1__1__95_left_grid_pin_30_ ; +wire [0:0] cby_1__1__95_left_grid_pin_31_ ; +wire [0:0] cby_1__1__96_ccff_tail ; +wire [0:29] cby_1__1__96_chany_bottom_out ; +wire [0:29] cby_1__1__96_chany_top_out ; +wire [0:0] cby_1__1__96_left_grid_pin_16_ ; +wire [0:0] cby_1__1__96_left_grid_pin_17_ ; +wire [0:0] cby_1__1__96_left_grid_pin_18_ ; +wire [0:0] cby_1__1__96_left_grid_pin_19_ ; +wire [0:0] cby_1__1__96_left_grid_pin_20_ ; +wire [0:0] cby_1__1__96_left_grid_pin_21_ ; +wire [0:0] cby_1__1__96_left_grid_pin_22_ ; +wire [0:0] cby_1__1__96_left_grid_pin_23_ ; +wire [0:0] cby_1__1__96_left_grid_pin_24_ ; +wire [0:0] cby_1__1__96_left_grid_pin_25_ ; +wire [0:0] cby_1__1__96_left_grid_pin_26_ ; +wire [0:0] cby_1__1__96_left_grid_pin_27_ ; +wire [0:0] cby_1__1__96_left_grid_pin_28_ ; +wire [0:0] cby_1__1__96_left_grid_pin_29_ ; +wire [0:0] cby_1__1__96_left_grid_pin_30_ ; +wire [0:0] cby_1__1__96_left_grid_pin_31_ ; +wire [0:0] cby_1__1__97_ccff_tail ; +wire [0:29] cby_1__1__97_chany_bottom_out ; +wire [0:29] cby_1__1__97_chany_top_out ; +wire [0:0] cby_1__1__97_left_grid_pin_16_ ; +wire [0:0] cby_1__1__97_left_grid_pin_17_ ; +wire [0:0] cby_1__1__97_left_grid_pin_18_ ; +wire [0:0] cby_1__1__97_left_grid_pin_19_ ; +wire [0:0] cby_1__1__97_left_grid_pin_20_ ; +wire [0:0] cby_1__1__97_left_grid_pin_21_ ; +wire [0:0] cby_1__1__97_left_grid_pin_22_ ; +wire [0:0] cby_1__1__97_left_grid_pin_23_ ; +wire [0:0] cby_1__1__97_left_grid_pin_24_ ; +wire [0:0] cby_1__1__97_left_grid_pin_25_ ; +wire [0:0] cby_1__1__97_left_grid_pin_26_ ; +wire [0:0] cby_1__1__97_left_grid_pin_27_ ; +wire [0:0] cby_1__1__97_left_grid_pin_28_ ; +wire [0:0] cby_1__1__97_left_grid_pin_29_ ; +wire [0:0] cby_1__1__97_left_grid_pin_30_ ; +wire [0:0] cby_1__1__97_left_grid_pin_31_ ; +wire [0:0] cby_1__1__98_ccff_tail ; +wire [0:29] cby_1__1__98_chany_bottom_out ; +wire [0:29] cby_1__1__98_chany_top_out ; +wire [0:0] cby_1__1__98_left_grid_pin_16_ ; +wire [0:0] cby_1__1__98_left_grid_pin_17_ ; +wire [0:0] cby_1__1__98_left_grid_pin_18_ ; +wire [0:0] cby_1__1__98_left_grid_pin_19_ ; +wire [0:0] cby_1__1__98_left_grid_pin_20_ ; +wire [0:0] cby_1__1__98_left_grid_pin_21_ ; +wire [0:0] cby_1__1__98_left_grid_pin_22_ ; +wire [0:0] cby_1__1__98_left_grid_pin_23_ ; +wire [0:0] cby_1__1__98_left_grid_pin_24_ ; +wire [0:0] cby_1__1__98_left_grid_pin_25_ ; +wire [0:0] cby_1__1__98_left_grid_pin_26_ ; +wire [0:0] cby_1__1__98_left_grid_pin_27_ ; +wire [0:0] cby_1__1__98_left_grid_pin_28_ ; +wire [0:0] cby_1__1__98_left_grid_pin_29_ ; +wire [0:0] cby_1__1__98_left_grid_pin_30_ ; +wire [0:0] cby_1__1__98_left_grid_pin_31_ ; +wire [0:0] cby_1__1__99_ccff_tail ; +wire [0:29] cby_1__1__99_chany_bottom_out ; +wire [0:29] cby_1__1__99_chany_top_out ; +wire [0:0] cby_1__1__99_left_grid_pin_16_ ; +wire [0:0] cby_1__1__99_left_grid_pin_17_ ; +wire [0:0] cby_1__1__99_left_grid_pin_18_ ; +wire [0:0] cby_1__1__99_left_grid_pin_19_ ; +wire [0:0] cby_1__1__99_left_grid_pin_20_ ; +wire [0:0] cby_1__1__99_left_grid_pin_21_ ; +wire [0:0] cby_1__1__99_left_grid_pin_22_ ; +wire [0:0] cby_1__1__99_left_grid_pin_23_ ; +wire [0:0] cby_1__1__99_left_grid_pin_24_ ; +wire [0:0] cby_1__1__99_left_grid_pin_25_ ; +wire [0:0] cby_1__1__99_left_grid_pin_26_ ; +wire [0:0] cby_1__1__99_left_grid_pin_27_ ; +wire [0:0] cby_1__1__99_left_grid_pin_28_ ; +wire [0:0] cby_1__1__99_left_grid_pin_29_ ; +wire [0:0] cby_1__1__99_left_grid_pin_30_ ; +wire [0:0] cby_1__1__99_left_grid_pin_31_ ; +wire [0:0] cby_1__1__9_ccff_tail ; +wire [0:29] cby_1__1__9_chany_bottom_out ; +wire [0:29] cby_1__1__9_chany_top_out ; +wire [0:0] cby_1__1__9_left_grid_pin_16_ ; +wire [0:0] cby_1__1__9_left_grid_pin_17_ ; +wire [0:0] cby_1__1__9_left_grid_pin_18_ ; +wire [0:0] cby_1__1__9_left_grid_pin_19_ ; +wire [0:0] cby_1__1__9_left_grid_pin_20_ ; +wire [0:0] cby_1__1__9_left_grid_pin_21_ ; +wire [0:0] cby_1__1__9_left_grid_pin_22_ ; +wire [0:0] cby_1__1__9_left_grid_pin_23_ ; +wire [0:0] cby_1__1__9_left_grid_pin_24_ ; +wire [0:0] cby_1__1__9_left_grid_pin_25_ ; +wire [0:0] cby_1__1__9_left_grid_pin_26_ ; +wire [0:0] cby_1__1__9_left_grid_pin_27_ ; +wire [0:0] cby_1__1__9_left_grid_pin_28_ ; +wire [0:0] cby_1__1__9_left_grid_pin_29_ ; +wire [0:0] cby_1__1__9_left_grid_pin_30_ ; +wire [0:0] cby_1__1__9_left_grid_pin_31_ ; +wire [0:0] direct_interc_0_out ; +wire [0:0] direct_interc_100_out ; +wire [0:0] direct_interc_101_out ; +wire [0:0] direct_interc_102_out ; +wire [0:0] direct_interc_103_out ; +wire [0:0] direct_interc_104_out ; +wire [0:0] direct_interc_105_out ; +wire [0:0] direct_interc_106_out ; +wire [0:0] direct_interc_107_out ; +wire [0:0] direct_interc_108_out ; +wire [0:0] direct_interc_109_out ; +wire [0:0] direct_interc_10_out ; +wire [0:0] direct_interc_110_out ; +wire [0:0] direct_interc_111_out ; +wire [0:0] direct_interc_112_out ; +wire [0:0] direct_interc_113_out ; +wire [0:0] direct_interc_114_out ; +wire [0:0] direct_interc_115_out ; +wire [0:0] direct_interc_116_out ; +wire [0:0] direct_interc_117_out ; +wire [0:0] direct_interc_118_out ; +wire [0:0] direct_interc_119_out ; +wire [0:0] direct_interc_11_out ; +wire [0:0] direct_interc_120_out ; +wire [0:0] direct_interc_121_out ; +wire [0:0] direct_interc_122_out ; +wire [0:0] direct_interc_123_out ; +wire [0:0] direct_interc_124_out ; +wire [0:0] direct_interc_125_out ; +wire [0:0] direct_interc_126_out ; +wire [0:0] direct_interc_127_out ; +wire [0:0] direct_interc_128_out ; +wire [0:0] direct_interc_129_out ; +wire [0:0] direct_interc_12_out ; +wire [0:0] direct_interc_130_out ; +wire [0:0] direct_interc_131_out ; +wire [0:0] direct_interc_132_out ; +wire [0:0] direct_interc_133_out ; +wire [0:0] direct_interc_134_out ; +wire [0:0] direct_interc_135_out ; +wire [0:0] direct_interc_136_out ; +wire [0:0] direct_interc_137_out ; +wire [0:0] direct_interc_138_out ; +wire [0:0] direct_interc_139_out ; +wire [0:0] direct_interc_13_out ; +wire [0:0] direct_interc_140_out ; +wire [0:0] direct_interc_141_out ; +wire [0:0] direct_interc_142_out ; +wire [0:0] direct_interc_143_out ; +wire [0:0] direct_interc_144_out ; +wire [0:0] direct_interc_145_out ; +wire [0:0] direct_interc_146_out ; +wire [0:0] direct_interc_147_out ; +wire [0:0] direct_interc_148_out ; +wire [0:0] direct_interc_149_out ; +wire [0:0] direct_interc_14_out ; +wire [0:0] direct_interc_150_out ; +wire [0:0] direct_interc_151_out ; +wire [0:0] direct_interc_152_out ; +wire [0:0] direct_interc_153_out ; +wire [0:0] direct_interc_154_out ; +wire [0:0] direct_interc_155_out ; +wire [0:0] direct_interc_156_out ; +wire [0:0] direct_interc_157_out ; +wire [0:0] direct_interc_158_out ; +wire [0:0] direct_interc_159_out ; +wire [0:0] direct_interc_15_out ; +wire [0:0] direct_interc_160_out ; +wire [0:0] direct_interc_161_out ; +wire [0:0] direct_interc_162_out ; +wire [0:0] direct_interc_163_out ; +wire [0:0] direct_interc_164_out ; +wire [0:0] direct_interc_165_out ; +wire [0:0] direct_interc_166_out ; +wire [0:0] direct_interc_167_out ; +wire [0:0] direct_interc_168_out ; +wire [0:0] direct_interc_169_out ; +wire [0:0] direct_interc_16_out ; +wire [0:0] direct_interc_170_out ; +wire [0:0] direct_interc_171_out ; +wire [0:0] direct_interc_172_out ; +wire [0:0] direct_interc_173_out ; +wire [0:0] direct_interc_174_out ; +wire [0:0] direct_interc_175_out ; +wire [0:0] direct_interc_176_out ; +wire [0:0] direct_interc_177_out ; +wire [0:0] direct_interc_178_out ; +wire [0:0] direct_interc_179_out ; +wire [0:0] direct_interc_17_out ; +wire [0:0] direct_interc_180_out ; +wire [0:0] direct_interc_181_out ; +wire [0:0] direct_interc_182_out ; +wire [0:0] direct_interc_183_out ; +wire [0:0] direct_interc_184_out ; +wire [0:0] direct_interc_185_out ; +wire [0:0] direct_interc_186_out ; +wire [0:0] direct_interc_187_out ; +wire [0:0] direct_interc_188_out ; +wire [0:0] direct_interc_189_out ; +wire [0:0] direct_interc_18_out ; +wire [0:0] direct_interc_190_out ; +wire [0:0] direct_interc_191_out ; +wire [0:0] direct_interc_192_out ; +wire [0:0] direct_interc_193_out ; +wire [0:0] direct_interc_194_out ; +wire [0:0] direct_interc_195_out ; +wire [0:0] direct_interc_196_out ; +wire [0:0] direct_interc_197_out ; +wire [0:0] direct_interc_198_out ; +wire [0:0] direct_interc_199_out ; +wire [0:0] direct_interc_19_out ; +wire [0:0] direct_interc_1_out ; +wire [0:0] direct_interc_200_out ; +wire [0:0] direct_interc_201_out ; +wire [0:0] direct_interc_202_out ; +wire [0:0] direct_interc_203_out ; +wire [0:0] direct_interc_204_out ; +wire [0:0] direct_interc_205_out ; +wire [0:0] direct_interc_206_out ; +wire [0:0] direct_interc_207_out ; +wire [0:0] direct_interc_208_out ; +wire [0:0] direct_interc_209_out ; +wire [0:0] direct_interc_20_out ; +wire [0:0] direct_interc_210_out ; +wire [0:0] direct_interc_211_out ; +wire [0:0] direct_interc_212_out ; +wire [0:0] direct_interc_213_out ; +wire [0:0] direct_interc_214_out ; +wire [0:0] direct_interc_215_out ; +wire [0:0] direct_interc_216_out ; +wire [0:0] direct_interc_217_out ; +wire [0:0] direct_interc_218_out ; +wire [0:0] direct_interc_219_out ; +wire [0:0] direct_interc_21_out ; +wire [0:0] direct_interc_220_out ; +wire [0:0] direct_interc_221_out ; +wire [0:0] direct_interc_222_out ; +wire [0:0] direct_interc_223_out ; +wire [0:0] direct_interc_224_out ; +wire [0:0] direct_interc_225_out ; +wire [0:0] direct_interc_226_out ; +wire [0:0] direct_interc_227_out ; +wire [0:0] direct_interc_228_out ; +wire [0:0] direct_interc_229_out ; +wire [0:0] direct_interc_22_out ; +wire [0:0] direct_interc_230_out ; +wire [0:0] direct_interc_231_out ; +wire [0:0] direct_interc_232_out ; +wire [0:0] direct_interc_233_out ; +wire [0:0] direct_interc_234_out ; +wire [0:0] direct_interc_235_out ; +wire [0:0] direct_interc_236_out ; +wire [0:0] direct_interc_237_out ; +wire [0:0] direct_interc_238_out ; +wire [0:0] direct_interc_239_out ; +wire [0:0] direct_interc_23_out ; +wire [0:0] direct_interc_240_out ; +wire [0:0] direct_interc_241_out ; +wire [0:0] direct_interc_242_out ; +wire [0:0] direct_interc_243_out ; +wire [0:0] direct_interc_244_out ; +wire [0:0] direct_interc_245_out ; +wire [0:0] direct_interc_246_out ; +wire [0:0] direct_interc_247_out ; +wire [0:0] direct_interc_248_out ; +wire [0:0] direct_interc_249_out ; +wire [0:0] direct_interc_24_out ; +wire [0:0] direct_interc_250_out ; +wire [0:0] direct_interc_251_out ; +wire [0:0] direct_interc_252_out ; +wire [0:0] direct_interc_253_out ; +wire [0:0] direct_interc_254_out ; +wire [0:0] direct_interc_255_out ; +wire [0:0] direct_interc_256_out ; +wire [0:0] direct_interc_257_out ; +wire [0:0] direct_interc_258_out ; +wire [0:0] direct_interc_259_out ; +wire [0:0] direct_interc_25_out ; +wire [0:0] direct_interc_260_out ; +wire [0:0] direct_interc_261_out ; +wire [0:0] direct_interc_262_out ; +wire [0:0] direct_interc_263_out ; +wire [0:0] direct_interc_264_out ; +wire [0:0] direct_interc_265_out ; +wire [0:0] direct_interc_266_out ; +wire [0:0] direct_interc_267_out ; +wire [0:0] direct_interc_268_out ; +wire [0:0] direct_interc_269_out ; +wire [0:0] direct_interc_26_out ; +wire [0:0] direct_interc_270_out ; +wire [0:0] direct_interc_271_out ; +wire [0:0] direct_interc_272_out ; +wire [0:0] direct_interc_273_out ; +wire [0:0] direct_interc_274_out ; +wire [0:0] direct_interc_275_out ; +wire [0:0] direct_interc_276_out ; +wire [0:0] direct_interc_277_out ; +wire [0:0] direct_interc_278_out ; +wire [0:0] direct_interc_279_out ; +wire [0:0] direct_interc_27_out ; +wire [0:0] direct_interc_280_out ; +wire [0:0] direct_interc_281_out ; +wire [0:0] direct_interc_282_out ; +wire [0:0] direct_interc_283_out ; +wire [0:0] direct_interc_284_out ; +wire [0:0] direct_interc_285_out ; +wire [0:0] direct_interc_286_out ; +wire [0:0] direct_interc_287_out ; +wire [0:0] direct_interc_288_out ; +wire [0:0] direct_interc_289_out ; +wire [0:0] direct_interc_28_out ; +wire [0:0] direct_interc_290_out ; +wire [0:0] direct_interc_291_out ; +wire [0:0] direct_interc_292_out ; +wire [0:0] direct_interc_293_out ; +wire [0:0] direct_interc_294_out ; +wire [0:0] direct_interc_295_out ; +wire [0:0] direct_interc_296_out ; +wire [0:0] direct_interc_297_out ; +wire [0:0] direct_interc_298_out ; +wire [0:0] direct_interc_299_out ; +wire [0:0] direct_interc_29_out ; +wire [0:0] direct_interc_2_out ; +wire [0:0] direct_interc_300_out ; +wire [0:0] direct_interc_301_out ; +wire [0:0] direct_interc_302_out ; +wire [0:0] direct_interc_303_out ; +wire [0:0] direct_interc_304_out ; +wire [0:0] direct_interc_305_out ; +wire [0:0] direct_interc_306_out ; +wire [0:0] direct_interc_307_out ; +wire [0:0] direct_interc_308_out ; +wire [0:0] direct_interc_309_out ; +wire [0:0] direct_interc_30_out ; +wire [0:0] direct_interc_310_out ; +wire [0:0] direct_interc_311_out ; +wire [0:0] direct_interc_312_out ; +wire [0:0] direct_interc_313_out ; +wire [0:0] direct_interc_314_out ; +wire [0:0] direct_interc_315_out ; +wire [0:0] direct_interc_316_out ; +wire [0:0] direct_interc_317_out ; +wire [0:0] direct_interc_318_out ; +wire [0:0] direct_interc_319_out ; +wire [0:0] direct_interc_31_out ; +wire [0:0] direct_interc_320_out ; +wire [0:0] direct_interc_321_out ; +wire [0:0] direct_interc_322_out ; +wire [0:0] direct_interc_323_out ; +wire [0:0] direct_interc_324_out ; +wire [0:0] direct_interc_325_out ; +wire [0:0] direct_interc_326_out ; +wire [0:0] direct_interc_327_out ; +wire [0:0] direct_interc_328_out ; +wire [0:0] direct_interc_329_out ; +wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_330_out ; +wire [0:0] direct_interc_331_out ; +wire [0:0] direct_interc_332_out ; +wire [0:0] direct_interc_333_out ; +wire [0:0] direct_interc_334_out ; +wire [0:0] direct_interc_335_out ; +wire [0:0] direct_interc_336_out ; +wire [0:0] direct_interc_337_out ; +wire [0:0] direct_interc_338_out ; +wire [0:0] direct_interc_339_out ; +wire [0:0] direct_interc_33_out ; +wire [0:0] direct_interc_340_out ; +wire [0:0] direct_interc_341_out ; +wire [0:0] direct_interc_342_out ; +wire [0:0] direct_interc_343_out ; +wire [0:0] direct_interc_344_out ; +wire [0:0] direct_interc_345_out ; +wire [0:0] direct_interc_346_out ; +wire [0:0] direct_interc_347_out ; +wire [0:0] direct_interc_348_out ; +wire [0:0] direct_interc_349_out ; +wire [0:0] direct_interc_34_out ; +wire [0:0] direct_interc_350_out ; +wire [0:0] direct_interc_351_out ; +wire [0:0] direct_interc_352_out ; +wire [0:0] direct_interc_353_out ; +wire [0:0] direct_interc_354_out ; +wire [0:0] direct_interc_355_out ; +wire [0:0] direct_interc_356_out ; +wire [0:0] direct_interc_357_out ; +wire [0:0] direct_interc_358_out ; +wire [0:0] direct_interc_359_out ; +wire [0:0] direct_interc_35_out ; +wire [0:0] direct_interc_360_out ; +wire [0:0] direct_interc_361_out ; +wire [0:0] direct_interc_362_out ; +wire [0:0] direct_interc_363_out ; +wire [0:0] direct_interc_364_out ; +wire [0:0] direct_interc_365_out ; +wire [0:0] direct_interc_366_out ; +wire [0:0] direct_interc_367_out ; +wire [0:0] direct_interc_368_out ; +wire [0:0] direct_interc_369_out ; +wire [0:0] direct_interc_36_out ; +wire [0:0] direct_interc_370_out ; +wire [0:0] direct_interc_371_out ; +wire [0:0] direct_interc_372_out ; +wire [0:0] direct_interc_373_out ; +wire [0:0] direct_interc_374_out ; +wire [0:0] direct_interc_375_out ; +wire [0:0] direct_interc_376_out ; +wire [0:0] direct_interc_377_out ; +wire [0:0] direct_interc_378_out ; +wire [0:0] direct_interc_379_out ; +wire [0:0] direct_interc_37_out ; +wire [0:0] direct_interc_380_out ; +wire [0:0] direct_interc_381_out ; +wire [0:0] direct_interc_382_out ; +wire [0:0] direct_interc_383_out ; +wire [0:0] direct_interc_384_out ; +wire [0:0] direct_interc_385_out ; +wire [0:0] direct_interc_386_out ; +wire [0:0] direct_interc_387_out ; +wire [0:0] direct_interc_388_out ; +wire [0:0] direct_interc_389_out ; +wire [0:0] direct_interc_38_out ; +wire [0:0] direct_interc_390_out ; +wire [0:0] direct_interc_391_out ; +wire [0:0] direct_interc_392_out ; +wire [0:0] direct_interc_393_out ; +wire [0:0] direct_interc_394_out ; +wire [0:0] direct_interc_395_out ; +wire [0:0] direct_interc_396_out ; +wire [0:0] direct_interc_397_out ; +wire [0:0] direct_interc_398_out ; +wire [0:0] direct_interc_399_out ; +wire [0:0] direct_interc_39_out ; +wire [0:0] direct_interc_3_out ; +wire [0:0] direct_interc_400_out ; +wire [0:0] direct_interc_401_out ; +wire [0:0] direct_interc_402_out ; +wire [0:0] direct_interc_403_out ; +wire [0:0] direct_interc_404_out ; +wire [0:0] direct_interc_405_out ; +wire [0:0] direct_interc_406_out ; +wire [0:0] direct_interc_40_out ; +wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_42_out ; +wire [0:0] direct_interc_43_out ; +wire [0:0] direct_interc_44_out ; +wire [0:0] direct_interc_45_out ; +wire [0:0] direct_interc_46_out ; +wire [0:0] direct_interc_47_out ; +wire [0:0] direct_interc_48_out ; +wire [0:0] direct_interc_49_out ; +wire [0:0] direct_interc_4_out ; +wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_51_out ; +wire [0:0] direct_interc_52_out ; +wire [0:0] direct_interc_53_out ; +wire [0:0] direct_interc_54_out ; +wire [0:0] direct_interc_55_out ; +wire [0:0] direct_interc_56_out ; +wire [0:0] direct_interc_57_out ; +wire [0:0] direct_interc_58_out ; +wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_60_out ; +wire [0:0] direct_interc_61_out ; +wire [0:0] direct_interc_62_out ; +wire [0:0] direct_interc_63_out ; +wire [0:0] direct_interc_64_out ; +wire [0:0] direct_interc_65_out ; +wire [0:0] direct_interc_66_out ; +wire [0:0] direct_interc_67_out ; +wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_69_out ; +wire [0:0] direct_interc_6_out ; +wire [0:0] direct_interc_70_out ; +wire [0:0] direct_interc_71_out ; +wire [0:0] direct_interc_72_out ; +wire [0:0] direct_interc_73_out ; +wire [0:0] direct_interc_74_out ; +wire [0:0] direct_interc_75_out ; +wire [0:0] direct_interc_76_out ; +wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_78_out ; +wire [0:0] direct_interc_79_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] direct_interc_80_out ; +wire [0:0] direct_interc_81_out ; +wire [0:0] direct_interc_82_out ; +wire [0:0] direct_interc_83_out ; +wire [0:0] direct_interc_84_out ; +wire [0:0] direct_interc_85_out ; +wire [0:0] direct_interc_86_out ; +wire [0:0] direct_interc_87_out ; +wire [0:0] direct_interc_88_out ; +wire [0:0] direct_interc_89_out ; +wire [0:0] direct_interc_8_out ; +wire [0:0] direct_interc_90_out ; +wire [0:0] direct_interc_91_out ; +wire [0:0] direct_interc_92_out ; +wire [0:0] direct_interc_93_out ; +wire [0:0] direct_interc_94_out ; +wire [0:0] direct_interc_95_out ; +wire [0:0] direct_interc_96_out ; +wire [0:0] direct_interc_97_out ; +wire [0:0] direct_interc_98_out ; +wire [0:0] direct_interc_99_out ; +wire [0:0] direct_interc_9_out ; +wire [0:0] grid_clb_0_ccff_tail ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_100_ccff_tail ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_101_ccff_tail ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_102_ccff_tail ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_103_ccff_tail ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_104_ccff_tail ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_105_ccff_tail ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_106_ccff_tail ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_107_ccff_tail ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_108_ccff_tail ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_109_ccff_tail ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_10_ccff_tail ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_110_ccff_tail ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_111_ccff_tail ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_112_ccff_tail ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_113_ccff_tail ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_114_ccff_tail ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_115_ccff_tail ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_116_ccff_tail ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_117_ccff_tail ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_118_ccff_tail ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_119_ccff_tail ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_11_ccff_tail ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_120_ccff_tail ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_121_ccff_tail ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_122_ccff_tail ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_123_ccff_tail ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_124_ccff_tail ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_125_ccff_tail ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_126_ccff_tail ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_127_ccff_tail ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_128_ccff_tail ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_129_ccff_tail ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_53_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_12_ccff_tail ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_130_ccff_tail ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_131_ccff_tail ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_132_ccff_tail ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_133_ccff_tail ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_134_ccff_tail ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_135_ccff_tail ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_136_ccff_tail ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_137_ccff_tail ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_138_ccff_tail ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_139_ccff_tail ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_13_ccff_tail ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_140_ccff_tail ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_141_ccff_tail ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_142_ccff_tail ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_143_ccff_tail ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_14_ccff_tail ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_15_ccff_tail ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_16_ccff_tail ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_17_ccff_tail ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_18_ccff_tail ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_19_ccff_tail ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_33_ ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_1_ccff_tail ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_20_ccff_tail ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_21_ccff_tail ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_22_ccff_tail ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_23_ccff_tail ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_24_ccff_tail ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_25_ccff_tail ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_26_ccff_tail ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_27_ccff_tail ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_28_ccff_tail ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_29_ccff_tail ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_2_ccff_tail ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_30_ccff_tail ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_31_ccff_tail ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_32_ccff_tail ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_33_ccff_tail ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_34_ccff_tail ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_35_ccff_tail ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_36_ccff_tail ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_37_ccff_tail ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_38_ccff_tail ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_39_ccff_tail ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_3_ccff_tail ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_40_ccff_tail ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_41_ccff_tail ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_42_ccff_tail ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_43_ccff_tail ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_44_ccff_tail ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_45_ccff_tail ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_46_ccff_tail ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_47_ccff_tail ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_48_ccff_tail ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_49_ccff_tail ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_4_ccff_tail ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_50_ccff_tail ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_51_ccff_tail ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_52_ccff_tail ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_53_ccff_tail ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_54_ccff_tail ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_55_ccff_tail ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_56_ccff_tail ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_57_ccff_tail ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_58_ccff_tail ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_59_ccff_tail ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_5_ccff_tail ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_60_ccff_tail ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_61_ccff_tail ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_62_ccff_tail ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_63_ccff_tail ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_64_ccff_tail ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_65_ccff_tail ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_66_ccff_tail ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_67_ccff_tail ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_68_ccff_tail ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_69_ccff_tail ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_6_ccff_tail ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_70_ccff_tail ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_71_ccff_tail ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_72_ccff_tail ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_73_ccff_tail ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_74_ccff_tail ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_75_ccff_tail ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_76_ccff_tail ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_77_ccff_tail ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_78_ccff_tail ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_79_ccff_tail ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_7_ccff_tail ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_80_ccff_tail ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_81_ccff_tail ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_82_ccff_tail ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_83_ccff_tail ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_84_ccff_tail ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_85_ccff_tail ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_86_ccff_tail ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_87_ccff_tail ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_88_ccff_tail ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_89_ccff_tail ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_8_ccff_tail ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_90_ccff_tail ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_91_ccff_tail ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_92_ccff_tail ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_93_ccff_tail ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_94_ccff_tail ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_95_ccff_tail ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_96_ccff_tail ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_97_ccff_tail ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_98_ccff_tail ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_99_ccff_tail ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_9_ccff_tail ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_10_ccff_tail ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_11_ccff_tail ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_2_ccff_tail ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_3_ccff_tail ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_4_ccff_tail ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_5_ccff_tail ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_6_ccff_tail ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_7_ccff_tail ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_8_ccff_tail ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_9_ccff_tail ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_left_0_ccff_tail ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_10_ccff_tail ; +wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_11_ccff_tail ; +wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_1_ccff_tail ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_2_ccff_tail ; +wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_3_ccff_tail ; +wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_4_ccff_tail ; +wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_5_ccff_tail ; +wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_6_ccff_tail ; +wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_7_ccff_tail ; +wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_8_ccff_tail ; +wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_9_ccff_tail ; +wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_0_ccff_tail ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_10_ccff_tail ; +wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_11_ccff_tail ; +wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_1_ccff_tail ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_2_ccff_tail ; +wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_3_ccff_tail ; +wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_4_ccff_tail ; +wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_5_ccff_tail ; +wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_6_ccff_tail ; +wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_7_ccff_tail ; +wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_8_ccff_tail ; +wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_9_ccff_tail ; +wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_ccff_tail ; +wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_10_ccff_tail ; +wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_11_ccff_tail ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_1_ccff_tail ; +wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_2_ccff_tail ; +wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_3_ccff_tail ; +wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_4_ccff_tail ; +wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_5_ccff_tail ; +wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_6_ccff_tail ; +wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_7_ccff_tail ; +wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_8_ccff_tail ; +wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_9_ccff_tail ; +wire [0:29] sb_0__0__0_chanx_right_out ; +wire [0:29] sb_0__0__0_chany_top_out ; +wire [0:0] sb_0__12__0_ccff_tail ; +wire [0:29] sb_0__12__0_chanx_right_out ; +wire [0:29] sb_0__12__0_chany_bottom_out ; +wire [0:0] sb_0__1__0_ccff_tail ; +wire [0:29] sb_0__1__0_chanx_right_out ; +wire [0:29] sb_0__1__0_chany_bottom_out ; +wire [0:29] sb_0__1__0_chany_top_out ; +wire [0:0] sb_0__1__10_ccff_tail ; +wire [0:29] sb_0__1__10_chanx_right_out ; +wire [0:29] sb_0__1__10_chany_bottom_out ; +wire [0:29] sb_0__1__10_chany_top_out ; +wire [0:0] sb_0__1__1_ccff_tail ; +wire [0:29] sb_0__1__1_chanx_right_out ; +wire [0:29] sb_0__1__1_chany_bottom_out ; +wire [0:29] sb_0__1__1_chany_top_out ; +wire [0:0] sb_0__1__2_ccff_tail ; +wire [0:29] sb_0__1__2_chanx_right_out ; +wire [0:29] sb_0__1__2_chany_bottom_out ; +wire [0:29] sb_0__1__2_chany_top_out ; +wire [0:0] sb_0__1__3_ccff_tail ; +wire [0:29] sb_0__1__3_chanx_right_out ; +wire [0:29] sb_0__1__3_chany_bottom_out ; +wire [0:29] sb_0__1__3_chany_top_out ; +wire [0:0] sb_0__1__4_ccff_tail ; +wire [0:29] sb_0__1__4_chanx_right_out ; +wire [0:29] sb_0__1__4_chany_bottom_out ; +wire [0:29] sb_0__1__4_chany_top_out ; +wire [0:0] sb_0__1__5_ccff_tail ; +wire [0:29] sb_0__1__5_chanx_right_out ; +wire [0:29] sb_0__1__5_chany_bottom_out ; +wire [0:29] sb_0__1__5_chany_top_out ; +wire [0:0] sb_0__1__6_ccff_tail ; +wire [0:29] sb_0__1__6_chanx_right_out ; +wire [0:29] sb_0__1__6_chany_bottom_out ; +wire [0:29] sb_0__1__6_chany_top_out ; +wire [0:0] sb_0__1__7_ccff_tail ; +wire [0:29] sb_0__1__7_chanx_right_out ; +wire [0:29] sb_0__1__7_chany_bottom_out ; +wire [0:29] sb_0__1__7_chany_top_out ; +wire [0:0] sb_0__1__8_ccff_tail ; +wire [0:29] sb_0__1__8_chanx_right_out ; +wire [0:29] sb_0__1__8_chany_bottom_out ; +wire [0:29] sb_0__1__8_chany_top_out ; +wire [0:0] sb_0__1__9_ccff_tail ; +wire [0:29] sb_0__1__9_chanx_right_out ; +wire [0:29] sb_0__1__9_chany_bottom_out ; +wire [0:29] sb_0__1__9_chany_top_out ; +wire [0:0] sb_12__0__0_ccff_tail ; +wire [0:29] sb_12__0__0_chanx_left_out ; +wire [0:29] sb_12__0__0_chany_top_out ; +wire [0:0] sb_12__12__0_ccff_tail ; +wire [0:29] sb_12__12__0_chanx_left_out ; +wire [0:29] sb_12__12__0_chany_bottom_out ; +wire [0:0] sb_12__1__0_ccff_tail ; +wire [0:29] sb_12__1__0_chanx_left_out ; +wire [0:29] sb_12__1__0_chany_bottom_out ; +wire [0:29] sb_12__1__0_chany_top_out ; +wire [0:0] sb_12__1__10_ccff_tail ; +wire [0:29] sb_12__1__10_chanx_left_out ; +wire [0:29] sb_12__1__10_chany_bottom_out ; +wire [0:29] sb_12__1__10_chany_top_out ; +wire [0:0] sb_12__1__1_ccff_tail ; +wire [0:29] sb_12__1__1_chanx_left_out ; +wire [0:29] sb_12__1__1_chany_bottom_out ; +wire [0:29] sb_12__1__1_chany_top_out ; +wire [0:0] sb_12__1__2_ccff_tail ; +wire [0:29] sb_12__1__2_chanx_left_out ; +wire [0:29] sb_12__1__2_chany_bottom_out ; +wire [0:29] sb_12__1__2_chany_top_out ; +wire [0:0] sb_12__1__3_ccff_tail ; +wire [0:29] sb_12__1__3_chanx_left_out ; +wire [0:29] sb_12__1__3_chany_bottom_out ; +wire [0:29] sb_12__1__3_chany_top_out ; +wire [0:0] sb_12__1__4_ccff_tail ; +wire [0:29] sb_12__1__4_chanx_left_out ; +wire [0:29] sb_12__1__4_chany_bottom_out ; +wire [0:29] sb_12__1__4_chany_top_out ; +wire [0:0] sb_12__1__5_ccff_tail ; +wire [0:29] sb_12__1__5_chanx_left_out ; +wire [0:29] sb_12__1__5_chany_bottom_out ; +wire [0:29] sb_12__1__5_chany_top_out ; +wire [0:0] sb_12__1__6_ccff_tail ; +wire [0:29] sb_12__1__6_chanx_left_out ; +wire [0:29] sb_12__1__6_chany_bottom_out ; +wire [0:29] sb_12__1__6_chany_top_out ; +wire [0:0] sb_12__1__7_ccff_tail ; +wire [0:29] sb_12__1__7_chanx_left_out ; +wire [0:29] sb_12__1__7_chany_bottom_out ; +wire [0:29] sb_12__1__7_chany_top_out ; +wire [0:0] sb_12__1__8_ccff_tail ; +wire [0:29] sb_12__1__8_chanx_left_out ; +wire [0:29] sb_12__1__8_chany_bottom_out ; +wire [0:29] sb_12__1__8_chany_top_out ; +wire [0:0] sb_12__1__9_ccff_tail ; +wire [0:29] sb_12__1__9_chanx_left_out ; +wire [0:29] sb_12__1__9_chany_bottom_out ; +wire [0:29] sb_12__1__9_chany_top_out ; +wire [0:0] sb_1__0__0_ccff_tail ; +wire [0:29] sb_1__0__0_chanx_left_out ; +wire [0:29] sb_1__0__0_chanx_right_out ; +wire [0:29] sb_1__0__0_chany_top_out ; +wire [0:0] sb_1__0__10_ccff_tail ; +wire [0:29] sb_1__0__10_chanx_left_out ; +wire [0:29] sb_1__0__10_chanx_right_out ; +wire [0:29] sb_1__0__10_chany_top_out ; +wire [0:0] sb_1__0__1_ccff_tail ; +wire [0:29] sb_1__0__1_chanx_left_out ; +wire [0:29] sb_1__0__1_chanx_right_out ; +wire [0:29] sb_1__0__1_chany_top_out ; +wire [0:0] sb_1__0__2_ccff_tail ; +wire [0:29] sb_1__0__2_chanx_left_out ; +wire [0:29] sb_1__0__2_chanx_right_out ; +wire [0:29] sb_1__0__2_chany_top_out ; +wire [0:0] sb_1__0__3_ccff_tail ; +wire [0:29] sb_1__0__3_chanx_left_out ; +wire [0:29] sb_1__0__3_chanx_right_out ; +wire [0:29] sb_1__0__3_chany_top_out ; +wire [0:0] sb_1__0__4_ccff_tail ; +wire [0:29] sb_1__0__4_chanx_left_out ; +wire [0:29] sb_1__0__4_chanx_right_out ; +wire [0:29] sb_1__0__4_chany_top_out ; +wire [0:0] sb_1__0__5_ccff_tail ; +wire [0:29] sb_1__0__5_chanx_left_out ; +wire [0:29] sb_1__0__5_chanx_right_out ; +wire [0:29] sb_1__0__5_chany_top_out ; +wire [0:0] sb_1__0__6_ccff_tail ; +wire [0:29] sb_1__0__6_chanx_left_out ; +wire [0:29] sb_1__0__6_chanx_right_out ; +wire [0:29] sb_1__0__6_chany_top_out ; +wire [0:0] sb_1__0__7_ccff_tail ; +wire [0:29] sb_1__0__7_chanx_left_out ; +wire [0:29] sb_1__0__7_chanx_right_out ; +wire [0:29] sb_1__0__7_chany_top_out ; +wire [0:0] sb_1__0__8_ccff_tail ; +wire [0:29] sb_1__0__8_chanx_left_out ; +wire [0:29] sb_1__0__8_chanx_right_out ; +wire [0:29] sb_1__0__8_chany_top_out ; +wire [0:0] sb_1__0__9_ccff_tail ; +wire [0:29] sb_1__0__9_chanx_left_out ; +wire [0:29] sb_1__0__9_chanx_right_out ; +wire [0:29] sb_1__0__9_chany_top_out ; +wire [0:0] sb_1__12__0_ccff_tail ; +wire [0:29] sb_1__12__0_chanx_left_out ; +wire [0:29] sb_1__12__0_chanx_right_out ; +wire [0:29] sb_1__12__0_chany_bottom_out ; +wire [0:0] sb_1__12__10_ccff_tail ; +wire [0:29] sb_1__12__10_chanx_left_out ; +wire [0:29] sb_1__12__10_chanx_right_out ; +wire [0:29] sb_1__12__10_chany_bottom_out ; +wire [0:0] sb_1__12__1_ccff_tail ; +wire [0:29] sb_1__12__1_chanx_left_out ; +wire [0:29] sb_1__12__1_chanx_right_out ; +wire [0:29] sb_1__12__1_chany_bottom_out ; +wire [0:0] sb_1__12__2_ccff_tail ; +wire [0:29] sb_1__12__2_chanx_left_out ; +wire [0:29] sb_1__12__2_chanx_right_out ; +wire [0:29] sb_1__12__2_chany_bottom_out ; +wire [0:0] sb_1__12__3_ccff_tail ; +wire [0:29] sb_1__12__3_chanx_left_out ; +wire [0:29] sb_1__12__3_chanx_right_out ; +wire [0:29] sb_1__12__3_chany_bottom_out ; +wire [0:0] sb_1__12__4_ccff_tail ; +wire [0:29] sb_1__12__4_chanx_left_out ; +wire [0:29] sb_1__12__4_chanx_right_out ; +wire [0:29] sb_1__12__4_chany_bottom_out ; +wire [0:0] sb_1__12__5_ccff_tail ; +wire [0:29] sb_1__12__5_chanx_left_out ; +wire [0:29] sb_1__12__5_chanx_right_out ; +wire [0:29] sb_1__12__5_chany_bottom_out ; +wire [0:0] sb_1__12__6_ccff_tail ; +wire [0:29] sb_1__12__6_chanx_left_out ; +wire [0:29] sb_1__12__6_chanx_right_out ; +wire [0:29] sb_1__12__6_chany_bottom_out ; +wire [0:0] sb_1__12__7_ccff_tail ; +wire [0:29] sb_1__12__7_chanx_left_out ; +wire [0:29] sb_1__12__7_chanx_right_out ; +wire [0:29] sb_1__12__7_chany_bottom_out ; +wire [0:0] sb_1__12__8_ccff_tail ; +wire [0:29] sb_1__12__8_chanx_left_out ; +wire [0:29] sb_1__12__8_chanx_right_out ; +wire [0:29] sb_1__12__8_chany_bottom_out ; +wire [0:0] sb_1__12__9_ccff_tail ; +wire [0:29] sb_1__12__9_chanx_left_out ; +wire [0:29] sb_1__12__9_chanx_right_out ; +wire [0:29] sb_1__12__9_chany_bottom_out ; +wire [0:0] sb_1__1__0_ccff_tail ; +wire [0:29] sb_1__1__0_chanx_left_out ; +wire [0:29] sb_1__1__0_chanx_right_out ; +wire [0:29] sb_1__1__0_chany_bottom_out ; +wire [0:29] sb_1__1__0_chany_top_out ; +wire [0:0] sb_1__1__100_ccff_tail ; +wire [0:29] sb_1__1__100_chanx_left_out ; +wire [0:29] sb_1__1__100_chanx_right_out ; +wire [0:29] sb_1__1__100_chany_bottom_out ; +wire [0:29] sb_1__1__100_chany_top_out ; +wire [0:0] sb_1__1__101_ccff_tail ; +wire [0:29] sb_1__1__101_chanx_left_out ; +wire [0:29] sb_1__1__101_chanx_right_out ; +wire [0:29] sb_1__1__101_chany_bottom_out ; +wire [0:29] sb_1__1__101_chany_top_out ; +wire [0:0] sb_1__1__102_ccff_tail ; +wire [0:29] sb_1__1__102_chanx_left_out ; +wire [0:29] sb_1__1__102_chanx_right_out ; +wire [0:29] sb_1__1__102_chany_bottom_out ; +wire [0:29] sb_1__1__102_chany_top_out ; +wire [0:0] sb_1__1__103_ccff_tail ; +wire [0:29] sb_1__1__103_chanx_left_out ; +wire [0:29] sb_1__1__103_chanx_right_out ; +wire [0:29] sb_1__1__103_chany_bottom_out ; +wire [0:29] sb_1__1__103_chany_top_out ; +wire [0:0] sb_1__1__104_ccff_tail ; +wire [0:29] sb_1__1__104_chanx_left_out ; +wire [0:29] sb_1__1__104_chanx_right_out ; +wire [0:29] sb_1__1__104_chany_bottom_out ; +wire [0:29] sb_1__1__104_chany_top_out ; +wire [0:0] sb_1__1__105_ccff_tail ; +wire [0:29] sb_1__1__105_chanx_left_out ; +wire [0:29] sb_1__1__105_chanx_right_out ; +wire [0:29] sb_1__1__105_chany_bottom_out ; +wire [0:29] sb_1__1__105_chany_top_out ; +wire [0:0] sb_1__1__106_ccff_tail ; +wire [0:29] sb_1__1__106_chanx_left_out ; +wire [0:29] sb_1__1__106_chanx_right_out ; +wire [0:29] sb_1__1__106_chany_bottom_out ; +wire [0:29] sb_1__1__106_chany_top_out ; +wire [0:0] sb_1__1__107_ccff_tail ; +wire [0:29] sb_1__1__107_chanx_left_out ; +wire [0:29] sb_1__1__107_chanx_right_out ; +wire [0:29] sb_1__1__107_chany_bottom_out ; +wire [0:29] sb_1__1__107_chany_top_out ; +wire [0:0] sb_1__1__108_ccff_tail ; +wire [0:29] sb_1__1__108_chanx_left_out ; +wire [0:29] sb_1__1__108_chanx_right_out ; +wire [0:29] sb_1__1__108_chany_bottom_out ; +wire [0:29] sb_1__1__108_chany_top_out ; +wire [0:0] sb_1__1__109_ccff_tail ; +wire [0:29] sb_1__1__109_chanx_left_out ; +wire [0:29] sb_1__1__109_chanx_right_out ; +wire [0:29] sb_1__1__109_chany_bottom_out ; +wire [0:29] sb_1__1__109_chany_top_out ; +wire [0:0] sb_1__1__10_ccff_tail ; +wire [0:29] sb_1__1__10_chanx_left_out ; +wire [0:29] sb_1__1__10_chanx_right_out ; +wire [0:29] sb_1__1__10_chany_bottom_out ; +wire [0:29] sb_1__1__10_chany_top_out ; +wire [0:0] sb_1__1__110_ccff_tail ; +wire [0:29] sb_1__1__110_chanx_left_out ; +wire [0:29] sb_1__1__110_chanx_right_out ; +wire [0:29] sb_1__1__110_chany_bottom_out ; +wire [0:29] sb_1__1__110_chany_top_out ; +wire [0:0] sb_1__1__111_ccff_tail ; +wire [0:29] sb_1__1__111_chanx_left_out ; +wire [0:29] sb_1__1__111_chanx_right_out ; +wire [0:29] sb_1__1__111_chany_bottom_out ; +wire [0:29] sb_1__1__111_chany_top_out ; +wire [0:0] sb_1__1__112_ccff_tail ; +wire [0:29] sb_1__1__112_chanx_left_out ; +wire [0:29] sb_1__1__112_chanx_right_out ; +wire [0:29] sb_1__1__112_chany_bottom_out ; +wire [0:29] sb_1__1__112_chany_top_out ; +wire [0:0] sb_1__1__113_ccff_tail ; +wire [0:29] sb_1__1__113_chanx_left_out ; +wire [0:29] sb_1__1__113_chanx_right_out ; +wire [0:29] sb_1__1__113_chany_bottom_out ; +wire [0:29] sb_1__1__113_chany_top_out ; +wire [0:0] sb_1__1__114_ccff_tail ; +wire [0:29] sb_1__1__114_chanx_left_out ; +wire [0:29] sb_1__1__114_chanx_right_out ; +wire [0:29] sb_1__1__114_chany_bottom_out ; +wire [0:29] sb_1__1__114_chany_top_out ; +wire [0:0] sb_1__1__115_ccff_tail ; +wire [0:29] sb_1__1__115_chanx_left_out ; +wire [0:29] sb_1__1__115_chanx_right_out ; +wire [0:29] sb_1__1__115_chany_bottom_out ; +wire [0:29] sb_1__1__115_chany_top_out ; +wire [0:0] sb_1__1__116_ccff_tail ; +wire [0:29] sb_1__1__116_chanx_left_out ; +wire [0:29] sb_1__1__116_chanx_right_out ; +wire [0:29] sb_1__1__116_chany_bottom_out ; +wire [0:29] sb_1__1__116_chany_top_out ; +wire [0:0] sb_1__1__117_ccff_tail ; +wire [0:29] sb_1__1__117_chanx_left_out ; +wire [0:29] sb_1__1__117_chanx_right_out ; +wire [0:29] sb_1__1__117_chany_bottom_out ; +wire [0:29] sb_1__1__117_chany_top_out ; +wire [0:0] sb_1__1__118_ccff_tail ; +wire [0:29] sb_1__1__118_chanx_left_out ; +wire [0:29] sb_1__1__118_chanx_right_out ; +wire [0:29] sb_1__1__118_chany_bottom_out ; +wire [0:29] sb_1__1__118_chany_top_out ; +wire [0:0] sb_1__1__119_ccff_tail ; +wire [0:29] sb_1__1__119_chanx_left_out ; +wire [0:29] sb_1__1__119_chanx_right_out ; +wire [0:29] sb_1__1__119_chany_bottom_out ; +wire [0:29] sb_1__1__119_chany_top_out ; +wire [0:0] sb_1__1__11_ccff_tail ; +wire [0:29] sb_1__1__11_chanx_left_out ; +wire [0:29] sb_1__1__11_chanx_right_out ; +wire [0:29] sb_1__1__11_chany_bottom_out ; +wire [0:29] sb_1__1__11_chany_top_out ; +wire [0:0] sb_1__1__120_ccff_tail ; +wire [0:29] sb_1__1__120_chanx_left_out ; +wire [0:29] sb_1__1__120_chanx_right_out ; +wire [0:29] sb_1__1__120_chany_bottom_out ; +wire [0:29] sb_1__1__120_chany_top_out ; +wire [0:0] sb_1__1__12_ccff_tail ; +wire [0:29] sb_1__1__12_chanx_left_out ; +wire [0:29] sb_1__1__12_chanx_right_out ; +wire [0:29] sb_1__1__12_chany_bottom_out ; +wire [0:29] sb_1__1__12_chany_top_out ; +wire [0:0] sb_1__1__13_ccff_tail ; +wire [0:29] sb_1__1__13_chanx_left_out ; +wire [0:29] sb_1__1__13_chanx_right_out ; +wire [0:29] sb_1__1__13_chany_bottom_out ; +wire [0:29] sb_1__1__13_chany_top_out ; +wire [0:0] sb_1__1__14_ccff_tail ; +wire [0:29] sb_1__1__14_chanx_left_out ; +wire [0:29] sb_1__1__14_chanx_right_out ; +wire [0:29] sb_1__1__14_chany_bottom_out ; +wire [0:29] sb_1__1__14_chany_top_out ; +wire [0:0] sb_1__1__15_ccff_tail ; +wire [0:29] sb_1__1__15_chanx_left_out ; +wire [0:29] sb_1__1__15_chanx_right_out ; +wire [0:29] sb_1__1__15_chany_bottom_out ; +wire [0:29] sb_1__1__15_chany_top_out ; +wire [0:0] sb_1__1__16_ccff_tail ; +wire [0:29] sb_1__1__16_chanx_left_out ; +wire [0:29] sb_1__1__16_chanx_right_out ; +wire [0:29] sb_1__1__16_chany_bottom_out ; +wire [0:29] sb_1__1__16_chany_top_out ; +wire [0:0] sb_1__1__17_ccff_tail ; +wire [0:29] sb_1__1__17_chanx_left_out ; +wire [0:29] sb_1__1__17_chanx_right_out ; +wire [0:29] sb_1__1__17_chany_bottom_out ; +wire [0:29] sb_1__1__17_chany_top_out ; +wire [0:0] sb_1__1__18_ccff_tail ; +wire [0:29] sb_1__1__18_chanx_left_out ; +wire [0:29] sb_1__1__18_chanx_right_out ; +wire [0:29] sb_1__1__18_chany_bottom_out ; +wire [0:29] sb_1__1__18_chany_top_out ; +wire [0:0] sb_1__1__19_ccff_tail ; +wire [0:29] sb_1__1__19_chanx_left_out ; +wire [0:29] sb_1__1__19_chanx_right_out ; +wire [0:29] sb_1__1__19_chany_bottom_out ; +wire [0:29] sb_1__1__19_chany_top_out ; +wire [0:0] sb_1__1__1_ccff_tail ; +wire [0:29] sb_1__1__1_chanx_left_out ; +wire [0:29] sb_1__1__1_chanx_right_out ; +wire [0:29] sb_1__1__1_chany_bottom_out ; +wire [0:29] sb_1__1__1_chany_top_out ; +wire [0:0] sb_1__1__20_ccff_tail ; +wire [0:29] sb_1__1__20_chanx_left_out ; +wire [0:29] sb_1__1__20_chanx_right_out ; +wire [0:29] sb_1__1__20_chany_bottom_out ; +wire [0:29] sb_1__1__20_chany_top_out ; +wire [0:0] sb_1__1__21_ccff_tail ; +wire [0:29] sb_1__1__21_chanx_left_out ; +wire [0:29] sb_1__1__21_chanx_right_out ; +wire [0:29] sb_1__1__21_chany_bottom_out ; +wire [0:29] sb_1__1__21_chany_top_out ; +wire [0:0] sb_1__1__22_ccff_tail ; +wire [0:29] sb_1__1__22_chanx_left_out ; +wire [0:29] sb_1__1__22_chanx_right_out ; +wire [0:29] sb_1__1__22_chany_bottom_out ; +wire [0:29] sb_1__1__22_chany_top_out ; +wire [0:0] sb_1__1__23_ccff_tail ; +wire [0:29] sb_1__1__23_chanx_left_out ; +wire [0:29] sb_1__1__23_chanx_right_out ; +wire [0:29] sb_1__1__23_chany_bottom_out ; +wire [0:29] sb_1__1__23_chany_top_out ; +wire [0:0] sb_1__1__24_ccff_tail ; +wire [0:29] sb_1__1__24_chanx_left_out ; +wire [0:29] sb_1__1__24_chanx_right_out ; +wire [0:29] sb_1__1__24_chany_bottom_out ; +wire [0:29] sb_1__1__24_chany_top_out ; +wire [0:0] sb_1__1__25_ccff_tail ; +wire [0:29] sb_1__1__25_chanx_left_out ; +wire [0:29] sb_1__1__25_chanx_right_out ; +wire [0:29] sb_1__1__25_chany_bottom_out ; +wire [0:29] sb_1__1__25_chany_top_out ; +wire [0:0] sb_1__1__26_ccff_tail ; +wire [0:29] sb_1__1__26_chanx_left_out ; +wire [0:29] sb_1__1__26_chanx_right_out ; +wire [0:29] sb_1__1__26_chany_bottom_out ; +wire [0:29] sb_1__1__26_chany_top_out ; +wire [0:0] sb_1__1__27_ccff_tail ; +wire [0:29] sb_1__1__27_chanx_left_out ; +wire [0:29] sb_1__1__27_chanx_right_out ; +wire [0:29] sb_1__1__27_chany_bottom_out ; +wire [0:29] sb_1__1__27_chany_top_out ; +wire [0:0] sb_1__1__28_ccff_tail ; +wire [0:29] sb_1__1__28_chanx_left_out ; +wire [0:29] sb_1__1__28_chanx_right_out ; +wire [0:29] sb_1__1__28_chany_bottom_out ; +wire [0:29] sb_1__1__28_chany_top_out ; +wire [0:0] sb_1__1__29_ccff_tail ; +wire [0:29] sb_1__1__29_chanx_left_out ; +wire [0:29] sb_1__1__29_chanx_right_out ; +wire [0:29] sb_1__1__29_chany_bottom_out ; +wire [0:29] sb_1__1__29_chany_top_out ; +wire [0:0] sb_1__1__2_ccff_tail ; +wire [0:29] sb_1__1__2_chanx_left_out ; +wire [0:29] sb_1__1__2_chanx_right_out ; +wire [0:29] sb_1__1__2_chany_bottom_out ; +wire [0:29] sb_1__1__2_chany_top_out ; +wire [0:0] sb_1__1__30_ccff_tail ; +wire [0:29] sb_1__1__30_chanx_left_out ; +wire [0:29] sb_1__1__30_chanx_right_out ; +wire [0:29] sb_1__1__30_chany_bottom_out ; +wire [0:29] sb_1__1__30_chany_top_out ; +wire [0:0] sb_1__1__31_ccff_tail ; +wire [0:29] sb_1__1__31_chanx_left_out ; +wire [0:29] sb_1__1__31_chanx_right_out ; +wire [0:29] sb_1__1__31_chany_bottom_out ; +wire [0:29] sb_1__1__31_chany_top_out ; +wire [0:0] sb_1__1__32_ccff_tail ; +wire [0:29] sb_1__1__32_chanx_left_out ; +wire [0:29] sb_1__1__32_chanx_right_out ; +wire [0:29] sb_1__1__32_chany_bottom_out ; +wire [0:29] sb_1__1__32_chany_top_out ; +wire [0:0] sb_1__1__33_ccff_tail ; +wire [0:29] sb_1__1__33_chanx_left_out ; +wire [0:29] sb_1__1__33_chanx_right_out ; +wire [0:29] sb_1__1__33_chany_bottom_out ; +wire [0:29] sb_1__1__33_chany_top_out ; +wire [0:0] sb_1__1__34_ccff_tail ; +wire [0:29] sb_1__1__34_chanx_left_out ; +wire [0:29] sb_1__1__34_chanx_right_out ; +wire [0:29] sb_1__1__34_chany_bottom_out ; +wire [0:29] sb_1__1__34_chany_top_out ; +wire [0:0] sb_1__1__35_ccff_tail ; +wire [0:29] sb_1__1__35_chanx_left_out ; +wire [0:29] sb_1__1__35_chanx_right_out ; +wire [0:29] sb_1__1__35_chany_bottom_out ; +wire [0:29] sb_1__1__35_chany_top_out ; +wire [0:0] sb_1__1__36_ccff_tail ; +wire [0:29] sb_1__1__36_chanx_left_out ; +wire [0:29] sb_1__1__36_chanx_right_out ; +wire [0:29] sb_1__1__36_chany_bottom_out ; +wire [0:29] sb_1__1__36_chany_top_out ; +wire [0:0] sb_1__1__37_ccff_tail ; +wire [0:29] sb_1__1__37_chanx_left_out ; +wire [0:29] sb_1__1__37_chanx_right_out ; +wire [0:29] sb_1__1__37_chany_bottom_out ; +wire [0:29] sb_1__1__37_chany_top_out ; +wire [0:0] sb_1__1__38_ccff_tail ; +wire [0:29] sb_1__1__38_chanx_left_out ; +wire [0:29] sb_1__1__38_chanx_right_out ; +wire [0:29] sb_1__1__38_chany_bottom_out ; +wire [0:29] sb_1__1__38_chany_top_out ; +wire [0:0] sb_1__1__39_ccff_tail ; +wire [0:29] sb_1__1__39_chanx_left_out ; +wire [0:29] sb_1__1__39_chanx_right_out ; +wire [0:29] sb_1__1__39_chany_bottom_out ; +wire [0:29] sb_1__1__39_chany_top_out ; +wire [0:0] sb_1__1__3_ccff_tail ; +wire [0:29] sb_1__1__3_chanx_left_out ; +wire [0:29] sb_1__1__3_chanx_right_out ; +wire [0:29] sb_1__1__3_chany_bottom_out ; +wire [0:29] sb_1__1__3_chany_top_out ; +wire [0:0] sb_1__1__40_ccff_tail ; +wire [0:29] sb_1__1__40_chanx_left_out ; +wire [0:29] sb_1__1__40_chanx_right_out ; +wire [0:29] sb_1__1__40_chany_bottom_out ; +wire [0:29] sb_1__1__40_chany_top_out ; +wire [0:0] sb_1__1__41_ccff_tail ; +wire [0:29] sb_1__1__41_chanx_left_out ; +wire [0:29] sb_1__1__41_chanx_right_out ; +wire [0:29] sb_1__1__41_chany_bottom_out ; +wire [0:29] sb_1__1__41_chany_top_out ; +wire [0:0] sb_1__1__42_ccff_tail ; +wire [0:29] sb_1__1__42_chanx_left_out ; +wire [0:29] sb_1__1__42_chanx_right_out ; +wire [0:29] sb_1__1__42_chany_bottom_out ; +wire [0:29] sb_1__1__42_chany_top_out ; +wire [0:0] sb_1__1__43_ccff_tail ; +wire [0:29] sb_1__1__43_chanx_left_out ; +wire [0:29] sb_1__1__43_chanx_right_out ; +wire [0:29] sb_1__1__43_chany_bottom_out ; +wire [0:29] sb_1__1__43_chany_top_out ; +wire [0:0] sb_1__1__44_ccff_tail ; +wire [0:29] sb_1__1__44_chanx_left_out ; +wire [0:29] sb_1__1__44_chanx_right_out ; +wire [0:29] sb_1__1__44_chany_bottom_out ; +wire [0:29] sb_1__1__44_chany_top_out ; +wire [0:0] sb_1__1__45_ccff_tail ; +wire [0:29] sb_1__1__45_chanx_left_out ; +wire [0:29] sb_1__1__45_chanx_right_out ; +wire [0:29] sb_1__1__45_chany_bottom_out ; +wire [0:29] sb_1__1__45_chany_top_out ; +wire [0:0] sb_1__1__46_ccff_tail ; +wire [0:29] sb_1__1__46_chanx_left_out ; +wire [0:29] sb_1__1__46_chanx_right_out ; +wire [0:29] sb_1__1__46_chany_bottom_out ; +wire [0:29] sb_1__1__46_chany_top_out ; +wire [0:0] sb_1__1__47_ccff_tail ; +wire [0:29] sb_1__1__47_chanx_left_out ; +wire [0:29] sb_1__1__47_chanx_right_out ; +wire [0:29] sb_1__1__47_chany_bottom_out ; +wire [0:29] sb_1__1__47_chany_top_out ; +wire [0:0] sb_1__1__48_ccff_tail ; +wire [0:29] sb_1__1__48_chanx_left_out ; +wire [0:29] sb_1__1__48_chanx_right_out ; +wire [0:29] sb_1__1__48_chany_bottom_out ; +wire [0:29] sb_1__1__48_chany_top_out ; +wire [0:0] sb_1__1__49_ccff_tail ; +wire [0:29] sb_1__1__49_chanx_left_out ; +wire [0:29] sb_1__1__49_chanx_right_out ; +wire [0:29] sb_1__1__49_chany_bottom_out ; +wire [0:29] sb_1__1__49_chany_top_out ; +wire [0:0] sb_1__1__4_ccff_tail ; +wire [0:29] sb_1__1__4_chanx_left_out ; +wire [0:29] sb_1__1__4_chanx_right_out ; +wire [0:29] sb_1__1__4_chany_bottom_out ; +wire [0:29] sb_1__1__4_chany_top_out ; +wire [0:0] sb_1__1__50_ccff_tail ; +wire [0:29] sb_1__1__50_chanx_left_out ; +wire [0:29] sb_1__1__50_chanx_right_out ; +wire [0:29] sb_1__1__50_chany_bottom_out ; +wire [0:29] sb_1__1__50_chany_top_out ; +wire [0:0] sb_1__1__51_ccff_tail ; +wire [0:29] sb_1__1__51_chanx_left_out ; +wire [0:29] sb_1__1__51_chanx_right_out ; +wire [0:29] sb_1__1__51_chany_bottom_out ; +wire [0:29] sb_1__1__51_chany_top_out ; +wire [0:0] sb_1__1__52_ccff_tail ; +wire [0:29] sb_1__1__52_chanx_left_out ; +wire [0:29] sb_1__1__52_chanx_right_out ; +wire [0:29] sb_1__1__52_chany_bottom_out ; +wire [0:29] sb_1__1__52_chany_top_out ; +wire [0:0] sb_1__1__53_ccff_tail ; +wire [0:29] sb_1__1__53_chanx_left_out ; +wire [0:29] sb_1__1__53_chanx_right_out ; +wire [0:29] sb_1__1__53_chany_bottom_out ; +wire [0:29] sb_1__1__53_chany_top_out ; +wire [0:0] sb_1__1__54_ccff_tail ; +wire [0:29] sb_1__1__54_chanx_left_out ; +wire [0:29] sb_1__1__54_chanx_right_out ; +wire [0:29] sb_1__1__54_chany_bottom_out ; +wire [0:29] sb_1__1__54_chany_top_out ; +wire [0:0] sb_1__1__55_ccff_tail ; +wire [0:29] sb_1__1__55_chanx_left_out ; +wire [0:29] sb_1__1__55_chanx_right_out ; +wire [0:29] sb_1__1__55_chany_bottom_out ; +wire [0:29] sb_1__1__55_chany_top_out ; +wire [0:0] sb_1__1__56_ccff_tail ; +wire [0:29] sb_1__1__56_chanx_left_out ; +wire [0:29] sb_1__1__56_chanx_right_out ; +wire [0:29] sb_1__1__56_chany_bottom_out ; +wire [0:29] sb_1__1__56_chany_top_out ; +wire [0:0] sb_1__1__57_ccff_tail ; +wire [0:29] sb_1__1__57_chanx_left_out ; +wire [0:29] sb_1__1__57_chanx_right_out ; +wire [0:29] sb_1__1__57_chany_bottom_out ; +wire [0:29] sb_1__1__57_chany_top_out ; +wire [0:0] sb_1__1__58_ccff_tail ; +wire [0:29] sb_1__1__58_chanx_left_out ; +wire [0:29] sb_1__1__58_chanx_right_out ; +wire [0:29] sb_1__1__58_chany_bottom_out ; +wire [0:29] sb_1__1__58_chany_top_out ; +wire [0:0] sb_1__1__59_ccff_tail ; +wire [0:29] sb_1__1__59_chanx_left_out ; +wire [0:29] sb_1__1__59_chanx_right_out ; +wire [0:29] sb_1__1__59_chany_bottom_out ; +wire [0:29] sb_1__1__59_chany_top_out ; +wire [0:0] sb_1__1__5_ccff_tail ; +wire [0:29] sb_1__1__5_chanx_left_out ; +wire [0:29] sb_1__1__5_chanx_right_out ; +wire [0:29] sb_1__1__5_chany_bottom_out ; +wire [0:29] sb_1__1__5_chany_top_out ; +wire [0:0] sb_1__1__60_ccff_tail ; +wire [0:29] sb_1__1__60_chanx_left_out ; +wire [0:29] sb_1__1__60_chanx_right_out ; +wire [0:29] sb_1__1__60_chany_bottom_out ; +wire [0:29] sb_1__1__60_chany_top_out ; +wire [0:0] sb_1__1__61_ccff_tail ; +wire [0:29] sb_1__1__61_chanx_left_out ; +wire [0:29] sb_1__1__61_chanx_right_out ; +wire [0:29] sb_1__1__61_chany_bottom_out ; +wire [0:29] sb_1__1__61_chany_top_out ; +wire [0:0] sb_1__1__62_ccff_tail ; +wire [0:29] sb_1__1__62_chanx_left_out ; +wire [0:29] sb_1__1__62_chanx_right_out ; +wire [0:29] sb_1__1__62_chany_bottom_out ; +wire [0:29] sb_1__1__62_chany_top_out ; +wire [0:0] sb_1__1__63_ccff_tail ; +wire [0:29] sb_1__1__63_chanx_left_out ; +wire [0:29] sb_1__1__63_chanx_right_out ; +wire [0:29] sb_1__1__63_chany_bottom_out ; +wire [0:29] sb_1__1__63_chany_top_out ; +wire [0:0] sb_1__1__64_ccff_tail ; +wire [0:29] sb_1__1__64_chanx_left_out ; +wire [0:29] sb_1__1__64_chanx_right_out ; +wire [0:29] sb_1__1__64_chany_bottom_out ; +wire [0:29] sb_1__1__64_chany_top_out ; +wire [0:0] sb_1__1__65_ccff_tail ; +wire [0:29] sb_1__1__65_chanx_left_out ; +wire [0:29] sb_1__1__65_chanx_right_out ; +wire [0:29] sb_1__1__65_chany_bottom_out ; +wire [0:29] sb_1__1__65_chany_top_out ; +wire [0:0] sb_1__1__66_ccff_tail ; +wire [0:29] sb_1__1__66_chanx_left_out ; +wire [0:29] sb_1__1__66_chanx_right_out ; +wire [0:29] sb_1__1__66_chany_bottom_out ; +wire [0:29] sb_1__1__66_chany_top_out ; +wire [0:0] sb_1__1__67_ccff_tail ; +wire [0:29] sb_1__1__67_chanx_left_out ; +wire [0:29] sb_1__1__67_chanx_right_out ; +wire [0:29] sb_1__1__67_chany_bottom_out ; +wire [0:29] sb_1__1__67_chany_top_out ; +wire [0:0] sb_1__1__68_ccff_tail ; +wire [0:29] sb_1__1__68_chanx_left_out ; +wire [0:29] sb_1__1__68_chanx_right_out ; +wire [0:29] sb_1__1__68_chany_bottom_out ; +wire [0:29] sb_1__1__68_chany_top_out ; +wire [0:0] sb_1__1__69_ccff_tail ; +wire [0:29] sb_1__1__69_chanx_left_out ; +wire [0:29] sb_1__1__69_chanx_right_out ; +wire [0:29] sb_1__1__69_chany_bottom_out ; +wire [0:29] sb_1__1__69_chany_top_out ; +wire [0:0] sb_1__1__6_ccff_tail ; +wire [0:29] sb_1__1__6_chanx_left_out ; +wire [0:29] sb_1__1__6_chanx_right_out ; +wire [0:29] sb_1__1__6_chany_bottom_out ; +wire [0:29] sb_1__1__6_chany_top_out ; +wire [0:0] sb_1__1__70_ccff_tail ; +wire [0:29] sb_1__1__70_chanx_left_out ; +wire [0:29] sb_1__1__70_chanx_right_out ; +wire [0:29] sb_1__1__70_chany_bottom_out ; +wire [0:29] sb_1__1__70_chany_top_out ; +wire [0:0] sb_1__1__71_ccff_tail ; +wire [0:29] sb_1__1__71_chanx_left_out ; +wire [0:29] sb_1__1__71_chanx_right_out ; +wire [0:29] sb_1__1__71_chany_bottom_out ; +wire [0:29] sb_1__1__71_chany_top_out ; +wire [0:0] sb_1__1__72_ccff_tail ; +wire [0:29] sb_1__1__72_chanx_left_out ; +wire [0:29] sb_1__1__72_chanx_right_out ; +wire [0:29] sb_1__1__72_chany_bottom_out ; +wire [0:29] sb_1__1__72_chany_top_out ; +wire [0:0] sb_1__1__73_ccff_tail ; +wire [0:29] sb_1__1__73_chanx_left_out ; +wire [0:29] sb_1__1__73_chanx_right_out ; +wire [0:29] sb_1__1__73_chany_bottom_out ; +wire [0:29] sb_1__1__73_chany_top_out ; +wire [0:0] sb_1__1__74_ccff_tail ; +wire [0:29] sb_1__1__74_chanx_left_out ; +wire [0:29] sb_1__1__74_chanx_right_out ; +wire [0:29] sb_1__1__74_chany_bottom_out ; +wire [0:29] sb_1__1__74_chany_top_out ; +wire [0:0] sb_1__1__75_ccff_tail ; +wire [0:29] sb_1__1__75_chanx_left_out ; +wire [0:29] sb_1__1__75_chanx_right_out ; +wire [0:29] sb_1__1__75_chany_bottom_out ; +wire [0:29] sb_1__1__75_chany_top_out ; +wire [0:0] sb_1__1__76_ccff_tail ; +wire [0:29] sb_1__1__76_chanx_left_out ; +wire [0:29] sb_1__1__76_chanx_right_out ; +wire [0:29] sb_1__1__76_chany_bottom_out ; +wire [0:29] sb_1__1__76_chany_top_out ; +wire [0:0] sb_1__1__77_ccff_tail ; +wire [0:29] sb_1__1__77_chanx_left_out ; +wire [0:29] sb_1__1__77_chanx_right_out ; +wire [0:29] sb_1__1__77_chany_bottom_out ; +wire [0:29] sb_1__1__77_chany_top_out ; +wire [0:0] sb_1__1__78_ccff_tail ; +wire [0:29] sb_1__1__78_chanx_left_out ; +wire [0:29] sb_1__1__78_chanx_right_out ; +wire [0:29] sb_1__1__78_chany_bottom_out ; +wire [0:29] sb_1__1__78_chany_top_out ; +wire [0:0] sb_1__1__79_ccff_tail ; +wire [0:29] sb_1__1__79_chanx_left_out ; +wire [0:29] sb_1__1__79_chanx_right_out ; +wire [0:29] sb_1__1__79_chany_bottom_out ; +wire [0:29] sb_1__1__79_chany_top_out ; +wire [0:0] sb_1__1__7_ccff_tail ; +wire [0:29] sb_1__1__7_chanx_left_out ; +wire [0:29] sb_1__1__7_chanx_right_out ; +wire [0:29] sb_1__1__7_chany_bottom_out ; +wire [0:29] sb_1__1__7_chany_top_out ; +wire [0:0] sb_1__1__80_ccff_tail ; +wire [0:29] sb_1__1__80_chanx_left_out ; +wire [0:29] sb_1__1__80_chanx_right_out ; +wire [0:29] sb_1__1__80_chany_bottom_out ; +wire [0:29] sb_1__1__80_chany_top_out ; +wire [0:0] sb_1__1__81_ccff_tail ; +wire [0:29] sb_1__1__81_chanx_left_out ; +wire [0:29] sb_1__1__81_chanx_right_out ; +wire [0:29] sb_1__1__81_chany_bottom_out ; +wire [0:29] sb_1__1__81_chany_top_out ; +wire [0:0] sb_1__1__82_ccff_tail ; +wire [0:29] sb_1__1__82_chanx_left_out ; +wire [0:29] sb_1__1__82_chanx_right_out ; +wire [0:29] sb_1__1__82_chany_bottom_out ; +wire [0:29] sb_1__1__82_chany_top_out ; +wire [0:0] sb_1__1__83_ccff_tail ; +wire [0:29] sb_1__1__83_chanx_left_out ; +wire [0:29] sb_1__1__83_chanx_right_out ; +wire [0:29] sb_1__1__83_chany_bottom_out ; +wire [0:29] sb_1__1__83_chany_top_out ; +wire [0:0] sb_1__1__84_ccff_tail ; +wire [0:29] sb_1__1__84_chanx_left_out ; +wire [0:29] sb_1__1__84_chanx_right_out ; +wire [0:29] sb_1__1__84_chany_bottom_out ; +wire [0:29] sb_1__1__84_chany_top_out ; +wire [0:0] sb_1__1__85_ccff_tail ; +wire [0:29] sb_1__1__85_chanx_left_out ; +wire [0:29] sb_1__1__85_chanx_right_out ; +wire [0:29] sb_1__1__85_chany_bottom_out ; +wire [0:29] sb_1__1__85_chany_top_out ; +wire [0:0] sb_1__1__86_ccff_tail ; +wire [0:29] sb_1__1__86_chanx_left_out ; +wire [0:29] sb_1__1__86_chanx_right_out ; +wire [0:29] sb_1__1__86_chany_bottom_out ; +wire [0:29] sb_1__1__86_chany_top_out ; +wire [0:0] sb_1__1__87_ccff_tail ; +wire [0:29] sb_1__1__87_chanx_left_out ; +wire [0:29] sb_1__1__87_chanx_right_out ; +wire [0:29] sb_1__1__87_chany_bottom_out ; +wire [0:29] sb_1__1__87_chany_top_out ; +wire [0:0] sb_1__1__88_ccff_tail ; +wire [0:29] sb_1__1__88_chanx_left_out ; +wire [0:29] sb_1__1__88_chanx_right_out ; +wire [0:29] sb_1__1__88_chany_bottom_out ; +wire [0:29] sb_1__1__88_chany_top_out ; +wire [0:0] sb_1__1__89_ccff_tail ; +wire [0:29] sb_1__1__89_chanx_left_out ; +wire [0:29] sb_1__1__89_chanx_right_out ; +wire [0:29] sb_1__1__89_chany_bottom_out ; +wire [0:29] sb_1__1__89_chany_top_out ; +wire [0:0] sb_1__1__8_ccff_tail ; +wire [0:29] sb_1__1__8_chanx_left_out ; +wire [0:29] sb_1__1__8_chanx_right_out ; +wire [0:29] sb_1__1__8_chany_bottom_out ; +wire [0:29] sb_1__1__8_chany_top_out ; +wire [0:0] sb_1__1__90_ccff_tail ; +wire [0:29] sb_1__1__90_chanx_left_out ; +wire [0:29] sb_1__1__90_chanx_right_out ; +wire [0:29] sb_1__1__90_chany_bottom_out ; +wire [0:29] sb_1__1__90_chany_top_out ; +wire [0:0] sb_1__1__91_ccff_tail ; +wire [0:29] sb_1__1__91_chanx_left_out ; +wire [0:29] sb_1__1__91_chanx_right_out ; +wire [0:29] sb_1__1__91_chany_bottom_out ; +wire [0:29] sb_1__1__91_chany_top_out ; +wire [0:0] sb_1__1__92_ccff_tail ; +wire [0:29] sb_1__1__92_chanx_left_out ; +wire [0:29] sb_1__1__92_chanx_right_out ; +wire [0:29] sb_1__1__92_chany_bottom_out ; +wire [0:29] sb_1__1__92_chany_top_out ; +wire [0:0] sb_1__1__93_ccff_tail ; +wire [0:29] sb_1__1__93_chanx_left_out ; +wire [0:29] sb_1__1__93_chanx_right_out ; +wire [0:29] sb_1__1__93_chany_bottom_out ; +wire [0:29] sb_1__1__93_chany_top_out ; +wire [0:0] sb_1__1__94_ccff_tail ; +wire [0:29] sb_1__1__94_chanx_left_out ; +wire [0:29] sb_1__1__94_chanx_right_out ; +wire [0:29] sb_1__1__94_chany_bottom_out ; +wire [0:29] sb_1__1__94_chany_top_out ; +wire [0:0] sb_1__1__95_ccff_tail ; +wire [0:29] sb_1__1__95_chanx_left_out ; +wire [0:29] sb_1__1__95_chanx_right_out ; +wire [0:29] sb_1__1__95_chany_bottom_out ; +wire [0:29] sb_1__1__95_chany_top_out ; +wire [0:0] sb_1__1__96_ccff_tail ; +wire [0:29] sb_1__1__96_chanx_left_out ; +wire [0:29] sb_1__1__96_chanx_right_out ; +wire [0:29] sb_1__1__96_chany_bottom_out ; +wire [0:29] sb_1__1__96_chany_top_out ; +wire [0:0] sb_1__1__97_ccff_tail ; +wire [0:29] sb_1__1__97_chanx_left_out ; +wire [0:29] sb_1__1__97_chanx_right_out ; +wire [0:29] sb_1__1__97_chany_bottom_out ; +wire [0:29] sb_1__1__97_chany_top_out ; +wire [0:0] sb_1__1__98_ccff_tail ; +wire [0:29] sb_1__1__98_chanx_left_out ; +wire [0:29] sb_1__1__98_chanx_right_out ; +wire [0:29] sb_1__1__98_chany_bottom_out ; +wire [0:29] sb_1__1__98_chany_top_out ; +wire [0:0] sb_1__1__99_ccff_tail ; +wire [0:29] sb_1__1__99_chanx_left_out ; +wire [0:29] sb_1__1__99_chanx_right_out ; +wire [0:29] sb_1__1__99_chany_bottom_out ; +wire [0:29] sb_1__1__99_chany_top_out ; +wire [0:0] sb_1__1__9_ccff_tail ; +wire [0:29] sb_1__1__9_chanx_left_out ; +wire [0:29] sb_1__1__9_chanx_right_out ; +wire [0:29] sb_1__1__9_chany_bottom_out ; +wire [0:29] sb_1__1__9_chany_top_out ; +wire [1:0] UNCONN ; +wire [317:0] scff_Wires ; +wire [132:0] regin_feedthrough_wires ; +wire [132:0] regout_feedthrough_wires ; +wire [132:0] cin_feedthrough_wires ; +wire [132:0] cout_feedthrough_wires ; +wire [287:0] Test_enWires ; +wire [636:0] pResetWires ; +wire [287:0] ResetWires ; +wire [624:0] prog_clk_0_wires ; +wire [251:0] prog_clk_1_wires ; +wire [135:0] prog_clk_2_wires ; +wire [100:0] prog_clk_3_wires ; +wire [251:0] clk_1_wires ; +wire [135:0] clk_2_wires ; +wire [100:0] clk_3_wires ; +supply1 VDD ; +supply0 VSS ; + +grid_clb grid_clb_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[0] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[0] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_3 } ) , + .ccff_head ( grid_io_left_0_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_0_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_0_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_0_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_0_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_0_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_0_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_0_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_0_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_4 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[23] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6 ) , .SC_OUT_BOT ( scff_Wires[25] ) , + .Test_en_E_in ( Test_enWires[24] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_8 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9 ) , + .pReset_N_in ( pResetWires[63] ) , .Reset_E_in ( ResetWires[24] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_10 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_11 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_12 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[4] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_13 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[0] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[1] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[3] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_14 ) , + .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_16 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[1] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_17 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[1] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_18 } ) , + .ccff_head ( grid_io_left_1_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_1_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_1_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_1_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_1_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_1_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_1_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_1_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_1_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[0] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_19 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[0] ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[21] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_20 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_OUT_BOT ( scff_Wires[22] ) , + .Test_en_E_in ( Test_enWires[46] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_22 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_23 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_24 ) , + .pReset_N_in ( pResetWires[112] ) , .Reset_E_in ( ResetWires[46] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_25 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_26 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_27 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_28 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[3] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[6] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[7] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[9] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_31 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[2] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_32 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[2] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_33 } ) , + .ccff_head ( grid_io_left_2_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_2_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_2_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_2_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_2_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_2_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_2_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_2_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_2_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[1] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_34 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[1] ) , + .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[19] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , .SC_OUT_BOT ( scff_Wires[20] ) , + .Test_en_E_in ( Test_enWires[68] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_37 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_38 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_39 ) , + .pReset_N_in ( pResetWires[161] ) , .Reset_E_in ( ResetWires[68] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_40 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_41 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_42 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[11] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_43 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[11] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[12] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[14] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_44 ) , + .clk_0_N_in ( clk_1_wires[11] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_46 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[3] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_47 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[3] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_48 } ) , + .ccff_head ( grid_io_left_3_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_3_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_3_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_3_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_3_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_3_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_3_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_3_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_3_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[2] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_49 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[2] ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[17] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires[18] ) , + .Test_en_E_in ( Test_enWires[90] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_52 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_53 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_54 ) , + .pReset_N_in ( pResetWires[210] ) , .Reset_E_in ( ResetWires[90] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_55 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_56 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_57 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_58 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[10] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[16] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[17] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[19] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) , + .clk_0_S_in ( clk_1_wires[10] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_61 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[4] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_62 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[4] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_63 } ) , + .ccff_head ( grid_io_left_4_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_4_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_4_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_4_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_4_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_4_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_4_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_4_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_4_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[3] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_64 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[3] ) , + .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[15] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_65 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_66 ) , .SC_OUT_BOT ( scff_Wires[16] ) , + .Test_en_E_in ( Test_enWires[112] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_67 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_68 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_69 ) , + .pReset_N_in ( pResetWires[259] ) , .Reset_E_in ( ResetWires[112] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_70 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_71 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_72 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[18] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_73 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[21] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[22] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[24] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_74 ) , + .clk_0_N_in ( clk_1_wires[18] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_76 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[5] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_77 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[5] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_78 } ) , + .ccff_head ( grid_io_left_5_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_5_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_5_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_5_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_5_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_5_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_5_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_5_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_5_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[4] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_79 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[4] ) , + .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[13] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_80 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_81 ) , .SC_OUT_BOT ( scff_Wires[14] ) , + .Test_en_E_in ( Test_enWires[134] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_82 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_83 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_84 ) , + .pReset_N_in ( pResetWires[308] ) , .Reset_E_in ( ResetWires[134] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_85 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_86 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_87 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_88 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[17] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[26] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[27] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[29] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_90 ) , + .clk_0_S_in ( clk_1_wires[17] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_91 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[6] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_92 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[6] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_93 } ) , + .ccff_head ( grid_io_left_6_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_6_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_6_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_6_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_6_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_6_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_6_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_6_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_6_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[5] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_94 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[5] ) , + .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[11] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_95 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_96 ) , .SC_OUT_BOT ( scff_Wires[12] ) , + .Test_en_E_in ( Test_enWires[156] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_97 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_98 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_99 ) , + .pReset_N_in ( pResetWires[357] ) , .Reset_E_in ( ResetWires[156] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_100 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_101 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_102 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[25] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_103 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[31] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[32] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[34] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_104 ) , + .clk_0_N_in ( clk_1_wires[25] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_106 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[7] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_107 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[7] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_108 } ) , + .ccff_head ( grid_io_left_7_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_7_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_7_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_7_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_7_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_7_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_7_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_7_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_7_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[6] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_109 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[6] ) , + .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[9] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_110 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_111 ) , + .SC_OUT_BOT ( scff_Wires[10] ) , .Test_en_E_in ( Test_enWires[178] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_112 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_113 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_114 ) , + .pReset_N_in ( pResetWires[406] ) , .Reset_E_in ( ResetWires[178] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_115 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_116 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_117 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_118 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[24] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[36] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[37] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[39] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_119 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_120 ) , + .clk_0_S_in ( clk_1_wires[24] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_121 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[8] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_122 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[8] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_123 } ) , + .ccff_head ( grid_io_left_8_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_8_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_8_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_8_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_8_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_8_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_8_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_8_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_8_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[7] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_124 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[7] ) , + .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[7] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_125 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_126 ) , .SC_OUT_BOT ( scff_Wires[8] ) , + .Test_en_E_in ( Test_enWires[200] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_127 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_128 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_129 ) , + .pReset_N_in ( pResetWires[455] ) , .Reset_E_in ( ResetWires[200] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_130 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_131 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_132 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[32] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_133 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[41] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[42] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[44] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_134 ) , + .clk_0_N_in ( clk_1_wires[32] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_136 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[9] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_137 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[9] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_138 } ) , + .ccff_head ( grid_io_left_9_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_9_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_9_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_9_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_9_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_9_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_9_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_9_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_9_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[8] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_139 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[8] ) , + .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[5] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_140 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_141 ) , .SC_OUT_BOT ( scff_Wires[6] ) , + .Test_en_E_in ( Test_enWires[222] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_142 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_143 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_144 ) , + .pReset_N_in ( pResetWires[504] ) , .Reset_E_in ( ResetWires[222] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_145 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_146 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_147 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_148 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[31] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[46] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[47] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[49] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_149 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_150 ) , + .clk_0_S_in ( clk_1_wires[31] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_151 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[10] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_152 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[10] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_153 } ) , + .ccff_head ( grid_io_left_10_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_10_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_10_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_10_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_10_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_10_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_10_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_10_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_10_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[9] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_154 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[9] ) , + .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[3] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_155 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_156 ) , .SC_OUT_BOT ( scff_Wires[4] ) , + .Test_en_E_in ( Test_enWires[244] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_157 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_158 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_159 ) , + .pReset_N_in ( pResetWires[553] ) , .Reset_E_in ( ResetWires[244] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_160 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_161 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_162 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[39] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_163 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[51] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[52] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[54] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_164 ) , + .clk_0_N_in ( clk_1_wires[39] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_166 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_167 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_168 } ) , + .ccff_head ( grid_io_left_11_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_11_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_11_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_11_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_11_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_11_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_11_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_11_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_11_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[10] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_169 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[10] ) , + .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires[1] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_170 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_171 ) , .SC_OUT_BOT ( scff_Wires[2] ) , + .Test_en_E_in ( Test_enWires[266] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_172 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_173 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_174 ) , + .pReset_N_in ( pResetWires[602] ) , .Reset_E_in ( ResetWires[266] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_175 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_176 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_177 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_178 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[38] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[56] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[57] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[61] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[59] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) , + .clk_0_S_in ( clk_1_wires[38] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_180 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[11] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_181 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[11] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_182 } ) , + .ccff_head ( cby_1__1__0_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_12_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_12_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_12_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_12_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_12_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_12_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_12_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_12_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_183 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_12_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_184 ) , .SC_IN_BOT ( scff_Wires[28] ) , + .SC_OUT_TOP ( scff_Wires[29] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_185 ) , + .Test_en_E_in ( Test_enWires[25] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_186 ) , + .Test_en_W_out ( Test_enWires[26] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_187 ) , + .pReset_N_in ( pResetWires[68] ) , .Reset_E_in ( ResetWires[25] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_188 ) , + .Reset_W_out ( ResetWires[26] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_189 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[6] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_190 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[63] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[64] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_191 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_192 ) , + .clk_0_N_in ( clk_1_wires[6] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_194 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[12] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_195 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[12] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_196 } ) , + .ccff_head ( cby_1__1__1_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_13_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_13_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_13_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_13_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_13_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_13_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_13_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_13_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[11] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_197 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[11] ) , + .ccff_tail ( grid_clb_13_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_198 ) , .SC_IN_BOT ( scff_Wires[30] ) , + .SC_OUT_TOP ( scff_Wires[31] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_199 ) , + .Test_en_E_in ( Test_enWires[47] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_200 ) , + .Test_en_W_out ( Test_enWires[48] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_201 ) , + .pReset_N_in ( pResetWires[117] ) , .Reset_E_in ( ResetWires[47] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_202 ) , + .Reset_W_out ( ResetWires[48] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_203 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_204 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[5] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[66] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[67] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_205 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_206 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_207 ) , + .clk_0_S_in ( clk_1_wires[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_208 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[13] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_209 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[13] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_210 } ) , + .ccff_head ( cby_1__1__2_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_14_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_14_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_14_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_14_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_14_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_14_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_14_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_14_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[12] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_211 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[12] ) , + .ccff_tail ( grid_clb_14_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_212 ) , .SC_IN_BOT ( scff_Wires[32] ) , + .SC_OUT_TOP ( scff_Wires[33] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_213 ) , + .Test_en_E_in ( Test_enWires[69] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_214 ) , + .Test_en_W_out ( Test_enWires[70] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_215 ) , + .pReset_N_in ( pResetWires[166] ) , .Reset_E_in ( ResetWires[69] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_216 ) , + .Reset_W_out ( ResetWires[70] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_217 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[13] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_218 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[69] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[70] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_219 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_220 ) , + .clk_0_N_in ( clk_1_wires[13] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_222 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[14] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_223 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[14] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_224 } ) , + .ccff_head ( cby_1__1__3_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_15_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_15_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_15_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_15_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_15_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_15_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_15_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_15_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[13] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_225 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[13] ) , + .ccff_tail ( grid_clb_15_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_226 ) , .SC_IN_BOT ( scff_Wires[34] ) , + .SC_OUT_TOP ( scff_Wires[35] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_227 ) , + .Test_en_E_in ( Test_enWires[91] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_228 ) , + .Test_en_W_out ( Test_enWires[92] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_229 ) , + .pReset_N_in ( pResetWires[215] ) , .Reset_E_in ( ResetWires[91] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_230 ) , + .Reset_W_out ( ResetWires[92] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_231 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_232 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[12] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[72] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[73] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_233 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_234 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_235 ) , + .clk_0_S_in ( clk_1_wires[12] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_236 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[15] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_237 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[15] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_238 } ) , + .ccff_head ( cby_1__1__4_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_16_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_16_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_16_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_16_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_16_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_16_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_16_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_16_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[14] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_239 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[14] ) , + .ccff_tail ( grid_clb_16_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_240 ) , .SC_IN_BOT ( scff_Wires[36] ) , + .SC_OUT_TOP ( scff_Wires[37] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_241 ) , + .Test_en_E_in ( Test_enWires[113] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_242 ) , + .Test_en_W_out ( Test_enWires[114] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_243 ) , + .pReset_N_in ( pResetWires[264] ) , .Reset_E_in ( ResetWires[113] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_244 ) , + .Reset_W_out ( ResetWires[114] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_245 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[20] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_246 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[75] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[76] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_247 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_248 ) , + .clk_0_N_in ( clk_1_wires[20] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_250 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[16] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_251 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[16] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_252 } ) , + .ccff_head ( cby_1__1__5_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_17_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_17_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_17_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_17_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_17_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_17_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_17_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_17_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[15] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_253 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[15] ) , + .ccff_tail ( grid_clb_17_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_254 ) , .SC_IN_BOT ( scff_Wires[38] ) , + .SC_OUT_TOP ( scff_Wires[39] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_255 ) , + .Test_en_E_in ( Test_enWires[135] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_256 ) , + .Test_en_W_out ( Test_enWires[136] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_257 ) , + .pReset_N_in ( pResetWires[313] ) , .Reset_E_in ( ResetWires[135] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_258 ) , + .Reset_W_out ( ResetWires[136] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_259 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_260 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[19] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[78] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[79] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_261 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_262 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_263 ) , + .clk_0_S_in ( clk_1_wires[19] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_264 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[17] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_265 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[17] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_266 } ) , + .ccff_head ( cby_1__1__6_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_18_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_18_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_18_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_18_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_18_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_18_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_18_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_18_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[16] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_267 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[16] ) , + .ccff_tail ( grid_clb_18_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_268 ) , .SC_IN_BOT ( scff_Wires[40] ) , + .SC_OUT_TOP ( scff_Wires[41] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_269 ) , + .Test_en_E_in ( Test_enWires[157] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_270 ) , + .Test_en_W_out ( Test_enWires[158] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_271 ) , + .pReset_N_in ( pResetWires[362] ) , .Reset_E_in ( ResetWires[157] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_272 ) , + .Reset_W_out ( ResetWires[158] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_273 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[27] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_274 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[81] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[82] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_275 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_276 ) , + .clk_0_N_in ( clk_1_wires[27] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_278 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[18] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_279 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[18] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_280 } ) , + .ccff_head ( cby_1__1__7_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_19_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_19_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_19_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_19_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_19_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_19_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_19_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_19_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[17] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_281 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[17] ) , + .ccff_tail ( grid_clb_19_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_282 ) , .SC_IN_BOT ( scff_Wires[42] ) , + .SC_OUT_TOP ( scff_Wires[43] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_283 ) , + .Test_en_E_in ( Test_enWires[179] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_284 ) , + .Test_en_W_out ( Test_enWires[180] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_285 ) , + .pReset_N_in ( pResetWires[411] ) , .Reset_E_in ( ResetWires[179] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_286 ) , + .Reset_W_out ( ResetWires[180] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_287 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_288 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[26] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[84] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[85] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_289 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_290 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_291 ) , + .clk_0_S_in ( clk_1_wires[26] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_292 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[19] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_293 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[19] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_294 } ) , + .ccff_head ( cby_1__1__8_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_20_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_20_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_20_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_20_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_20_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_20_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_20_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_20_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[18] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_295 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[18] ) , + .ccff_tail ( grid_clb_20_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_296 ) , .SC_IN_BOT ( scff_Wires[44] ) , + .SC_OUT_TOP ( scff_Wires[45] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_297 ) , + .Test_en_E_in ( Test_enWires[201] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_298 ) , + .Test_en_W_out ( Test_enWires[202] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_299 ) , + .pReset_N_in ( pResetWires[460] ) , .Reset_E_in ( ResetWires[201] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_300 ) , + .Reset_W_out ( ResetWires[202] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_301 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[34] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_302 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[87] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[88] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_303 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_304 ) , + .clk_0_N_in ( clk_1_wires[34] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_306 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[20] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_307 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[20] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_308 } ) , + .ccff_head ( cby_1__1__9_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_21_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_21_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_21_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_21_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_21_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_21_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_21_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_21_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[19] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_309 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[19] ) , + .ccff_tail ( grid_clb_21_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_310 ) , .SC_IN_BOT ( scff_Wires[46] ) , + .SC_OUT_TOP ( scff_Wires[47] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_311 ) , + .Test_en_E_in ( Test_enWires[223] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_312 ) , + .Test_en_W_out ( Test_enWires[224] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_313 ) , + .pReset_N_in ( pResetWires[509] ) , .Reset_E_in ( ResetWires[223] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_314 ) , + .Reset_W_out ( ResetWires[224] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_315 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_316 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[33] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[90] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[91] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_317 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_318 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_319 ) , + .clk_0_S_in ( clk_1_wires[33] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_320 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[21] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_321 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[21] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_322 } ) , + .ccff_head ( cby_1__1__10_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_22_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_22_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_22_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_22_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_22_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_22_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_22_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_22_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[20] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_323 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[20] ) , + .ccff_tail ( grid_clb_22_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_324 ) , .SC_IN_BOT ( scff_Wires[48] ) , + .SC_OUT_TOP ( scff_Wires[49] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_325 ) , + .Test_en_E_in ( Test_enWires[245] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_326 ) , + .Test_en_W_out ( Test_enWires[246] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_327 ) , + .pReset_N_in ( pResetWires[558] ) , .Reset_E_in ( ResetWires[245] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_328 ) , + .Reset_W_out ( ResetWires[246] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_329 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[41] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_330 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[93] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[94] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_331 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_332 ) , + .clk_0_N_in ( clk_1_wires[41] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_334 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_335 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_336 } ) , + .ccff_head ( cby_1__1__11_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_23_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_23_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_23_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_23_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_23_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_23_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_23_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_23_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[21] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_337 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[21] ) , + .ccff_tail ( grid_clb_23_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_338 ) , .SC_IN_BOT ( scff_Wires[50] ) , + .SC_OUT_TOP ( scff_Wires[51] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_339 ) , + .Test_en_E_in ( Test_enWires[267] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_340 ) , + .Test_en_W_out ( Test_enWires[268] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_341 ) , + .pReset_N_in ( pResetWires[606] ) , .Reset_E_in ( ResetWires[267] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_342 ) , + .Reset_W_out ( ResetWires[268] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_343 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_344 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[40] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[96] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[97] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_345 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[99] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_346 ) , + .clk_0_S_in ( clk_1_wires[40] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_347 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[22] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_348 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[22] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_349 } ) , + .ccff_head ( cby_1__1__12_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_24_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_24_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_24_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_24_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_24_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_24_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_24_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_24_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_350 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[76] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_351 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_352 ) , + .SC_OUT_BOT ( scff_Wires[78] ) , .Test_en_E_in ( Test_enWires[27] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_353 ) , + .Test_en_W_out ( Test_enWires[28] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_354 ) , + .pReset_N_in ( pResetWires[72] ) , .Reset_E_in ( ResetWires[27] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_355 ) , + .Reset_W_out ( ResetWires[28] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_356 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[46] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_357 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[101] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[102] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_358 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_359 ) , + .clk_0_N_in ( clk_1_wires[46] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_361 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[23] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_362 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[23] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_363 } ) , + .ccff_head ( cby_1__1__13_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_25_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_25_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_25_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_25_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_25_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_25_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_25_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_25_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[22] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_364 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[22] ) , + .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[74] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_365 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_366 ) , + .SC_OUT_BOT ( scff_Wires[75] ) , .Test_en_E_in ( Test_enWires[49] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_367 ) , + .Test_en_W_out ( Test_enWires[50] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_368 ) , + .pReset_N_in ( pResetWires[121] ) , .Reset_E_in ( ResetWires[49] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_369 ) , + .Reset_W_out ( ResetWires[50] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_370 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_371 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[45] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[104] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[105] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_372 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_373 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) , + .clk_0_S_in ( clk_1_wires[45] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_375 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[24] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_376 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[24] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_377 } ) , + .ccff_head ( cby_1__1__14_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_26_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_26_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_26_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_26_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_26_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_26_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_26_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_26_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[23] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_378 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[23] ) , + .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[72] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_379 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_380 ) , + .SC_OUT_BOT ( scff_Wires[73] ) , .Test_en_E_in ( Test_enWires[71] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_381 ) , + .Test_en_W_out ( Test_enWires[72] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_382 ) , + .pReset_N_in ( pResetWires[170] ) , .Reset_E_in ( ResetWires[71] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_383 ) , + .Reset_W_out ( ResetWires[72] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_384 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[53] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_385 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[107] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[108] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_386 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_387 ) , + .clk_0_N_in ( clk_1_wires[53] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_389 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[25] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_390 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[25] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_391 } ) , + .ccff_head ( cby_1__1__15_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_27_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_27_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_27_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_27_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_27_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_27_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_27_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_27_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[24] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_392 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[24] ) , + .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[70] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_393 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_394 ) , + .SC_OUT_BOT ( scff_Wires[71] ) , .Test_en_E_in ( Test_enWires[93] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_395 ) , + .Test_en_W_out ( Test_enWires[94] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_396 ) , + .pReset_N_in ( pResetWires[219] ) , .Reset_E_in ( ResetWires[93] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_397 ) , + .Reset_W_out ( ResetWires[94] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_398 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_399 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[52] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[110] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[111] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_400 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_401 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_402 ) , + .clk_0_S_in ( clk_1_wires[52] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_403 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[26] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_404 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[26] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_405 } ) , + .ccff_head ( cby_1__1__16_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_28_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_28_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_28_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_28_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_28_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_28_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_28_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_28_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[25] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_406 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[25] ) , + .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[68] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_407 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_408 ) , + .SC_OUT_BOT ( scff_Wires[69] ) , .Test_en_E_in ( Test_enWires[115] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_409 ) , + .Test_en_W_out ( Test_enWires[116] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_410 ) , + .pReset_N_in ( pResetWires[268] ) , .Reset_E_in ( ResetWires[115] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_411 ) , + .Reset_W_out ( ResetWires[116] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_412 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[60] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_413 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[113] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[114] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_414 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_415 ) , + .clk_0_N_in ( clk_1_wires[60] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_417 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[27] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[27] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_419 } ) , + .ccff_head ( cby_1__1__17_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_29_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_29_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_29_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_29_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_29_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_29_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_29_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_29_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[26] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_420 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[26] ) , + .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[66] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_421 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_422 ) , + .SC_OUT_BOT ( scff_Wires[67] ) , .Test_en_E_in ( Test_enWires[137] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_423 ) , + .Test_en_W_out ( Test_enWires[138] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_424 ) , + .pReset_N_in ( pResetWires[317] ) , .Reset_E_in ( ResetWires[137] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_425 ) , + .Reset_W_out ( ResetWires[138] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_426 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_427 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[59] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[116] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[117] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_428 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_429 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_430 ) , + .clk_0_S_in ( clk_1_wires[59] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_431 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[28] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_432 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[28] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_433 } ) , + .ccff_head ( cby_1__1__18_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_30_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_30_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_30_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_30_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_30_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_30_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_30_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_30_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[27] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_434 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[27] ) , + .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[64] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_435 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_436 ) , + .SC_OUT_BOT ( scff_Wires[65] ) , .Test_en_E_in ( Test_enWires[159] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_437 ) , + .Test_en_W_out ( Test_enWires[160] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_438 ) , + .pReset_N_in ( pResetWires[366] ) , .Reset_E_in ( ResetWires[159] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_439 ) , + .Reset_W_out ( ResetWires[160] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_440 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[67] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_441 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[119] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[120] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_442 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_443 ) , + .clk_0_N_in ( clk_1_wires[67] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_445 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[29] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_446 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[29] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_447 } ) , + .ccff_head ( cby_1__1__19_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_31_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_31_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_31_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_31_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_31_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_31_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_31_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_31_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[28] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_448 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[28] ) , + .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[62] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_449 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_450 ) , + .SC_OUT_BOT ( scff_Wires[63] ) , .Test_en_E_in ( Test_enWires[181] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_451 ) , + .Test_en_W_out ( Test_enWires[182] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_452 ) , + .pReset_N_in ( pResetWires[415] ) , .Reset_E_in ( ResetWires[181] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_453 ) , + .Reset_W_out ( ResetWires[182] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_454 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_455 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[66] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[122] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[123] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_456 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_457 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_458 ) , + .clk_0_S_in ( clk_1_wires[66] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_459 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[30] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_460 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[30] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_461 } ) , + .ccff_head ( cby_1__1__20_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_32_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_32_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_32_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_32_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_32_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_32_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_32_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_32_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[29] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_462 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[29] ) , + .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[60] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_463 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_464 ) , + .SC_OUT_BOT ( scff_Wires[61] ) , .Test_en_E_in ( Test_enWires[203] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_465 ) , + .Test_en_W_out ( Test_enWires[204] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_466 ) , + .pReset_N_in ( pResetWires[464] ) , .Reset_E_in ( ResetWires[203] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_467 ) , + .Reset_W_out ( ResetWires[204] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_468 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[74] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_469 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[125] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[126] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_470 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_471 ) , + .clk_0_N_in ( clk_1_wires[74] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_473 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[31] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_474 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[31] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_475 } ) , + .ccff_head ( cby_1__1__21_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_33_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_33_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_33_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_33_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_33_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_33_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_33_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_33_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[30] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_476 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[30] ) , + .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires[58] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_477 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_478 ) , + .SC_OUT_BOT ( scff_Wires[59] ) , .Test_en_E_in ( Test_enWires[225] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_479 ) , + .Test_en_W_out ( Test_enWires[226] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_480 ) , + .pReset_N_in ( pResetWires[513] ) , .Reset_E_in ( ResetWires[225] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_481 ) , + .Reset_W_out ( ResetWires[226] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_482 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_483 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[73] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[128] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[129] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_486 ) , + .clk_0_S_in ( clk_1_wires[73] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_487 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[32] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_488 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[32] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_489 } ) , + .ccff_head ( cby_1__1__22_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_34_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_34_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_34_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_34_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_34_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_34_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_34_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_34_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[31] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_490 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[31] ) , + .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires[56] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_491 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_492 ) , + .SC_OUT_BOT ( scff_Wires[57] ) , .Test_en_E_in ( Test_enWires[247] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_493 ) , + .Test_en_W_out ( Test_enWires[248] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_494 ) , + .pReset_N_in ( pResetWires[562] ) , .Reset_E_in ( ResetWires[247] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_495 ) , + .Reset_W_out ( ResetWires[248] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_496 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[81] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_497 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[131] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[132] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_498 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_499 ) , + .clk_0_N_in ( clk_1_wires[81] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_501 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_502 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_503 } ) , + .ccff_head ( cby_1__1__23_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_35_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_35_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_35_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_35_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_35_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_35_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_35_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_35_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[32] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_504 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[32] ) , + .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires[54] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_505 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_506 ) , + .SC_OUT_BOT ( scff_Wires[55] ) , .Test_en_E_in ( Test_enWires[269] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_507 ) , + .Test_en_W_out ( Test_enWires[270] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_508 ) , + .pReset_N_in ( pResetWires[609] ) , .Reset_E_in ( ResetWires[269] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_509 ) , + .Reset_W_out ( ResetWires[270] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_510 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_511 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[80] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[134] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[135] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_512 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[137] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) , + .clk_0_S_in ( clk_1_wires[80] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_514 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[33] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_515 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[33] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_516 } ) , + .ccff_head ( cby_1__1__24_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_36_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_36_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_36_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_36_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_36_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_36_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_36_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_36_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_517 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_36_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_518 ) , .SC_IN_BOT ( scff_Wires[81] ) , + .SC_OUT_TOP ( scff_Wires[82] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_519 ) , + .Test_en_E_in ( Test_enWires[29] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_520 ) , + .Test_en_W_out ( Test_enWires[30] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_521 ) , + .pReset_N_in ( pResetWires[76] ) , .Reset_E_in ( ResetWires[29] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_522 ) , + .Reset_W_out ( ResetWires[30] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_523 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[48] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_524 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[139] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[140] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_525 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_526 ) , + .clk_0_N_in ( clk_1_wires[48] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_528 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[34] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_529 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[34] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_530 } ) , + .ccff_head ( cby_1__1__25_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_37_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_37_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_37_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_37_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_37_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_37_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_37_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_37_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[33] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_531 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[33] ) , + .ccff_tail ( grid_clb_37_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_532 ) , .SC_IN_BOT ( scff_Wires[83] ) , + .SC_OUT_TOP ( scff_Wires[84] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_533 ) , + .Test_en_E_in ( Test_enWires[51] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_534 ) , + .Test_en_W_out ( Test_enWires[52] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_535 ) , + .pReset_N_in ( pResetWires[125] ) , .Reset_E_in ( ResetWires[51] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_536 ) , + .Reset_W_out ( ResetWires[52] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_537 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_538 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[47] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[142] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[143] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_539 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_540 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_541 ) , + .clk_0_S_in ( clk_1_wires[47] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_542 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[35] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_543 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[35] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_544 } ) , + .ccff_head ( cby_1__1__26_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_38_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_38_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_38_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_38_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_38_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_38_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_38_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_38_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[34] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_545 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[34] ) , + .ccff_tail ( grid_clb_38_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_546 ) , .SC_IN_BOT ( scff_Wires[85] ) , + .SC_OUT_TOP ( scff_Wires[86] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_547 ) , + .Test_en_E_in ( Test_enWires[73] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_548 ) , + .Test_en_W_out ( Test_enWires[74] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_549 ) , + .pReset_N_in ( pResetWires[174] ) , .Reset_E_in ( ResetWires[73] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_550 ) , + .Reset_W_out ( ResetWires[74] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_551 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[55] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_552 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[145] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[146] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_553 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_554 ) , + .clk_0_N_in ( clk_1_wires[55] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_556 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[36] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_557 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[36] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_558 } ) , + .ccff_head ( cby_1__1__27_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_39_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_39_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_39_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_39_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_39_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_39_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_39_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_39_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[35] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_559 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[35] ) , + .ccff_tail ( grid_clb_39_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_560 ) , .SC_IN_BOT ( scff_Wires[87] ) , + .SC_OUT_TOP ( scff_Wires[88] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_561 ) , + .Test_en_E_in ( Test_enWires[95] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_562 ) , + .Test_en_W_out ( Test_enWires[96] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_563 ) , + .pReset_N_in ( pResetWires[223] ) , .Reset_E_in ( ResetWires[95] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_564 ) , + .Reset_W_out ( ResetWires[96] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_565 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_566 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[54] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[148] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[149] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_567 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_568 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_569 ) , + .clk_0_S_in ( clk_1_wires[54] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_570 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[37] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_571 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[37] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_572 } ) , + .ccff_head ( cby_1__1__28_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_40_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_40_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_40_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_40_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_40_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_40_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_40_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_40_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[36] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_573 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[36] ) , + .ccff_tail ( grid_clb_40_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_574 ) , .SC_IN_BOT ( scff_Wires[89] ) , + .SC_OUT_TOP ( scff_Wires[90] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_575 ) , + .Test_en_E_in ( Test_enWires[117] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_576 ) , + .Test_en_W_out ( Test_enWires[118] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_577 ) , + .pReset_N_in ( pResetWires[272] ) , .Reset_E_in ( ResetWires[117] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_578 ) , + .Reset_W_out ( ResetWires[118] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_579 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[62] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_580 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[151] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[152] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_581 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_582 ) , + .clk_0_N_in ( clk_1_wires[62] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_584 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[38] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_585 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[38] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_586 } ) , + .ccff_head ( cby_1__1__29_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_41_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_41_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_41_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_41_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_41_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_41_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_41_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_41_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[37] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_587 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[37] ) , + .ccff_tail ( grid_clb_41_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_588 ) , .SC_IN_BOT ( scff_Wires[91] ) , + .SC_OUT_TOP ( scff_Wires[92] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_589 ) , + .Test_en_E_in ( Test_enWires[139] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_590 ) , + .Test_en_W_out ( Test_enWires[140] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_591 ) , + .pReset_N_in ( pResetWires[321] ) , .Reset_E_in ( ResetWires[139] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_592 ) , + .Reset_W_out ( ResetWires[140] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_593 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_594 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[61] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[154] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[155] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_595 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_596 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_597 ) , + .clk_0_S_in ( clk_1_wires[61] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_598 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[39] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_599 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[39] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_600 } ) , + .ccff_head ( cby_1__1__30_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_42_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_42_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_42_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_42_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_42_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_42_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_42_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_42_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[38] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_601 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[38] ) , + .ccff_tail ( grid_clb_42_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_602 ) , .SC_IN_BOT ( scff_Wires[93] ) , + .SC_OUT_TOP ( scff_Wires[94] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_603 ) , + .Test_en_E_in ( Test_enWires[161] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_604 ) , + .Test_en_W_out ( Test_enWires[162] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_605 ) , + .pReset_N_in ( pResetWires[370] ) , .Reset_E_in ( ResetWires[161] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_606 ) , + .Reset_W_out ( ResetWires[162] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_607 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[69] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_608 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[157] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[158] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_609 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_610 ) , + .clk_0_N_in ( clk_1_wires[69] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_612 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[40] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_613 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[40] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_614 } ) , + .ccff_head ( cby_1__1__31_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_43_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_43_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_43_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_43_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_43_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_43_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_43_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_43_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[39] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_615 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[39] ) , + .ccff_tail ( grid_clb_43_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_616 ) , .SC_IN_BOT ( scff_Wires[95] ) , + .SC_OUT_TOP ( scff_Wires[96] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_617 ) , + .Test_en_E_in ( Test_enWires[183] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_618 ) , + .Test_en_W_out ( Test_enWires[184] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_619 ) , + .pReset_N_in ( pResetWires[419] ) , .Reset_E_in ( ResetWires[183] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_620 ) , + .Reset_W_out ( ResetWires[184] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_621 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_622 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[68] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[160] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[161] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_625 ) , + .clk_0_S_in ( clk_1_wires[68] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_626 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[41] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_627 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[41] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_628 } ) , + .ccff_head ( cby_1__1__32_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_44_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_44_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_44_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_44_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_44_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_44_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_44_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_44_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[40] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_629 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[40] ) , + .ccff_tail ( grid_clb_44_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_630 ) , .SC_IN_BOT ( scff_Wires[97] ) , + .SC_OUT_TOP ( scff_Wires[98] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_631 ) , + .Test_en_E_in ( Test_enWires[205] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_632 ) , + .Test_en_W_out ( Test_enWires[206] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_633 ) , + .pReset_N_in ( pResetWires[468] ) , .Reset_E_in ( ResetWires[205] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_634 ) , + .Reset_W_out ( ResetWires[206] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_635 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[76] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_636 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[163] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[164] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_637 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_638 ) , + .clk_0_N_in ( clk_1_wires[76] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_640 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[42] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_641 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[42] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_642 } ) , + .ccff_head ( cby_1__1__33_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_45_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_45_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_45_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_45_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_45_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_45_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_45_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_45_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[41] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_643 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[41] ) , + .ccff_tail ( grid_clb_45_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_644 ) , .SC_IN_BOT ( scff_Wires[99] ) , + .SC_OUT_TOP ( scff_Wires[100] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_645 ) , + .Test_en_E_in ( Test_enWires[227] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_646 ) , + .Test_en_W_out ( Test_enWires[228] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_647 ) , + .pReset_N_in ( pResetWires[517] ) , .Reset_E_in ( ResetWires[227] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_648 ) , + .Reset_W_out ( ResetWires[228] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_649 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_650 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[75] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[166] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[167] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_651 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_652 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_653 ) , + .clk_0_S_in ( clk_1_wires[75] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_654 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[43] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_655 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[43] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_656 } ) , + .ccff_head ( cby_1__1__34_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_46_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_46_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_46_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_46_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_46_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_46_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_46_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_46_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[42] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_657 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[42] ) , + .ccff_tail ( grid_clb_46_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_658 ) , .SC_IN_BOT ( scff_Wires[101] ) , + .SC_OUT_TOP ( scff_Wires[102] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_659 ) , + .Test_en_E_in ( Test_enWires[249] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_660 ) , + .Test_en_W_out ( Test_enWires[250] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_661 ) , + .pReset_N_in ( pResetWires[566] ) , .Reset_E_in ( ResetWires[249] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_662 ) , + .Reset_W_out ( ResetWires[250] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_663 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[83] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_664 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[169] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[170] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_665 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_666 ) , + .clk_0_N_in ( clk_1_wires[83] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_668 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_669 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_670 } ) , + .ccff_head ( cby_1__1__35_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_47_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_47_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_47_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_47_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_47_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_47_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_47_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_47_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[43] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_671 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[43] ) , + .ccff_tail ( grid_clb_47_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_672 ) , .SC_IN_BOT ( scff_Wires[103] ) , + .SC_OUT_TOP ( scff_Wires[104] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_673 ) , + .Test_en_E_in ( Test_enWires[271] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_674 ) , + .Test_en_W_out ( Test_enWires[272] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_675 ) , + .pReset_N_in ( pResetWires[612] ) , .Reset_E_in ( ResetWires[271] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_676 ) , + .Reset_W_out ( ResetWires[272] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_677 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_678 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[82] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[172] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[173] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_679 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[175] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_680 ) , + .clk_0_S_in ( clk_1_wires[82] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_681 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[44] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_682 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[44] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_683 } ) , + .ccff_head ( cby_1__1__36_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_48_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_48_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_48_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_48_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_48_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_48_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_48_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_48_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_684 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[129] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_685 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_686 ) , + .SC_OUT_BOT ( scff_Wires[131] ) , .Test_en_E_in ( Test_enWires[31] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_687 ) , + .Test_en_W_out ( Test_enWires[32] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_688 ) , + .pReset_N_in ( pResetWires[80] ) , .Reset_E_in ( ResetWires[31] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_689 ) , + .Reset_W_out ( ResetWires[32] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_690 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[88] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_691 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[177] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[178] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_692 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_693 ) , + .clk_0_N_in ( clk_1_wires[88] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_695 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[45] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[45] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_697 } ) , + .ccff_head ( cby_1__1__37_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_49_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_49_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_49_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_49_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_49_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_49_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_49_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_49_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[44] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_698 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[44] ) , + .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[127] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_699 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_700 ) , + .SC_OUT_BOT ( scff_Wires[128] ) , .Test_en_E_in ( Test_enWires[53] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_701 ) , + .Test_en_W_out ( Test_enWires[54] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_702 ) , + .pReset_N_in ( pResetWires[129] ) , .Reset_E_in ( ResetWires[53] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_703 ) , + .Reset_W_out ( ResetWires[54] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_704 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_705 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[87] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[180] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[181] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_706 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_707 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_708 ) , + .clk_0_S_in ( clk_1_wires[87] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_709 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[46] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_710 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[46] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_711 } ) , + .ccff_head ( cby_1__1__38_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_50_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_50_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_50_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_50_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_50_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_50_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_50_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_50_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[45] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_712 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[45] ) , + .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[125] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_713 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_714 ) , + .SC_OUT_BOT ( scff_Wires[126] ) , .Test_en_E_in ( Test_enWires[75] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_715 ) , + .Test_en_W_out ( Test_enWires[76] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_716 ) , + .pReset_N_in ( pResetWires[178] ) , .Reset_E_in ( ResetWires[75] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_717 ) , + .Reset_W_out ( ResetWires[76] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_718 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[95] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_719 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[183] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[184] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_720 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_721 ) , + .clk_0_N_in ( clk_1_wires[95] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_723 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[47] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_724 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[47] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_725 } ) , + .ccff_head ( cby_1__1__39_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_51_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_51_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_51_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_51_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_51_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_51_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_51_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_51_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[46] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_726 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[46] ) , + .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[123] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_727 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_728 ) , + .SC_OUT_BOT ( scff_Wires[124] ) , .Test_en_E_in ( Test_enWires[97] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_729 ) , + .Test_en_W_out ( Test_enWires[98] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_730 ) , + .pReset_N_in ( pResetWires[227] ) , .Reset_E_in ( ResetWires[97] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_731 ) , + .Reset_W_out ( ResetWires[98] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_732 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_733 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[94] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[186] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[187] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_734 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_735 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_736 ) , + .clk_0_S_in ( clk_1_wires[94] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_737 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[48] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_738 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[48] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_739 } ) , + .ccff_head ( cby_1__1__40_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_52_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_52_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_52_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_52_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_52_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_52_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_52_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_52_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[47] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_740 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[47] ) , + .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[121] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_741 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_742 ) , + .SC_OUT_BOT ( scff_Wires[122] ) , .Test_en_E_in ( Test_enWires[119] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_743 ) , + .Test_en_W_out ( Test_enWires[120] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_744 ) , + .pReset_N_in ( pResetWires[276] ) , .Reset_E_in ( ResetWires[119] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_745 ) , + .Reset_W_out ( ResetWires[120] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_746 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[102] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_747 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[189] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[190] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_748 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_749 ) , + .clk_0_N_in ( clk_1_wires[102] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_751 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[49] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_752 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[49] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_753 } ) , + .ccff_head ( cby_1__1__41_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_53_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_53_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_53_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_53_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_53_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_53_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_53_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_53_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[48] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_754 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[48] ) , + .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[119] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_755 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_756 ) , + .SC_OUT_BOT ( scff_Wires[120] ) , .Test_en_E_in ( Test_enWires[141] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_757 ) , + .Test_en_W_out ( Test_enWires[142] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_758 ) , + .pReset_N_in ( pResetWires[325] ) , .Reset_E_in ( ResetWires[141] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_759 ) , + .Reset_W_out ( ResetWires[142] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_760 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_761 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[101] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[192] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[193] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_764 ) , + .clk_0_S_in ( clk_1_wires[101] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_765 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[50] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_766 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[50] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_767 } ) , + .ccff_head ( cby_1__1__42_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_54_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_54_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_54_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_54_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_54_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_54_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_54_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_54_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[49] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_768 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[49] ) , + .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[117] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_769 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_770 ) , + .SC_OUT_BOT ( scff_Wires[118] ) , .Test_en_E_in ( Test_enWires[163] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_771 ) , + .Test_en_W_out ( Test_enWires[164] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_772 ) , + .pReset_N_in ( pResetWires[374] ) , .Reset_E_in ( ResetWires[163] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_773 ) , + .Reset_W_out ( ResetWires[164] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_774 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[109] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_775 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[195] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[196] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_776 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_777 ) , + .clk_0_N_in ( clk_1_wires[109] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_779 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[51] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_780 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[51] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_781 } ) , + .ccff_head ( cby_1__1__43_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_55_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_55_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_55_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_55_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_55_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_55_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_55_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_55_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[50] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_782 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[50] ) , + .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires[115] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_783 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_784 ) , + .SC_OUT_BOT ( scff_Wires[116] ) , .Test_en_E_in ( Test_enWires[185] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_785 ) , + .Test_en_W_out ( Test_enWires[186] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_786 ) , + .pReset_N_in ( pResetWires[423] ) , .Reset_E_in ( ResetWires[185] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_787 ) , + .Reset_W_out ( ResetWires[186] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_788 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_789 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[108] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[198] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[199] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_790 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_791 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_792 ) , + .clk_0_S_in ( clk_1_wires[108] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_793 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[52] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_794 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[52] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_795 } ) , + .ccff_head ( cby_1__1__44_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_56_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_56_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_56_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_56_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_56_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_56_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_56_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_56_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[51] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_796 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[51] ) , + .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires[113] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_797 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_798 ) , + .SC_OUT_BOT ( scff_Wires[114] ) , .Test_en_E_in ( Test_enWires[207] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_799 ) , + .Test_en_W_out ( Test_enWires[208] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_800 ) , + .pReset_N_in ( pResetWires[472] ) , .Reset_E_in ( ResetWires[207] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_801 ) , + .Reset_W_out ( ResetWires[208] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_802 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[116] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_803 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[201] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[202] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_804 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_805 ) , + .clk_0_N_in ( clk_1_wires[116] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_807 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[53] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_808 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[53] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_809 } ) , + .ccff_head ( cby_1__1__45_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_57_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_57_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_57_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_57_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_57_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_57_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_57_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_57_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[52] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_810 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[52] ) , + .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires[111] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_811 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_812 ) , + .SC_OUT_BOT ( scff_Wires[112] ) , .Test_en_E_in ( Test_enWires[229] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_813 ) , + .Test_en_W_out ( Test_enWires[230] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_814 ) , + .pReset_N_in ( pResetWires[521] ) , .Reset_E_in ( ResetWires[229] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_815 ) , + .Reset_W_out ( ResetWires[230] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_816 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_817 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[115] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[204] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[205] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_818 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_819 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_820 ) , + .clk_0_S_in ( clk_1_wires[115] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_821 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[54] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_822 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[54] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_823 } ) , + .ccff_head ( cby_1__1__46_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_58_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_58_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_58_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_58_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_58_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_58_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_58_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_58_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[53] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_824 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[53] ) , + .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires[109] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_825 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_826 ) , + .SC_OUT_BOT ( scff_Wires[110] ) , .Test_en_E_in ( Test_enWires[251] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_827 ) , + .Test_en_W_out ( Test_enWires[252] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_828 ) , + .pReset_N_in ( pResetWires[570] ) , .Reset_E_in ( ResetWires[251] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_829 ) , + .Reset_W_out ( ResetWires[252] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_830 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[123] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_831 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[207] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[208] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_833 ) , + .clk_0_N_in ( clk_1_wires[123] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_835 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_836 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_837 } ) , + .ccff_head ( cby_1__1__47_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_59_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_59_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_59_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_59_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_59_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_59_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_59_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_59_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[54] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_838 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[54] ) , + .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires[107] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_839 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_840 ) , + .SC_OUT_BOT ( scff_Wires[108] ) , .Test_en_E_in ( Test_enWires[273] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_841 ) , + .Test_en_W_out ( Test_enWires[274] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_842 ) , + .pReset_N_in ( pResetWires[615] ) , .Reset_E_in ( ResetWires[273] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_843 ) , + .Reset_W_out ( ResetWires[274] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_844 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_845 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[122] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[210] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[211] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_846 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[213] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_847 ) , + .clk_0_S_in ( clk_1_wires[122] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_848 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[55] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_849 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[55] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_850 } ) , + .ccff_head ( cby_1__1__48_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_60_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_60_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_60_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_60_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_60_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_60_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_60_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_60_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_851 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_60_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_852 ) , .SC_IN_BOT ( scff_Wires[134] ) , + .SC_OUT_TOP ( scff_Wires[135] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_853 ) , + .Test_en_E_in ( Test_enWires[33] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_854 ) , + .Test_en_W_out ( Test_enWires[34] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_855 ) , + .pReset_N_in ( pResetWires[84] ) , .Reset_E_in ( ResetWires[33] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_856 ) , + .Reset_W_out ( ResetWires[34] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_857 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[90] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_858 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[215] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[216] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_859 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_860 ) , + .clk_0_N_in ( clk_1_wires[90] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_862 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[56] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_863 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[56] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_864 } ) , + .ccff_head ( cby_1__1__49_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_61_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_61_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_61_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_61_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_61_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_61_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_61_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_61_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[55] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_865 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[55] ) , + .ccff_tail ( grid_clb_61_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_866 ) , .SC_IN_BOT ( scff_Wires[136] ) , + .SC_OUT_TOP ( scff_Wires[137] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_867 ) , + .Test_en_E_in ( Test_enWires[55] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_868 ) , + .Test_en_W_out ( Test_enWires[56] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_869 ) , + .pReset_N_in ( pResetWires[133] ) , .Reset_E_in ( ResetWires[55] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_870 ) , + .Reset_W_out ( ResetWires[56] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_871 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_872 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[89] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[218] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[219] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_873 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_874 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_875 ) , + .clk_0_S_in ( clk_1_wires[89] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_876 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[57] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_877 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[57] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_878 } ) , + .ccff_head ( cby_1__1__50_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_62_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_62_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_62_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_62_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_62_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_62_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_62_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_62_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[56] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_879 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[56] ) , + .ccff_tail ( grid_clb_62_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_880 ) , .SC_IN_BOT ( scff_Wires[138] ) , + .SC_OUT_TOP ( scff_Wires[139] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_881 ) , + .Test_en_E_in ( Test_enWires[77] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_882 ) , + .Test_en_W_out ( Test_enWires[78] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_883 ) , + .pReset_N_in ( pResetWires[182] ) , .Reset_E_in ( ResetWires[77] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_884 ) , + .Reset_W_out ( ResetWires[78] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_885 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[97] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_886 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[221] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[222] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_887 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_888 ) , + .clk_0_N_in ( clk_1_wires[97] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_890 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[58] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_891 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[58] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_892 } ) , + .ccff_head ( cby_1__1__51_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_63_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_63_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_63_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_63_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_63_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_63_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_63_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_63_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[57] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_893 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[57] ) , + .ccff_tail ( grid_clb_63_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_894 ) , .SC_IN_BOT ( scff_Wires[140] ) , + .SC_OUT_TOP ( scff_Wires[141] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_895 ) , + .Test_en_E_in ( Test_enWires[99] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_896 ) , + .Test_en_W_out ( Test_enWires[100] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_897 ) , + .pReset_N_in ( pResetWires[231] ) , .Reset_E_in ( ResetWires[99] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_898 ) , + .Reset_W_out ( ResetWires[100] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_899 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_900 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[96] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[224] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[225] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_903 ) , + .clk_0_S_in ( clk_1_wires[96] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_904 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[59] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_905 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[59] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_906 } ) , + .ccff_head ( cby_1__1__52_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_64_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_64_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_64_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_64_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_64_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_64_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_64_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_64_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[58] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_907 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[58] ) , + .ccff_tail ( grid_clb_64_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_908 ) , .SC_IN_BOT ( scff_Wires[142] ) , + .SC_OUT_TOP ( scff_Wires[143] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_909 ) , + .Test_en_E_in ( Test_enWires[121] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_910 ) , + .Test_en_W_out ( Test_enWires[122] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_911 ) , + .pReset_N_in ( pResetWires[280] ) , .Reset_E_in ( ResetWires[121] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_912 ) , + .Reset_W_out ( ResetWires[122] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_913 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[104] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_914 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[227] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[228] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_915 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_916 ) , + .clk_0_N_in ( clk_1_wires[104] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_918 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[60] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_919 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[60] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_920 } ) , + .ccff_head ( cby_1__1__53_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_65_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_65_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_65_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_65_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_65_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_65_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_65_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_65_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[59] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_921 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[59] ) , + .ccff_tail ( grid_clb_65_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_922 ) , .SC_IN_BOT ( scff_Wires[144] ) , + .SC_OUT_TOP ( scff_Wires[145] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_923 ) , + .Test_en_E_in ( Test_enWires[143] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_924 ) , + .Test_en_W_out ( Test_enWires[144] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_925 ) , + .pReset_N_in ( pResetWires[329] ) , .Reset_E_in ( ResetWires[143] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_926 ) , + .Reset_W_out ( ResetWires[144] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_927 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_928 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[103] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[230] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[231] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_929 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_930 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_931 ) , + .clk_0_S_in ( clk_1_wires[103] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_932 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[61] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_933 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[61] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_934 } ) , + .ccff_head ( cby_1__1__54_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_66_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_66_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_66_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_66_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_66_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_66_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_66_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_66_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[60] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_935 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[60] ) , + .ccff_tail ( grid_clb_66_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_936 ) , .SC_IN_BOT ( scff_Wires[146] ) , + .SC_OUT_TOP ( scff_Wires[147] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_937 ) , + .Test_en_E_in ( Test_enWires[165] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_938 ) , + .Test_en_W_out ( Test_enWires[166] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_939 ) , + .pReset_N_in ( pResetWires[378] ) , .Reset_E_in ( ResetWires[165] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_940 ) , + .Reset_W_out ( ResetWires[166] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_941 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[111] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_942 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[233] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[234] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_943 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_944 ) , + .clk_0_N_in ( clk_1_wires[111] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_946 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[62] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_947 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[62] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_948 } ) , + .ccff_head ( cby_1__1__55_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_67_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_67_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_67_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_67_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_67_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_67_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_67_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_67_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[61] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_949 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[61] ) , + .ccff_tail ( grid_clb_67_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_950 ) , .SC_IN_BOT ( scff_Wires[148] ) , + .SC_OUT_TOP ( scff_Wires[149] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_951 ) , + .Test_en_E_in ( Test_enWires[187] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_952 ) , + .Test_en_W_out ( Test_enWires[188] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_953 ) , + .pReset_N_in ( pResetWires[427] ) , .Reset_E_in ( ResetWires[187] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_954 ) , + .Reset_W_out ( ResetWires[188] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_955 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_956 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[110] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[236] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[237] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_957 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_958 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_959 ) , + .clk_0_S_in ( clk_1_wires[110] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_960 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[63] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_961 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[63] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_962 } ) , + .ccff_head ( cby_1__1__56_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_68_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_68_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_68_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_68_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_68_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_68_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_68_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_68_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[62] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_963 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[62] ) , + .ccff_tail ( grid_clb_68_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_964 ) , .SC_IN_BOT ( scff_Wires[150] ) , + .SC_OUT_TOP ( scff_Wires[151] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_965 ) , + .Test_en_E_in ( Test_enWires[209] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_966 ) , + .Test_en_W_out ( Test_enWires[210] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_967 ) , + .pReset_N_in ( pResetWires[476] ) , .Reset_E_in ( ResetWires[209] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_968 ) , + .Reset_W_out ( ResetWires[210] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_969 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[118] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_970 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[239] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[240] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_971 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_972 ) , + .clk_0_N_in ( clk_1_wires[118] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_974 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[64] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_975 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[64] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_976 } ) , + .ccff_head ( cby_1__1__57_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_69_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_69_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_69_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_69_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_69_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_69_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_69_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_69_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[63] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_977 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[63] ) , + .ccff_tail ( grid_clb_69_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_978 ) , .SC_IN_BOT ( scff_Wires[152] ) , + .SC_OUT_TOP ( scff_Wires[153] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_979 ) , + .Test_en_E_in ( Test_enWires[231] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_980 ) , + .Test_en_W_out ( Test_enWires[232] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_981 ) , + .pReset_N_in ( pResetWires[525] ) , .Reset_E_in ( ResetWires[231] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_982 ) , + .Reset_W_out ( ResetWires[232] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_983 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_984 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[117] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[242] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[243] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_985 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_986 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_987 ) , + .clk_0_S_in ( clk_1_wires[117] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_988 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[65] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_989 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[65] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_990 } ) , + .ccff_head ( cby_1__1__58_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_70_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_70_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_70_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_70_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_70_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_70_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_70_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_70_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[64] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_991 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[64] ) , + .ccff_tail ( grid_clb_70_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_992 ) , .SC_IN_BOT ( scff_Wires[154] ) , + .SC_OUT_TOP ( scff_Wires[155] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_993 ) , + .Test_en_E_in ( Test_enWires[253] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_994 ) , + .Test_en_W_out ( Test_enWires[254] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_995 ) , + .pReset_N_in ( pResetWires[574] ) , .Reset_E_in ( ResetWires[253] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_996 ) , + .Reset_W_out ( ResetWires[254] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_997 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[125] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_998 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[245] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[246] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_999 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1000 ) , + .clk_0_N_in ( clk_1_wires[125] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1002 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1003 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1004 } ) , + .ccff_head ( cby_1__1__59_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_71_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_71_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_71_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_71_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_71_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_71_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_71_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_71_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[65] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1005 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[65] ) , + .ccff_tail ( grid_clb_71_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1006 ) , + .SC_IN_BOT ( scff_Wires[156] ) , .SC_OUT_TOP ( scff_Wires[157] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1007 ) , + .Test_en_E_in ( Test_enWires[275] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_1008 ) , + .Test_en_W_out ( Test_enWires[276] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1009 ) , + .pReset_N_in ( pResetWires[618] ) , .Reset_E_in ( ResetWires[275] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_1010 ) , + .Reset_W_out ( ResetWires[276] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1011 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1012 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[124] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[248] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[249] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1013 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[251] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1014 ) , + .clk_0_S_in ( clk_1_wires[124] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1015 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[66] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1016 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[66] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1017 } ) , + .ccff_head ( cby_1__1__60_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_72_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_72_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_72_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_72_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_72_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_72_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_72_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_72_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1018 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[182] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1019 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1020 ) , + .SC_OUT_BOT ( scff_Wires[184] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1021 ) , + .Test_en_W_in ( Test_enWires[35] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1022 ) , + .Test_en_E_out ( Test_enWires[36] ) , .pReset_N_in ( pResetWires[88] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1023 ) , + .Reset_W_in ( ResetWires[35] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1024 ) , + .Reset_E_out ( ResetWires[36] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[130] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1025 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[253] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[254] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1026 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1027 ) , + .clk_0_N_in ( clk_1_wires[130] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1029 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[67] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1030 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[67] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1031 } ) , + .ccff_head ( cby_1__1__61_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_73_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_73_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_73_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_73_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_73_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_73_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_73_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_73_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[66] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1032 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[66] ) , + .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[180] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1033 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1034 ) , + .SC_OUT_BOT ( scff_Wires[181] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1035 ) , + .Test_en_W_in ( Test_enWires[57] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1036 ) , + .Test_en_E_out ( Test_enWires[58] ) , .pReset_N_in ( pResetWires[137] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1037 ) , + .Reset_W_in ( ResetWires[57] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1038 ) , + .Reset_E_out ( ResetWires[58] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1039 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[129] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[256] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[257] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1042 ) , + .clk_0_S_in ( clk_1_wires[129] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1043 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[68] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1044 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[68] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1045 } ) , + .ccff_head ( cby_1__1__62_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_74_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_74_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_74_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_74_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_74_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_74_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_74_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_74_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[67] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1046 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[67] ) , + .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[178] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1047 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1048 ) , + .SC_OUT_BOT ( scff_Wires[179] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1049 ) , + .Test_en_W_in ( Test_enWires[79] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1050 ) , + .Test_en_E_out ( Test_enWires[80] ) , .pReset_N_in ( pResetWires[186] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1051 ) , + .Reset_W_in ( ResetWires[79] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1052 ) , + .Reset_E_out ( ResetWires[80] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[137] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1053 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[259] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[260] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1054 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1055 ) , + .clk_0_N_in ( clk_1_wires[137] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1057 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[69] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1058 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[69] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1059 } ) , + .ccff_head ( cby_1__1__63_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_75_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_75_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_75_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_75_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_75_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_75_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_75_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_75_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[68] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1060 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[68] ) , + .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[176] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1061 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1062 ) , + .SC_OUT_BOT ( scff_Wires[177] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1063 ) , + .Test_en_W_in ( Test_enWires[101] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1064 ) , + .Test_en_E_out ( Test_enWires[102] ) , .pReset_N_in ( pResetWires[235] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1065 ) , + .Reset_W_in ( ResetWires[101] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1066 ) , + .Reset_E_out ( ResetWires[102] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1067 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[136] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[262] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[263] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1068 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1069 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1070 ) , + .clk_0_S_in ( clk_1_wires[136] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1071 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[70] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1072 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[70] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1073 } ) , + .ccff_head ( cby_1__1__64_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_76_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_76_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_76_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_76_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_76_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_76_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_76_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_76_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[69] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1074 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[69] ) , + .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[174] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1075 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1076 ) , + .SC_OUT_BOT ( scff_Wires[175] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1077 ) , + .Test_en_W_in ( Test_enWires[123] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1078 ) , + .Test_en_E_out ( Test_enWires[124] ) , .pReset_N_in ( pResetWires[284] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1079 ) , + .Reset_W_in ( ResetWires[123] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1080 ) , + .Reset_E_out ( ResetWires[124] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[144] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1081 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[265] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[266] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1082 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1083 ) , + .clk_0_N_in ( clk_1_wires[144] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1085 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[71] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1086 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[71] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1087 } ) , + .ccff_head ( cby_1__1__65_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_77_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_77_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_77_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_77_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_77_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_77_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_77_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_77_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[70] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1088 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[70] ) , + .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires[172] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1089 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1090 ) , + .SC_OUT_BOT ( scff_Wires[173] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1091 ) , + .Test_en_W_in ( Test_enWires[145] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1092 ) , + .Test_en_E_out ( Test_enWires[146] ) , .pReset_N_in ( pResetWires[333] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1093 ) , + .Reset_W_in ( ResetWires[145] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1094 ) , + .Reset_E_out ( ResetWires[146] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1095 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[143] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[268] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[269] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1096 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1097 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1098 ) , + .clk_0_S_in ( clk_1_wires[143] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1099 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[72] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1100 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[72] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1101 } ) , + .ccff_head ( cby_1__1__66_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_78_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_78_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_78_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_78_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_78_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_78_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_78_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_78_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[71] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1102 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[71] ) , + .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires[170] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1103 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1104 ) , + .SC_OUT_BOT ( scff_Wires[171] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1105 ) , + .Test_en_W_in ( Test_enWires[167] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1106 ) , + .Test_en_E_out ( Test_enWires[168] ) , .pReset_N_in ( pResetWires[382] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1107 ) , + .Reset_W_in ( ResetWires[167] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1108 ) , + .Reset_E_out ( ResetWires[168] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[151] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1109 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[271] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[272] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1110 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1111 ) , + .clk_0_N_in ( clk_1_wires[151] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1113 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[73] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1114 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[73] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1115 } ) , + .ccff_head ( cby_1__1__67_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_79_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_79_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_79_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_79_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_79_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_79_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_79_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_79_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[72] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1116 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[72] ) , + .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires[168] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1117 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1118 ) , + .SC_OUT_BOT ( scff_Wires[169] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1119 ) , + .Test_en_W_in ( Test_enWires[189] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1120 ) , + .Test_en_E_out ( Test_enWires[190] ) , .pReset_N_in ( pResetWires[431] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1121 ) , + .Reset_W_in ( ResetWires[189] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1122 ) , + .Reset_E_out ( ResetWires[190] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1123 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[150] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[274] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[275] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1124 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1125 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1126 ) , + .clk_0_S_in ( clk_1_wires[150] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1127 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[74] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1128 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[74] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1129 } ) , + .ccff_head ( cby_1__1__68_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_80_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_80_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_80_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_80_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_80_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_80_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_80_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_80_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[73] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1130 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[73] ) , + .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires[166] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1131 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1132 ) , + .SC_OUT_BOT ( scff_Wires[167] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1133 ) , + .Test_en_W_in ( Test_enWires[211] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1134 ) , + .Test_en_E_out ( Test_enWires[212] ) , .pReset_N_in ( pResetWires[480] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1135 ) , + .Reset_W_in ( ResetWires[211] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1136 ) , + .Reset_E_out ( ResetWires[212] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[158] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1137 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[277] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[278] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1138 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1139 ) , + .clk_0_N_in ( clk_1_wires[158] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1141 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[75] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1142 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[75] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1143 } ) , + .ccff_head ( cby_1__1__69_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_81_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_81_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_81_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_81_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_81_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_81_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_81_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_81_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[74] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1144 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[74] ) , + .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires[164] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1145 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1146 ) , + .SC_OUT_BOT ( scff_Wires[165] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1147 ) , + .Test_en_W_in ( Test_enWires[233] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1148 ) , + .Test_en_E_out ( Test_enWires[234] ) , .pReset_N_in ( pResetWires[529] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1149 ) , + .Reset_W_in ( ResetWires[233] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1150 ) , + .Reset_E_out ( ResetWires[234] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1151 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[157] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[280] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[281] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1152 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1153 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1154 ) , + .clk_0_S_in ( clk_1_wires[157] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1155 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[76] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1156 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[76] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1157 } ) , + .ccff_head ( cby_1__1__70_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_82_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_82_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_82_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_82_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_82_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_82_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_82_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_82_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[75] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1158 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[75] ) , + .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires[162] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1159 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1160 ) , + .SC_OUT_BOT ( scff_Wires[163] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1161 ) , + .Test_en_W_in ( Test_enWires[255] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1162 ) , + .Test_en_E_out ( Test_enWires[256] ) , .pReset_N_in ( pResetWires[578] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1163 ) , + .Reset_W_in ( ResetWires[255] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1164 ) , + .Reset_E_out ( ResetWires[256] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[165] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1165 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[283] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[284] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1166 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1167 ) , + .clk_0_N_in ( clk_1_wires[165] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1169 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1170 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1171 } ) , + .ccff_head ( cby_1__1__71_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_83_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_83_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_83_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_83_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_83_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_83_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_83_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_83_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[76] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1172 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[76] ) , + .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires[160] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1173 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1174 ) , + .SC_OUT_BOT ( scff_Wires[161] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1175 ) , + .Test_en_W_in ( Test_enWires[277] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1176 ) , + .Test_en_E_out ( Test_enWires[278] ) , .pReset_N_in ( pResetWires[621] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1177 ) , + .Reset_W_in ( ResetWires[277] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1178 ) , + .Reset_E_out ( ResetWires[278] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1179 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[164] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[286] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[287] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1180 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[289] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1181 ) , + .clk_0_S_in ( clk_1_wires[164] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1182 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[77] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1183 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[77] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1184 } ) , + .ccff_head ( cby_1__1__72_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_84_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_84_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_84_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_84_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_84_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_84_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_84_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_84_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1185 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_84_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1186 ) , + .SC_IN_BOT ( scff_Wires[187] ) , .SC_OUT_TOP ( scff_Wires[188] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1187 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1188 ) , + .Test_en_W_in ( Test_enWires[37] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1189 ) , + .Test_en_E_out ( Test_enWires[38] ) , .pReset_N_in ( pResetWires[92] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1190 ) , + .Reset_W_in ( ResetWires[37] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1191 ) , + .Reset_E_out ( ResetWires[38] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[132] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1192 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[291] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[292] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1193 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1194 ) , + .clk_0_N_in ( clk_1_wires[132] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1196 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[78] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1197 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[78] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1198 } ) , + .ccff_head ( cby_1__1__73_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_85_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_85_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_85_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_85_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_85_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_85_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_85_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_85_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[77] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1199 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[77] ) , + .ccff_tail ( grid_clb_85_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1200 ) , + .SC_IN_BOT ( scff_Wires[189] ) , .SC_OUT_TOP ( scff_Wires[190] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1201 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1202 ) , + .Test_en_W_in ( Test_enWires[59] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1203 ) , + .Test_en_E_out ( Test_enWires[60] ) , .pReset_N_in ( pResetWires[141] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1204 ) , + .Reset_W_in ( ResetWires[59] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1205 ) , + .Reset_E_out ( ResetWires[60] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1206 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[131] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[294] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[295] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1207 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1208 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1209 ) , + .clk_0_S_in ( clk_1_wires[131] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1210 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[79] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1211 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[79] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1212 } ) , + .ccff_head ( cby_1__1__74_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_86_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_86_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_86_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_86_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_86_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_86_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_86_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_86_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[78] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1213 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[78] ) , + .ccff_tail ( grid_clb_86_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1214 ) , + .SC_IN_BOT ( scff_Wires[191] ) , .SC_OUT_TOP ( scff_Wires[192] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1215 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1216 ) , + .Test_en_W_in ( Test_enWires[81] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1217 ) , + .Test_en_E_out ( Test_enWires[82] ) , .pReset_N_in ( pResetWires[190] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1218 ) , + .Reset_W_in ( ResetWires[81] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1219 ) , + .Reset_E_out ( ResetWires[82] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[139] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1220 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[297] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[298] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1221 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1222 ) , + .clk_0_N_in ( clk_1_wires[139] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1224 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[80] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1225 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[80] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1226 } ) , + .ccff_head ( cby_1__1__75_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_87_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_87_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_87_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_87_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_87_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_87_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_87_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_87_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[79] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1227 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[79] ) , + .ccff_tail ( grid_clb_87_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1228 ) , + .SC_IN_BOT ( scff_Wires[193] ) , .SC_OUT_TOP ( scff_Wires[194] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1229 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1230 ) , + .Test_en_W_in ( Test_enWires[103] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1231 ) , + .Test_en_E_out ( Test_enWires[104] ) , .pReset_N_in ( pResetWires[239] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1232 ) , + .Reset_W_in ( ResetWires[103] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1233 ) , + .Reset_E_out ( ResetWires[104] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1234 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[138] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[300] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[301] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1235 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1236 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1237 ) , + .clk_0_S_in ( clk_1_wires[138] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1238 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[81] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1239 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[81] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1240 } ) , + .ccff_head ( cby_1__1__76_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_88_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_88_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_88_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_88_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_88_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_88_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_88_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_88_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[80] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1241 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[80] ) , + .ccff_tail ( grid_clb_88_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1242 ) , + .SC_IN_BOT ( scff_Wires[195] ) , .SC_OUT_TOP ( scff_Wires[196] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1243 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1244 ) , + .Test_en_W_in ( Test_enWires[125] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1245 ) , + .Test_en_E_out ( Test_enWires[126] ) , .pReset_N_in ( pResetWires[288] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1246 ) , + .Reset_W_in ( ResetWires[125] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1247 ) , + .Reset_E_out ( ResetWires[126] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[146] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1248 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[303] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[304] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1249 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1250 ) , + .clk_0_N_in ( clk_1_wires[146] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1252 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[82] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1253 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[82] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1254 } ) , + .ccff_head ( cby_1__1__77_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_89_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_89_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_89_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_89_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_89_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_89_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_89_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_89_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[81] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1255 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[81] ) , + .ccff_tail ( grid_clb_89_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1256 ) , + .SC_IN_BOT ( scff_Wires[197] ) , .SC_OUT_TOP ( scff_Wires[198] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1257 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1258 ) , + .Test_en_W_in ( Test_enWires[147] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1259 ) , + .Test_en_E_out ( Test_enWires[148] ) , .pReset_N_in ( pResetWires[337] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1260 ) , + .Reset_W_in ( ResetWires[147] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1261 ) , + .Reset_E_out ( ResetWires[148] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1262 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[145] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[306] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[307] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1263 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1264 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1265 ) , + .clk_0_S_in ( clk_1_wires[145] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1266 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[83] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1267 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[83] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1268 } ) , + .ccff_head ( cby_1__1__78_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_90_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_90_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_90_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_90_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_90_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_90_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_90_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_90_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[82] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1269 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[82] ) , + .ccff_tail ( grid_clb_90_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1270 ) , + .SC_IN_BOT ( scff_Wires[199] ) , .SC_OUT_TOP ( scff_Wires[200] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1272 ) , + .Test_en_W_in ( Test_enWires[169] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1273 ) , + .Test_en_E_out ( Test_enWires[170] ) , .pReset_N_in ( pResetWires[386] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1274 ) , + .Reset_W_in ( ResetWires[169] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1275 ) , + .Reset_E_out ( ResetWires[170] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[153] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1276 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[309] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[310] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1277 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1278 ) , + .clk_0_N_in ( clk_1_wires[153] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1280 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[84] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1281 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[84] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1282 } ) , + .ccff_head ( cby_1__1__79_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_91_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_91_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_91_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_91_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_91_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_91_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_91_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_91_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[83] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1283 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[83] ) , + .ccff_tail ( grid_clb_91_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1284 ) , + .SC_IN_BOT ( scff_Wires[201] ) , .SC_OUT_TOP ( scff_Wires[202] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1285 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1286 ) , + .Test_en_W_in ( Test_enWires[191] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1287 ) , + .Test_en_E_out ( Test_enWires[192] ) , .pReset_N_in ( pResetWires[435] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1288 ) , + .Reset_W_in ( ResetWires[191] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1289 ) , + .Reset_E_out ( ResetWires[192] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1290 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[152] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[312] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[313] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1291 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1292 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1293 ) , + .clk_0_S_in ( clk_1_wires[152] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1294 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[85] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1295 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[85] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1296 } ) , + .ccff_head ( cby_1__1__80_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_92_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_92_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_92_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_92_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_92_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_92_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_92_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_92_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[84] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1297 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[84] ) , + .ccff_tail ( grid_clb_92_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1298 ) , + .SC_IN_BOT ( scff_Wires[203] ) , .SC_OUT_TOP ( scff_Wires[204] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1299 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1300 ) , + .Test_en_W_in ( Test_enWires[213] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1301 ) , + .Test_en_E_out ( Test_enWires[214] ) , .pReset_N_in ( pResetWires[484] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1302 ) , + .Reset_W_in ( ResetWires[213] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1303 ) , + .Reset_E_out ( ResetWires[214] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[160] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1304 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[315] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[316] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1305 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1306 ) , + .clk_0_N_in ( clk_1_wires[160] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1308 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[86] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1309 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[86] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1310 } ) , + .ccff_head ( cby_1__1__81_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_93_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_93_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_93_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_93_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_93_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_93_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_93_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_93_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[85] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1311 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[85] ) , + .ccff_tail ( grid_clb_93_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1312 ) , + .SC_IN_BOT ( scff_Wires[205] ) , .SC_OUT_TOP ( scff_Wires[206] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1313 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1314 ) , + .Test_en_W_in ( Test_enWires[235] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1315 ) , + .Test_en_E_out ( Test_enWires[236] ) , .pReset_N_in ( pResetWires[533] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1316 ) , + .Reset_W_in ( ResetWires[235] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1317 ) , + .Reset_E_out ( ResetWires[236] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1318 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[159] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[318] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[319] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1319 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1320 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1321 ) , + .clk_0_S_in ( clk_1_wires[159] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1322 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[87] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1323 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[87] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1324 } ) , + .ccff_head ( cby_1__1__82_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_94_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_94_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_94_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_94_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_94_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_94_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_94_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_94_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[86] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1325 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[86] ) , + .ccff_tail ( grid_clb_94_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1326 ) , + .SC_IN_BOT ( scff_Wires[207] ) , .SC_OUT_TOP ( scff_Wires[208] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1327 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1328 ) , + .Test_en_W_in ( Test_enWires[257] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1329 ) , + .Test_en_E_out ( Test_enWires[258] ) , .pReset_N_in ( pResetWires[582] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1330 ) , + .Reset_W_in ( ResetWires[257] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1331 ) , + .Reset_E_out ( ResetWires[258] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[167] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1332 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[321] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[322] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1333 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1334 ) , + .clk_0_N_in ( clk_1_wires[167] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1336 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1337 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1338 } ) , + .ccff_head ( cby_1__1__83_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_95_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_95_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_95_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_95_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_95_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_95_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_95_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_95_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[87] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1339 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[87] ) , + .ccff_tail ( grid_clb_95_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1340 ) , + .SC_IN_BOT ( scff_Wires[209] ) , .SC_OUT_TOP ( scff_Wires[210] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1341 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1342 ) , + .Test_en_W_in ( Test_enWires[279] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1343 ) , + .Test_en_E_out ( Test_enWires[280] ) , .pReset_N_in ( pResetWires[624] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1344 ) , + .Reset_W_in ( ResetWires[279] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1345 ) , + .Reset_E_out ( ResetWires[280] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1346 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[166] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[324] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[325] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1347 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[327] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1348 ) , + .clk_0_S_in ( clk_1_wires[166] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1349 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[88] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1350 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[88] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1351 } ) , + .ccff_head ( cby_1__1__84_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_96_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_96_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_96_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_96_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_96_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_96_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_96_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_96_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1352 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[235] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1353 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1354 ) , + .SC_OUT_BOT ( scff_Wires[237] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1355 ) , + .Test_en_W_in ( Test_enWires[39] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1356 ) , + .Test_en_E_out ( Test_enWires[40] ) , .pReset_N_in ( pResetWires[96] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1357 ) , + .Reset_W_in ( ResetWires[39] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1358 ) , + .Reset_E_out ( ResetWires[40] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[172] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1359 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[329] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[330] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1360 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1361 ) , + .clk_0_N_in ( clk_1_wires[172] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1363 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[89] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1364 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[89] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1365 } ) , + .ccff_head ( cby_1__1__85_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_97_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_97_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_97_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_97_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_97_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_97_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_97_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_97_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[88] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1366 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[88] ) , + .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[233] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1367 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1368 ) , + .SC_OUT_BOT ( scff_Wires[234] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1369 ) , + .Test_en_W_in ( Test_enWires[61] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1370 ) , + .Test_en_E_out ( Test_enWires[62] ) , .pReset_N_in ( pResetWires[145] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1371 ) , + .Reset_W_in ( ResetWires[61] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1372 ) , + .Reset_E_out ( ResetWires[62] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1373 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[171] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[332] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[333] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1374 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1375 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1376 ) , + .clk_0_S_in ( clk_1_wires[171] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1377 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[90] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1378 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[90] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1379 } ) , + .ccff_head ( cby_1__1__86_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_98_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_98_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_98_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_98_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_98_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_98_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_98_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_98_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[89] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1380 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[89] ) , + .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[231] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1381 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1382 ) , + .SC_OUT_BOT ( scff_Wires[232] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1383 ) , + .Test_en_W_in ( Test_enWires[83] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1384 ) , + .Test_en_E_out ( Test_enWires[84] ) , .pReset_N_in ( pResetWires[194] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1385 ) , + .Reset_W_in ( ResetWires[83] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1386 ) , + .Reset_E_out ( ResetWires[84] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[179] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1387 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[335] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[336] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1388 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1389 ) , + .clk_0_N_in ( clk_1_wires[179] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1391 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[91] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1392 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[91] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1393 } ) , + .ccff_head ( cby_1__1__87_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_99_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_99_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_99_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_99_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_99_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_99_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_99_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_99_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[90] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1394 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[90] ) , + .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires[229] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1395 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1396 ) , + .SC_OUT_BOT ( scff_Wires[230] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1397 ) , + .Test_en_W_in ( Test_enWires[105] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1398 ) , + .Test_en_E_out ( Test_enWires[106] ) , .pReset_N_in ( pResetWires[243] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1399 ) , + .Reset_W_in ( ResetWires[105] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1400 ) , + .Reset_E_out ( ResetWires[106] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1401 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[178] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[338] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[339] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1402 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1403 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1404 ) , + .clk_0_S_in ( clk_1_wires[178] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1405 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[92] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1406 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[92] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1407 } ) , + .ccff_head ( cby_1__1__88_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_100_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_100_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_100_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_100_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_100_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_100_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_100_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_100_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[91] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1408 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[91] ) , + .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires[227] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1409 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1410 ) , + .SC_OUT_BOT ( scff_Wires[228] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1411 ) , + .Test_en_W_in ( Test_enWires[127] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1412 ) , + .Test_en_E_out ( Test_enWires[128] ) , .pReset_N_in ( pResetWires[292] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1413 ) , + .Reset_W_in ( ResetWires[127] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1414 ) , + .Reset_E_out ( ResetWires[128] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[186] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1415 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[341] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[342] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1416 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1417 ) , + .clk_0_N_in ( clk_1_wires[186] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1419 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[93] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1420 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[93] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1421 } ) , + .ccff_head ( cby_1__1__89_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_101_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_101_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_101_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_101_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_101_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_101_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_101_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_101_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[92] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1422 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[92] ) , + .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires[225] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1423 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1424 ) , + .SC_OUT_BOT ( scff_Wires[226] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1425 ) , + .Test_en_W_in ( Test_enWires[149] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1426 ) , + .Test_en_E_out ( Test_enWires[150] ) , .pReset_N_in ( pResetWires[341] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1427 ) , + .Reset_W_in ( ResetWires[149] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1428 ) , + .Reset_E_out ( ResetWires[150] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1429 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[185] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[344] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[345] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1430 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1431 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1432 ) , + .clk_0_S_in ( clk_1_wires[185] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1433 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[94] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1434 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[94] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1435 } ) , + .ccff_head ( cby_1__1__90_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_102_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_102_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_102_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_102_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_102_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_102_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_102_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_102_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[93] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1436 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[93] ) , + .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires[223] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1437 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1438 ) , + .SC_OUT_BOT ( scff_Wires[224] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1439 ) , + .Test_en_W_in ( Test_enWires[171] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1440 ) , + .Test_en_E_out ( Test_enWires[172] ) , .pReset_N_in ( pResetWires[390] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1441 ) , + .Reset_W_in ( ResetWires[171] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1442 ) , + .Reset_E_out ( ResetWires[172] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[193] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1443 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[347] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[348] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1444 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1445 ) , + .clk_0_N_in ( clk_1_wires[193] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1447 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[95] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1448 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[95] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1449 } ) , + .ccff_head ( cby_1__1__91_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_103_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_103_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_103_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_103_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_103_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_103_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_103_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_103_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[94] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1450 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[94] ) , + .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires[221] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1451 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1452 ) , + .SC_OUT_BOT ( scff_Wires[222] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1453 ) , + .Test_en_W_in ( Test_enWires[193] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1454 ) , + .Test_en_E_out ( Test_enWires[194] ) , .pReset_N_in ( pResetWires[439] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1455 ) , + .Reset_W_in ( ResetWires[193] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1456 ) , + .Reset_E_out ( ResetWires[194] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1457 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[192] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[350] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[351] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1458 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1459 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1460 ) , + .clk_0_S_in ( clk_1_wires[192] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1461 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[96] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1462 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[96] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1463 } ) , + .ccff_head ( cby_1__1__92_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_104_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_104_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_104_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_104_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_104_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_104_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_104_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_104_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[95] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1464 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[95] ) , + .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires[219] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1465 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1466 ) , + .SC_OUT_BOT ( scff_Wires[220] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1467 ) , + .Test_en_W_in ( Test_enWires[215] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1468 ) , + .Test_en_E_out ( Test_enWires[216] ) , .pReset_N_in ( pResetWires[488] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1469 ) , + .Reset_W_in ( ResetWires[215] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1470 ) , + .Reset_E_out ( ResetWires[216] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[200] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1471 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[353] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[354] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1472 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1473 ) , + .clk_0_N_in ( clk_1_wires[200] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1475 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[97] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1476 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[97] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1477 } ) , + .ccff_head ( cby_1__1__93_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_105_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_105_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_105_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_105_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_105_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_105_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_105_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_105_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[96] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1478 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[96] ) , + .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires[217] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1479 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1480 ) , + .SC_OUT_BOT ( scff_Wires[218] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1481 ) , + .Test_en_W_in ( Test_enWires[237] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1482 ) , + .Test_en_E_out ( Test_enWires[238] ) , .pReset_N_in ( pResetWires[537] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1483 ) , + .Reset_W_in ( ResetWires[237] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1484 ) , + .Reset_E_out ( ResetWires[238] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1485 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[199] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[356] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[357] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1486 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1487 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1488 ) , + .clk_0_S_in ( clk_1_wires[199] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1489 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[98] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1490 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[98] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1491 } ) , + .ccff_head ( cby_1__1__94_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_106_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_106_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_106_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_106_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_106_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_106_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_106_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_106_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[97] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1492 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[97] ) , + .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires[215] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1493 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1494 ) , + .SC_OUT_BOT ( scff_Wires[216] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1495 ) , + .Test_en_W_in ( Test_enWires[259] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1496 ) , + .Test_en_E_out ( Test_enWires[260] ) , .pReset_N_in ( pResetWires[586] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1497 ) , + .Reset_W_in ( ResetWires[259] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1498 ) , + .Reset_E_out ( ResetWires[260] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[207] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1499 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[359] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[360] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1500 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1501 ) , + .clk_0_N_in ( clk_1_wires[207] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1503 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1504 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1505 } ) , + .ccff_head ( cby_1__1__95_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_107_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_107_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_107_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_107_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_107_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_107_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_107_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_107_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[98] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1506 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[98] ) , + .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires[213] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1507 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1508 ) , + .SC_OUT_BOT ( scff_Wires[214] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1509 ) , + .Test_en_W_in ( Test_enWires[281] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1510 ) , + .Test_en_E_out ( Test_enWires[282] ) , .pReset_N_in ( pResetWires[627] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1511 ) , + .Reset_W_in ( ResetWires[281] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1512 ) , + .Reset_E_out ( ResetWires[282] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1513 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[206] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[362] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[363] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1514 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[365] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1515 ) , + .clk_0_S_in ( clk_1_wires[206] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1516 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[99] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1517 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[99] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1518 } ) , + .ccff_head ( cby_1__1__96_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_108_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_108_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_108_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_108_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_108_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_108_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_108_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_108_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1519 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_108_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1520 ) , + .SC_IN_BOT ( scff_Wires[240] ) , .SC_OUT_TOP ( scff_Wires[241] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1521 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1522 ) , + .Test_en_W_in ( Test_enWires[41] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1523 ) , + .Test_en_E_out ( Test_enWires[42] ) , .pReset_N_in ( pResetWires[100] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1524 ) , + .Reset_W_in ( ResetWires[41] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1525 ) , + .Reset_E_out ( ResetWires[42] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[174] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1526 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[367] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[368] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1527 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1528 ) , + .clk_0_N_in ( clk_1_wires[174] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1530 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[100] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1531 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[100] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1532 } ) , + .ccff_head ( cby_1__1__97_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_109_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_109_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_109_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_109_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_109_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_109_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_109_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_109_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[99] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1533 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[99] ) , + .ccff_tail ( grid_clb_109_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1534 ) , + .SC_IN_BOT ( scff_Wires[242] ) , .SC_OUT_TOP ( scff_Wires[243] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1535 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1536 ) , + .Test_en_W_in ( Test_enWires[63] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1537 ) , + .Test_en_E_out ( Test_enWires[64] ) , .pReset_N_in ( pResetWires[149] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1538 ) , + .Reset_W_in ( ResetWires[63] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1539 ) , + .Reset_E_out ( ResetWires[64] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1540 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[173] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[370] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[371] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1541 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1542 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1543 ) , + .clk_0_S_in ( clk_1_wires[173] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1544 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[101] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1545 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[101] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1546 } ) , + .ccff_head ( cby_1__1__98_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_110_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_110_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_110_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_110_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_110_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_110_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_110_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_110_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[100] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1547 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[100] ) , + .ccff_tail ( grid_clb_110_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1548 ) , + .SC_IN_BOT ( scff_Wires[244] ) , .SC_OUT_TOP ( scff_Wires[245] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1549 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1550 ) , + .Test_en_W_in ( Test_enWires[85] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1551 ) , + .Test_en_E_out ( Test_enWires[86] ) , .pReset_N_in ( pResetWires[198] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1552 ) , + .Reset_W_in ( ResetWires[85] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1553 ) , + .Reset_E_out ( ResetWires[86] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[181] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1554 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[373] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[374] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1555 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1556 ) , + .clk_0_N_in ( clk_1_wires[181] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1558 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[102] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1559 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[102] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1560 } ) , + .ccff_head ( cby_1__1__99_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_111_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_111_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_111_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_111_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_111_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_111_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_111_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_111_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[101] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1561 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[101] ) , + .ccff_tail ( grid_clb_111_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1562 ) , + .SC_IN_BOT ( scff_Wires[246] ) , .SC_OUT_TOP ( scff_Wires[247] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1563 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1564 ) , + .Test_en_W_in ( Test_enWires[107] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1565 ) , + .Test_en_E_out ( Test_enWires[108] ) , .pReset_N_in ( pResetWires[247] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1566 ) , + .Reset_W_in ( ResetWires[107] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1567 ) , + .Reset_E_out ( ResetWires[108] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1568 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[180] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[376] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[377] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1569 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1570 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1571 ) , + .clk_0_S_in ( clk_1_wires[180] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1572 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[103] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1573 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[103] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1574 } ) , + .ccff_head ( cby_1__1__100_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_112_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_112_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_112_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_112_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_112_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_112_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_112_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_112_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[102] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1575 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[102] ) , + .ccff_tail ( grid_clb_112_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1576 ) , + .SC_IN_BOT ( scff_Wires[248] ) , .SC_OUT_TOP ( scff_Wires[249] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1577 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1578 ) , + .Test_en_W_in ( Test_enWires[129] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1579 ) , + .Test_en_E_out ( Test_enWires[130] ) , .pReset_N_in ( pResetWires[296] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1580 ) , + .Reset_W_in ( ResetWires[129] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1581 ) , + .Reset_E_out ( ResetWires[130] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[188] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1582 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[379] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[380] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1583 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1584 ) , + .clk_0_N_in ( clk_1_wires[188] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1586 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[104] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1587 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[104] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1588 } ) , + .ccff_head ( cby_1__1__101_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_113_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_113_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_113_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_113_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_113_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_113_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_113_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_113_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[103] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1589 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[103] ) , + .ccff_tail ( grid_clb_113_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1590 ) , + .SC_IN_BOT ( scff_Wires[250] ) , .SC_OUT_TOP ( scff_Wires[251] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1591 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1592 ) , + .Test_en_W_in ( Test_enWires[151] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1593 ) , + .Test_en_E_out ( Test_enWires[152] ) , .pReset_N_in ( pResetWires[345] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1594 ) , + .Reset_W_in ( ResetWires[151] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1595 ) , + .Reset_E_out ( ResetWires[152] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1596 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[187] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[382] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[383] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1597 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1598 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1599 ) , + .clk_0_S_in ( clk_1_wires[187] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1600 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[105] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1601 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[105] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1602 } ) , + .ccff_head ( cby_1__1__102_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_114_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_114_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_114_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_114_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_114_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_114_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_114_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_114_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[104] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1603 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[104] ) , + .ccff_tail ( grid_clb_114_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1604 ) , + .SC_IN_BOT ( scff_Wires[252] ) , .SC_OUT_TOP ( scff_Wires[253] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1605 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1606 ) , + .Test_en_W_in ( Test_enWires[173] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1607 ) , + .Test_en_E_out ( Test_enWires[174] ) , .pReset_N_in ( pResetWires[394] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1608 ) , + .Reset_W_in ( ResetWires[173] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1609 ) , + .Reset_E_out ( ResetWires[174] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[195] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1610 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[385] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[386] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1611 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1612 ) , + .clk_0_N_in ( clk_1_wires[195] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1614 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[106] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1615 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[106] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1616 } ) , + .ccff_head ( cby_1__1__103_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_115_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_115_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_115_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_115_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_115_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_115_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_115_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_115_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[105] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1617 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[105] ) , + .ccff_tail ( grid_clb_115_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1618 ) , + .SC_IN_BOT ( scff_Wires[254] ) , .SC_OUT_TOP ( scff_Wires[255] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1619 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1620 ) , + .Test_en_W_in ( Test_enWires[195] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1621 ) , + .Test_en_E_out ( Test_enWires[196] ) , .pReset_N_in ( pResetWires[443] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1622 ) , + .Reset_W_in ( ResetWires[195] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1623 ) , + .Reset_E_out ( ResetWires[196] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1624 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[194] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[388] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[389] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1625 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1626 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1627 ) , + .clk_0_S_in ( clk_1_wires[194] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1628 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[107] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1629 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[107] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1630 } ) , + .ccff_head ( cby_1__1__104_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_116_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_116_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_116_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_116_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_116_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_116_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_116_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_116_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[106] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1631 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[106] ) , + .ccff_tail ( grid_clb_116_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1632 ) , + .SC_IN_BOT ( scff_Wires[256] ) , .SC_OUT_TOP ( scff_Wires[257] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1633 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1634 ) , + .Test_en_W_in ( Test_enWires[217] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1635 ) , + .Test_en_E_out ( Test_enWires[218] ) , .pReset_N_in ( pResetWires[492] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1636 ) , + .Reset_W_in ( ResetWires[217] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1637 ) , + .Reset_E_out ( ResetWires[218] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[202] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1638 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[391] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[392] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1639 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1640 ) , + .clk_0_N_in ( clk_1_wires[202] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1642 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[108] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1643 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[108] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1644 } ) , + .ccff_head ( cby_1__1__105_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_117_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_117_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_117_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_117_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_117_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_117_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_117_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_117_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[107] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1645 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[107] ) , + .ccff_tail ( grid_clb_117_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1646 ) , + .SC_IN_BOT ( scff_Wires[258] ) , .SC_OUT_TOP ( scff_Wires[259] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1647 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1648 ) , + .Test_en_W_in ( Test_enWires[239] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1649 ) , + .Test_en_E_out ( Test_enWires[240] ) , .pReset_N_in ( pResetWires[541] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1650 ) , + .Reset_W_in ( ResetWires[239] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1651 ) , + .Reset_E_out ( ResetWires[240] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1652 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[201] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[394] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[395] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1653 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1654 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1655 ) , + .clk_0_S_in ( clk_1_wires[201] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1656 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[109] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1657 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[109] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1658 } ) , + .ccff_head ( cby_1__1__106_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_118_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_118_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_118_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_118_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_118_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_118_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_118_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_118_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[108] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1659 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[108] ) , + .ccff_tail ( grid_clb_118_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1660 ) , + .SC_IN_BOT ( scff_Wires[260] ) , .SC_OUT_TOP ( scff_Wires[261] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1661 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1662 ) , + .Test_en_W_in ( Test_enWires[261] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1663 ) , + .Test_en_E_out ( Test_enWires[262] ) , .pReset_N_in ( pResetWires[590] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1664 ) , + .Reset_W_in ( ResetWires[261] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1665 ) , + .Reset_E_out ( ResetWires[262] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[209] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1666 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[397] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[398] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1667 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1668 ) , + .clk_0_N_in ( clk_1_wires[209] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1670 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1671 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1672 } ) , + .ccff_head ( cby_1__1__107_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_119_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_119_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_119_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_119_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_119_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_119_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_119_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_119_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[109] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1673 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[109] ) , + .ccff_tail ( grid_clb_119_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1674 ) , + .SC_IN_BOT ( scff_Wires[262] ) , .SC_OUT_TOP ( scff_Wires[263] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1675 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1676 ) , + .Test_en_W_in ( Test_enWires[283] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1677 ) , + .Test_en_E_out ( Test_enWires[284] ) , .pReset_N_in ( pResetWires[630] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1678 ) , + .Reset_W_in ( ResetWires[283] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1679 ) , + .Reset_E_out ( ResetWires[284] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1680 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[208] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[400] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[401] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1681 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[403] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1682 ) , + .clk_0_S_in ( clk_1_wires[208] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1683 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[110] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1684 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[110] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1685 } ) , + .ccff_head ( cby_1__1__108_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_120_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_120_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_120_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_120_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_120_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_120_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_120_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_120_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1686 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[288] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1687 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1688 ) , + .SC_OUT_BOT ( scff_Wires[290] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1689 ) , + .Test_en_W_in ( Test_enWires[43] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1690 ) , + .Test_en_E_out ( Test_enWires[44] ) , .pReset_N_in ( pResetWires[104] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1691 ) , + .Reset_W_in ( ResetWires[43] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1692 ) , + .Reset_E_out ( ResetWires[44] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[214] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1693 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[405] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[406] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1694 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1695 ) , + .clk_0_N_in ( clk_1_wires[214] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1697 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[111] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1698 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[111] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1699 } ) , + .ccff_head ( cby_1__1__109_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_121_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_121_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_121_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_121_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_121_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_121_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_121_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_121_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[110] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1700 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[110] ) , + .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires[286] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1701 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1702 ) , + .SC_OUT_BOT ( scff_Wires[287] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1703 ) , + .Test_en_W_in ( Test_enWires[65] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1704 ) , + .Test_en_E_out ( Test_enWires[66] ) , .pReset_N_in ( pResetWires[153] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1705 ) , + .Reset_W_in ( ResetWires[65] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1706 ) , + .Reset_E_out ( ResetWires[66] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1707 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[213] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[408] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[409] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1708 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1709 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1710 ) , + .clk_0_S_in ( clk_1_wires[213] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1711 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[112] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1712 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[112] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1713 } ) , + .ccff_head ( cby_1__1__110_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_122_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_122_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_122_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_122_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_122_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_122_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_122_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_122_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[111] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1714 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[111] ) , + .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires[284] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1715 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1716 ) , + .SC_OUT_BOT ( scff_Wires[285] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1717 ) , + .Test_en_W_in ( Test_enWires[87] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1718 ) , + .Test_en_E_out ( Test_enWires[88] ) , .pReset_N_in ( pResetWires[202] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1719 ) , + .Reset_W_in ( ResetWires[87] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1720 ) , + .Reset_E_out ( ResetWires[88] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[221] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1721 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[411] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[412] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1722 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1723 ) , + .clk_0_N_in ( clk_1_wires[221] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1725 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[113] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1726 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[113] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1727 } ) , + .ccff_head ( cby_1__1__111_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_123_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_123_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_123_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_123_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_123_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_123_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_123_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_123_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[112] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1728 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[112] ) , + .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires[282] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1729 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1730 ) , + .SC_OUT_BOT ( scff_Wires[283] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1731 ) , + .Test_en_W_in ( Test_enWires[109] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1732 ) , + .Test_en_E_out ( Test_enWires[110] ) , .pReset_N_in ( pResetWires[251] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1733 ) , + .Reset_W_in ( ResetWires[109] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1734 ) , + .Reset_E_out ( ResetWires[110] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1735 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[220] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[414] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[415] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1736 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1737 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1738 ) , + .clk_0_S_in ( clk_1_wires[220] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1739 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[114] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1740 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[114] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1741 } ) , + .ccff_head ( cby_1__1__112_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_124_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_124_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_124_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_124_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_124_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_124_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_124_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_124_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[113] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1742 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[113] ) , + .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires[280] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1743 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1744 ) , + .SC_OUT_BOT ( scff_Wires[281] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1745 ) , + .Test_en_W_in ( Test_enWires[131] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1746 ) , + .Test_en_E_out ( Test_enWires[132] ) , .pReset_N_in ( pResetWires[300] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1747 ) , + .Reset_W_in ( ResetWires[131] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1748 ) , + .Reset_E_out ( ResetWires[132] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[228] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1749 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[417] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[418] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1750 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1751 ) , + .clk_0_N_in ( clk_1_wires[228] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1753 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[115] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1754 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[115] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1755 } ) , + .ccff_head ( cby_1__1__113_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_125_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_125_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_125_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_125_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_125_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_125_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_125_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_125_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[114] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1756 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[114] ) , + .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires[278] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1757 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1758 ) , + .SC_OUT_BOT ( scff_Wires[279] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1759 ) , + .Test_en_W_in ( Test_enWires[153] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1760 ) , + .Test_en_E_out ( Test_enWires[154] ) , .pReset_N_in ( pResetWires[349] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1761 ) , + .Reset_W_in ( ResetWires[153] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1762 ) , + .Reset_E_out ( ResetWires[154] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1763 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[227] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[420] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[421] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1764 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1765 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1766 ) , + .clk_0_S_in ( clk_1_wires[227] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1767 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[116] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1768 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[116] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1769 } ) , + .ccff_head ( cby_1__1__114_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_126_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_126_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_126_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_126_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_126_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_126_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_126_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_126_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[115] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1770 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[115] ) , + .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires[276] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1771 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1772 ) , + .SC_OUT_BOT ( scff_Wires[277] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1773 ) , + .Test_en_W_in ( Test_enWires[175] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1774 ) , + .Test_en_E_out ( Test_enWires[176] ) , .pReset_N_in ( pResetWires[398] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1775 ) , + .Reset_W_in ( ResetWires[175] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1776 ) , + .Reset_E_out ( ResetWires[176] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[235] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1777 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[423] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[424] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1778 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1779 ) , + .clk_0_N_in ( clk_1_wires[235] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1781 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[117] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1782 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[117] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1783 } ) , + .ccff_head ( cby_1__1__115_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_127_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_127_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_127_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_127_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_127_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_127_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_127_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_127_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[116] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1784 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[116] ) , + .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires[274] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1785 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1786 ) , + .SC_OUT_BOT ( scff_Wires[275] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1787 ) , + .Test_en_W_in ( Test_enWires[197] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1788 ) , + .Test_en_E_out ( Test_enWires[198] ) , .pReset_N_in ( pResetWires[447] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1789 ) , + .Reset_W_in ( ResetWires[197] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1790 ) , + .Reset_E_out ( ResetWires[198] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1791 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[234] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[426] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[427] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1792 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1793 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1794 ) , + .clk_0_S_in ( clk_1_wires[234] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1795 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[118] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1796 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[118] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1797 } ) , + .ccff_head ( cby_1__1__116_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_128_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_128_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_128_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_128_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_128_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_128_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_128_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_128_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[117] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1798 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[117] ) , + .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires[272] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1799 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1800 ) , + .SC_OUT_BOT ( scff_Wires[273] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1801 ) , + .Test_en_W_in ( Test_enWires[219] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1802 ) , + .Test_en_E_out ( Test_enWires[220] ) , .pReset_N_in ( pResetWires[496] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1803 ) , + .Reset_W_in ( ResetWires[219] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1804 ) , + .Reset_E_out ( ResetWires[220] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[242] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1805 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[429] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[430] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1806 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1807 ) , + .clk_0_N_in ( clk_1_wires[242] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1809 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[119] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1810 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[119] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1811 } ) , + .ccff_head ( cby_1__1__117_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_129_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_129_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_129_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_129_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_129_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_129_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_129_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_129_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[118] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1812 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[118] ) , + .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires[270] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1813 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1814 ) , + .SC_OUT_BOT ( scff_Wires[271] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1815 ) , + .Test_en_W_in ( Test_enWires[241] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1816 ) , + .Test_en_E_out ( Test_enWires[242] ) , .pReset_N_in ( pResetWires[545] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1817 ) , + .Reset_W_in ( ResetWires[241] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1818 ) , + .Reset_E_out ( ResetWires[242] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1819 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[241] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[432] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[433] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1820 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1821 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1822 ) , + .clk_0_S_in ( clk_1_wires[241] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1823 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[120] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1824 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[120] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1825 } ) , + .ccff_head ( cby_1__1__118_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_130_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_130_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_130_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_130_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_130_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_130_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_130_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_130_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[119] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1826 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[119] ) , + .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires[268] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1827 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1828 ) , + .SC_OUT_BOT ( scff_Wires[269] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1829 ) , + .Test_en_W_in ( Test_enWires[263] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1830 ) , + .Test_en_E_out ( Test_enWires[264] ) , .pReset_N_in ( pResetWires[594] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1831 ) , + .Reset_W_in ( ResetWires[263] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1832 ) , + .Reset_E_out ( ResetWires[264] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[249] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1833 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[435] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[436] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1834 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1835 ) , + .clk_0_N_in ( clk_1_wires[249] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1837 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1838 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1839 } ) , + .ccff_head ( cby_1__1__119_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_131_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_131_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_131_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_131_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_131_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_131_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_131_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_131_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[120] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1840 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[120] ) , + .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires[266] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1841 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1842 ) , + .SC_OUT_BOT ( scff_Wires[267] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1843 ) , + .Test_en_W_in ( Test_enWires[285] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1844 ) , + .Test_en_E_out ( Test_enWires[286] ) , .pReset_N_in ( pResetWires[633] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1845 ) , + .Reset_W_in ( ResetWires[285] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1846 ) , + .Reset_E_out ( ResetWires[286] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1847 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[248] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[438] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[439] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1848 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[441] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1849 ) , + .clk_0_S_in ( clk_1_wires[248] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1850 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[121] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1851 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[121] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1852 } ) , + .ccff_head ( cby_1__1__120_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_132_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_132_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_132_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_132_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_132_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_132_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_132_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_132_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1853 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_132_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1854 ) , + .SC_IN_BOT ( scff_Wires[293] ) , .SC_OUT_TOP ( scff_Wires[294] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1855 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1856 ) , + .Test_en_W_in ( Test_enWires[45] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1857 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1858 ) , + .pReset_N_in ( pResetWires[108] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1859 ) , + .Reset_W_in ( ResetWires[45] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1860 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1861 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[216] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1862 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[443] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[444] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1863 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1864 ) , + .clk_0_N_in ( clk_1_wires[216] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1866 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[122] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1867 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[122] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1868 } ) , + .ccff_head ( cby_1__1__121_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_133_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_133_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_133_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_133_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_133_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_133_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_133_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_133_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[121] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1869 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[121] ) , + .ccff_tail ( grid_clb_133_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1870 ) , + .SC_IN_BOT ( scff_Wires[295] ) , .SC_OUT_TOP ( scff_Wires[296] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1871 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1872 ) , + .Test_en_W_in ( Test_enWires[67] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1873 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1874 ) , + .pReset_N_in ( pResetWires[157] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1875 ) , + .Reset_W_in ( ResetWires[67] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1876 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1877 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1878 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[215] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[446] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[447] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1879 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1880 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1881 ) , + .clk_0_S_in ( clk_1_wires[215] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1882 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[123] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1883 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[123] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1884 } ) , + .ccff_head ( cby_1__1__122_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_134_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_134_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_134_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_134_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_134_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_134_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_134_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_134_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[122] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1885 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[122] ) , + .ccff_tail ( grid_clb_134_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1886 ) , + .SC_IN_BOT ( scff_Wires[297] ) , .SC_OUT_TOP ( scff_Wires[298] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1887 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1888 ) , + .Test_en_W_in ( Test_enWires[89] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1889 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1890 ) , + .pReset_N_in ( pResetWires[206] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1891 ) , + .Reset_W_in ( ResetWires[89] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1892 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1893 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[223] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1894 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[449] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[450] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1895 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1896 ) , + .clk_0_N_in ( clk_1_wires[223] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1898 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[124] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1899 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[124] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1900 } ) , + .ccff_head ( cby_1__1__123_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_135_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_135_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_135_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_135_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_135_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_135_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_135_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_135_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[123] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1901 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[123] ) , + .ccff_tail ( grid_clb_135_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1902 ) , + .SC_IN_BOT ( scff_Wires[299] ) , .SC_OUT_TOP ( scff_Wires[300] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1903 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1904 ) , + .Test_en_W_in ( Test_enWires[111] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1905 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1906 ) , + .pReset_N_in ( pResetWires[255] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1907 ) , + .Reset_W_in ( ResetWires[111] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1908 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1909 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1910 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[222] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[452] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[453] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1911 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1912 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1913 ) , + .clk_0_S_in ( clk_1_wires[222] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1914 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[125] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1915 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[125] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1916 } ) , + .ccff_head ( cby_1__1__124_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_136_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_136_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_136_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_136_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_136_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_136_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_136_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_136_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[124] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1917 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[124] ) , + .ccff_tail ( grid_clb_136_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1918 ) , + .SC_IN_BOT ( scff_Wires[301] ) , .SC_OUT_TOP ( scff_Wires[302] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1919 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1920 ) , + .Test_en_W_in ( Test_enWires[133] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1921 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1922 ) , + .pReset_N_in ( pResetWires[304] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1923 ) , + .Reset_W_in ( ResetWires[133] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1924 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1925 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[230] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1926 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[455] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[456] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1927 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1928 ) , + .clk_0_N_in ( clk_1_wires[230] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1930 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[126] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1931 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[126] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1932 } ) , + .ccff_head ( cby_1__1__125_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_137_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_137_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_137_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_137_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_137_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_137_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_137_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_137_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[125] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1933 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[125] ) , + .ccff_tail ( grid_clb_137_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1934 ) , + .SC_IN_BOT ( scff_Wires[303] ) , .SC_OUT_TOP ( scff_Wires[304] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1935 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1936 ) , + .Test_en_W_in ( Test_enWires[155] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1937 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1938 ) , + .pReset_N_in ( pResetWires[353] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1939 ) , + .Reset_W_in ( ResetWires[155] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1940 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1941 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1942 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[229] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[458] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[459] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1943 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1944 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1945 ) , + .clk_0_S_in ( clk_1_wires[229] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1946 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[127] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1947 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[127] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1948 } ) , + .ccff_head ( cby_1__1__126_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_138_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_138_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_138_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_138_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_138_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_138_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_138_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_138_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[126] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1949 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[126] ) , + .ccff_tail ( grid_clb_138_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1950 ) , + .SC_IN_BOT ( scff_Wires[305] ) , .SC_OUT_TOP ( scff_Wires[306] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1951 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1952 ) , + .Test_en_W_in ( Test_enWires[177] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1953 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1954 ) , + .pReset_N_in ( pResetWires[402] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1955 ) , + .Reset_W_in ( ResetWires[177] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1956 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1957 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[237] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1958 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[461] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[462] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1959 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1960 ) , + .clk_0_N_in ( clk_1_wires[237] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1962 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[128] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1963 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[128] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1964 } ) , + .ccff_head ( cby_1__1__127_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_139_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_139_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_139_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_139_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_139_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_139_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_139_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_139_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[127] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1965 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[127] ) , + .ccff_tail ( grid_clb_139_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1966 ) , + .SC_IN_BOT ( scff_Wires[307] ) , .SC_OUT_TOP ( scff_Wires[308] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1967 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1968 ) , + .Test_en_W_in ( Test_enWires[199] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1969 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1970 ) , + .pReset_N_in ( pResetWires[451] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1971 ) , + .Reset_W_in ( ResetWires[199] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1972 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1973 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1974 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[236] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[464] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[465] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1975 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1976 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1977 ) , + .clk_0_S_in ( clk_1_wires[236] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1978 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[129] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1979 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[129] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1980 } ) , + .ccff_head ( cby_1__1__128_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_140_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_140_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_140_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_140_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_140_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_140_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_140_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_140_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[128] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1981 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[128] ) , + .ccff_tail ( grid_clb_140_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1982 ) , + .SC_IN_BOT ( scff_Wires[309] ) , .SC_OUT_TOP ( scff_Wires[310] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1983 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1984 ) , + .Test_en_W_in ( Test_enWires[221] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1985 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1986 ) , + .pReset_N_in ( pResetWires[500] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1987 ) , + .Reset_W_in ( ResetWires[221] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1988 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1989 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[244] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1990 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[467] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[468] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1991 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1992 ) , + .clk_0_N_in ( clk_1_wires[244] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1994 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[130] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1995 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[130] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1996 } ) , + .ccff_head ( cby_1__1__129_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_141_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_141_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_141_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_141_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_141_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_141_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_141_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_141_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[129] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1997 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[129] ) , + .ccff_tail ( grid_clb_141_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1998 ) , + .SC_IN_BOT ( scff_Wires[311] ) , .SC_OUT_TOP ( scff_Wires[312] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1999 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2000 ) , + .Test_en_W_in ( Test_enWires[243] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2001 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2002 ) , + .pReset_N_in ( pResetWires[549] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2003 ) , + .Reset_W_in ( ResetWires[243] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2004 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2005 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2006 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[243] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[470] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[471] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2007 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2008 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2009 ) , + .clk_0_S_in ( clk_1_wires[243] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2010 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[131] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2011 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[131] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_2012 } ) , + .ccff_head ( cby_1__1__130_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_142_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_142_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_142_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_142_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_142_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_142_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_142_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_142_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[130] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2013 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[130] ) , + .ccff_tail ( grid_clb_142_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2014 ) , + .SC_IN_BOT ( scff_Wires[313] ) , .SC_OUT_TOP ( scff_Wires[314] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2015 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2016 ) , + .Test_en_W_in ( Test_enWires[265] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2017 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2018 ) , + .pReset_N_in ( pResetWires[598] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2019 ) , + .Reset_W_in ( ResetWires[265] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2020 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2021 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[251] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_2022 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[473] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[474] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2023 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2024 ) , + .clk_0_N_in ( clk_1_wires[251] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb grid_clb_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2026 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2027 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_2028 } ) , + .ccff_head ( cby_1__1__131_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_143_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_143_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_143_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_143_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_143_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_143_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_143_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_143_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[131] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2029 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[131] ) , + .ccff_tail ( grid_clb_143_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2030 ) , + .SC_IN_BOT ( scff_Wires[315] ) , .SC_OUT_TOP ( scff_Wires[316] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2031 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2032 ) , + .Test_en_W_in ( Test_enWires[287] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2033 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2034 ) , + .pReset_N_in ( pResetWires[636] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2035 ) , + .Reset_W_in ( ResetWires[287] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2036 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2037 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2038 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[250] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[476] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[477] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2039 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[479] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2040 ) , + .clk_0_S_in ( clk_1_wires[250] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__0_ sb_0__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2041 } ) , + .chany_top_in ( cby_0__1__0_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , + .ccff_head ( grid_io_bottom_11_ccff_tail ) , + .chany_top_out ( sb_0__0__0_chany_top_out ) , + .chanx_right_out ( sb_0__0__0_chanx_right_out ) , + .ccff_tail ( ccff_tail ) , .pReset_E_in ( pResetWires[25] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2042 } ) , + .chany_top_in ( cby_0__1__1_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__0_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__0_ccff_tail ) , + .chany_top_out ( sb_0__1__0_chany_top_out ) , + .chanx_right_out ( sb_0__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , .pReset_E_in ( pResetWires[61] ) , + .pReset_S_out ( pResetWires[64] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[4] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2043 } ) , + .chany_top_in ( cby_0__1__2_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__1_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__1_ccff_tail ) , + .chany_top_out ( sb_0__1__1_chany_top_out ) , + .chanx_right_out ( sb_0__1__1_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) , + .ccff_tail ( sb_0__1__1_ccff_tail ) , .pReset_E_in ( pResetWires[110] ) , + .pReset_S_out ( pResetWires[113] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[10] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2044 } ) , + .chany_top_in ( cby_0__1__3_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__2_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__2_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__2_ccff_tail ) , + .chany_top_out ( sb_0__1__2_chany_top_out ) , + .chanx_right_out ( sb_0__1__2_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) , + .ccff_tail ( sb_0__1__2_ccff_tail ) , .pReset_E_in ( pResetWires[159] ) , + .pReset_S_out ( pResetWires[162] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[15] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2045 } ) , + .chany_top_in ( cby_0__1__4_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__3_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__3_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__3_ccff_tail ) , + .chany_top_out ( sb_0__1__3_chany_top_out ) , + .chanx_right_out ( sb_0__1__3_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) , + .ccff_tail ( sb_0__1__3_ccff_tail ) , .pReset_E_in ( pResetWires[208] ) , + .pReset_S_out ( pResetWires[211] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[20] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2046 } ) , + .chany_top_in ( cby_0__1__5_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__4_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__4_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__4_ccff_tail ) , + .chany_top_out ( sb_0__1__4_chany_top_out ) , + .chanx_right_out ( sb_0__1__4_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) , + .ccff_tail ( sb_0__1__4_ccff_tail ) , .pReset_E_in ( pResetWires[257] ) , + .pReset_S_out ( pResetWires[260] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[25] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2047 } ) , + .chany_top_in ( cby_0__1__6_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__5_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__5_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__5_ccff_tail ) , + .chany_top_out ( sb_0__1__5_chany_top_out ) , + .chanx_right_out ( sb_0__1__5_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) , + .ccff_tail ( sb_0__1__5_ccff_tail ) , .pReset_E_in ( pResetWires[306] ) , + .pReset_S_out ( pResetWires[309] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[30] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2048 } ) , + .chany_top_in ( cby_0__1__7_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__6_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__6_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__6_ccff_tail ) , + .chany_top_out ( sb_0__1__6_chany_top_out ) , + .chanx_right_out ( sb_0__1__6_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) , + .ccff_tail ( sb_0__1__6_ccff_tail ) , .pReset_E_in ( pResetWires[355] ) , + .pReset_S_out ( pResetWires[358] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[35] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2049 } ) , + .chany_top_in ( cby_0__1__8_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__7_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__7_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__7_ccff_tail ) , + .chany_top_out ( sb_0__1__7_chany_top_out ) , + .chanx_right_out ( sb_0__1__7_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) , + .ccff_tail ( sb_0__1__7_ccff_tail ) , .pReset_E_in ( pResetWires[404] ) , + .pReset_S_out ( pResetWires[407] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[40] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2050 } ) , + .chany_top_in ( cby_0__1__9_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__8_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__8_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__8_ccff_tail ) , + .chany_top_out ( sb_0__1__8_chany_top_out ) , + .chanx_right_out ( sb_0__1__8_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) , + .ccff_tail ( sb_0__1__8_ccff_tail ) , .pReset_E_in ( pResetWires[453] ) , + .pReset_S_out ( pResetWires[456] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[45] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2051 } ) , + .chany_top_in ( cby_0__1__10_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__9_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__9_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__9_ccff_tail ) , + .chany_top_out ( sb_0__1__9_chany_top_out ) , + .chanx_right_out ( sb_0__1__9_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) , + .ccff_tail ( sb_0__1__9_ccff_tail ) , .pReset_E_in ( pResetWires[502] ) , + .pReset_S_out ( pResetWires[505] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[50] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__1_ sb_0__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2052 } ) , + .chany_top_in ( cby_0__1__11_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__10_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__10_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__10_ccff_tail ) , + .chany_top_out ( sb_0__1__10_chany_top_out ) , + .chanx_right_out ( sb_0__1__10_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) , + .ccff_tail ( sb_0__1__10_ccff_tail ) , .pReset_E_in ( pResetWires[551] ) , + .pReset_S_out ( pResetWires[554] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[55] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_0__2_ sb_0__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2053 } ) , + .chanx_right_in ( cbx_1__12__0_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__11_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( grid_io_top_0_ccff_tail ) , + .chanx_right_out ( sb_0__12__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) , + .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , + .SC_OUT_BOT ( scff_Wires[0] ) , .pReset_E_in ( pResetWires[600] ) , + .pReset_S_out ( pResetWires[603] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[62] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_1__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2054 } ) , + .chany_top_in ( cby_1__1__0_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_10_ccff_tail ) , + .chany_top_out ( sb_1__0__0_chany_top_out ) , + .chanx_right_out ( sb_1__0__0_chanx_right_out ) , + .chanx_left_out ( sb_1__0__0_chanx_left_out ) , + .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) , + .pReset_E_in ( pResetWires[28] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) , + .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_2__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) , + .chany_top_in ( cby_1__1__12_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__2_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_9_ccff_tail ) , + .chany_top_out ( sb_1__0__1_chany_top_out ) , + .chanx_right_out ( sb_1__0__1_chanx_right_out ) , + .chanx_left_out ( sb_1__0__1_chanx_left_out ) , + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , + .pReset_E_in ( pResetWires[31] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) , + .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_3__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) , + .chany_top_in ( cby_1__1__24_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__3_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__2_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_8_ccff_tail ) , + .chany_top_out ( sb_1__0__2_chany_top_out ) , + .chanx_right_out ( sb_1__0__2_chanx_right_out ) , + .chanx_left_out ( sb_1__0__2_chanx_left_out ) , + .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) , + .pReset_E_in ( pResetWires[34] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) , + .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_4__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) , + .chany_top_in ( cby_1__1__36_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__4_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__3_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_7_ccff_tail ) , + .chany_top_out ( sb_1__0__3_chany_top_out ) , + .chanx_right_out ( sb_1__0__3_chanx_right_out ) , + .chanx_left_out ( sb_1__0__3_chanx_left_out ) , + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) , + .pReset_E_in ( pResetWires[37] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , + .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_5__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) , + .chany_top_in ( cby_1__1__48_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__5_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__4_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_6_ccff_tail ) , + .chany_top_out ( sb_1__0__4_chany_top_out ) , + .chanx_right_out ( sb_1__0__4_chanx_right_out ) , + .chanx_left_out ( sb_1__0__4_chanx_left_out ) , + .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , + .pReset_E_in ( pResetWires[40] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) , + .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_6__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) , + .chany_top_in ( cby_1__1__60_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__6_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__5_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_5_ccff_tail ) , + .chany_top_out ( sb_1__0__5_chany_top_out ) , + .chanx_right_out ( sb_1__0__5_chanx_right_out ) , + .chanx_left_out ( sb_1__0__5_chanx_left_out ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) , + .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) , + .pReset_E_in ( h_incr0 ) , .pReset_W_in ( h_incr0 ) , + .pReset_N_out ( pResetWires[42] ) , .pReset_W_out ( pResetWires[41] ) , + .pReset_E_out ( pResetWires[43] ) , .Reset_S_in ( Reset[0] ) , + .Reset_N_out ( ResetWires[1] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[217] ) , + .prog_clk_3_S_in ( prog_clk[0] ) , + .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) , + .clk_3_N_out ( clk_3_wires[90] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_7__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2098 } ) , + .chany_top_in ( cby_1__1__72_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__7_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__6_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_4_ccff_tail ) , + .chany_top_out ( sb_1__0__6_chany_top_out ) , + .chanx_right_out ( sb_1__0__6_chanx_right_out ) , + .chanx_left_out ( sb_1__0__6_chanx_left_out ) , + .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2099 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2100 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2101 ) , + .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2102 ) , + .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2103 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2104 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2105 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_8__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2106 } ) , + .chany_top_in ( cby_1__1__84_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__8_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__7_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_3_ccff_tail ) , + .chany_top_out ( sb_1__0__7_chany_top_out ) , + .chanx_right_out ( sb_1__0__7_chanx_right_out ) , + .chanx_left_out ( sb_1__0__7_chanx_left_out ) , + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2107 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2108 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2109 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2110 ) , + .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2111 ) , + .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2112 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2113 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2114 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_9__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2115 } ) , + .chany_top_in ( cby_1__1__96_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__9_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__8_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_2_ccff_tail ) , + .chany_top_out ( sb_1__0__8_chany_top_out ) , + .chanx_right_out ( sb_1__0__8_chanx_right_out ) , + .chanx_left_out ( sb_1__0__8_chanx_left_out ) , + .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2116 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2117 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2118 ) , + .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2119 ) , + .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2120 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2121 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2122 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_10__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2123 } ) , + .chany_top_in ( cby_1__1__108_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__10_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__9_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_1_ccff_tail ) , + .chany_top_out ( sb_1__0__9_chany_top_out ) , + .chanx_right_out ( sb_1__0__9_chanx_right_out ) , + .chanx_left_out ( sb_1__0__9_chanx_left_out ) , + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2124 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2125 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2126 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2127 ) , + .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2128 ) , + .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2129 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2130 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2131 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__0_ sb_11__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2132 } ) , + .chany_top_in ( cby_1__1__120_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__11_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__10_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_0_ccff_tail ) , + .chany_top_out ( sb_1__0__10_chany_top_out ) , + .chanx_right_out ( sb_1__0__10_chanx_right_out ) , + .chanx_left_out ( sb_1__0__10_chanx_left_out ) , + .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2133 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2134 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2135 ) , + .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2136 ) , + .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2137 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2138 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2139 ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2140 } ) , + .chany_top_in ( cby_1__1__1_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__11_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__0_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__11_ccff_tail ) , + .chany_top_out ( sb_1__1__0_chany_top_out ) , + .chanx_right_out ( sb_1__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__0_chanx_left_out ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2141 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2142 ) , + .pReset_E_in ( pResetWires[66] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2143 ) , + .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2144 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2145 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2146 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( h_incr0 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2147 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2148 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2149 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2150 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2151 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2152 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2154 ) , + .clk_1_N_in ( clk_2_wires[4] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2155 ) , + .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2156 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2157 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2159 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2160 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2161 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2162 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2163 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2164 } ) , + .chany_top_in ( cby_1__1__2_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__12_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__1_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__12_ccff_tail ) , + .chany_top_out ( sb_1__1__1_chany_top_out ) , + .chanx_right_out ( sb_1__1__1_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__1_chanx_left_out ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2165 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2166 ) , + .pReset_E_in ( pResetWires[115] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2167 ) , + .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2168 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2169 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2171 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2172 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[1] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2173 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2174 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2175 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2176 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2177 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2178 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2179 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2180 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2181 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2182 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2183 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2184 ) , + .clk_2_E_in ( clk_2_wires[1] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2185 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2186 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2187 ) , + .clk_2_S_out ( clk_2_wires[3] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2188 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2189 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2190 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2191 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2192 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2193 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2194 } ) , + .chany_top_in ( cby_1__1__3_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__13_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__2_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__13_ccff_tail ) , + .chany_top_out ( sb_1__1__2_chany_top_out ) , + .chanx_right_out ( sb_1__1__2_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__2_chanx_left_out ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2195 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2196 ) , + .pReset_E_in ( pResetWires[164] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2197 ) , + .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2198 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2199 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2200 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( h_incr0 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2201 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2202 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2203 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2204 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2205 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2206 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2207 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2208 ) , + .clk_1_N_in ( clk_2_wires[11] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2209 ) , + .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2210 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2211 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2213 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2214 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2215 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2216 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2217 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2218 } ) , + .chany_top_in ( cby_1__1__4_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__14_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__3_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__14_ccff_tail ) , + .chany_top_out ( sb_1__1__3_chany_top_out ) , + .chanx_right_out ( sb_1__1__3_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__3_chanx_left_out ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2219 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2220 ) , + .pReset_E_in ( pResetWires[213] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2221 ) , + .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2222 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2223 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2225 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2226 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[6] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2227 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2228 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2229 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2230 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2231 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2232 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2233 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2234 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2235 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2236 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2237 ) , + .clk_2_E_in ( clk_2_wires[6] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2238 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2239 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2240 ) , + .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2241 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2242 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2243 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2244 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2245 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2246 } ) , + .chany_top_in ( cby_1__1__5_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__15_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__4_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__4_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__15_ccff_tail ) , + .chany_top_out ( sb_1__1__4_chany_top_out ) , + .chanx_right_out ( sb_1__1__4_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__4_chanx_left_out ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2247 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2248 ) , + .pReset_E_in ( pResetWires[262] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2249 ) , + .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2250 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2251 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2252 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2253 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2254 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2255 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2256 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2257 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2258 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2259 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2260 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2261 ) , + .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2262 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2263 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2264 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2265 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2266 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2267 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2268 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2269 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2270 } ) , + .chany_top_in ( cby_1__1__6_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__16_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__5_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__5_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__16_ccff_tail ) , + .chany_top_out ( sb_1__1__5_chany_top_out ) , + .chanx_right_out ( sb_1__1__5_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__5_chanx_left_out ) , + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2271 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2272 ) , + .pReset_E_in ( pResetWires[311] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2273 ) , + .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2274 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2275 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2277 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2278 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2279 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2280 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2281 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2282 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2283 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2284 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2285 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2286 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2288 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2289 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2290 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2291 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2292 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2293 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2294 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2295 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2296 } ) , + .chany_top_in ( cby_1__1__7_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__17_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__6_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__6_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__17_ccff_tail ) , + .chany_top_out ( sb_1__1__6_chany_top_out ) , + .chanx_right_out ( sb_1__1__6_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__6_chanx_left_out ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2297 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2298 ) , + .pReset_E_in ( pResetWires[360] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2299 ) , + .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2300 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2301 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2302 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2303 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2304 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2305 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2306 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2307 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2308 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2309 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2310 ) , + .clk_1_N_in ( clk_2_wires[18] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2311 ) , + .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2312 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2313 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2315 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2316 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2317 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2318 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2319 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2320 } ) , + .chany_top_in ( cby_1__1__8_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__18_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__7_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__7_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__18_ccff_tail ) , + .chany_top_out ( sb_1__1__7_chany_top_out ) , + .chanx_right_out ( sb_1__1__7_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__7_chanx_left_out ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2321 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2322 ) , + .pReset_E_in ( pResetWires[409] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2323 ) , + .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2324 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2325 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2327 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2328 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[13] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2329 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2330 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2331 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2332 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2333 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2334 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2335 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2336 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2337 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2338 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2339 ) , + .clk_2_E_in ( clk_2_wires[13] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2340 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2341 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2342 ) , + .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2343 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2345 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2346 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2347 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2348 } ) , + .chany_top_in ( cby_1__1__9_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__19_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__8_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__8_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__19_ccff_tail ) , + .chany_top_out ( sb_1__1__8_chany_top_out ) , + .chanx_right_out ( sb_1__1__8_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__8_chanx_left_out ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2349 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2350 ) , + .pReset_E_in ( pResetWires[458] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2351 ) , + .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2352 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2353 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2354 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2355 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2356 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2357 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2358 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2359 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2360 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2361 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2362 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2363 ) , + .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2364 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2365 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2366 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2367 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2368 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2369 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2370 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2371 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2372 } ) , + .chany_top_in ( cby_1__1__10_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__20_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__9_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__9_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__20_ccff_tail ) , + .chany_top_out ( sb_1__1__9_chany_top_out ) , + .chanx_right_out ( sb_1__1__9_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__9_chanx_left_out ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2373 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2374 ) , + .pReset_E_in ( pResetWires[507] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2375 ) , + .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2376 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2377 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2379 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2380 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[20] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2381 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2382 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2383 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2384 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2385 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2386 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2387 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2388 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2389 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2390 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2391 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2392 ) , + .clk_2_E_in ( clk_2_wires[20] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2393 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2394 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2395 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2396 ) , + .clk_2_N_out ( clk_2_wires[22] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2397 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2398 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2399 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2400 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2401 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2402 } ) , + .chany_top_in ( cby_1__1__11_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__21_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__10_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__10_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__21_ccff_tail ) , + .chany_top_out ( sb_1__1__10_chany_top_out ) , + .chanx_right_out ( sb_1__1__10_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__10_chanx_left_out ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2403 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2404 ) , + .pReset_E_in ( pResetWires[556] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2405 ) , + .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2406 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2407 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2408 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2409 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2410 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2411 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2412 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2413 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2414 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2415 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2416 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2417 ) , + .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2418 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2419 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2422 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2423 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2424 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2425 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2426 } ) , + .chany_top_in ( cby_1__1__13_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__22_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__12_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__11_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__22_ccff_tail ) , + .chany_top_out ( sb_1__1__11_chany_top_out ) , + .chanx_right_out ( sb_1__1__11_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__11_chanx_left_out ) , + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2427 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2428 ) , + .pReset_E_in ( pResetWires[70] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2429 ) , + .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2430 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2431 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2433 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2434 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2435 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2436 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2437 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2438 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2439 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2440 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2441 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2442 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2445 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2446 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2447 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2449 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2450 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2451 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2452 } ) , + .chany_top_in ( cby_1__1__14_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__23_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__13_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__12_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__23_ccff_tail ) , + .chany_top_out ( sb_1__1__12_chany_top_out ) , + .chanx_right_out ( sb_1__1__12_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__12_chanx_left_out ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2453 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2454 ) , + .pReset_E_in ( pResetWires[119] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2455 ) , + .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2456 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2459 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2460 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2461 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2462 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[2] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2463 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2464 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2465 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2466 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2467 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2468 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2469 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2470 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2471 ) , + .clk_2_N_in ( clk_3_wires[69] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2472 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2473 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2474 ) , + .clk_2_W_out ( clk_2_wires[2] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2475 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2476 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2477 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2478 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2479 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2480 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2481 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2482 } ) , + .chany_top_in ( cby_1__1__15_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__24_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__14_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__13_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__24_ccff_tail ) , + .chany_top_out ( sb_1__1__13_chany_top_out ) , + .chanx_right_out ( sb_1__1__13_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__13_chanx_left_out ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2483 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2484 ) , + .pReset_E_in ( pResetWires[168] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2485 ) , + .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2486 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2487 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2489 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2490 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2491 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2492 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2493 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2494 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2495 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2496 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[65] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2497 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2498 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2499 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2500 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2501 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2502 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2503 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2504 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2505 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2506 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2507 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2508 ) , + .clk_3_N_in ( clk_3_wires[65] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2509 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2510 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2511 ) , + .clk_3_S_out ( clk_3_wires[68] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2512 } ) , + .chany_top_in ( cby_1__1__16_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__25_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__15_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__14_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__25_ccff_tail ) , + .chany_top_out ( sb_1__1__14_chany_top_out ) , + .chanx_right_out ( sb_1__1__14_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__14_chanx_left_out ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2513 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2514 ) , + .pReset_E_in ( pResetWires[217] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2515 ) , + .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2516 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2517 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2519 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2520 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2521 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2522 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[7] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2523 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2524 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2525 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2526 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2527 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2528 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[59] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2529 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2530 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2531 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2532 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2533 ) , + .clk_2_N_in ( clk_3_wires[59] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2534 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2535 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2536 ) , + .clk_2_W_out ( clk_2_wires[7] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2537 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2538 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2539 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2540 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2541 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2542 ) , + .clk_3_N_in ( clk_3_wires[59] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2543 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2544 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2545 ) , + .clk_3_S_out ( clk_3_wires[64] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2546 } ) , + .chany_top_in ( cby_1__1__17_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__26_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__16_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__15_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__26_ccff_tail ) , + .chany_top_out ( sb_1__1__15_chany_top_out ) , + .chanx_right_out ( sb_1__1__15_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__15_chanx_left_out ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2547 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2548 ) , + .pReset_E_in ( pResetWires[266] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2549 ) , + .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2550 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2551 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2553 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2554 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2555 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2556 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2557 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2558 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2559 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2560 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[55] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2561 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2562 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2563 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2564 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2565 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2567 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2569 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2570 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2571 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2572 ) , + .clk_3_N_in ( clk_3_wires[55] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2573 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2574 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2575 ) , + .clk_3_S_out ( clk_3_wires[58] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2576 } ) , + .chany_top_in ( cby_1__1__18_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__27_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__17_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__16_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__27_ccff_tail ) , + .chany_top_out ( sb_1__1__16_chany_top_out ) , + .chanx_right_out ( sb_1__1__16_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__16_chanx_left_out ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2577 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2578 ) , + .pReset_E_in ( pResetWires[315] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2579 ) , + .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2580 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2581 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2583 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2584 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2585 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2586 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2587 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2588 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[51] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2589 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2590 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2591 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2592 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2595 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2596 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2597 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2598 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2599 ) , + .clk_3_E_in ( clk_3_wires[51] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2600 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2601 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2603 ) , + .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2604 } ) , + .chany_top_in ( cby_1__1__19_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__28_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__18_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__17_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__28_ccff_tail ) , + .chany_top_out ( sb_1__1__17_chany_top_out ) , + .chanx_right_out ( sb_1__1__17_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__17_chanx_left_out ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2605 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2606 ) , + .pReset_E_in ( pResetWires[364] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2607 ) , + .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2608 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2609 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2611 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2612 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2613 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2614 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2615 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2616 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2617 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[53] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2618 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2619 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2620 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2621 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2622 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2625 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2626 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2627 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2628 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2629 ) , + .clk_3_S_in ( clk_3_wires[53] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2630 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2631 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2632 ) , + .clk_3_N_out ( clk_3_wires[56] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2633 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2634 } ) , + .chany_top_in ( cby_1__1__20_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__29_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__19_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__18_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__29_ccff_tail ) , + .chany_top_out ( sb_1__1__18_chany_top_out ) , + .chanx_right_out ( sb_1__1__18_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__18_chanx_left_out ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2635 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2636 ) , + .pReset_E_in ( pResetWires[413] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2637 ) , + .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2638 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2639 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2641 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2642 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2643 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[57] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2644 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[14] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2645 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2646 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2647 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2648 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2649 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[57] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2650 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2651 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2652 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2653 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2654 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2655 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2656 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2657 ) , + .clk_2_S_in ( clk_3_wires[57] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2658 ) , + .clk_2_W_out ( clk_2_wires[14] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2659 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2660 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2661 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2662 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2663 ) , + .clk_3_S_in ( clk_3_wires[57] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2664 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2665 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2666 ) , + .clk_3_N_out ( clk_3_wires[62] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2667 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2668 } ) , + .chany_top_in ( cby_1__1__21_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__30_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__20_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__19_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__30_ccff_tail ) , + .chany_top_out ( sb_1__1__19_chany_top_out ) , + .chanx_right_out ( sb_1__1__19_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__19_chanx_left_out ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2669 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2670 ) , + .pReset_E_in ( pResetWires[462] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2671 ) , + .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2672 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2673 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2675 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2676 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2677 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2678 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2679 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2680 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2681 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[63] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2682 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2683 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2684 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2685 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2686 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2688 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2689 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2691 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2692 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2693 ) , + .clk_3_S_in ( clk_3_wires[63] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2694 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2695 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2696 ) , + .clk_3_N_out ( clk_3_wires[66] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2697 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2698 } ) , + .chany_top_in ( cby_1__1__22_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__31_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__21_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__20_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__31_ccff_tail ) , + .chany_top_out ( sb_1__1__20_chany_top_out ) , + .chanx_right_out ( sb_1__1__20_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__20_chanx_left_out ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2699 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2700 ) , + .pReset_E_in ( pResetWires[511] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2701 ) , + .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2702 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2703 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2705 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2706 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2707 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[67] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2708 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[21] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2709 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2710 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2711 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2712 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2713 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2714 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2715 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2716 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2717 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2718 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2719 ) , + .clk_2_S_in ( clk_3_wires[67] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2720 ) , + .clk_2_W_out ( clk_2_wires[21] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2721 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2723 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2724 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2725 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2726 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2727 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2728 } ) , + .chany_top_in ( cby_1__1__23_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__32_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__22_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__21_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__32_ccff_tail ) , + .chany_top_out ( sb_1__1__21_chany_top_out ) , + .chanx_right_out ( sb_1__1__21_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__21_chanx_left_out ) , + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2729 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2730 ) , + .pReset_E_in ( pResetWires[560] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2731 ) , + .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2732 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2733 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2735 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2736 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2737 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2738 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2739 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2740 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2741 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2742 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2743 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2744 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2747 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2748 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2749 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2750 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2751 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2752 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2753 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2754 } ) , + .chany_top_in ( cby_1__1__25_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__33_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__24_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__22_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__33_ccff_tail ) , + .chany_top_out ( sb_1__1__22_chany_top_out ) , + .chanx_right_out ( sb_1__1__22_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__22_chanx_left_out ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2755 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2756 ) , + .pReset_E_in ( pResetWires[74] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2757 ) , + .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2758 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2760 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2761 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2762 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2763 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2764 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2765 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2766 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2767 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2768 ) , + .clk_1_N_in ( clk_2_wires[30] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2769 ) , + .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2770 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2771 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2772 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2773 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2774 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2775 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2776 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2777 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2778 } ) , + .chany_top_in ( cby_1__1__26_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__34_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__25_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__23_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__34_ccff_tail ) , + .chany_top_out ( sb_1__1__23_chany_top_out ) , + .chanx_right_out ( sb_1__1__23_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__23_chanx_left_out ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2779 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2780 ) , + .pReset_E_in ( pResetWires[123] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2781 ) , + .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2782 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2783 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2785 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2786 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[28] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2787 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2788 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2789 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2790 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2791 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2792 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2793 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2794 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2795 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2796 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2797 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2798 ) , + .clk_2_E_in ( clk_2_wires[28] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2799 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2800 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2801 ) , + .clk_2_S_out ( clk_2_wires[29] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2802 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2803 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2805 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2806 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2807 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2808 } ) , + .chany_top_in ( cby_1__1__27_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__35_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__26_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__24_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__35_ccff_tail ) , + .chany_top_out ( sb_1__1__24_chany_top_out ) , + .chanx_right_out ( sb_1__1__24_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__24_chanx_left_out ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2809 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2810 ) , + .pReset_E_in ( pResetWires[172] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2811 ) , + .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2812 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2813 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2814 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2815 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2816 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2817 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2818 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2819 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2820 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2821 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2822 ) , + .clk_1_N_in ( clk_2_wires[41] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2823 ) , + .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2824 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2825 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2827 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2828 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2829 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2830 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2831 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2832 } ) , + .chany_top_in ( cby_1__1__28_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__36_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__27_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__25_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__36_ccff_tail ) , + .chany_top_out ( sb_1__1__25_chany_top_out ) , + .chanx_right_out ( sb_1__1__25_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__25_chanx_left_out ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2833 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2834 ) , + .pReset_E_in ( pResetWires[221] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2835 ) , + .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2836 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2837 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2839 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2840 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[37] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2841 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2842 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2843 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2844 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2845 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2846 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2847 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2848 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2849 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2850 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2851 ) , + .clk_2_E_in ( clk_2_wires[37] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2852 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2853 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2854 ) , + .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2855 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2856 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2857 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2858 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2859 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2860 } ) , + .chany_top_in ( cby_1__1__29_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__37_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__28_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__26_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__37_ccff_tail ) , + .chany_top_out ( sb_1__1__26_chany_top_out ) , + .chanx_right_out ( sb_1__1__26_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__26_chanx_left_out ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2861 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2862 ) , + .pReset_E_in ( pResetWires[270] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2863 ) , + .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2864 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2865 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2866 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2867 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2869 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2870 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2871 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2872 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2873 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2874 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2875 ) , + .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2876 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2877 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2878 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2879 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2880 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2881 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2882 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2883 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2884 } ) , + .chany_top_in ( cby_1__1__30_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__38_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__29_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__27_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__38_ccff_tail ) , + .chany_top_out ( sb_1__1__27_chany_top_out ) , + .chanx_right_out ( sb_1__1__27_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__27_chanx_left_out ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2885 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2886 ) , + .pReset_E_in ( pResetWires[319] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2887 ) , + .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2888 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2889 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2891 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2892 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2893 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2894 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2895 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2896 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[47] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2897 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2898 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2899 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2900 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2901 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2902 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2904 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2905 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2906 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2907 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2908 ) , + .clk_3_E_in ( clk_3_wires[47] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2909 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2910 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2911 ) , + .clk_3_W_out ( clk_3_wires[50] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2912 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2913 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2914 } ) , + .chany_top_in ( cby_1__1__31_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__39_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__30_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__28_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__39_ccff_tail ) , + .chany_top_out ( sb_1__1__28_chany_top_out ) , + .chanx_right_out ( sb_1__1__28_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__28_chanx_left_out ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2915 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2916 ) , + .pReset_E_in ( pResetWires[368] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2917 ) , + .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2918 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2919 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2920 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2921 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2922 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2923 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2924 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2925 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2926 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2927 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2928 ) , + .clk_1_N_in ( clk_2_wires[54] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2929 ) , + .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2930 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2931 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2933 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2934 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2935 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2936 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2937 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2938 } ) , + .chany_top_in ( cby_1__1__32_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__40_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__31_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__29_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__40_ccff_tail ) , + .chany_top_out ( sb_1__1__29_chany_top_out ) , + .chanx_right_out ( sb_1__1__29_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__29_chanx_left_out ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2939 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2940 ) , + .pReset_E_in ( pResetWires[417] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2941 ) , + .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2942 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2943 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2945 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2946 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[50] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2947 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2948 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2949 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2950 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2951 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2952 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2953 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2954 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2955 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2956 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2957 ) , + .clk_2_E_in ( clk_2_wires[50] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2958 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2959 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2960 ) , + .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2961 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2962 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2963 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2964 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2965 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2966 } ) , + .chany_top_in ( cby_1__1__33_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__41_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__32_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__30_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__41_ccff_tail ) , + .chany_top_out ( sb_1__1__30_chany_top_out ) , + .chanx_right_out ( sb_1__1__30_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__30_chanx_left_out ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2967 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2968 ) , + .pReset_E_in ( pResetWires[466] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2969 ) , + .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2970 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2971 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2972 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2973 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2974 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2975 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2976 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2978 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2979 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2980 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2981 ) , + .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2982 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2983 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2984 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2985 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2986 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2987 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2988 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2989 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2990 } ) , + .chany_top_in ( cby_1__1__34_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__42_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__33_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__31_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__42_ccff_tail ) , + .chany_top_out ( sb_1__1__31_chany_top_out ) , + .chanx_right_out ( sb_1__1__31_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__31_chanx_left_out ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2991 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2992 ) , + .pReset_E_in ( pResetWires[515] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2993 ) , + .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2994 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2995 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2997 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2998 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[63] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2999 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3000 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3001 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3002 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3003 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3004 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3005 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3007 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3008 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3009 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3010 ) , + .clk_2_E_in ( clk_2_wires[63] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3011 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3012 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3013 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3014 ) , + .clk_2_N_out ( clk_2_wires[64] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3015 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3016 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3017 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3018 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3019 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3020 } ) , + .chany_top_in ( cby_1__1__35_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__43_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__34_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__32_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__43_ccff_tail ) , + .chany_top_out ( sb_1__1__32_chany_top_out ) , + .chanx_right_out ( sb_1__1__32_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__32_chanx_left_out ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3021 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3022 ) , + .pReset_E_in ( pResetWires[564] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3023 ) , + .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3024 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3025 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3026 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3027 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3028 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3029 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3030 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3031 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3032 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3033 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3034 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3035 ) , + .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3036 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3037 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3039 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3040 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3041 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3042 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3043 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3044 } ) , + .chany_top_in ( cby_1__1__37_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__44_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__36_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__33_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__44_ccff_tail ) , + .chany_top_out ( sb_1__1__33_chany_top_out ) , + .chanx_right_out ( sb_1__1__33_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__33_chanx_left_out ) , + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3045 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3046 ) , + .pReset_E_in ( pResetWires[78] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3047 ) , + .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3048 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3049 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3051 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3052 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3053 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3054 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3055 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3056 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3057 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3058 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3059 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3060 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3064 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3065 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3066 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3067 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3068 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3069 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3070 } ) , + .chany_top_in ( cby_1__1__38_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__45_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__37_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__34_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__45_ccff_tail ) , + .chany_top_out ( sb_1__1__34_chany_top_out ) , + .chanx_right_out ( sb_1__1__34_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__34_chanx_left_out ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3071 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3072 ) , + .pReset_E_in ( pResetWires[127] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3073 ) , + .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3074 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3075 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3077 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3078 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3079 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3080 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3081 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3082 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3083 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3084 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3085 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3086 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3087 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3088 ) , + .clk_2_N_in ( clk_3_wires[25] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3089 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3090 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3091 ) , + .clk_2_W_out ( clk_2_wires[27] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3092 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3093 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3094 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3095 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3096 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3097 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3098 } ) , + .chany_top_in ( cby_1__1__39_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__46_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__38_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__35_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__46_ccff_tail ) , + .chany_top_out ( sb_1__1__35_chany_top_out ) , + .chanx_right_out ( sb_1__1__35_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__35_chanx_left_out ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3099 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3100 ) , + .pReset_E_in ( pResetWires[176] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3101 ) , + .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3102 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3103 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3105 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3106 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3107 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3108 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3109 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3110 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3111 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3112 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[21] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3113 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3114 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3115 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3116 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3117 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3118 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3119 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3120 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3121 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3122 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3123 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3124 ) , + .clk_3_N_in ( clk_3_wires[21] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3125 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3126 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3127 ) , + .clk_3_S_out ( clk_3_wires[24] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3128 } ) , + .chany_top_in ( cby_1__1__40_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__47_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__39_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__36_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__47_ccff_tail ) , + .chany_top_out ( sb_1__1__36_chany_top_out ) , + .chanx_right_out ( sb_1__1__36_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__36_chanx_left_out ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3129 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3130 ) , + .pReset_E_in ( pResetWires[225] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3131 ) , + .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3132 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3133 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3135 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3136 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3137 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3138 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[36] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3139 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3140 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[34] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3141 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3142 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3143 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[15] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3144 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3145 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3146 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3147 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3148 ) , + .clk_2_N_in ( clk_3_wires[15] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3149 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3150 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3151 ) , + .clk_2_W_out ( clk_2_wires[36] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3152 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3153 ) , + .clk_2_E_out ( clk_2_wires[34] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3154 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3155 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3156 ) , + .clk_3_N_in ( clk_3_wires[15] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3157 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3158 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3159 ) , + .clk_3_S_out ( clk_3_wires[20] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3160 } ) , + .chany_top_in ( cby_1__1__41_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__48_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__40_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__37_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__48_ccff_tail ) , + .chany_top_out ( sb_1__1__37_chany_top_out ) , + .chanx_right_out ( sb_1__1__37_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__37_chanx_left_out ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3161 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3162 ) , + .pReset_E_in ( pResetWires[274] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3163 ) , + .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3164 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3165 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3167 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3168 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3169 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3170 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3171 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3172 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3173 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3174 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[11] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3175 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3176 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3177 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3178 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3179 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3181 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3182 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3183 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3184 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3185 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3186 ) , + .clk_3_N_in ( clk_3_wires[11] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3187 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3188 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3189 ) , + .clk_3_S_out ( clk_3_wires[14] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3190 } ) , + .chany_top_in ( cby_1__1__42_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__49_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__41_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__38_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__49_ccff_tail ) , + .chany_top_out ( sb_1__1__38_chany_top_out ) , + .chanx_right_out ( sb_1__1__38_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__38_chanx_left_out ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3191 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3192 ) , + .pReset_E_in ( pResetWires[323] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3193 ) , + .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3194 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3195 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3197 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3198 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3199 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3200 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3201 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3202 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[7] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3203 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3204 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3205 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , + .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3206 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3207 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3209 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3210 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3211 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3212 ) , + .clk_3_E_in ( clk_3_wires[7] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3213 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3214 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3215 ) , + .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) , + .clk_3_S_out ( clk_3_wires[10] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3216 } ) , + .chany_top_in ( cby_1__1__43_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__50_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__42_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__39_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__50_ccff_tail ) , + .chany_top_out ( sb_1__1__39_chany_top_out ) , + .chanx_right_out ( sb_1__1__39_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__39_chanx_left_out ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3217 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3218 ) , + .pReset_E_in ( pResetWires[372] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3219 ) , + .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3220 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3221 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3223 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3224 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3225 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3226 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3227 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3228 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3229 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[9] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3230 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3231 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3232 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3233 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3234 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3237 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3238 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3239 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3240 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3241 ) , + .clk_3_S_in ( clk_3_wires[9] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3242 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3243 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3244 ) , + .clk_3_N_out ( clk_3_wires[12] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3245 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3246 } ) , + .chany_top_in ( cby_1__1__44_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__51_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__43_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__40_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__51_ccff_tail ) , + .chany_top_out ( sb_1__1__40_chany_top_out ) , + .chanx_right_out ( sb_1__1__40_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__40_chanx_left_out ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3247 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3248 ) , + .pReset_E_in ( pResetWires[421] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3249 ) , + .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3250 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3251 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3253 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3254 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3255 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[13] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3256 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[49] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3257 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3258 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[47] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3259 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3260 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[13] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3261 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3262 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3263 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3264 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3265 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3266 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3267 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3268 ) , + .clk_2_S_in ( clk_3_wires[13] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3269 ) , + .clk_2_W_out ( clk_2_wires[49] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3270 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3271 ) , + .clk_2_E_out ( clk_2_wires[47] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3272 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3273 ) , + .clk_3_S_in ( clk_3_wires[13] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3274 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3275 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3276 ) , + .clk_3_N_out ( clk_3_wires[18] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3277 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3278 } ) , + .chany_top_in ( cby_1__1__45_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__52_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__44_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__41_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__52_ccff_tail ) , + .chany_top_out ( sb_1__1__41_chany_top_out ) , + .chanx_right_out ( sb_1__1__41_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__41_chanx_left_out ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3279 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3280 ) , + .pReset_E_in ( pResetWires[470] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3281 ) , + .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3282 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3283 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3285 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3286 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3287 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3288 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3289 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3290 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3291 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[19] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3292 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3293 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3294 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3295 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3296 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3299 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3301 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3302 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3303 ) , + .clk_3_S_in ( clk_3_wires[19] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3304 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3305 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3306 ) , + .clk_3_N_out ( clk_3_wires[22] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3307 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3308 } ) , + .chany_top_in ( cby_1__1__46_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__53_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__45_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__42_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__53_ccff_tail ) , + .chany_top_out ( sb_1__1__42_chany_top_out ) , + .chanx_right_out ( sb_1__1__42_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__42_chanx_left_out ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3309 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3310 ) , + .pReset_E_in ( pResetWires[519] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3311 ) , + .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3312 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3313 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3315 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3316 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3317 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[23] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3318 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3319 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3320 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3322 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3323 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3324 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3325 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3326 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3327 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3328 ) , + .clk_2_S_in ( clk_3_wires[23] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3329 ) , + .clk_2_W_out ( clk_2_wires[62] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3330 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3331 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3332 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3333 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3334 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3335 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3336 } ) , + .chany_top_in ( cby_1__1__47_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__54_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__46_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__43_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__54_ccff_tail ) , + .chany_top_out ( sb_1__1__43_chany_top_out ) , + .chanx_right_out ( sb_1__1__43_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__43_chanx_left_out ) , + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3337 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3338 ) , + .pReset_E_in ( pResetWires[568] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3339 ) , + .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3340 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3341 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3343 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3344 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3345 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3346 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3347 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3348 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3349 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3350 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3351 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3352 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3355 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3356 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3357 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3358 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3359 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3360 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3361 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3362 } ) , + .chany_top_in ( cby_1__1__49_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__55_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__48_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__44_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__55_ccff_tail ) , + .chany_top_out ( sb_1__1__44_chany_top_out ) , + .chanx_right_out ( sb_1__1__44_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__44_chanx_left_out ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3363 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3364 ) , + .pReset_E_in ( pResetWires[82] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3365 ) , + .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3366 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3367 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3368 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3369 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3370 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3371 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3372 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3373 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3374 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3375 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3376 ) , + .clk_1_N_in ( clk_2_wires[32] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3377 ) , + .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3378 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3379 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3381 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3382 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3383 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3384 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3385 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3386 } ) , + .chany_top_in ( cby_1__1__50_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__56_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__49_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__45_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__56_ccff_tail ) , + .chany_top_out ( sb_1__1__45_chany_top_out ) , + .chanx_right_out ( sb_1__1__45_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__45_chanx_left_out ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3387 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3388 ) , + .pReset_E_in ( pResetWires[131] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3389 ) , + .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3390 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3391 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3393 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3394 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3395 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3396 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[26] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3397 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3398 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3399 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3400 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3401 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3402 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3403 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3404 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3405 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3406 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3407 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3408 ) , + .clk_2_W_in ( clk_2_wires[26] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3409 ) , + .clk_2_S_out ( clk_2_wires[31] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3410 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3411 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3412 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3413 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3414 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3415 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3416 } ) , + .chany_top_in ( cby_1__1__51_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__57_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__50_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__46_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__57_ccff_tail ) , + .chany_top_out ( sb_1__1__46_chany_top_out ) , + .chanx_right_out ( sb_1__1__46_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__46_chanx_left_out ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3417 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3418 ) , + .pReset_E_in ( pResetWires[180] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3419 ) , + .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3420 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3421 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3422 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3423 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3424 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3425 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3426 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3427 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3428 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3429 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3430 ) , + .clk_1_N_in ( clk_2_wires[45] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3431 ) , + .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3432 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3433 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3435 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3436 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3437 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3438 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3439 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3440 } ) , + .chany_top_in ( cby_1__1__52_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__58_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__51_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__47_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__58_ccff_tail ) , + .chany_top_out ( sb_1__1__47_chany_top_out ) , + .chanx_right_out ( sb_1__1__47_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__47_chanx_left_out ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3441 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3442 ) , + .pReset_E_in ( pResetWires[229] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3443 ) , + .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3444 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3445 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3447 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3448 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3449 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3450 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[35] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3451 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3452 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3453 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3454 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3455 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3456 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3457 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3458 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3459 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3460 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3461 ) , + .clk_2_W_in ( clk_2_wires[35] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3462 ) , + .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3463 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3464 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3465 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3466 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3467 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3468 } ) , + .chany_top_in ( cby_1__1__53_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__59_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__52_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__48_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__59_ccff_tail ) , + .chany_top_out ( sb_1__1__48_chany_top_out ) , + .chanx_right_out ( sb_1__1__48_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__48_chanx_left_out ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3469 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3470 ) , + .pReset_E_in ( pResetWires[278] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3471 ) , + .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3472 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3473 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3474 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3475 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3476 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3477 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3478 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3479 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3480 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3481 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3482 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3483 ) , + .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3484 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3485 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3486 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3487 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3488 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3489 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3490 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3491 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3492 } ) , + .chany_top_in ( cby_1__1__54_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__60_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__53_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__49_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__60_ccff_tail ) , + .chany_top_out ( sb_1__1__49_chany_top_out ) , + .chanx_right_out ( sb_1__1__49_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__49_chanx_left_out ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3493 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3494 ) , + .pReset_E_in ( pResetWires[327] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3495 ) , + .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3496 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3497 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3499 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3500 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3501 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3502 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3503 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3504 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[3] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3505 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3506 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3507 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3508 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3509 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3510 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3513 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3514 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3515 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3516 ) , + .clk_3_E_in ( clk_3_wires[3] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3517 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3518 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3519 ) , + .clk_3_W_out ( clk_3_wires[6] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3520 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3521 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3522 } ) , + .chany_top_in ( cby_1__1__55_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__61_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__54_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__50_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__61_ccff_tail ) , + .chany_top_out ( sb_1__1__50_chany_top_out ) , + .chanx_right_out ( sb_1__1__50_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__50_chanx_left_out ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3523 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3524 ) , + .pReset_E_in ( pResetWires[376] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3525 ) , + .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3526 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3527 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3528 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3529 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3530 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3531 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3532 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3533 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3534 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3535 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3536 ) , + .clk_1_N_in ( clk_2_wires[58] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3537 ) , + .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3538 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3539 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3540 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3541 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3542 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3543 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3544 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3545 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3546 } ) , + .chany_top_in ( cby_1__1__56_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__62_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__55_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__51_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__62_ccff_tail ) , + .chany_top_out ( sb_1__1__51_chany_top_out ) , + .chanx_right_out ( sb_1__1__51_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__51_chanx_left_out ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3547 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3548 ) , + .pReset_E_in ( pResetWires[425] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3549 ) , + .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3550 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3551 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3553 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3554 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3555 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3556 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[48] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3557 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3558 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3559 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3560 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3561 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3562 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3563 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3564 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3565 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3566 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3567 ) , + .clk_2_W_in ( clk_2_wires[48] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3568 ) , + .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3569 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3570 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3571 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3572 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3573 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3574 } ) , + .chany_top_in ( cby_1__1__57_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__63_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__56_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__52_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__63_ccff_tail ) , + .chany_top_out ( sb_1__1__52_chany_top_out ) , + .chanx_right_out ( sb_1__1__52_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__52_chanx_left_out ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3575 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3576 ) , + .pReset_E_in ( pResetWires[474] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3577 ) , + .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3578 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3579 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3580 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3581 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3582 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3583 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3584 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3585 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3586 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3587 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3588 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3589 ) , + .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3590 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3591 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3592 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3594 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3595 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3596 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3597 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3598 } ) , + .chany_top_in ( cby_1__1__58_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__64_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__57_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__53_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__64_ccff_tail ) , + .chany_top_out ( sb_1__1__53_chany_top_out ) , + .chanx_right_out ( sb_1__1__53_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__53_chanx_left_out ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3599 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3600 ) , + .pReset_E_in ( pResetWires[523] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3601 ) , + .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3602 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3603 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3605 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3606 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3607 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3608 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[61] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3609 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3610 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3611 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3612 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3613 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3614 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3615 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3616 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3617 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3618 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3619 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3620 ) , + .clk_2_W_in ( clk_2_wires[61] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3621 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3622 ) , + .clk_2_N_out ( clk_2_wires[66] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3623 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3624 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3625 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3626 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3627 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3628 } ) , + .chany_top_in ( cby_1__1__59_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__65_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__58_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__54_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__65_ccff_tail ) , + .chany_top_out ( sb_1__1__54_chany_top_out ) , + .chanx_right_out ( sb_1__1__54_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__54_chanx_left_out ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3629 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3630 ) , + .pReset_E_in ( pResetWires[572] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3631 ) , + .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3632 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3633 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3634 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3635 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3636 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3637 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3638 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3639 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3640 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3641 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3642 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3643 ) , + .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3644 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3645 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3646 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3647 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3648 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3649 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3650 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3651 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3652 } ) , + .chany_top_in ( cby_1__1__61_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__66_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__60_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__55_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__66_ccff_tail ) , + .chany_top_out ( sb_1__1__55_chany_top_out ) , + .chanx_right_out ( sb_1__1__55_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__55_chanx_left_out ) , + .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) , + .Test_en_N_out ( Test_enWires[3] ) , .pReset_S_in ( pResetWires[2] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3653 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3654 ) , + .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) , + .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) , + .Reset_N_out ( ResetWires[3] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3655 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3656 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3657 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3658 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3659 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3660 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3661 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3662 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[89] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3663 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3664 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3665 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3666 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3667 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3669 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3670 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3671 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3672 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3673 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3674 ) , + .clk_3_S_in ( clk_3_wires[89] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3675 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3676 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3677 ) , + .clk_3_N_out ( clk_3_wires[92] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3678 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3679 } ) , + .chany_top_in ( cby_1__1__62_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__67_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__61_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__56_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__67_ccff_tail ) , + .chany_top_out ( sb_1__1__56_chany_top_out ) , + .chanx_right_out ( sb_1__1__56_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__56_chanx_left_out ) , + .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) , + .Test_en_N_out ( Test_enWires[5] ) , .pReset_S_in ( pResetWires[4] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3680 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3681 ) , + .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) , + .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) , + .Reset_N_out ( ResetWires[5] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3682 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3683 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3684 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3685 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3686 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3687 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3688 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3689 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[91] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3690 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3691 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3692 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3693 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3694 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3697 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3698 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3699 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3700 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3701 ) , + .clk_3_S_in ( clk_3_wires[91] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3702 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3703 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3704 ) , + .clk_3_N_out ( clk_3_wires[94] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3705 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3706 } ) , + .chany_top_in ( cby_1__1__63_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__68_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__62_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__57_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__68_ccff_tail ) , + .chany_top_out ( sb_1__1__57_chany_top_out ) , + .chanx_right_out ( sb_1__1__57_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__57_chanx_left_out ) , + .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) , + .Test_en_N_out ( Test_enWires[7] ) , .pReset_S_in ( pResetWires[6] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3707 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3708 ) , + .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) , + .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) , + .Reset_N_out ( ResetWires[7] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3709 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3710 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3711 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3712 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3713 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3714 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3715 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3716 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[93] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3717 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3718 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3719 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3720 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3721 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3723 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3724 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3725 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3726 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3727 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3728 ) , + .clk_3_S_in ( clk_3_wires[93] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3729 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3730 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3731 ) , + .clk_3_N_out ( clk_3_wires[96] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3732 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3733 } ) , + .chany_top_in ( cby_1__1__64_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__69_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__63_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__58_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__69_ccff_tail ) , + .chany_top_out ( sb_1__1__58_chany_top_out ) , + .chanx_right_out ( sb_1__1__58_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__58_chanx_left_out ) , + .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) , + .Test_en_N_out ( Test_enWires[9] ) , .pReset_S_in ( pResetWires[8] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3734 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3735 ) , + .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) , + .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) , + .Reset_N_out ( ResetWires[9] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3736 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3737 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3738 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3739 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3740 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3741 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3742 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3743 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[95] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3744 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3745 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3746 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3747 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3748 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3751 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3752 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3753 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3754 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3755 ) , + .clk_3_S_in ( clk_3_wires[95] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3756 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3757 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3758 ) , + .clk_3_N_out ( clk_3_wires[98] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3759 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3760 } ) , + .chany_top_in ( cby_1__1__65_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__70_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__64_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__59_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__70_ccff_tail ) , + .chany_top_out ( sb_1__1__59_chany_top_out ) , + .chanx_right_out ( sb_1__1__59_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__59_chanx_left_out ) , + .ccff_tail ( sb_1__1__59_ccff_tail ) , + .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) , + .pReset_S_in ( pResetWires[10] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3761 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3762 ) , + .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) , + .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) , + .Reset_N_out ( ResetWires[11] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3763 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3764 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3765 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3766 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3767 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3768 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3769 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3770 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[97] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3771 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3772 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3773 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3774 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3775 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3778 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3779 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3780 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3781 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3782 ) , + .clk_3_S_in ( clk_3_wires[97] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3783 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3784 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3785 ) , + .clk_3_N_out ( clk_3_wires[100] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3786 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3787 } ) , + .chany_top_in ( cby_1__1__66_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__71_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__65_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__60_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__71_ccff_tail ) , + .chany_top_out ( sb_1__1__60_chany_top_out ) , + .chanx_right_out ( sb_1__1__60_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__60_chanx_left_out ) , + .ccff_tail ( sb_1__1__60_ccff_tail ) , + .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) , + .pReset_S_in ( pResetWires[12] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3788 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3789 ) , + .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) , + .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) , + .Reset_N_out ( ResetWires[13] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3790 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3791 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3792 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3793 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3795 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3796 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3797 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[99] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3798 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , + .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3799 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3800 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3801 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3804 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3805 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3806 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3807 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3808 ) , + .clk_3_S_in ( clk_3_wires[99] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3809 ) , + .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3810 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3811 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3812 } ) , + .chany_top_in ( cby_1__1__67_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__72_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__66_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__61_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__72_ccff_tail ) , + .chany_top_out ( sb_1__1__61_chany_top_out ) , + .chanx_right_out ( sb_1__1__61_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__61_chanx_left_out ) , + .ccff_tail ( sb_1__1__61_ccff_tail ) , + .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) , + .pReset_S_in ( pResetWires[14] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3813 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3814 ) , + .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) , + .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) , + .Reset_N_out ( ResetWires[15] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3815 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3816 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3817 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3818 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3819 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3820 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3821 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3822 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3823 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3824 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3825 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3828 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3829 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3831 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3832 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3833 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3834 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3835 } ) , + .chany_top_in ( cby_1__1__68_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__73_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__67_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__62_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__73_ccff_tail ) , + .chany_top_out ( sb_1__1__62_chany_top_out ) , + .chanx_right_out ( sb_1__1__62_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__62_chanx_left_out ) , + .ccff_tail ( sb_1__1__62_ccff_tail ) , + .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) , + .pReset_S_in ( pResetWires[16] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3836 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3837 ) , + .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) , + .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) , + .Reset_N_out ( ResetWires[17] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3838 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3839 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3840 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3841 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3842 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3843 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3844 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3845 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3846 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3847 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3848 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3850 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3853 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3854 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3855 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3856 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3857 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3858 } ) , + .chany_top_in ( cby_1__1__69_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__74_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__68_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__63_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__74_ccff_tail ) , + .chany_top_out ( sb_1__1__63_chany_top_out ) , + .chanx_right_out ( sb_1__1__63_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__63_chanx_left_out ) , + .ccff_tail ( sb_1__1__63_ccff_tail ) , + .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) , + .pReset_S_in ( pResetWires[18] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3859 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3860 ) , + .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) , + .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) , + .Reset_N_out ( ResetWires[19] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3861 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3862 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3863 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3864 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3865 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3866 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3867 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3868 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3869 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3870 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3871 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3874 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3875 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3876 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3878 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3879 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3880 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3881 } ) , + .chany_top_in ( cby_1__1__70_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__75_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__69_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__64_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__75_ccff_tail ) , + .chany_top_out ( sb_1__1__64_chany_top_out ) , + .chanx_right_out ( sb_1__1__64_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__64_chanx_left_out ) , + .ccff_tail ( sb_1__1__64_ccff_tail ) , + .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) , + .pReset_S_in ( pResetWires[20] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3882 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3883 ) , + .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) , + .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) , + .Reset_N_out ( ResetWires[21] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3884 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3885 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3886 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3887 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3888 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3889 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3890 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3891 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3892 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3893 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3894 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3897 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3898 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3899 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3901 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3902 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3903 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3904 } ) , + .chany_top_in ( cby_1__1__71_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__76_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__70_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__65_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__76_ccff_tail ) , + .chany_top_out ( sb_1__1__65_chany_top_out ) , + .chanx_right_out ( sb_1__1__65_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__65_chanx_left_out ) , + .ccff_tail ( sb_1__1__65_ccff_tail ) , + .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) , + .pReset_S_in ( pResetWires[22] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3905 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3906 ) , + .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) , + .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) , + .Reset_N_out ( ResetWires[23] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3907 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3908 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3909 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3910 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3911 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3912 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3913 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3914 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3915 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3916 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3917 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3919 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3920 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3921 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3922 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3923 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3924 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3925 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3926 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3927 } ) , + .chany_top_in ( cby_1__1__73_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__77_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__72_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__66_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__77_ccff_tail ) , + .chany_top_out ( sb_1__1__66_chany_top_out ) , + .chanx_right_out ( sb_1__1__66_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__66_chanx_left_out ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3928 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3929 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3930 ) , + .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3931 ) , + .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3932 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3933 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3934 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3935 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3936 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3937 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3938 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3939 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3940 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3941 ) , + .clk_1_N_in ( clk_2_wires[74] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3942 ) , + .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3943 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3944 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3946 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3947 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3948 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3949 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3950 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3951 } ) , + .chany_top_in ( cby_1__1__74_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__78_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__73_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__67_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__78_ccff_tail ) , + .chany_top_out ( sb_1__1__67_chany_top_out ) , + .chanx_right_out ( sb_1__1__67_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__67_chanx_left_out ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3952 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3953 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3954 ) , + .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3955 ) , + .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3956 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3957 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3958 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3959 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[72] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3960 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3961 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3962 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3963 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3964 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3965 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3966 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3967 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3968 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3969 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3970 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3971 ) , + .clk_2_E_in ( clk_2_wires[72] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3972 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3973 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3974 ) , + .clk_2_S_out ( clk_2_wires[73] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3975 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3976 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3977 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3978 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3979 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3980 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3981 } ) , + .chany_top_in ( cby_1__1__75_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__79_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__74_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__68_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__79_ccff_tail ) , + .chany_top_out ( sb_1__1__68_chany_top_out ) , + .chanx_right_out ( sb_1__1__68_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__68_chanx_left_out ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3982 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3983 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3984 ) , + .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3985 ) , + .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3986 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3987 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3988 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3989 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3990 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3991 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3992 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3993 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3994 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3995 ) , + .clk_1_N_in ( clk_2_wires[85] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3996 ) , + .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3997 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3998 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4002 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4003 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4004 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4005 } ) , + .chany_top_in ( cby_1__1__76_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__80_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__75_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__69_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__80_ccff_tail ) , + .chany_top_out ( sb_1__1__69_chany_top_out ) , + .chanx_right_out ( sb_1__1__69_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__69_chanx_left_out ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4006 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4007 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4008 ) , + .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4009 ) , + .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4010 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4011 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4012 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4013 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[81] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4014 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4015 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4016 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4017 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4018 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4019 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4020 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4021 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4022 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4023 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4024 ) , + .clk_2_E_in ( clk_2_wires[81] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4025 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4026 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4027 ) , + .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4028 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4029 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4030 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4031 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4032 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4033 } ) , + .chany_top_in ( cby_1__1__77_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__81_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__76_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__70_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__81_ccff_tail ) , + .chany_top_out ( sb_1__1__70_chany_top_out ) , + .chanx_right_out ( sb_1__1__70_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__70_chanx_left_out ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4034 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4035 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4036 ) , + .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4037 ) , + .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4038 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4039 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4040 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4041 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4042 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4043 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4044 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4045 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4046 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4047 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4048 ) , + .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4049 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4050 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4051 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4052 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4053 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4054 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4055 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4056 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4057 } ) , + .chany_top_in ( cby_1__1__78_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__82_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__77_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__71_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__82_ccff_tail ) , + .chany_top_out ( sb_1__1__71_chany_top_out ) , + .chanx_right_out ( sb_1__1__71_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__71_chanx_left_out ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4058 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4059 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4060 ) , + .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4061 ) , + .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4062 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4063 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4064 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4065 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4066 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4067 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4068 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[1] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4069 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4070 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4071 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4072 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4073 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4074 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4075 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4078 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4079 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4080 ) , + .clk_3_W_in ( clk_3_wires[1] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4081 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4082 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4083 ) , + .clk_3_E_out ( clk_3_wires[4] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4084 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4085 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4086 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4087 } ) , + .chany_top_in ( cby_1__1__79_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__83_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__78_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__72_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__83_ccff_tail ) , + .chany_top_out ( sb_1__1__72_chany_top_out ) , + .chanx_right_out ( sb_1__1__72_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__72_chanx_left_out ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4088 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4089 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4090 ) , + .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4091 ) , + .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4092 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4093 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4094 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4095 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4096 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4097 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4098 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4099 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4100 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4101 ) , + .clk_1_N_in ( clk_2_wires[98] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4102 ) , + .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4103 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4104 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4105 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4106 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4107 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4108 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4109 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4110 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4111 } ) , + .chany_top_in ( cby_1__1__80_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__84_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__79_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__73_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__84_ccff_tail ) , + .chany_top_out ( sb_1__1__73_chany_top_out ) , + .chanx_right_out ( sb_1__1__73_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__73_chanx_left_out ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4112 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4113 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4114 ) , + .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4115 ) , + .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4116 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4117 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4118 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4119 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[94] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4120 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4121 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4122 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4123 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4124 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4125 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4126 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4127 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4128 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4129 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4130 ) , + .clk_2_E_in ( clk_2_wires[94] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4131 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4132 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4133 ) , + .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4134 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4135 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4136 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4137 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4138 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4139 } ) , + .chany_top_in ( cby_1__1__81_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__85_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__80_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__74_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__85_ccff_tail ) , + .chany_top_out ( sb_1__1__74_chany_top_out ) , + .chanx_right_out ( sb_1__1__74_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__74_chanx_left_out ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4140 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4141 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4142 ) , + .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4143 ) , + .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4144 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4145 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4146 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4147 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4148 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4149 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4150 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4151 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4152 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4153 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4154 ) , + .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4155 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4156 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4157 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4158 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4159 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4160 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4161 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4162 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4163 } ) , + .chany_top_in ( cby_1__1__82_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__86_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__81_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__75_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__86_ccff_tail ) , + .chany_top_out ( sb_1__1__75_chany_top_out ) , + .chanx_right_out ( sb_1__1__75_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__75_chanx_left_out ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4164 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4165 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4166 ) , + .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4167 ) , + .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4168 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4169 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4170 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4171 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[107] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4172 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4173 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4174 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4175 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4176 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4177 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4178 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4179 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4180 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4181 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4182 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4183 ) , + .clk_2_E_in ( clk_2_wires[107] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4184 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4185 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4186 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4187 ) , + .clk_2_N_out ( clk_2_wires[108] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4188 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4189 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4190 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4192 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4193 } ) , + .chany_top_in ( cby_1__1__83_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__87_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__82_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__76_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__87_ccff_tail ) , + .chany_top_out ( sb_1__1__76_chany_top_out ) , + .chanx_right_out ( sb_1__1__76_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__76_chanx_left_out ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4194 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4195 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4196 ) , + .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4197 ) , + .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4198 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4199 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4200 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4201 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4202 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4203 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4204 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4205 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4206 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4207 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4208 ) , + .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4209 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4210 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4211 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4212 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4213 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4214 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4215 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4216 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4217 } ) , + .chany_top_in ( cby_1__1__85_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__88_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__84_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__77_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__88_ccff_tail ) , + .chany_top_out ( sb_1__1__77_chany_top_out ) , + .chanx_right_out ( sb_1__1__77_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__77_chanx_left_out ) , + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4218 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4219 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4220 ) , + .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4221 ) , + .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4222 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4223 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4224 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4225 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4226 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4227 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4228 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4229 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4230 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4231 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4232 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4233 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4236 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4237 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4239 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4240 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4241 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4242 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4243 } ) , + .chany_top_in ( cby_1__1__86_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__89_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__85_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__78_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__89_ccff_tail ) , + .chany_top_out ( sb_1__1__78_chany_top_out ) , + .chanx_right_out ( sb_1__1__78_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__78_chanx_left_out ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4244 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4245 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4246 ) , + .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4247 ) , + .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4248 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4249 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4250 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4251 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4252 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4253 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4254 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4255 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4256 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4257 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4258 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4259 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4260 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4261 ) , + .clk_2_N_in ( clk_3_wires[43] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4262 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4263 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4264 ) , + .clk_2_W_out ( clk_2_wires[71] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4265 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4266 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4267 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4268 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4269 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4270 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4271 } ) , + .chany_top_in ( cby_1__1__87_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__90_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__86_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__79_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__90_ccff_tail ) , + .chany_top_out ( sb_1__1__79_chany_top_out ) , + .chanx_right_out ( sb_1__1__79_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__79_chanx_left_out ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4272 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4273 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4274 ) , + .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4275 ) , + .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4276 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4277 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4278 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4279 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4280 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4281 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4282 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4283 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4284 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4285 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[39] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4286 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4287 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4288 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4289 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4290 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4292 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4293 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4294 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4295 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4296 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4297 ) , + .clk_3_N_in ( clk_3_wires[39] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4298 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4299 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4300 ) , + .clk_3_S_out ( clk_3_wires[42] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4301 } ) , + .chany_top_in ( cby_1__1__88_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__91_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__87_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__80_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__91_ccff_tail ) , + .chany_top_out ( sb_1__1__80_chany_top_out ) , + .chanx_right_out ( sb_1__1__80_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__80_chanx_left_out ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4302 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4303 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4304 ) , + .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4305 ) , + .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4306 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4307 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4308 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4309 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4310 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4311 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[80] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4312 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4313 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[78] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4314 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4315 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4316 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[33] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4317 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4318 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4319 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4320 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4321 ) , + .clk_2_N_in ( clk_3_wires[33] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4322 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4323 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4324 ) , + .clk_2_W_out ( clk_2_wires[80] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4325 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4326 ) , + .clk_2_E_out ( clk_2_wires[78] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4327 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4328 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4329 ) , + .clk_3_N_in ( clk_3_wires[33] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4330 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4331 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4332 ) , + .clk_3_S_out ( clk_3_wires[38] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4333 } ) , + .chany_top_in ( cby_1__1__89_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__92_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__88_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__81_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__92_ccff_tail ) , + .chany_top_out ( sb_1__1__81_chany_top_out ) , + .chanx_right_out ( sb_1__1__81_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__81_chanx_left_out ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4334 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4335 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4336 ) , + .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4337 ) , + .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4338 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4339 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4340 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4341 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4342 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4343 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4344 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4345 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4346 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4347 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[29] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4348 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4349 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4350 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4351 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4352 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4353 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4354 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4355 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4356 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4357 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4358 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4359 ) , + .clk_3_N_in ( clk_3_wires[29] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4360 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4361 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4362 ) , + .clk_3_S_out ( clk_3_wires[32] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4363 } ) , + .chany_top_in ( cby_1__1__90_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__93_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__89_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__82_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__93_ccff_tail ) , + .chany_top_out ( sb_1__1__82_chany_top_out ) , + .chanx_right_out ( sb_1__1__82_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__82_chanx_left_out ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4364 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4365 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4366 ) , + .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4367 ) , + .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4368 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4369 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4370 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4371 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4372 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4373 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4374 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[5] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4375 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4376 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4377 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4378 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4379 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4380 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4382 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4383 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4384 ) , + .clk_3_W_in ( clk_3_wires[5] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4385 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4386 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4387 ) , + .clk_3_E_out ( clk_3_wires[44] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4388 ) , + .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4389 } ) , + .chany_top_in ( cby_1__1__91_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__94_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__90_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__83_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__94_ccff_tail ) , + .chany_top_out ( sb_1__1__83_chany_top_out ) , + .chanx_right_out ( sb_1__1__83_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__83_chanx_left_out ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4390 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4391 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4392 ) , + .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4393 ) , + .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4394 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4395 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4396 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4397 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4398 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4399 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4400 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4401 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4402 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[27] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4403 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4404 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4405 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4406 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4407 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4410 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4411 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4412 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4413 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4414 ) , + .clk_3_S_in ( clk_3_wires[27] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4415 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4416 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4417 ) , + .clk_3_N_out ( clk_3_wires[30] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4418 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4419 } ) , + .chany_top_in ( cby_1__1__92_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__95_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__91_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__84_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__95_ccff_tail ) , + .chany_top_out ( sb_1__1__84_chany_top_out ) , + .chanx_right_out ( sb_1__1__84_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__84_chanx_left_out ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4420 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4421 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4422 ) , + .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4423 ) , + .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4424 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4425 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4426 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4427 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4428 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[31] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4429 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[93] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4430 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4431 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[91] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4432 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4433 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[31] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4434 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4436 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4437 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4438 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4439 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4440 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4441 ) , + .clk_2_S_in ( clk_3_wires[31] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4442 ) , + .clk_2_W_out ( clk_2_wires[93] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4443 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4444 ) , + .clk_2_E_out ( clk_2_wires[91] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4445 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4446 ) , + .clk_3_S_in ( clk_3_wires[31] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4447 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4449 ) , + .clk_3_N_out ( clk_3_wires[36] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4450 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4451 } ) , + .chany_top_in ( cby_1__1__93_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__96_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__92_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__85_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__96_ccff_tail ) , + .chany_top_out ( sb_1__1__85_chany_top_out ) , + .chanx_right_out ( sb_1__1__85_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__85_chanx_left_out ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4452 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4453 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4454 ) , + .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4455 ) , + .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4456 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4457 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4458 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4459 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4460 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4461 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4462 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4463 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4464 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[37] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4465 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4466 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4467 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4468 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4469 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4471 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4472 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4473 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4474 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4475 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4476 ) , + .clk_3_S_in ( clk_3_wires[37] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4477 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4478 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4479 ) , + .clk_3_N_out ( clk_3_wires[40] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4480 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4481 } ) , + .chany_top_in ( cby_1__1__94_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__97_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__93_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__86_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__97_ccff_tail ) , + .chany_top_out ( sb_1__1__86_chany_top_out ) , + .chanx_right_out ( sb_1__1__86_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__86_chanx_left_out ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4482 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4483 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4484 ) , + .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4485 ) , + .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4486 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4487 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4488 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4489 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4490 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[41] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4491 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4492 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4493 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4494 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4495 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4496 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4497 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4498 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4499 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4500 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4501 ) , + .clk_2_S_in ( clk_3_wires[41] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4502 ) , + .clk_2_W_out ( clk_2_wires[106] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4503 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4504 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4505 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4506 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4507 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4508 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4509 } ) , + .chany_top_in ( cby_1__1__95_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__98_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__94_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__87_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__98_ccff_tail ) , + .chany_top_out ( sb_1__1__87_chany_top_out ) , + .chanx_right_out ( sb_1__1__87_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__87_chanx_left_out ) , + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4510 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4511 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4512 ) , + .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4513 ) , + .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4514 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4515 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4516 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4517 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4518 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4519 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4520 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4521 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4522 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4523 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4524 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4525 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4527 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4528 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4529 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4530 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4531 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4532 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4533 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4534 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4535 } ) , + .chany_top_in ( cby_1__1__97_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__99_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__96_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__88_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__99_ccff_tail ) , + .chany_top_out ( sb_1__1__88_chany_top_out ) , + .chanx_right_out ( sb_1__1__88_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__88_chanx_left_out ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4536 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4537 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4538 ) , + .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4539 ) , + .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4540 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4541 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4542 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4543 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4544 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4545 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4546 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4547 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4548 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4549 ) , + .clk_1_N_in ( clk_2_wires[76] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4550 ) , + .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4551 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4552 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4553 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4554 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4555 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4556 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4557 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4558 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4559 } ) , + .chany_top_in ( cby_1__1__98_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__100_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__97_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__89_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__100_ccff_tail ) , + .chany_top_out ( sb_1__1__89_chany_top_out ) , + .chanx_right_out ( sb_1__1__89_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__89_chanx_left_out ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4560 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4561 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4562 ) , + .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4563 ) , + .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4564 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4565 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4566 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4567 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4568 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4569 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[70] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4570 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4571 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4572 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4573 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4574 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4575 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4576 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4577 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4578 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4579 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4580 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4581 ) , + .clk_2_W_in ( clk_2_wires[70] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4582 ) , + .clk_2_S_out ( clk_2_wires[75] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4583 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4584 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4585 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4586 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4587 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4588 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4589 } ) , + .chany_top_in ( cby_1__1__99_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__101_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__98_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__90_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__101_ccff_tail ) , + .chany_top_out ( sb_1__1__90_chany_top_out ) , + .chanx_right_out ( sb_1__1__90_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__90_chanx_left_out ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4590 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4591 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4592 ) , + .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4593 ) , + .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4594 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4595 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4596 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4597 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4598 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4599 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4600 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4601 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4602 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4603 ) , + .clk_1_N_in ( clk_2_wires[89] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4604 ) , + .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4605 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4606 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4607 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4608 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4609 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4610 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4611 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4612 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4613 } ) , + .chany_top_in ( cby_1__1__100_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__102_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__99_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__91_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__102_ccff_tail ) , + .chany_top_out ( sb_1__1__91_chany_top_out ) , + .chanx_right_out ( sb_1__1__91_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__91_chanx_left_out ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4614 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4615 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4616 ) , + .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4617 ) , + .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4618 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4619 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4620 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4621 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4622 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4623 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[79] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4624 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4625 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4626 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4627 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4628 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4629 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4630 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4631 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4632 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4633 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4634 ) , + .clk_2_W_in ( clk_2_wires[79] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4635 ) , + .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4636 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4637 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4638 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4639 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4640 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4641 } ) , + .chany_top_in ( cby_1__1__101_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__103_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__100_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__92_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__103_ccff_tail ) , + .chany_top_out ( sb_1__1__92_chany_top_out ) , + .chanx_right_out ( sb_1__1__92_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__92_chanx_left_out ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4642 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4643 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4644 ) , + .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4645 ) , + .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4646 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4647 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4648 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4649 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4650 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4651 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4652 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4653 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4654 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4655 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4656 ) , + .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4657 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4658 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4659 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4660 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4661 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4662 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4663 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4664 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4665 } ) , + .chany_top_in ( cby_1__1__102_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__104_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__101_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__93_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__104_ccff_tail ) , + .chany_top_out ( sb_1__1__93_chany_top_out ) , + .chanx_right_out ( sb_1__1__93_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__93_chanx_left_out ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4666 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4667 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4668 ) , + .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4669 ) , + .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4670 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4671 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4672 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4673 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4674 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4675 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4676 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[45] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4677 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4678 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4679 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4680 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4682 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4683 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4686 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4687 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4688 ) , + .clk_3_W_in ( clk_3_wires[45] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4689 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4690 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4691 ) , + .clk_3_E_out ( clk_3_wires[48] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4692 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4693 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4694 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4695 } ) , + .chany_top_in ( cby_1__1__103_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__105_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__102_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__94_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__105_ccff_tail ) , + .chany_top_out ( sb_1__1__94_chany_top_out ) , + .chanx_right_out ( sb_1__1__94_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__94_chanx_left_out ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4696 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4697 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4698 ) , + .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4699 ) , + .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4700 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4701 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4702 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4703 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4704 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4705 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4706 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4707 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4708 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4709 ) , + .clk_1_N_in ( clk_2_wires[102] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4710 ) , + .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4711 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4712 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4713 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4714 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4715 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4716 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4717 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4718 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4719 } ) , + .chany_top_in ( cby_1__1__104_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__106_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__103_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__95_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__106_ccff_tail ) , + .chany_top_out ( sb_1__1__95_chany_top_out ) , + .chanx_right_out ( sb_1__1__95_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__95_chanx_left_out ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4720 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4721 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4722 ) , + .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4723 ) , + .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4724 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4725 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4726 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4727 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4728 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4729 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[92] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4730 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4731 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4733 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4734 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4735 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4736 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4737 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4738 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4739 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4740 ) , + .clk_2_W_in ( clk_2_wires[92] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4741 ) , + .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4742 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4743 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4744 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4745 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4746 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4747 } ) , + .chany_top_in ( cby_1__1__105_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__107_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__104_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__96_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__107_ccff_tail ) , + .chany_top_out ( sb_1__1__96_chany_top_out ) , + .chanx_right_out ( sb_1__1__96_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__96_chanx_left_out ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4748 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4749 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4750 ) , + .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4751 ) , + .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4752 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4753 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4754 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4755 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4756 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4757 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4758 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4759 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4760 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4761 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4762 ) , + .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4763 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4764 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4765 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4766 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4767 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4768 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4769 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4770 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4771 } ) , + .chany_top_in ( cby_1__1__106_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__108_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__105_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__97_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__108_ccff_tail ) , + .chany_top_out ( sb_1__1__97_chany_top_out ) , + .chanx_right_out ( sb_1__1__97_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__97_chanx_left_out ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4772 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4773 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4774 ) , + .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4775 ) , + .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4776 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4777 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4778 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4779 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4780 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4781 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[105] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4782 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4783 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4784 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4785 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4786 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4787 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4788 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4789 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4790 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4791 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4792 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4793 ) , + .clk_2_W_in ( clk_2_wires[105] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4794 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4795 ) , + .clk_2_N_out ( clk_2_wires[110] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4796 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4797 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4798 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4799 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4800 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4801 } ) , + .chany_top_in ( cby_1__1__107_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__109_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__106_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__98_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__109_ccff_tail ) , + .chany_top_out ( sb_1__1__98_chany_top_out ) , + .chanx_right_out ( sb_1__1__98_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__98_chanx_left_out ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4802 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4803 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4804 ) , + .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4805 ) , + .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4806 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4807 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4808 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4809 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4810 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4811 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4812 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4813 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4814 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4815 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4816 ) , + .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4817 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4818 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4819 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4820 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4821 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4822 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4823 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4824 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4825 } ) , + .chany_top_in ( cby_1__1__109_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__110_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__108_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__99_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__110_ccff_tail ) , + .chany_top_out ( sb_1__1__99_chany_top_out ) , + .chanx_right_out ( sb_1__1__99_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__99_chanx_left_out ) , + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4826 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4827 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4828 ) , + .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4829 ) , + .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4830 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4831 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4832 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4833 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4834 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4835 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4836 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4837 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4838 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4839 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4840 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4841 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4844 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4845 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4846 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4847 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4848 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4849 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4850 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4851 } ) , + .chany_top_in ( cby_1__1__110_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__111_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__109_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__100_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__111_ccff_tail ) , + .chany_top_out ( sb_1__1__100_chany_top_out ) , + .chanx_right_out ( sb_1__1__100_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__100_chanx_left_out ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4852 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4853 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4854 ) , + .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4855 ) , + .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4856 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4857 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4858 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4859 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4860 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4861 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4862 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4863 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4864 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4865 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4866 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4867 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4868 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4869 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4870 ) , + .clk_2_N_in ( clk_3_wires[87] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4871 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4872 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4873 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4874 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4875 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4876 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4878 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4879 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4880 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4881 } ) , + .chany_top_in ( cby_1__1__111_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__112_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__110_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__101_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__112_ccff_tail ) , + .chany_top_out ( sb_1__1__101_chany_top_out ) , + .chanx_right_out ( sb_1__1__101_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__101_chanx_left_out ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4882 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4883 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4884 ) , + .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4885 ) , + .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4886 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4887 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4888 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4889 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4890 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4891 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4892 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4893 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4894 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4895 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[83] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4896 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4897 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4898 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4899 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4900 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4902 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4903 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4904 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4905 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4906 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4907 ) , + .clk_3_N_in ( clk_3_wires[83] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4908 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4909 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4910 ) , + .clk_3_S_out ( clk_3_wires[86] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4911 } ) , + .chany_top_in ( cby_1__1__112_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__113_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__111_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__102_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__113_ccff_tail ) , + .chany_top_out ( sb_1__1__102_chany_top_out ) , + .chanx_right_out ( sb_1__1__102_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__102_chanx_left_out ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4912 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4913 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4914 ) , + .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4915 ) , + .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4916 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4917 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4918 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4919 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4920 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4921 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4922 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4923 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4924 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[119] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4925 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4926 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4927 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[77] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4928 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4929 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4930 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4931 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4932 ) , + .clk_2_N_in ( clk_3_wires[77] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4933 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4934 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4935 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4936 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4937 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4938 ) , + .clk_2_E_out ( clk_2_wires[119] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4939 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4940 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4941 ) , + .clk_3_N_in ( clk_3_wires[77] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4942 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4943 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4944 ) , + .clk_3_S_out ( clk_3_wires[82] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4945 } ) , + .chany_top_in ( cby_1__1__113_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__114_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__112_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__103_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__114_ccff_tail ) , + .chany_top_out ( sb_1__1__103_chany_top_out ) , + .chanx_right_out ( sb_1__1__103_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__103_chanx_left_out ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4946 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4947 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4948 ) , + .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4949 ) , + .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4950 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4951 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4952 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4953 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4954 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4955 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4956 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4957 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4958 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4959 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[73] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4960 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4961 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4962 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4963 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4964 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4965 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4966 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4967 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4968 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4969 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4970 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4971 ) , + .clk_3_N_in ( clk_3_wires[73] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4972 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4973 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4974 ) , + .clk_3_S_out ( clk_3_wires[76] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4975 } ) , + .chany_top_in ( cby_1__1__114_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__115_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__113_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__104_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__115_ccff_tail ) , + .chany_top_out ( sb_1__1__104_chany_top_out ) , + .chanx_right_out ( sb_1__1__104_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__104_chanx_left_out ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4976 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4977 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4978 ) , + .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4979 ) , + .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4980 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4981 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4982 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4983 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4984 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4985 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4986 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[49] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4987 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4988 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4989 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4990 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4991 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4992 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4993 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4995 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4996 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4997 ) , + .clk_3_W_in ( clk_3_wires[49] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4998 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4999 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5000 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5002 ) , + .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5003 } ) , + .chany_top_in ( cby_1__1__115_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__116_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__114_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__105_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__116_ccff_tail ) , + .chany_top_out ( sb_1__1__105_chany_top_out ) , + .chanx_right_out ( sb_1__1__105_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__105_chanx_left_out ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5004 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5005 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5006 ) , + .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5007 ) , + .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5008 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5009 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5010 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5011 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5012 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5013 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5014 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5015 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5016 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[71] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5017 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5018 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5019 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5020 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5021 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5023 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5024 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5025 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5026 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5027 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5028 ) , + .clk_3_S_in ( clk_3_wires[71] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5029 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5030 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5031 ) , + .clk_3_N_out ( clk_3_wires[74] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5032 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5033 } ) , + .chany_top_in ( cby_1__1__116_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__117_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__115_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__106_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__117_ccff_tail ) , + .chany_top_out ( sb_1__1__106_chany_top_out ) , + .chanx_right_out ( sb_1__1__106_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__106_chanx_left_out ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5034 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5035 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5036 ) , + .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5037 ) , + .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5038 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5039 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5040 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5041 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5042 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[75] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5043 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5044 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5045 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5046 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[126] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5047 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5048 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[75] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5049 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5050 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5051 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5052 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5053 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5054 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5055 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5056 ) , + .clk_2_S_in ( clk_3_wires[75] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5057 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5058 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5059 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5060 ) , + .clk_2_E_out ( clk_2_wires[126] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5061 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5062 ) , + .clk_3_S_in ( clk_3_wires[75] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5063 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5064 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5065 ) , + .clk_3_N_out ( clk_3_wires[80] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5066 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5067 } ) , + .chany_top_in ( cby_1__1__117_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__118_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__116_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__107_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__118_ccff_tail ) , + .chany_top_out ( sb_1__1__107_chany_top_out ) , + .chanx_right_out ( sb_1__1__107_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__107_chanx_left_out ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5068 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5069 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5070 ) , + .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5071 ) , + .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5072 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5073 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5074 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5075 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5076 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5077 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5078 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5079 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5080 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[81] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5081 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5082 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5083 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5084 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5085 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5087 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5088 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5089 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5090 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5091 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5092 ) , + .clk_3_S_in ( clk_3_wires[81] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5093 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5094 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5095 ) , + .clk_3_N_out ( clk_3_wires[84] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5096 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5097 } ) , + .chany_top_in ( cby_1__1__118_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__119_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__117_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__108_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__119_ccff_tail ) , + .chany_top_out ( sb_1__1__108_chany_top_out ) , + .chanx_right_out ( sb_1__1__108_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__108_chanx_left_out ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5098 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5099 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5100 ) , + .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5101 ) , + .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5102 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5103 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5104 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5105 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5106 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[85] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5107 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5108 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5109 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5110 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5111 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5112 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5113 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5114 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5115 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5116 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5117 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5118 ) , + .clk_2_S_in ( clk_3_wires[85] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5119 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5120 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5121 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5122 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5123 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5124 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5125 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5126 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5127 } ) , + .chany_top_in ( cby_1__1__119_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__120_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__118_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__109_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__120_ccff_tail ) , + .chany_top_out ( sb_1__1__109_chany_top_out ) , + .chanx_right_out ( sb_1__1__109_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__109_chanx_left_out ) , + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5128 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5129 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5130 ) , + .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5131 ) , + .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5132 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5133 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5134 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5135 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5136 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5137 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5138 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5139 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5140 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5141 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5142 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5143 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5146 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5147 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5148 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5149 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5150 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5151 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5152 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5153 } ) , + .chany_top_in ( cby_1__1__121_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__121_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__120_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__110_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__121_ccff_tail ) , + .chany_top_out ( sb_1__1__110_chany_top_out ) , + .chanx_right_out ( sb_1__1__110_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__110_chanx_left_out ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5154 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5155 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5156 ) , + .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5157 ) , + .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5158 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5159 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5160 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5161 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5162 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5163 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5164 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5165 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5166 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5167 ) , + .clk_1_N_in ( clk_2_wires[116] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5168 ) , + .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5169 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5170 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5172 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5173 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5174 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5175 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5176 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5177 } ) , + .chany_top_in ( cby_1__1__122_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__122_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__121_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__111_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__122_ccff_tail ) , + .chany_top_out ( sb_1__1__111_chany_top_out ) , + .chanx_right_out ( sb_1__1__111_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__111_chanx_left_out ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5178 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5179 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5180 ) , + .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5181 ) , + .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5182 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5183 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5184 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5185 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5186 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5187 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[113] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5188 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5189 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5190 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5191 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5192 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5193 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5194 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5195 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5196 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5197 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5198 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5199 ) , + .clk_2_W_in ( clk_2_wires[113] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5200 ) , + .clk_2_S_out ( clk_2_wires[115] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5201 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5202 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5203 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5204 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5205 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5206 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5207 } ) , + .chany_top_in ( cby_1__1__123_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__123_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__122_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__112_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__123_ccff_tail ) , + .chany_top_out ( sb_1__1__112_chany_top_out ) , + .chanx_right_out ( sb_1__1__112_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__112_chanx_left_out ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5208 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5209 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5210 ) , + .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5211 ) , + .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5212 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5213 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5214 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5215 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5216 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5217 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5218 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5219 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5220 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5221 ) , + .clk_1_N_in ( clk_2_wires[123] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5222 ) , + .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5223 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5224 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5225 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5227 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5228 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5229 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5230 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5231 } ) , + .chany_top_in ( cby_1__1__124_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__124_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__123_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__113_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__124_ccff_tail ) , + .chany_top_out ( sb_1__1__113_chany_top_out ) , + .chanx_right_out ( sb_1__1__113_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__113_chanx_left_out ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5232 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5233 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5234 ) , + .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5235 ) , + .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5236 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5237 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5238 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5239 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5240 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5241 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[118] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5242 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5243 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5245 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5246 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5247 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5248 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5249 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5250 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5251 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5252 ) , + .clk_2_W_in ( clk_2_wires[118] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5253 ) , + .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5254 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5255 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5256 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5257 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5258 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5259 } ) , + .chany_top_in ( cby_1__1__125_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__125_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__124_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__114_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__125_ccff_tail ) , + .chany_top_out ( sb_1__1__114_chany_top_out ) , + .chanx_right_out ( sb_1__1__114_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__114_chanx_left_out ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5260 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5261 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5262 ) , + .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5263 ) , + .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5264 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5265 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5266 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5267 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5268 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5269 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5270 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5271 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5272 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5273 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5274 ) , + .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5275 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5276 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5277 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5278 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5279 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5280 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5281 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5282 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5283 } ) , + .chany_top_in ( cby_1__1__126_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__126_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__125_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__115_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__126_ccff_tail ) , + .chany_top_out ( sb_1__1__115_chany_top_out ) , + .chanx_right_out ( sb_1__1__115_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__115_chanx_left_out ) , + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5284 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5285 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5286 ) , + .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5287 ) , + .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5288 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5289 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5290 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5291 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5292 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5293 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5294 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5295 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5296 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5297 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5298 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5299 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5301 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5302 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5303 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5305 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5306 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5307 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5308 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5309 } ) , + .chany_top_in ( cby_1__1__127_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__127_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__126_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__116_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__127_ccff_tail ) , + .chany_top_out ( sb_1__1__116_chany_top_out ) , + .chanx_right_out ( sb_1__1__116_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__116_chanx_left_out ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5310 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5311 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5312 ) , + .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5313 ) , + .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5314 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5315 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5316 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5317 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5318 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5319 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5320 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5321 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5322 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5323 ) , + .clk_1_N_in ( clk_2_wires[130] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5324 ) , + .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5325 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5326 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5327 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5328 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5329 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5330 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5331 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5332 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5333 } ) , + .chany_top_in ( cby_1__1__128_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__128_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__127_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__117_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__128_ccff_tail ) , + .chany_top_out ( sb_1__1__117_chany_top_out ) , + .chanx_right_out ( sb_1__1__117_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__117_chanx_left_out ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5334 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5335 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5336 ) , + .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5337 ) , + .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5338 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5339 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5340 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5341 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5342 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5343 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[125] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5344 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5345 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5346 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5347 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5348 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5349 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5350 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5351 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5352 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5353 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5354 ) , + .clk_2_W_in ( clk_2_wires[125] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5355 ) , + .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5356 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5357 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5358 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5359 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5360 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5361 } ) , + .chany_top_in ( cby_1__1__129_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__129_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__128_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__118_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__129_ccff_tail ) , + .chany_top_out ( sb_1__1__118_chany_top_out ) , + .chanx_right_out ( sb_1__1__118_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__118_chanx_left_out ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5362 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5363 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5364 ) , + .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5365 ) , + .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5366 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5367 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5368 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5369 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5370 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5371 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5372 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5373 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5374 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5375 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5376 ) , + .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5377 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5378 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5379 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5380 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5381 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5382 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5383 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5384 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5385 } ) , + .chany_top_in ( cby_1__1__130_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__130_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__129_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__119_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__130_ccff_tail ) , + .chany_top_out ( sb_1__1__119_chany_top_out ) , + .chanx_right_out ( sb_1__1__119_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__119_chanx_left_out ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5386 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5387 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5388 ) , + .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5389 ) , + .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5390 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5391 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5392 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5393 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5394 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5395 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[132] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5396 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5397 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5398 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5399 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5400 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5402 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5403 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5404 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5405 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5406 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5407 ) , + .clk_2_W_in ( clk_2_wires[132] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5408 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5409 ) , + .clk_2_N_out ( clk_2_wires[134] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5410 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5411 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5412 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5413 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5414 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__1_ sb_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5415 } ) , + .chany_top_in ( cby_1__1__131_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__131_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__130_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__120_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__131_ccff_tail ) , + .chany_top_out ( sb_1__1__120_chany_top_out ) , + .chanx_right_out ( sb_1__1__120_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__120_chanx_left_out ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5416 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5417 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5418 ) , + .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5419 ) , + .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5420 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5421 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5422 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5423 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5424 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5425 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5426 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5427 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5428 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5429 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5430 ) , + .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5431 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5432 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5433 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5434 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5435 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5436 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5437 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5438 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5439 } ) , + .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__11_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__0_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_1_ccff_tail ) , + .chanx_right_out ( sb_1__12__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__0_chanx_left_out ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5440 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5441 ) , + .pReset_E_in ( pResetWires[604] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5442 ) , + .pReset_W_out ( pResetWires[601] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5443 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[60] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5444 } ) , + .chanx_right_in ( cbx_1__12__2_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__23_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__1_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_2_ccff_tail ) , + .chanx_right_out ( sb_1__12__1_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__1_chanx_left_out ) , + .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_BOT ( scff_Wires[52] ) , + .SC_OUT_BOT ( scff_Wires[53] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5445 ) , + .pReset_E_in ( pResetWires[607] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5446 ) , + .pReset_W_out ( pResetWires[605] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5447 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[100] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5448 } ) , + .chanx_right_in ( cbx_1__12__3_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__35_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__2_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_3_ccff_tail ) , + .chanx_right_out ( sb_1__12__2_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__2_chanx_left_out ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5449 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5450 ) , + .pReset_E_in ( pResetWires[610] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5451 ) , + .pReset_W_out ( pResetWires[608] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5452 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[138] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5453 } ) , + .chanx_right_in ( cbx_1__12__4_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__47_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__3_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_4_ccff_tail ) , + .chanx_right_out ( sb_1__12__3_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__3_chanx_left_out ) , + .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_BOT ( scff_Wires[105] ) , + .SC_OUT_BOT ( scff_Wires[106] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5454 ) , + .pReset_E_in ( pResetWires[613] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5455 ) , + .pReset_W_out ( pResetWires[611] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5456 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[176] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5457 } ) , + .chanx_right_in ( cbx_1__12__5_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__59_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__4_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_5_ccff_tail ) , + .chanx_right_out ( sb_1__12__4_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__4_chanx_left_out ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5458 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5459 ) , + .pReset_E_in ( pResetWires[616] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5460 ) , + .pReset_W_out ( pResetWires[614] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5461 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[214] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5462 } ) , + .chanx_right_in ( cbx_1__12__6_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__71_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__5_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_6_ccff_tail ) , + .chanx_right_out ( sb_1__12__5_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__5_chanx_left_out ) , + .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_BOT ( scff_Wires[158] ) , + .SC_OUT_BOT ( scff_Wires[159] ) , .pReset_S_in ( pResetWires[24] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5463 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5464 ) , + .pReset_W_out ( pResetWires[617] ) , .pReset_E_out ( pResetWires[619] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[252] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5465 } ) , + .chanx_right_in ( cbx_1__12__7_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__83_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__6_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_7_ccff_tail ) , + .chanx_right_out ( sb_1__12__6_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__6_chanx_left_out ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5466 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5467 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5468 ) , + .pReset_W_in ( pResetWires[620] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5469 ) , + .pReset_E_out ( pResetWires[622] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[290] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5470 } ) , + .chanx_right_in ( cbx_1__12__8_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__95_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__7_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_8_ccff_tail ) , + .chanx_right_out ( sb_1__12__7_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__7_chanx_left_out ) , + .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_BOT ( scff_Wires[211] ) , + .SC_OUT_BOT ( scff_Wires[212] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5471 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5472 ) , + .pReset_W_in ( pResetWires[623] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5473 ) , + .pReset_E_out ( pResetWires[625] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[328] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5474 } ) , + .chanx_right_in ( cbx_1__12__9_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__107_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__8_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_9_ccff_tail ) , + .chanx_right_out ( sb_1__12__8_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__8_chanx_left_out ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5475 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5476 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5477 ) , + .pReset_W_in ( pResetWires[626] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5478 ) , + .pReset_E_out ( pResetWires[628] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[366] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5479 } ) , + .chanx_right_in ( cbx_1__12__10_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__119_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__9_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_10_ccff_tail ) , + .chanx_right_out ( sb_1__12__9_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__9_chanx_left_out ) , + .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_BOT ( scff_Wires[264] ) , + .SC_OUT_BOT ( scff_Wires[265] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5480 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5481 ) , + .pReset_W_in ( pResetWires[629] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5482 ) , + .pReset_E_out ( pResetWires[631] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[404] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_1__2_ sb_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5483 } ) , + .chanx_right_in ( cbx_1__12__11_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__131_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__10_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_11_ccff_tail ) , + .chanx_right_out ( sb_1__12__10_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__10_chanx_left_out ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5484 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5485 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5486 ) , + .pReset_W_in ( pResetWires[632] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5487 ) , + .pReset_E_out ( pResetWires[634] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[442] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__0_ sb_12__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5488 } ) , + .chany_top_in ( cby_12__1__0_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , + .chanx_left_in ( cbx_1__0__11_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_right_11_ccff_tail ) , + .chany_top_out ( sb_12__0__0_chany_top_out ) , + .chanx_left_out ( sb_12__0__0_chanx_left_out ) , + .ccff_tail ( sb_12__0__0_ccff_tail ) , .pReset_W_in ( pResetWires[59] ) , + .pReset_N_out ( pResetWires[60] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[445] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5489 } ) , + .chany_top_in ( cby_12__1__1_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__0_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__121_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_10_ccff_tail ) , + .chany_top_out ( sb_12__1__0_chany_top_out ) , + .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__0_chanx_left_out ) , + .ccff_tail ( sb_12__1__0_ccff_tail ) , .pReset_W_in ( pResetWires[107] ) , + .pReset_N_out ( pResetWires[109] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[448] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5490 } ) , + .chany_top_in ( cby_12__1__2_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__1_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__122_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_9_ccff_tail ) , + .chany_top_out ( sb_12__1__1_chany_top_out ) , + .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__1_chanx_left_out ) , + .ccff_tail ( sb_12__1__1_ccff_tail ) , .pReset_W_in ( pResetWires[156] ) , + .pReset_N_out ( pResetWires[158] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[451] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5491 } ) , + .chany_top_in ( cby_12__1__3_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__2_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__123_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_8_ccff_tail ) , + .chany_top_out ( sb_12__1__2_chany_top_out ) , + .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__2_chanx_left_out ) , + .ccff_tail ( sb_12__1__2_ccff_tail ) , .pReset_W_in ( pResetWires[205] ) , + .pReset_N_out ( pResetWires[207] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[454] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5492 } ) , + .chany_top_in ( cby_12__1__4_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__3_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__124_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_7_ccff_tail ) , + .chany_top_out ( sb_12__1__3_chany_top_out ) , + .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__3_chanx_left_out ) , + .ccff_tail ( sb_12__1__3_ccff_tail ) , .pReset_W_in ( pResetWires[254] ) , + .pReset_N_out ( pResetWires[256] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[457] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5493 } ) , + .chany_top_in ( cby_12__1__5_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__4_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__125_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_6_ccff_tail ) , + .chany_top_out ( sb_12__1__4_chany_top_out ) , + .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__4_chanx_left_out ) , + .ccff_tail ( sb_12__1__4_ccff_tail ) , .pReset_W_in ( pResetWires[303] ) , + .pReset_N_out ( pResetWires[305] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[460] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5494 } ) , + .chany_top_in ( cby_12__1__6_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__5_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__126_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_5_ccff_tail ) , + .chany_top_out ( sb_12__1__5_chany_top_out ) , + .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__5_chanx_left_out ) , + .ccff_tail ( sb_12__1__5_ccff_tail ) , .pReset_W_in ( pResetWires[352] ) , + .pReset_N_out ( pResetWires[354] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[463] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5495 } ) , + .chany_top_in ( cby_12__1__7_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__6_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__127_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_4_ccff_tail ) , + .chany_top_out ( sb_12__1__6_chany_top_out ) , + .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__6_chanx_left_out ) , + .ccff_tail ( sb_12__1__6_ccff_tail ) , .pReset_W_in ( pResetWires[401] ) , + .pReset_N_out ( pResetWires[403] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[466] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5496 } ) , + .chany_top_in ( cby_12__1__8_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__7_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__128_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_3_ccff_tail ) , + .chany_top_out ( sb_12__1__7_chany_top_out ) , + .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__7_chanx_left_out ) , + .ccff_tail ( sb_12__1__7_ccff_tail ) , .pReset_W_in ( pResetWires[450] ) , + .pReset_N_out ( pResetWires[452] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[469] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5497 } ) , + .chany_top_in ( cby_12__1__9_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__8_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__129_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_2_ccff_tail ) , + .chany_top_out ( sb_12__1__8_chany_top_out ) , + .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__8_chanx_left_out ) , + .ccff_tail ( sb_12__1__8_ccff_tail ) , .pReset_W_in ( pResetWires[499] ) , + .pReset_N_out ( pResetWires[501] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[472] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5498 } ) , + .chany_top_in ( cby_12__1__10_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__9_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__130_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_1_ccff_tail ) , + .chany_top_out ( sb_12__1__9_chany_top_out ) , + .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__9_chanx_left_out ) , + .ccff_tail ( sb_12__1__9_ccff_tail ) , .pReset_W_in ( pResetWires[548] ) , + .pReset_N_out ( pResetWires[550] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[475] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__1_ sb_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5499 } ) , + .chany_top_in ( cby_12__1__11_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__10_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__131_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_0_ccff_tail ) , + .chany_top_out ( sb_12__1__10_chany_top_out ) , + .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__10_chanx_left_out ) , + .ccff_tail ( sb_12__1__10_ccff_tail ) , + .pReset_W_in ( pResetWires[597] ) , .pReset_N_out ( pResetWires[599] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[478] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sb_2__2_ sb_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5500 } ) , + .chany_bottom_in ( cby_12__1__11_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__11_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( ccff_head ) , + .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) , + .chanx_left_out ( sb_12__12__0_chanx_left_out ) , + .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) , + .SC_OUT_BOT ( sc_tail ) , .pReset_W_in ( pResetWires[635] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[480] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0_ cbx_1__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5501 } ) , + .chanx_left_in ( sb_0__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__0_chanx_left_out ) , + .ccff_head ( sb_1__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123:131] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123:131] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123:131] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5502 ) , + .pReset_E_in ( pResetWires[26] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5503 ) , + .pReset_W_out ( pResetWires[25] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5504 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[0] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[5] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__0_ cbx_2__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5505 } ) , + .chanx_left_in ( sb_1__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__1_chanx_left_out ) , + .ccff_head ( sb_1__0__1_ccff_tail ) , + .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114:122] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114:122] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114:122] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5506 ) , + .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , + .pReset_E_in ( pResetWires[29] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5507 ) , + .pReset_W_out ( pResetWires[28] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5508 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[63] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5509 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_3__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5510 } ) , + .chanx_left_in ( sb_1__0__1_chanx_right_out ) , + .chanx_right_in ( sb_1__0__2_chanx_left_out ) , + .ccff_head ( sb_1__0__2_ccff_tail ) , + .chanx_left_out ( cbx_1__0__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__2_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105:113] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105:113] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105:113] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5511 ) , + .pReset_E_in ( pResetWires[32] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5512 ) , + .pReset_W_out ( pResetWires[31] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5513 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[101] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5514 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_4__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5515 } ) , + .chanx_left_in ( sb_1__0__2_chanx_right_out ) , + .chanx_right_in ( sb_1__0__3_chanx_left_out ) , + .ccff_head ( sb_1__0__3_ccff_tail ) , + .chanx_left_out ( cbx_1__0__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__3_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:104] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:104] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:104] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5516 ) , + .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , + .pReset_E_in ( pResetWires[35] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5517 ) , + .pReset_W_out ( pResetWires[34] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5518 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[139] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5519 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_5__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5520 } ) , + .chanx_left_in ( sb_1__0__3_chanx_right_out ) , + .chanx_right_in ( sb_1__0__4_chanx_left_out ) , + .ccff_head ( sb_1__0__4_ccff_tail ) , + .chanx_left_out ( cbx_1__0__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__4_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87:95] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87:95] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87:95] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5521 ) , + .pReset_E_in ( pResetWires[38] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5522 ) , + .pReset_W_out ( pResetWires[37] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[177] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5524 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_6__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5525 } ) , + .chanx_left_in ( sb_1__0__4_chanx_right_out ) , + .chanx_right_in ( sb_1__0__5_chanx_left_out ) , + .ccff_head ( sb_1__0__5_ccff_tail ) , + .chanx_left_out ( cbx_1__0__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__5_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78:86] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78:86] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78:86] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5526 ) , + .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , + .pReset_E_in ( pResetWires[41] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5527 ) , + .pReset_W_out ( pResetWires[40] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5528 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[215] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5529 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_7__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5530 } ) , + .chanx_left_in ( sb_1__0__5_chanx_right_out ) , + .chanx_right_in ( sb_1__0__6_chanx_left_out ) , + .ccff_head ( sb_1__0__6_ccff_tail ) , + .chanx_left_out ( cbx_1__0__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__6_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69:77] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69:77] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69:77] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5531 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5532 ) , + .pReset_W_in ( pResetWires[43] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5533 ) , + .pReset_E_out ( pResetWires[44] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[253] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5534 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_8__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5535 } ) , + .chanx_left_in ( sb_1__0__6_chanx_right_out ) , + .chanx_right_in ( sb_1__0__7_chanx_left_out ) , + .ccff_head ( sb_1__0__7_ccff_tail ) , + .chanx_left_out ( cbx_1__0__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__7_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:68] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:68] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:68] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5536 ) , + .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5537 ) , + .pReset_W_in ( pResetWires[46] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5538 ) , + .pReset_E_out ( pResetWires[47] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[291] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5539 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_9__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5540 } ) , + .chanx_left_in ( sb_1__0__7_chanx_right_out ) , + .chanx_right_in ( sb_1__0__8_chanx_left_out ) , + .ccff_head ( sb_1__0__8_ccff_tail ) , + .chanx_left_out ( cbx_1__0__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__8_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51:59] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51:59] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51:59] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5541 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5542 ) , + .pReset_W_in ( pResetWires[49] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5543 ) , + .pReset_E_out ( pResetWires[50] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[329] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5544 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_10__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5545 } ) , + .chanx_left_in ( sb_1__0__8_chanx_right_out ) , + .chanx_right_in ( sb_1__0__9_chanx_left_out ) , + .ccff_head ( sb_1__0__9_ccff_tail ) , + .chanx_left_out ( cbx_1__0__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__9_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42:50] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42:50] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42:50] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5546 ) , + .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5547 ) , + .pReset_W_in ( pResetWires[52] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5548 ) , + .pReset_E_out ( pResetWires[53] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[367] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5549 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_11__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5550 } ) , + .chanx_left_in ( sb_1__0__9_chanx_right_out ) , + .chanx_right_in ( sb_1__0__10_chanx_left_out ) , + .ccff_head ( sb_1__0__10_ccff_tail ) , + .chanx_left_out ( cbx_1__0__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__10_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33:41] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33:41] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33:41] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5551 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5552 ) , + .pReset_W_in ( pResetWires[55] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5553 ) , + .pReset_E_out ( pResetWires[56] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[405] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5554 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0_ cbx_12__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5555 } ) , + .chanx_left_in ( sb_1__0__10_chanx_right_out ) , + .chanx_right_in ( sb_12__0__0_chanx_left_out ) , + .ccff_head ( sb_12__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__11_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:32] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:32] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:32] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5556 ) , + .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5557 ) , + .pReset_W_in ( pResetWires[58] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5558 ) , + .pReset_E_out ( pResetWires[59] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[443] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5559 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5560 } ) , + .chanx_left_in ( sb_0__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__0_chanx_left_out ) , + .ccff_head ( sb_1__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5561 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[0] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[0] ) , + .pReset_E_in ( pResetWires[62] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5562 ) , + .pReset_W_out ( pResetWires[61] ) , .pReset_S_out ( pResetWires[63] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5563 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[6] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[4] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5564 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5565 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5566 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5567 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5568 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5569 ) , + .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5570 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5571 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5572 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5573 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5574 } ) , + .chanx_left_in ( sb_0__1__1_chanx_right_out ) , + .chanx_right_in ( sb_1__1__1_chanx_left_out ) , + .ccff_head ( sb_1__1__1_ccff_tail ) , + .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5575 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[1] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[1] ) , + .pReset_E_in ( pResetWires[111] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5576 ) , + .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5577 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5578 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5579 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5580 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5581 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5582 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5583 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5584 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5589 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5590 } ) , + .chanx_left_in ( sb_0__1__2_chanx_right_out ) , + .chanx_right_in ( sb_1__1__2_chanx_left_out ) , + .ccff_head ( sb_1__1__2_ccff_tail ) , + .chanx_left_out ( cbx_1__1__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__2_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5591 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[2] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[2] ) , + .pReset_E_in ( pResetWires[160] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5592 ) , + .pReset_W_out ( pResetWires[159] ) , .pReset_S_out ( pResetWires[161] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5593 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[16] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[15] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5594 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5595 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5596 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5597 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5598 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5599 ) , + .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5603 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5604 } ) , + .chanx_left_in ( sb_0__1__3_chanx_right_out ) , + .chanx_right_in ( sb_1__1__3_chanx_left_out ) , + .ccff_head ( sb_1__1__3_ccff_tail ) , + .chanx_left_out ( cbx_1__1__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__3_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5605 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[3] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[3] ) , + .pReset_E_in ( pResetWires[209] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5606 ) , + .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5607 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5608 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5609 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5610 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5611 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5612 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5613 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5614 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5618 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5619 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5620 } ) , + .chanx_left_in ( sb_0__1__4_chanx_right_out ) , + .chanx_right_in ( sb_1__1__4_chanx_left_out ) , + .ccff_head ( sb_1__1__4_ccff_tail ) , + .chanx_left_out ( cbx_1__1__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__4_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5621 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[4] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[4] ) , + .pReset_E_in ( pResetWires[258] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5622 ) , + .pReset_W_out ( pResetWires[257] ) , .pReset_S_out ( pResetWires[259] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5623 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[26] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[25] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5624 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5625 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5626 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5627 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5628 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5629 ) , + .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5631 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5632 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5633 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5634 } ) , + .chanx_left_in ( sb_0__1__5_chanx_right_out ) , + .chanx_right_in ( sb_1__1__5_chanx_left_out ) , + .ccff_head ( sb_1__1__5_ccff_tail ) , + .chanx_left_out ( cbx_1__1__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__5_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5635 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[5] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[5] ) , + .pReset_E_in ( pResetWires[307] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5636 ) , + .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5637 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5638 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5639 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5640 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5641 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5642 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5643 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5644 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5649 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5650 } ) , + .chanx_left_in ( sb_0__1__6_chanx_right_out ) , + .chanx_right_in ( sb_1__1__6_chanx_left_out ) , + .ccff_head ( sb_1__1__6_ccff_tail ) , + .chanx_left_out ( cbx_1__1__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__6_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5651 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[6] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[6] ) , + .pReset_E_in ( pResetWires[356] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5652 ) , + .pReset_W_out ( pResetWires[355] ) , .pReset_S_out ( pResetWires[357] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5653 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[36] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[35] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5654 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5655 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5656 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5657 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5658 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5659 ) , + .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5660 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5661 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5663 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5664 } ) , + .chanx_left_in ( sb_0__1__7_chanx_right_out ) , + .chanx_right_in ( sb_1__1__7_chanx_left_out ) , + .ccff_head ( sb_1__1__7_ccff_tail ) , + .chanx_left_out ( cbx_1__1__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__7_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5665 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[7] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[7] ) , + .pReset_E_in ( pResetWires[405] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5666 ) , + .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5667 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5668 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5669 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5670 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5671 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5672 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5673 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5674 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5678 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5679 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5680 } ) , + .chanx_left_in ( sb_0__1__8_chanx_right_out ) , + .chanx_right_in ( sb_1__1__8_chanx_left_out ) , + .ccff_head ( sb_1__1__8_ccff_tail ) , + .chanx_left_out ( cbx_1__1__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__8_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5681 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[8] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[8] ) , + .pReset_E_in ( pResetWires[454] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5682 ) , + .pReset_W_out ( pResetWires[453] ) , .pReset_S_out ( pResetWires[455] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5683 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[46] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[45] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5684 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5686 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5687 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5688 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5689 ) , + .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5693 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5694 } ) , + .chanx_left_in ( sb_0__1__9_chanx_right_out ) , + .chanx_right_in ( sb_1__1__9_chanx_left_out ) , + .ccff_head ( sb_1__1__9_ccff_tail ) , + .chanx_left_out ( cbx_1__1__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__9_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5695 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[9] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[9] ) , + .pReset_E_in ( pResetWires[503] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5696 ) , + .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5697 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5698 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5699 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5700 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5701 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5702 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5703 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5704 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5708 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5709 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5710 } ) , + .chanx_left_in ( sb_0__1__10_chanx_right_out ) , + .chanx_right_in ( sb_1__1__10_chanx_left_out ) , + .ccff_head ( sb_1__1__10_ccff_tail ) , + .chanx_left_out ( cbx_1__1__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__10_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5711 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[10] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[10] ) , + .pReset_E_in ( pResetWires[552] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5712 ) , + .pReset_W_out ( pResetWires[551] ) , .pReset_S_out ( pResetWires[553] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5713 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[56] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[55] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5714 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5715 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5716 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5717 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5718 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5719 ) , + .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5720 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5721 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5723 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5724 } ) , + .chanx_left_in ( sb_1__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__11_chanx_left_out ) , + .ccff_head ( sb_1__1__11_ccff_tail ) , + .chanx_left_out ( cbx_1__1__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__11_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5725 ) , + .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[11] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[11] ) , + .pReset_E_in ( pResetWires[67] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5726 ) , + .pReset_W_out ( pResetWires[66] ) , .pReset_S_out ( pResetWires[68] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5727 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[66] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5728 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5729 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5730 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5731 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5733 ) , + .clk_1_W_in ( clk_1_wires[1] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5734 ) , + .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5736 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5737 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5738 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5739 } ) , + .chanx_left_in ( sb_1__1__1_chanx_right_out ) , + .chanx_right_in ( sb_1__1__12_chanx_left_out ) , + .ccff_head ( sb_1__1__12_ccff_tail ) , + .chanx_left_out ( cbx_1__1__12_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__12_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5740 ) , + .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[12] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[12] ) , + .pReset_E_in ( pResetWires[116] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5741 ) , + .pReset_W_out ( pResetWires[115] ) , .pReset_S_out ( pResetWires[117] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5742 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5743 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5744 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5745 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5746 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5747 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5748 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5749 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5750 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5751 ) , + .clk_2_E_in ( clk_2_wires[2] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5752 ) , + .clk_2_W_out ( clk_2_wires[1] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5754 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5755 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5756 } ) , + .chanx_left_in ( sb_1__1__2_chanx_right_out ) , + .chanx_right_in ( sb_1__1__13_chanx_left_out ) , + .ccff_head ( sb_1__1__13_ccff_tail ) , + .chanx_left_out ( cbx_1__1__13_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__13_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5757 ) , + .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[13] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[13] ) , + .pReset_E_in ( pResetWires[165] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5758 ) , + .pReset_W_out ( pResetWires[164] ) , .pReset_S_out ( pResetWires[166] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[72] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5760 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5761 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5762 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5763 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5764 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5765 ) , + .clk_1_W_in ( clk_1_wires[8] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5766 ) , + .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5767 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5768 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5769 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5770 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5771 } ) , + .chanx_left_in ( sb_1__1__3_chanx_right_out ) , + .chanx_right_in ( sb_1__1__14_chanx_left_out ) , + .ccff_head ( sb_1__1__14_ccff_tail ) , + .chanx_left_out ( cbx_1__1__14_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__14_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5772 ) , + .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[14] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[14] ) , + .pReset_E_in ( pResetWires[214] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5773 ) , + .pReset_W_out ( pResetWires[213] ) , .pReset_S_out ( pResetWires[215] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5774 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5775 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5776 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5777 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5778 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5779 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5780 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5781 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5782 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5783 ) , + .clk_2_E_in ( clk_2_wires[7] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5784 ) , + .clk_2_W_out ( clk_2_wires[6] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5785 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5786 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5787 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5788 } ) , + .chanx_left_in ( sb_1__1__4_chanx_right_out ) , + .chanx_right_in ( sb_1__1__15_chanx_left_out ) , + .ccff_head ( sb_1__1__15_ccff_tail ) , + .chanx_left_out ( cbx_1__1__15_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__15_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5789 ) , + .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[15] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[15] ) , + .pReset_E_in ( pResetWires[263] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5790 ) , + .pReset_W_out ( pResetWires[262] ) , .pReset_S_out ( pResetWires[264] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5791 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[78] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5792 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5793 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5795 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5796 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5797 ) , + .clk_1_W_in ( clk_1_wires[15] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5798 ) , + .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5800 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5801 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5802 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5803 } ) , + .chanx_left_in ( sb_1__1__5_chanx_right_out ) , + .chanx_right_in ( sb_1__1__16_chanx_left_out ) , + .ccff_head ( sb_1__1__16_ccff_tail ) , + .chanx_left_out ( cbx_1__1__16_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__16_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5804 ) , + .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[16] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[16] ) , + .pReset_E_in ( pResetWires[312] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5805 ) , + .pReset_W_out ( pResetWires[311] ) , .pReset_S_out ( pResetWires[313] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5806 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5807 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5808 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5809 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5810 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5811 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5812 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5813 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5814 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5819 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5820 } ) , + .chanx_left_in ( sb_1__1__6_chanx_right_out ) , + .chanx_right_in ( sb_1__1__17_chanx_left_out ) , + .ccff_head ( sb_1__1__17_ccff_tail ) , + .chanx_left_out ( cbx_1__1__17_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__17_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5821 ) , + .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[17] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[17] ) , + .pReset_E_in ( pResetWires[361] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5822 ) , + .pReset_W_out ( pResetWires[360] ) , .pReset_S_out ( pResetWires[362] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5823 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[84] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5824 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5825 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5826 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5827 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5828 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5829 ) , + .clk_1_W_in ( clk_1_wires[22] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5830 ) , + .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5832 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5833 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5834 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5835 } ) , + .chanx_left_in ( sb_1__1__7_chanx_right_out ) , + .chanx_right_in ( sb_1__1__18_chanx_left_out ) , + .ccff_head ( sb_1__1__18_ccff_tail ) , + .chanx_left_out ( cbx_1__1__18_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__18_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5836 ) , + .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[18] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[18] ) , + .pReset_E_in ( pResetWires[410] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5837 ) , + .pReset_W_out ( pResetWires[409] ) , .pReset_S_out ( pResetWires[411] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5838 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5839 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5840 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5841 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5842 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5843 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5844 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5845 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5846 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5847 ) , + .clk_2_E_in ( clk_2_wires[14] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5848 ) , + .clk_2_W_out ( clk_2_wires[13] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5849 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5850 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5851 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5852 } ) , + .chanx_left_in ( sb_1__1__8_chanx_right_out ) , + .chanx_right_in ( sb_1__1__19_chanx_left_out ) , + .ccff_head ( sb_1__1__19_ccff_tail ) , + .chanx_left_out ( cbx_1__1__19_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__19_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5853 ) , + .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[19] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[19] ) , + .pReset_E_in ( pResetWires[459] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5854 ) , + .pReset_W_out ( pResetWires[458] ) , .pReset_S_out ( pResetWires[460] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5855 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[90] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5856 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5857 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5858 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5859 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5860 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5861 ) , + .clk_1_W_in ( clk_1_wires[29] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5862 ) , + .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5864 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5865 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5866 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5867 } ) , + .chanx_left_in ( sb_1__1__9_chanx_right_out ) , + .chanx_right_in ( sb_1__1__20_chanx_left_out ) , + .ccff_head ( sb_1__1__20_ccff_tail ) , + .chanx_left_out ( cbx_1__1__20_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__20_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5868 ) , + .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[20] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[20] ) , + .pReset_E_in ( pResetWires[508] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5869 ) , + .pReset_W_out ( pResetWires[507] ) , .pReset_S_out ( pResetWires[509] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5870 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5871 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5872 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5873 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5874 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5875 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5876 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5877 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5878 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5879 ) , + .clk_2_E_in ( clk_2_wires[21] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5880 ) , + .clk_2_W_out ( clk_2_wires[20] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5881 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5882 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5883 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5884 } ) , + .chanx_left_in ( sb_1__1__10_chanx_right_out ) , + .chanx_right_in ( sb_1__1__21_chanx_left_out ) , + .ccff_head ( sb_1__1__21_ccff_tail ) , + .chanx_left_out ( cbx_1__1__21_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__21_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5885 ) , + .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[21] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[21] ) , + .pReset_E_in ( pResetWires[557] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5886 ) , + .pReset_W_out ( pResetWires[556] ) , .pReset_S_out ( pResetWires[558] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5887 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[96] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5888 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5889 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5890 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5891 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5892 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5893 ) , + .clk_1_W_in ( clk_1_wires[36] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5894 ) , + .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5896 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5897 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5898 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5899 } ) , + .chanx_left_in ( sb_1__1__11_chanx_right_out ) , + .chanx_right_in ( sb_1__1__22_chanx_left_out ) , + .ccff_head ( sb_1__1__22_ccff_tail ) , + .chanx_left_out ( cbx_1__1__22_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__22_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5900 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[22] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[22] ) , + .pReset_E_in ( pResetWires[71] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5901 ) , + .pReset_W_out ( pResetWires[70] ) , .pReset_S_out ( pResetWires[72] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5902 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[104] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5903 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5904 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5905 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5906 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5907 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5908 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5909 ) , + .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5913 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5914 } ) , + .chanx_left_in ( sb_1__1__12_chanx_right_out ) , + .chanx_right_in ( sb_1__1__23_chanx_left_out ) , + .ccff_head ( sb_1__1__23_ccff_tail ) , + .chanx_left_out ( cbx_1__1__23_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__23_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5915 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[23] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[23] ) , + .pReset_E_in ( pResetWires[120] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5916 ) , + .pReset_W_out ( pResetWires[119] ) , .pReset_S_out ( pResetWires[121] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5917 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5918 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5919 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5920 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5921 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5922 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5923 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5924 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5925 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5927 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5929 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5930 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5931 } ) , + .chanx_left_in ( sb_1__1__13_chanx_right_out ) , + .chanx_right_in ( sb_1__1__24_chanx_left_out ) , + .ccff_head ( sb_1__1__24_ccff_tail ) , + .chanx_left_out ( cbx_1__1__24_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__24_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5932 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[24] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[24] ) , + .pReset_E_in ( pResetWires[169] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5933 ) , + .pReset_W_out ( pResetWires[168] ) , .pReset_S_out ( pResetWires[170] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5934 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[110] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5935 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5936 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5937 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5938 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5939 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5940 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5941 ) , + .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5943 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5945 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5946 } ) , + .chanx_left_in ( sb_1__1__14_chanx_right_out ) , + .chanx_right_in ( sb_1__1__25_chanx_left_out ) , + .ccff_head ( sb_1__1__25_ccff_tail ) , + .chanx_left_out ( cbx_1__1__25_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__25_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5947 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[25] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[25] ) , + .pReset_E_in ( pResetWires[218] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5948 ) , + .pReset_W_out ( pResetWires[217] ) , .pReset_S_out ( pResetWires[219] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5949 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5950 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5951 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5952 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5953 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5954 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5955 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5956 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5957 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5959 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5962 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5963 } ) , + .chanx_left_in ( sb_1__1__15_chanx_right_out ) , + .chanx_right_in ( sb_1__1__26_chanx_left_out ) , + .ccff_head ( sb_1__1__26_ccff_tail ) , + .chanx_left_out ( cbx_1__1__26_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__26_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5964 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[26] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[26] ) , + .pReset_E_in ( pResetWires[267] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5965 ) , + .pReset_W_out ( pResetWires[266] ) , .pReset_S_out ( pResetWires[268] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5966 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[116] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5967 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5968 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5969 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5970 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5971 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5972 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5973 ) , + .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5974 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5975 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5976 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5977 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5978 } ) , + .chanx_left_in ( sb_1__1__16_chanx_right_out ) , + .chanx_right_in ( sb_1__1__27_chanx_left_out ) , + .ccff_head ( sb_1__1__27_ccff_tail ) , + .chanx_left_out ( cbx_1__1__27_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__27_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5979 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[27] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[27] ) , + .pReset_E_in ( pResetWires[316] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5980 ) , + .pReset_W_out ( pResetWires[315] ) , .pReset_S_out ( pResetWires[317] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5981 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5982 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5983 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5984 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5985 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5986 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5987 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5988 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5989 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5990 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5991 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5992 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5993 ) , + .clk_3_E_in ( clk_3_wires[50] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5994 ) , + .clk_3_W_out ( clk_3_wires[51] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5995 } ) , + .chanx_left_in ( sb_1__1__17_chanx_right_out ) , + .chanx_right_in ( sb_1__1__28_chanx_left_out ) , + .ccff_head ( sb_1__1__28_ccff_tail ) , + .chanx_left_out ( cbx_1__1__28_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__28_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5996 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[28] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[28] ) , + .pReset_E_in ( pResetWires[365] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5997 ) , + .pReset_W_out ( pResetWires[364] ) , .pReset_S_out ( pResetWires[366] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5998 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[122] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5999 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6000 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6001 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6002 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6003 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6004 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6005 ) , + .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6006 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6007 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6009 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6010 } ) , + .chanx_left_in ( sb_1__1__18_chanx_right_out ) , + .chanx_right_in ( sb_1__1__29_chanx_left_out ) , + .ccff_head ( sb_1__1__29_ccff_tail ) , + .chanx_left_out ( cbx_1__1__29_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__29_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6011 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[29] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[29] ) , + .pReset_E_in ( pResetWires[414] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6012 ) , + .pReset_W_out ( pResetWires[413] ) , .pReset_S_out ( pResetWires[415] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6013 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6014 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6015 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6016 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6017 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6018 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6019 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6020 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6021 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6023 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6025 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6026 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6027 } ) , + .chanx_left_in ( sb_1__1__19_chanx_right_out ) , + .chanx_right_in ( sb_1__1__30_chanx_left_out ) , + .ccff_head ( sb_1__1__30_ccff_tail ) , + .chanx_left_out ( cbx_1__1__30_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__30_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6028 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[30] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[30] ) , + .pReset_E_in ( pResetWires[463] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6029 ) , + .pReset_W_out ( pResetWires[462] ) , .pReset_S_out ( pResetWires[464] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6030 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[128] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6031 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6032 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6033 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6034 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6035 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6036 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6037 ) , + .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6039 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6040 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6041 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6042 } ) , + .chanx_left_in ( sb_1__1__20_chanx_right_out ) , + .chanx_right_in ( sb_1__1__31_chanx_left_out ) , + .ccff_head ( sb_1__1__31_ccff_tail ) , + .chanx_left_out ( cbx_1__1__31_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__31_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6043 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[31] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[31] ) , + .pReset_E_in ( pResetWires[512] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6044 ) , + .pReset_W_out ( pResetWires[511] ) , .pReset_S_out ( pResetWires[513] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6045 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6046 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6047 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6048 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6049 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6050 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6051 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6052 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6053 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6055 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6057 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6058 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6059 } ) , + .chanx_left_in ( sb_1__1__21_chanx_right_out ) , + .chanx_right_in ( sb_1__1__32_chanx_left_out ) , + .ccff_head ( sb_1__1__32_ccff_tail ) , + .chanx_left_out ( cbx_1__1__32_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__32_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6060 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[32] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[32] ) , + .pReset_E_in ( pResetWires[561] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6061 ) , + .pReset_W_out ( pResetWires[560] ) , .pReset_S_out ( pResetWires[562] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6062 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[134] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6063 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6064 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6065 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6066 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6067 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6068 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6069 ) , + .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6070 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6071 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6072 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6073 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6074 } ) , + .chanx_left_in ( sb_1__1__22_chanx_right_out ) , + .chanx_right_in ( sb_1__1__33_chanx_left_out ) , + .ccff_head ( sb_1__1__33_ccff_tail ) , + .chanx_left_out ( cbx_1__1__33_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__33_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6075 ) , + .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[33] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[33] ) , + .pReset_E_in ( pResetWires[75] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6076 ) , + .pReset_W_out ( pResetWires[74] ) , .pReset_S_out ( pResetWires[76] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6077 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[142] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6078 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6079 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6080 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6081 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6082 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6083 ) , + .clk_1_W_in ( clk_1_wires[43] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6084 ) , + .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6085 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6086 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6087 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6088 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6089 } ) , + .chanx_left_in ( sb_1__1__23_chanx_right_out ) , + .chanx_right_in ( sb_1__1__34_chanx_left_out ) , + .ccff_head ( sb_1__1__34_ccff_tail ) , + .chanx_left_out ( cbx_1__1__34_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__34_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6090 ) , + .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[34] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[34] ) , + .pReset_E_in ( pResetWires[124] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6091 ) , + .pReset_W_out ( pResetWires[123] ) , .pReset_S_out ( pResetWires[125] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6092 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6093 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6094 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6095 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6096 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6097 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6098 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6099 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6100 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6101 ) , + .clk_2_E_in ( clk_2_wires[27] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6102 ) , + .clk_2_W_out ( clk_2_wires[28] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6103 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6104 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6105 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6106 } ) , + .chanx_left_in ( sb_1__1__24_chanx_right_out ) , + .chanx_right_in ( sb_1__1__35_chanx_left_out ) , + .ccff_head ( sb_1__1__35_ccff_tail ) , + .chanx_left_out ( cbx_1__1__35_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__35_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6107 ) , + .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[35] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[35] ) , + .pReset_E_in ( pResetWires[173] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6108 ) , + .pReset_W_out ( pResetWires[172] ) , .pReset_S_out ( pResetWires[174] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6109 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[148] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6110 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6111 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6112 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6113 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6114 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6115 ) , + .clk_1_W_in ( clk_1_wires[50] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6116 ) , + .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6117 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6118 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6119 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6120 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6121 } ) , + .chanx_left_in ( sb_1__1__25_chanx_right_out ) , + .chanx_right_in ( sb_1__1__36_chanx_left_out ) , + .ccff_head ( sb_1__1__36_ccff_tail ) , + .chanx_left_out ( cbx_1__1__36_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__36_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6122 ) , + .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[36] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[36] ) , + .pReset_E_in ( pResetWires[222] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6123 ) , + .pReset_W_out ( pResetWires[221] ) , .pReset_S_out ( pResetWires[223] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6124 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6125 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6126 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6127 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6128 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6129 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6130 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6131 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6132 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6133 ) , + .clk_2_E_in ( clk_2_wires[36] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6134 ) , + .clk_2_W_out ( clk_2_wires[37] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6135 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6136 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6137 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6138 } ) , + .chanx_left_in ( sb_1__1__26_chanx_right_out ) , + .chanx_right_in ( sb_1__1__37_chanx_left_out ) , + .ccff_head ( sb_1__1__37_ccff_tail ) , + .chanx_left_out ( cbx_1__1__37_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__37_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6139 ) , + .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[37] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[37] ) , + .pReset_E_in ( pResetWires[271] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6140 ) , + .pReset_W_out ( pResetWires[270] ) , .pReset_S_out ( pResetWires[272] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6141 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[154] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6142 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6143 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6144 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6145 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6146 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6147 ) , + .clk_1_W_in ( clk_1_wires[57] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6148 ) , + .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6149 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6150 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6151 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6152 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6153 } ) , + .chanx_left_in ( sb_1__1__27_chanx_right_out ) , + .chanx_right_in ( sb_1__1__38_chanx_left_out ) , + .ccff_head ( sb_1__1__38_ccff_tail ) , + .chanx_left_out ( cbx_1__1__38_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__38_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6154 ) , + .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[38] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[38] ) , + .pReset_E_in ( pResetWires[320] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6155 ) , + .pReset_W_out ( pResetWires[319] ) , .pReset_S_out ( pResetWires[321] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6156 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6157 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6158 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6159 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6160 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6161 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6162 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6163 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6164 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6165 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6167 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6168 ) , + .clk_3_E_in ( clk_3_wires[46] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , + .clk_3_W_out ( clk_3_wires[47] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6170 } ) , + .chanx_left_in ( sb_1__1__28_chanx_right_out ) , + .chanx_right_in ( sb_1__1__39_chanx_left_out ) , + .ccff_head ( sb_1__1__39_ccff_tail ) , + .chanx_left_out ( cbx_1__1__39_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__39_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6171 ) , + .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[39] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[39] ) , + .pReset_E_in ( pResetWires[369] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6172 ) , + .pReset_W_out ( pResetWires[368] ) , .pReset_S_out ( pResetWires[370] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6173 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[160] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6174 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6175 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6176 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6177 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6178 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6179 ) , + .clk_1_W_in ( clk_1_wires[64] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6180 ) , + .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6181 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6182 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6183 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6184 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6185 } ) , + .chanx_left_in ( sb_1__1__29_chanx_right_out ) , + .chanx_right_in ( sb_1__1__40_chanx_left_out ) , + .ccff_head ( sb_1__1__40_ccff_tail ) , + .chanx_left_out ( cbx_1__1__40_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__40_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6186 ) , + .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[40] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[40] ) , + .pReset_E_in ( pResetWires[418] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6187 ) , + .pReset_W_out ( pResetWires[417] ) , .pReset_S_out ( pResetWires[419] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6188 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6189 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6190 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6191 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6192 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6193 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6194 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6195 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6196 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6197 ) , + .clk_2_E_in ( clk_2_wires[49] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6198 ) , + .clk_2_W_out ( clk_2_wires[50] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6199 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6200 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6201 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6202 } ) , + .chanx_left_in ( sb_1__1__30_chanx_right_out ) , + .chanx_right_in ( sb_1__1__41_chanx_left_out ) , + .ccff_head ( sb_1__1__41_ccff_tail ) , + .chanx_left_out ( cbx_1__1__41_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__41_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6203 ) , + .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[41] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[41] ) , + .pReset_E_in ( pResetWires[467] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6204 ) , + .pReset_W_out ( pResetWires[466] ) , .pReset_S_out ( pResetWires[468] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6205 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[166] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6206 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6207 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6208 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6209 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6210 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6211 ) , + .clk_1_W_in ( clk_1_wires[71] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6212 ) , + .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6213 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6214 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6215 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6216 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6217 } ) , + .chanx_left_in ( sb_1__1__31_chanx_right_out ) , + .chanx_right_in ( sb_1__1__42_chanx_left_out ) , + .ccff_head ( sb_1__1__42_ccff_tail ) , + .chanx_left_out ( cbx_1__1__42_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__42_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6218 ) , + .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[42] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[42] ) , + .pReset_E_in ( pResetWires[516] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6219 ) , + .pReset_W_out ( pResetWires[515] ) , .pReset_S_out ( pResetWires[517] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6220 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6221 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6222 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6223 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6224 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6225 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6226 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6227 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6228 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6229 ) , + .clk_2_E_in ( clk_2_wires[62] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6230 ) , + .clk_2_W_out ( clk_2_wires[63] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6231 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6232 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6233 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6234 } ) , + .chanx_left_in ( sb_1__1__32_chanx_right_out ) , + .chanx_right_in ( sb_1__1__43_chanx_left_out ) , + .ccff_head ( sb_1__1__43_ccff_tail ) , + .chanx_left_out ( cbx_1__1__43_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__43_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6235 ) , + .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[43] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[43] ) , + .pReset_E_in ( pResetWires[565] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6236 ) , + .pReset_W_out ( pResetWires[564] ) , .pReset_S_out ( pResetWires[566] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6237 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[172] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6238 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6239 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6240 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6241 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6242 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6243 ) , + .clk_1_W_in ( clk_1_wires[78] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6244 ) , + .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6245 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6246 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6247 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6248 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6249 } ) , + .chanx_left_in ( sb_1__1__33_chanx_right_out ) , + .chanx_right_in ( sb_1__1__44_chanx_left_out ) , + .ccff_head ( sb_1__1__44_ccff_tail ) , + .chanx_left_out ( cbx_1__1__44_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__44_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6250 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[44] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[44] ) , + .pReset_E_in ( pResetWires[79] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6251 ) , + .pReset_W_out ( pResetWires[78] ) , .pReset_S_out ( pResetWires[80] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6252 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[180] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6253 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6254 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6255 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6256 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6257 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6258 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6259 ) , + .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6261 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6262 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6263 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6264 } ) , + .chanx_left_in ( sb_1__1__34_chanx_right_out ) , + .chanx_right_in ( sb_1__1__45_chanx_left_out ) , + .ccff_head ( sb_1__1__45_ccff_tail ) , + .chanx_left_out ( cbx_1__1__45_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__45_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6265 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[45] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[45] ) , + .pReset_E_in ( pResetWires[128] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6266 ) , + .pReset_W_out ( pResetWires[127] ) , .pReset_S_out ( pResetWires[129] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6267 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6268 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6269 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6270 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6271 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6272 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6273 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6274 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6275 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6276 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6277 ) , + .clk_2_W_in ( clk_2_wires[25] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6278 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6279 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6280 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6281 } ) , + .chanx_left_in ( sb_1__1__35_chanx_right_out ) , + .chanx_right_in ( sb_1__1__46_chanx_left_out ) , + .ccff_head ( sb_1__1__46_ccff_tail ) , + .chanx_left_out ( cbx_1__1__46_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__46_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6282 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[46] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[46] ) , + .pReset_E_in ( pResetWires[177] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6283 ) , + .pReset_W_out ( pResetWires[176] ) , .pReset_S_out ( pResetWires[178] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6284 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[186] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6285 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6286 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6287 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6288 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6289 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6290 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6291 ) , + .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6293 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6294 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6295 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6296 } ) , + .chanx_left_in ( sb_1__1__36_chanx_right_out ) , + .chanx_right_in ( sb_1__1__47_chanx_left_out ) , + .ccff_head ( sb_1__1__47_ccff_tail ) , + .chanx_left_out ( cbx_1__1__47_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__47_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6297 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[47] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[47] ) , + .pReset_E_in ( pResetWires[226] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6298 ) , + .pReset_W_out ( pResetWires[225] ) , .pReset_S_out ( pResetWires[227] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6299 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6300 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6301 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6302 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6303 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6304 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6305 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6306 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6307 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6308 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6309 ) , + .clk_2_W_in ( clk_2_wires[34] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6310 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6311 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6312 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6313 } ) , + .chanx_left_in ( sb_1__1__37_chanx_right_out ) , + .chanx_right_in ( sb_1__1__48_chanx_left_out ) , + .ccff_head ( sb_1__1__48_ccff_tail ) , + .chanx_left_out ( cbx_1__1__48_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__48_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6314 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[48] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[48] ) , + .pReset_E_in ( pResetWires[275] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6315 ) , + .pReset_W_out ( pResetWires[274] ) , .pReset_S_out ( pResetWires[276] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6316 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[192] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6317 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6318 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6319 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6320 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6322 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6323 ) , + .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6324 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6325 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6326 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6327 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6328 } ) , + .chanx_left_in ( sb_1__1__38_chanx_right_out ) , + .chanx_right_in ( sb_1__1__49_chanx_left_out ) , + .ccff_head ( sb_1__1__49_ccff_tail ) , + .chanx_left_out ( cbx_1__1__49_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__49_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6329 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[49] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[49] ) , + .pReset_E_in ( pResetWires[324] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6330 ) , + .pReset_W_out ( pResetWires[323] ) , .pReset_S_out ( pResetWires[325] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6331 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6332 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6333 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6334 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6335 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6336 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6337 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6338 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6339 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6340 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6342 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6343 ) , + .clk_3_E_in ( clk_3_wires[6] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6344 ) , + .clk_3_W_out ( clk_3_wires[7] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6345 } ) , + .chanx_left_in ( sb_1__1__39_chanx_right_out ) , + .chanx_right_in ( sb_1__1__50_chanx_left_out ) , + .ccff_head ( sb_1__1__50_ccff_tail ) , + .chanx_left_out ( cbx_1__1__50_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__50_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6346 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[50] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[50] ) , + .pReset_E_in ( pResetWires[373] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6347 ) , + .pReset_W_out ( pResetWires[372] ) , .pReset_S_out ( pResetWires[374] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6348 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[198] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6349 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6350 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6351 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6352 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6353 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6354 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6355 ) , + .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6356 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6357 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6359 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6360 } ) , + .chanx_left_in ( sb_1__1__40_chanx_right_out ) , + .chanx_right_in ( sb_1__1__51_chanx_left_out ) , + .ccff_head ( sb_1__1__51_ccff_tail ) , + .chanx_left_out ( cbx_1__1__51_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__51_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6361 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[51] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[51] ) , + .pReset_E_in ( pResetWires[422] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6362 ) , + .pReset_W_out ( pResetWires[421] ) , .pReset_S_out ( pResetWires[423] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6363 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6364 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6365 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6366 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6367 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6368 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6369 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6370 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6371 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6372 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6373 ) , + .clk_2_W_in ( clk_2_wires[47] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6374 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6375 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6376 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6377 } ) , + .chanx_left_in ( sb_1__1__41_chanx_right_out ) , + .chanx_right_in ( sb_1__1__52_chanx_left_out ) , + .ccff_head ( sb_1__1__52_ccff_tail ) , + .chanx_left_out ( cbx_1__1__52_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__52_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6378 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[52] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[52] ) , + .pReset_E_in ( pResetWires[471] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6379 ) , + .pReset_W_out ( pResetWires[470] ) , .pReset_S_out ( pResetWires[472] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6380 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[204] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6381 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6382 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6383 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6384 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6385 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6386 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6387 ) , + .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6388 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6389 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6390 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6391 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6392 } ) , + .chanx_left_in ( sb_1__1__42_chanx_right_out ) , + .chanx_right_in ( sb_1__1__53_chanx_left_out ) , + .ccff_head ( sb_1__1__53_ccff_tail ) , + .chanx_left_out ( cbx_1__1__53_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__53_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6393 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[53] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[53] ) , + .pReset_E_in ( pResetWires[520] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6394 ) , + .pReset_W_out ( pResetWires[519] ) , .pReset_S_out ( pResetWires[521] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6395 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6396 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6397 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6398 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6399 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6400 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6401 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6402 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6403 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6404 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6405 ) , + .clk_2_W_in ( clk_2_wires[60] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6406 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6407 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6408 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6409 } ) , + .chanx_left_in ( sb_1__1__43_chanx_right_out ) , + .chanx_right_in ( sb_1__1__54_chanx_left_out ) , + .ccff_head ( sb_1__1__54_ccff_tail ) , + .chanx_left_out ( cbx_1__1__54_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__54_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6410 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[54] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[54] ) , + .pReset_E_in ( pResetWires[569] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6411 ) , + .pReset_W_out ( pResetWires[568] ) , .pReset_S_out ( pResetWires[570] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6412 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[210] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6413 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6414 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6415 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6416 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6417 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6418 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6419 ) , + .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6421 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6423 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6424 } ) , + .chanx_left_in ( sb_1__1__44_chanx_right_out ) , + .chanx_right_in ( sb_1__1__55_chanx_left_out ) , + .ccff_head ( sb_1__1__55_ccff_tail ) , + .chanx_left_out ( cbx_1__1__55_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__55_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6425 ) , + .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[55] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[55] ) , + .pReset_E_in ( pResetWires[83] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6426 ) , + .pReset_W_out ( pResetWires[82] ) , .pReset_S_out ( pResetWires[84] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6427 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[218] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6428 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6429 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6430 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6431 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6432 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6433 ) , + .clk_1_W_in ( clk_1_wires[85] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6434 ) , + .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6435 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6436 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6437 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6438 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6439 } ) , + .chanx_left_in ( sb_1__1__45_chanx_right_out ) , + .chanx_right_in ( sb_1__1__56_chanx_left_out ) , + .ccff_head ( sb_1__1__56_ccff_tail ) , + .chanx_left_out ( cbx_1__1__56_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__56_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6440 ) , + .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[56] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[56] ) , + .pReset_E_in ( pResetWires[132] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6441 ) , + .pReset_W_out ( pResetWires[131] ) , .pReset_S_out ( pResetWires[133] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6442 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6443 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6444 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6445 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6446 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6447 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6448 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6449 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6450 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6452 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6454 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6455 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6456 } ) , + .chanx_left_in ( sb_1__1__46_chanx_right_out ) , + .chanx_right_in ( sb_1__1__57_chanx_left_out ) , + .ccff_head ( sb_1__1__57_ccff_tail ) , + .chanx_left_out ( cbx_1__1__57_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__57_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6457 ) , + .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[57] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[57] ) , + .pReset_E_in ( pResetWires[181] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6458 ) , + .pReset_W_out ( pResetWires[180] ) , .pReset_S_out ( pResetWires[182] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6459 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[224] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6460 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6461 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6462 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6463 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6464 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6465 ) , + .clk_1_W_in ( clk_1_wires[92] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6466 ) , + .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6467 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6468 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6469 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6470 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6471 } ) , + .chanx_left_in ( sb_1__1__47_chanx_right_out ) , + .chanx_right_in ( sb_1__1__58_chanx_left_out ) , + .ccff_head ( sb_1__1__58_ccff_tail ) , + .chanx_left_out ( cbx_1__1__58_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__58_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6472 ) , + .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[58] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[58] ) , + .pReset_E_in ( pResetWires[230] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6473 ) , + .pReset_W_out ( pResetWires[229] ) , .pReset_S_out ( pResetWires[231] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6474 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6475 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6476 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6477 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6478 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6479 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6480 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6481 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6482 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6486 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6487 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6488 } ) , + .chanx_left_in ( sb_1__1__48_chanx_right_out ) , + .chanx_right_in ( sb_1__1__59_chanx_left_out ) , + .ccff_head ( sb_1__1__59_ccff_tail ) , + .chanx_left_out ( cbx_1__1__59_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__59_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6489 ) , + .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[59] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[59] ) , + .pReset_E_in ( pResetWires[279] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6490 ) , + .pReset_W_out ( pResetWires[278] ) , .pReset_S_out ( pResetWires[280] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6491 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[230] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6492 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6493 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6494 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6495 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6496 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6497 ) , + .clk_1_W_in ( clk_1_wires[99] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6498 ) , + .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6500 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6501 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6502 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6503 } ) , + .chanx_left_in ( sb_1__1__49_chanx_right_out ) , + .chanx_right_in ( sb_1__1__60_chanx_left_out ) , + .ccff_head ( sb_1__1__60_ccff_tail ) , + .chanx_left_out ( cbx_1__1__60_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__60_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6504 ) , + .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[60] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[60] ) , + .pReset_E_in ( pResetWires[328] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6505 ) , + .pReset_W_out ( pResetWires[327] ) , .pReset_S_out ( pResetWires[329] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6506 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6507 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6508 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6509 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6510 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6511 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6512 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6513 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6514 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6515 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6516 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6517 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6518 ) , + .clk_3_E_in ( clk_3_wires[2] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6519 ) , + .clk_3_W_out ( clk_3_wires[3] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6520 } ) , + .chanx_left_in ( sb_1__1__50_chanx_right_out ) , + .chanx_right_in ( sb_1__1__61_chanx_left_out ) , + .ccff_head ( sb_1__1__61_ccff_tail ) , + .chanx_left_out ( cbx_1__1__61_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__61_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6521 ) , + .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[61] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[61] ) , + .pReset_E_in ( pResetWires[377] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6522 ) , + .pReset_W_out ( pResetWires[376] ) , .pReset_S_out ( pResetWires[378] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[236] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6524 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6525 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6526 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6527 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6528 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6529 ) , + .clk_1_W_in ( clk_1_wires[106] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6530 ) , + .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6531 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6532 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6533 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6534 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6535 } ) , + .chanx_left_in ( sb_1__1__51_chanx_right_out ) , + .chanx_right_in ( sb_1__1__62_chanx_left_out ) , + .ccff_head ( sb_1__1__62_ccff_tail ) , + .chanx_left_out ( cbx_1__1__62_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__62_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6536 ) , + .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[62] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[62] ) , + .pReset_E_in ( pResetWires[426] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6537 ) , + .pReset_W_out ( pResetWires[425] ) , .pReset_S_out ( pResetWires[427] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6538 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6539 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6540 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6541 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6542 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6543 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6544 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6545 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6546 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6548 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6551 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6552 } ) , + .chanx_left_in ( sb_1__1__52_chanx_right_out ) , + .chanx_right_in ( sb_1__1__63_chanx_left_out ) , + .ccff_head ( sb_1__1__63_ccff_tail ) , + .chanx_left_out ( cbx_1__1__63_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__63_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6553 ) , + .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[63] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[63] ) , + .pReset_E_in ( pResetWires[475] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6554 ) , + .pReset_W_out ( pResetWires[474] ) , .pReset_S_out ( pResetWires[476] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6555 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[242] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6556 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6557 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6558 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6559 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6560 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6561 ) , + .clk_1_W_in ( clk_1_wires[113] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6562 ) , + .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6563 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6564 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6565 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6566 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6567 } ) , + .chanx_left_in ( sb_1__1__53_chanx_right_out ) , + .chanx_right_in ( sb_1__1__64_chanx_left_out ) , + .ccff_head ( sb_1__1__64_ccff_tail ) , + .chanx_left_out ( cbx_1__1__64_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__64_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6568 ) , + .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[64] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[64] ) , + .pReset_E_in ( pResetWires[524] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6569 ) , + .pReset_W_out ( pResetWires[523] ) , .pReset_S_out ( pResetWires[525] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6570 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6571 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6572 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6573 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6574 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6575 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6576 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6577 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6578 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6580 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6582 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6583 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6584 } ) , + .chanx_left_in ( sb_1__1__54_chanx_right_out ) , + .chanx_right_in ( sb_1__1__65_chanx_left_out ) , + .ccff_head ( sb_1__1__65_ccff_tail ) , + .chanx_left_out ( cbx_1__1__65_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__65_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6585 ) , + .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[65] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[65] ) , + .pReset_E_in ( pResetWires[573] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6586 ) , + .pReset_W_out ( pResetWires[572] ) , .pReset_S_out ( pResetWires[574] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6587 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[248] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6588 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6589 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6590 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6591 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6592 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6593 ) , + .clk_1_W_in ( clk_1_wires[120] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6594 ) , + .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6595 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6596 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6597 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6598 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6599 } ) , + .chanx_left_in ( sb_1__1__55_chanx_right_out ) , + .chanx_right_in ( sb_1__1__66_chanx_left_out ) , + .ccff_head ( sb_1__1__66_ccff_tail ) , + .chanx_left_out ( cbx_1__1__66_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__66_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6600 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[66] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[66] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6601 ) , + .pReset_W_in ( pResetWires[86] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6602 ) , + .pReset_S_out ( pResetWires[88] ) , .pReset_E_out ( pResetWires[87] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[256] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6603 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6604 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6605 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6606 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6607 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6608 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6609 ) , + .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6610 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6611 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6612 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6613 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6614 } ) , + .chanx_left_in ( sb_1__1__56_chanx_right_out ) , + .chanx_right_in ( sb_1__1__67_chanx_left_out ) , + .ccff_head ( sb_1__1__67_ccff_tail ) , + .chanx_left_out ( cbx_1__1__67_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__67_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6615 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[67] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[67] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6616 ) , + .pReset_W_in ( pResetWires[135] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6617 ) , + .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6618 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6619 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6620 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6621 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6622 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6623 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6624 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6625 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6630 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6631 } ) , + .chanx_left_in ( sb_1__1__57_chanx_right_out ) , + .chanx_right_in ( sb_1__1__68_chanx_left_out ) , + .ccff_head ( sb_1__1__68_ccff_tail ) , + .chanx_left_out ( cbx_1__1__68_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__68_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6632 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[68] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[68] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6633 ) , + .pReset_W_in ( pResetWires[184] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6634 ) , + .pReset_S_out ( pResetWires[186] ) , .pReset_E_out ( pResetWires[185] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[262] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6635 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6636 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6637 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6638 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6639 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6640 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6641 ) , + .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6645 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6646 } ) , + .chanx_left_in ( sb_1__1__58_chanx_right_out ) , + .chanx_right_in ( sb_1__1__69_chanx_left_out ) , + .ccff_head ( sb_1__1__69_ccff_tail ) , + .chanx_left_out ( cbx_1__1__69_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__69_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6647 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[69] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[69] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6648 ) , + .pReset_W_in ( pResetWires[233] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6649 ) , + .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6650 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6651 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6652 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6653 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6654 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6655 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6656 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6657 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6661 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6662 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6663 } ) , + .chanx_left_in ( sb_1__1__59_chanx_right_out ) , + .chanx_right_in ( sb_1__1__70_chanx_left_out ) , + .ccff_head ( sb_1__1__70_ccff_tail ) , + .chanx_left_out ( cbx_1__1__70_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__70_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6664 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[70] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[70] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6665 ) , + .pReset_W_in ( pResetWires[282] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6666 ) , + .pReset_S_out ( pResetWires[284] ) , .pReset_E_out ( pResetWires[283] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[268] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6667 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6668 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6669 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6670 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6671 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6672 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6673 ) , + .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6674 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6675 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6676 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6677 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6678 } ) , + .chanx_left_in ( sb_1__1__60_chanx_right_out ) , + .chanx_right_in ( sb_1__1__71_chanx_left_out ) , + .ccff_head ( sb_1__1__71_ccff_tail ) , + .chanx_left_out ( cbx_1__1__71_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__71_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6679 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[71] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[71] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6680 ) , + .pReset_W_in ( pResetWires[331] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6681 ) , + .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6682 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6683 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6684 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6686 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6687 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6688 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6689 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6692 ) , + .clk_3_W_in ( clk_3_wires[0] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6693 ) , + .clk_3_E_out ( clk_3_wires[1] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6694 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6695 } ) , + .chanx_left_in ( sb_1__1__61_chanx_right_out ) , + .chanx_right_in ( sb_1__1__72_chanx_left_out ) , + .ccff_head ( sb_1__1__72_ccff_tail ) , + .chanx_left_out ( cbx_1__1__72_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__72_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6696 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[72] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[72] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6697 ) , + .pReset_W_in ( pResetWires[380] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6698 ) , + .pReset_S_out ( pResetWires[382] ) , .pReset_E_out ( pResetWires[381] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[274] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6699 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6700 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6701 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6702 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6703 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6704 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6705 ) , + .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6709 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6710 } ) , + .chanx_left_in ( sb_1__1__62_chanx_right_out ) , + .chanx_right_in ( sb_1__1__73_chanx_left_out ) , + .ccff_head ( sb_1__1__73_ccff_tail ) , + .chanx_left_out ( cbx_1__1__73_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__73_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6711 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[73] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[73] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6712 ) , + .pReset_W_in ( pResetWires[429] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6713 ) , + .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6714 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6715 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6716 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6717 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6718 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6719 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6720 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6721 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6723 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6726 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6727 } ) , + .chanx_left_in ( sb_1__1__63_chanx_right_out ) , + .chanx_right_in ( sb_1__1__74_chanx_left_out ) , + .ccff_head ( sb_1__1__74_ccff_tail ) , + .chanx_left_out ( cbx_1__1__74_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__74_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6728 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[74] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[74] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6729 ) , + .pReset_W_in ( pResetWires[478] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6730 ) , + .pReset_S_out ( pResetWires[480] ) , .pReset_E_out ( pResetWires[479] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[280] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6731 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6732 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6733 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6734 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6735 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6736 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6737 ) , + .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6738 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6739 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6740 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6741 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6742 } ) , + .chanx_left_in ( sb_1__1__64_chanx_right_out ) , + .chanx_right_in ( sb_1__1__75_chanx_left_out ) , + .ccff_head ( sb_1__1__75_ccff_tail ) , + .chanx_left_out ( cbx_1__1__75_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__75_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6743 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[75] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[75] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6744 ) , + .pReset_W_in ( pResetWires[527] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6745 ) , + .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6746 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6747 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6748 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6749 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6750 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6751 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6752 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6753 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6755 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6757 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6758 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6759 } ) , + .chanx_left_in ( sb_1__1__65_chanx_right_out ) , + .chanx_right_in ( sb_1__1__76_chanx_left_out ) , + .ccff_head ( sb_1__1__76_ccff_tail ) , + .chanx_left_out ( cbx_1__1__76_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__76_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6760 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[76] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[76] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6761 ) , + .pReset_W_in ( pResetWires[576] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6762 ) , + .pReset_S_out ( pResetWires[578] ) , .pReset_E_out ( pResetWires[577] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[286] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6763 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6764 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6765 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6766 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6767 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6768 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6769 ) , + .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6770 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6771 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6772 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6773 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6774 } ) , + .chanx_left_in ( sb_1__1__66_chanx_right_out ) , + .chanx_right_in ( sb_1__1__77_chanx_left_out ) , + .ccff_head ( sb_1__1__77_ccff_tail ) , + .chanx_left_out ( cbx_1__1__77_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__77_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6775 ) , + .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[77] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[77] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6776 ) , + .pReset_W_in ( pResetWires[90] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6777 ) , + .pReset_S_out ( pResetWires[92] ) , .pReset_E_out ( pResetWires[91] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[294] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6778 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6779 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6780 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6781 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6782 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6783 ) , + .clk_1_W_in ( clk_1_wires[127] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6784 ) , + .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6785 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6787 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6788 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6789 } ) , + .chanx_left_in ( sb_1__1__67_chanx_right_out ) , + .chanx_right_in ( sb_1__1__78_chanx_left_out ) , + .ccff_head ( sb_1__1__78_ccff_tail ) , + .chanx_left_out ( cbx_1__1__78_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__78_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6790 ) , + .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[78] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[78] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6791 ) , + .pReset_W_in ( pResetWires[139] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6792 ) , + .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6793 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6794 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6795 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6796 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6797 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6798 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6799 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6800 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6801 ) , + .clk_2_E_in ( clk_2_wires[71] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6802 ) , + .clk_2_W_out ( clk_2_wires[72] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6803 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6805 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6806 } ) , + .chanx_left_in ( sb_1__1__68_chanx_right_out ) , + .chanx_right_in ( sb_1__1__79_chanx_left_out ) , + .ccff_head ( sb_1__1__79_ccff_tail ) , + .chanx_left_out ( cbx_1__1__79_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__79_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6807 ) , + .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[79] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[79] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6808 ) , + .pReset_W_in ( pResetWires[188] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6809 ) , + .pReset_S_out ( pResetWires[190] ) , .pReset_E_out ( pResetWires[189] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[300] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6810 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6811 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6812 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6813 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6814 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6815 ) , + .clk_1_W_in ( clk_1_wires[134] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6816 ) , + .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6817 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6818 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6819 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6820 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6821 } ) , + .chanx_left_in ( sb_1__1__69_chanx_right_out ) , + .chanx_right_in ( sb_1__1__80_chanx_left_out ) , + .ccff_head ( sb_1__1__80_ccff_tail ) , + .chanx_left_out ( cbx_1__1__80_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__80_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6822 ) , + .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[80] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[80] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6823 ) , + .pReset_W_in ( pResetWires[237] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6824 ) , + .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6825 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6826 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6827 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6828 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6829 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6830 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6831 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6832 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6833 ) , + .clk_2_E_in ( clk_2_wires[80] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6834 ) , + .clk_2_W_out ( clk_2_wires[81] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6835 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6836 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6837 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6838 } ) , + .chanx_left_in ( sb_1__1__70_chanx_right_out ) , + .chanx_right_in ( sb_1__1__81_chanx_left_out ) , + .ccff_head ( sb_1__1__81_ccff_tail ) , + .chanx_left_out ( cbx_1__1__81_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__81_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6839 ) , + .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[81] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[81] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6840 ) , + .pReset_W_in ( pResetWires[286] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6841 ) , + .pReset_S_out ( pResetWires[288] ) , .pReset_E_out ( pResetWires[287] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[306] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6842 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6843 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6844 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6845 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6846 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6847 ) , + .clk_1_W_in ( clk_1_wires[141] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6848 ) , + .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6849 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6850 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6851 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6852 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6853 } ) , + .chanx_left_in ( sb_1__1__71_chanx_right_out ) , + .chanx_right_in ( sb_1__1__82_chanx_left_out ) , + .ccff_head ( sb_1__1__82_ccff_tail ) , + .chanx_left_out ( cbx_1__1__82_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__82_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6854 ) , + .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[82] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[82] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6855 ) , + .pReset_W_in ( pResetWires[335] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6856 ) , + .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6857 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6858 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6859 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6860 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6861 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6862 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6863 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6864 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6866 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6867 ) , + .clk_3_W_in ( clk_3_wires[4] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6868 ) , + .clk_3_E_out ( clk_3_wires[5] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6869 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6870 } ) , + .chanx_left_in ( sb_1__1__72_chanx_right_out ) , + .chanx_right_in ( sb_1__1__83_chanx_left_out ) , + .ccff_head ( sb_1__1__83_ccff_tail ) , + .chanx_left_out ( cbx_1__1__83_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__83_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6871 ) , + .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[83] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[83] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6872 ) , + .pReset_W_in ( pResetWires[384] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6873 ) , + .pReset_S_out ( pResetWires[386] ) , .pReset_E_out ( pResetWires[385] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[312] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6874 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6875 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6876 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6877 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6878 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6879 ) , + .clk_1_W_in ( clk_1_wires[148] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6880 ) , + .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6881 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6882 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6883 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6884 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6885 } ) , + .chanx_left_in ( sb_1__1__73_chanx_right_out ) , + .chanx_right_in ( sb_1__1__84_chanx_left_out ) , + .ccff_head ( sb_1__1__84_ccff_tail ) , + .chanx_left_out ( cbx_1__1__84_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__84_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6886 ) , + .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[84] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[84] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6887 ) , + .pReset_W_in ( pResetWires[433] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6888 ) , + .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6889 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6890 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6891 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6892 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6893 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6894 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6895 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6896 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6897 ) , + .clk_2_E_in ( clk_2_wires[93] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6898 ) , + .clk_2_W_out ( clk_2_wires[94] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6899 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6901 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6902 } ) , + .chanx_left_in ( sb_1__1__74_chanx_right_out ) , + .chanx_right_in ( sb_1__1__85_chanx_left_out ) , + .ccff_head ( sb_1__1__85_ccff_tail ) , + .chanx_left_out ( cbx_1__1__85_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__85_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6903 ) , + .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[85] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[85] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6904 ) , + .pReset_W_in ( pResetWires[482] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6905 ) , + .pReset_S_out ( pResetWires[484] ) , .pReset_E_out ( pResetWires[483] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[318] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6906 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6907 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6908 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6909 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6910 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6911 ) , + .clk_1_W_in ( clk_1_wires[155] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6912 ) , + .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6913 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6914 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6915 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6916 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6917 } ) , + .chanx_left_in ( sb_1__1__75_chanx_right_out ) , + .chanx_right_in ( sb_1__1__86_chanx_left_out ) , + .ccff_head ( sb_1__1__86_ccff_tail ) , + .chanx_left_out ( cbx_1__1__86_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__86_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6918 ) , + .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[86] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[86] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6919 ) , + .pReset_W_in ( pResetWires[531] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6920 ) , + .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6921 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6922 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6923 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6924 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6925 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6926 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6927 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6928 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6929 ) , + .clk_2_E_in ( clk_2_wires[106] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6930 ) , + .clk_2_W_out ( clk_2_wires[107] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6931 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6932 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6933 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6934 } ) , + .chanx_left_in ( sb_1__1__76_chanx_right_out ) , + .chanx_right_in ( sb_1__1__87_chanx_left_out ) , + .ccff_head ( sb_1__1__87_ccff_tail ) , + .chanx_left_out ( cbx_1__1__87_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__87_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6935 ) , + .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[87] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[87] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6936 ) , + .pReset_W_in ( pResetWires[580] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6937 ) , + .pReset_S_out ( pResetWires[582] ) , .pReset_E_out ( pResetWires[581] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[324] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6938 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6939 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6940 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6941 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6942 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6943 ) , + .clk_1_W_in ( clk_1_wires[162] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6944 ) , + .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6945 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6946 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6947 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6948 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6949 } ) , + .chanx_left_in ( sb_1__1__77_chanx_right_out ) , + .chanx_right_in ( sb_1__1__88_chanx_left_out ) , + .ccff_head ( sb_1__1__88_ccff_tail ) , + .chanx_left_out ( cbx_1__1__88_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__88_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6950 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[88] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[88] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6951 ) , + .pReset_W_in ( pResetWires[94] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6952 ) , + .pReset_S_out ( pResetWires[96] ) , .pReset_E_out ( pResetWires[95] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[332] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6953 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6954 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6955 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6956 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6957 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6958 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6959 ) , + .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6960 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6961 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6962 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6963 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6964 } ) , + .chanx_left_in ( sb_1__1__78_chanx_right_out ) , + .chanx_right_in ( sb_1__1__89_chanx_left_out ) , + .ccff_head ( sb_1__1__89_ccff_tail ) , + .chanx_left_out ( cbx_1__1__89_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__89_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6965 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[89] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[89] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6966 ) , + .pReset_W_in ( pResetWires[143] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6967 ) , + .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6968 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6969 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6970 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6971 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6972 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6973 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6974 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6975 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6976 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6977 ) , + .clk_2_W_in ( clk_2_wires[69] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6978 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6979 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6980 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6981 } ) , + .chanx_left_in ( sb_1__1__79_chanx_right_out ) , + .chanx_right_in ( sb_1__1__90_chanx_left_out ) , + .ccff_head ( sb_1__1__90_ccff_tail ) , + .chanx_left_out ( cbx_1__1__90_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__90_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6982 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[90] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[90] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6983 ) , + .pReset_W_in ( pResetWires[192] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6984 ) , + .pReset_S_out ( pResetWires[194] ) , .pReset_E_out ( pResetWires[193] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[338] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6985 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6986 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6987 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6988 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6989 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6990 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6991 ) , + .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6992 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6993 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6994 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6995 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6996 } ) , + .chanx_left_in ( sb_1__1__80_chanx_right_out ) , + .chanx_right_in ( sb_1__1__91_chanx_left_out ) , + .ccff_head ( sb_1__1__91_ccff_tail ) , + .chanx_left_out ( cbx_1__1__91_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__91_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6997 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[91] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[91] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6998 ) , + .pReset_W_in ( pResetWires[241] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6999 ) , + .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7000 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7001 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7002 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7003 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7004 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7005 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7006 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7007 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7008 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7009 ) , + .clk_2_W_in ( clk_2_wires[78] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7010 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7011 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7012 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7013 } ) , + .chanx_left_in ( sb_1__1__81_chanx_right_out ) , + .chanx_right_in ( sb_1__1__92_chanx_left_out ) , + .ccff_head ( sb_1__1__92_ccff_tail ) , + .chanx_left_out ( cbx_1__1__92_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__92_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7014 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[92] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[92] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7015 ) , + .pReset_W_in ( pResetWires[290] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7016 ) , + .pReset_S_out ( pResetWires[292] ) , .pReset_E_out ( pResetWires[291] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[344] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7017 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7018 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7019 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7020 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7021 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7022 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7023 ) , + .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7024 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7025 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7026 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7027 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7028 } ) , + .chanx_left_in ( sb_1__1__82_chanx_right_out ) , + .chanx_right_in ( sb_1__1__93_chanx_left_out ) , + .ccff_head ( sb_1__1__93_ccff_tail ) , + .chanx_left_out ( cbx_1__1__93_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__93_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7029 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[93] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[93] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7030 ) , + .pReset_W_in ( pResetWires[339] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7031 ) , + .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7032 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7033 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7034 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7035 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7036 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7037 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7038 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7039 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7041 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7042 ) , + .clk_3_W_in ( clk_3_wires[44] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7043 ) , + .clk_3_E_out ( clk_3_wires[45] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7044 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7045 } ) , + .chanx_left_in ( sb_1__1__83_chanx_right_out ) , + .chanx_right_in ( sb_1__1__94_chanx_left_out ) , + .ccff_head ( sb_1__1__94_ccff_tail ) , + .chanx_left_out ( cbx_1__1__94_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__94_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7046 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[94] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[94] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7047 ) , + .pReset_W_in ( pResetWires[388] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7048 ) , + .pReset_S_out ( pResetWires[390] ) , .pReset_E_out ( pResetWires[389] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[350] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7049 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7050 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7051 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7052 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7053 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7054 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7055 ) , + .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7056 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7057 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7058 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7059 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7060 } ) , + .chanx_left_in ( sb_1__1__84_chanx_right_out ) , + .chanx_right_in ( sb_1__1__95_chanx_left_out ) , + .ccff_head ( sb_1__1__95_ccff_tail ) , + .chanx_left_out ( cbx_1__1__95_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__95_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7061 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[95] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[95] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7062 ) , + .pReset_W_in ( pResetWires[437] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7063 ) , + .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7064 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7065 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7066 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7067 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7068 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7069 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7070 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7071 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7072 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7073 ) , + .clk_2_W_in ( clk_2_wires[91] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7074 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7075 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7076 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7077 } ) , + .chanx_left_in ( sb_1__1__85_chanx_right_out ) , + .chanx_right_in ( sb_1__1__96_chanx_left_out ) , + .ccff_head ( sb_1__1__96_ccff_tail ) , + .chanx_left_out ( cbx_1__1__96_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__96_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7078 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[96] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[96] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7079 ) , + .pReset_W_in ( pResetWires[486] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7080 ) , + .pReset_S_out ( pResetWires[488] ) , .pReset_E_out ( pResetWires[487] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[356] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7081 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7082 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7083 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7084 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7085 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7086 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7087 ) , + .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7089 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7090 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7091 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7092 } ) , + .chanx_left_in ( sb_1__1__86_chanx_right_out ) , + .chanx_right_in ( sb_1__1__97_chanx_left_out ) , + .ccff_head ( sb_1__1__97_ccff_tail ) , + .chanx_left_out ( cbx_1__1__97_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__97_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7093 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[97] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[97] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7094 ) , + .pReset_W_in ( pResetWires[535] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7095 ) , + .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7096 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7097 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7098 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7099 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7100 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7101 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7103 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7104 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7105 ) , + .clk_2_W_in ( clk_2_wires[104] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7106 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7107 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7108 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7109 } ) , + .chanx_left_in ( sb_1__1__87_chanx_right_out ) , + .chanx_right_in ( sb_1__1__98_chanx_left_out ) , + .ccff_head ( sb_1__1__98_ccff_tail ) , + .chanx_left_out ( cbx_1__1__98_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__98_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7110 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[98] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[98] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7111 ) , + .pReset_W_in ( pResetWires[584] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7112 ) , + .pReset_S_out ( pResetWires[586] ) , .pReset_E_out ( pResetWires[585] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[362] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7113 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7114 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7115 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7116 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7117 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7118 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7119 ) , + .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7120 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7121 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7122 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7123 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7124 } ) , + .chanx_left_in ( sb_1__1__88_chanx_right_out ) , + .chanx_right_in ( sb_1__1__99_chanx_left_out ) , + .ccff_head ( sb_1__1__99_ccff_tail ) , + .chanx_left_out ( cbx_1__1__99_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__99_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7125 ) , + .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[99] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[99] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7126 ) , + .pReset_W_in ( pResetWires[98] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7127 ) , + .pReset_S_out ( pResetWires[100] ) , .pReset_E_out ( pResetWires[99] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[370] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7128 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7129 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7130 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7131 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7132 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7133 ) , + .clk_1_W_in ( clk_1_wires[169] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7134 ) , + .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7135 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7136 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7137 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7138 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7139 } ) , + .chanx_left_in ( sb_1__1__89_chanx_right_out ) , + .chanx_right_in ( sb_1__1__100_chanx_left_out ) , + .ccff_head ( sb_1__1__100_ccff_tail ) , + .chanx_left_out ( cbx_1__1__100_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__100_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7140 ) , + .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[100] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[100] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7141 ) , + .pReset_W_in ( pResetWires[147] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7142 ) , + .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7143 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7144 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7145 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7146 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7147 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7148 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7149 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7150 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7154 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7155 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7156 } ) , + .chanx_left_in ( sb_1__1__90_chanx_right_out ) , + .chanx_right_in ( sb_1__1__101_chanx_left_out ) , + .ccff_head ( sb_1__1__101_ccff_tail ) , + .chanx_left_out ( cbx_1__1__101_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__101_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7157 ) , + .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[101] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[101] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7158 ) , + .pReset_W_in ( pResetWires[196] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7159 ) , + .pReset_S_out ( pResetWires[198] ) , .pReset_E_out ( pResetWires[197] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[376] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7160 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7161 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7162 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7163 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7164 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7165 ) , + .clk_1_W_in ( clk_1_wires[176] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7166 ) , + .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7168 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7169 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7170 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7171 } ) , + .chanx_left_in ( sb_1__1__91_chanx_right_out ) , + .chanx_right_in ( sb_1__1__102_chanx_left_out ) , + .ccff_head ( sb_1__1__102_ccff_tail ) , + .chanx_left_out ( cbx_1__1__102_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__102_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7172 ) , + .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[102] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[102] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7173 ) , + .pReset_W_in ( pResetWires[245] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7174 ) , + .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7175 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7176 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7177 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7178 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7179 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7180 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7181 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7182 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7187 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7188 } ) , + .chanx_left_in ( sb_1__1__92_chanx_right_out ) , + .chanx_right_in ( sb_1__1__103_chanx_left_out ) , + .ccff_head ( sb_1__1__103_ccff_tail ) , + .chanx_left_out ( cbx_1__1__103_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__103_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7189 ) , + .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[103] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[103] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7190 ) , + .pReset_W_in ( pResetWires[294] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7191 ) , + .pReset_S_out ( pResetWires[296] ) , .pReset_E_out ( pResetWires[295] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[382] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7192 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7193 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7194 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7195 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7196 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7197 ) , + .clk_1_W_in ( clk_1_wires[183] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7198 ) , + .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7199 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7200 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7201 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7202 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7203 } ) , + .chanx_left_in ( sb_1__1__93_chanx_right_out ) , + .chanx_right_in ( sb_1__1__104_chanx_left_out ) , + .ccff_head ( sb_1__1__104_ccff_tail ) , + .chanx_left_out ( cbx_1__1__104_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__104_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7204 ) , + .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[104] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[104] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7205 ) , + .pReset_W_in ( pResetWires[343] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7206 ) , + .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7207 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7208 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7209 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7210 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7211 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7212 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7213 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7214 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7217 ) , + .clk_3_W_in ( clk_3_wires[48] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7218 ) , + .clk_3_E_out ( clk_3_wires[49] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7219 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7220 } ) , + .chanx_left_in ( sb_1__1__94_chanx_right_out ) , + .chanx_right_in ( sb_1__1__105_chanx_left_out ) , + .ccff_head ( sb_1__1__105_ccff_tail ) , + .chanx_left_out ( cbx_1__1__105_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__105_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7221 ) , + .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[105] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[105] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7222 ) , + .pReset_W_in ( pResetWires[392] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7223 ) , + .pReset_S_out ( pResetWires[394] ) , .pReset_E_out ( pResetWires[393] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[388] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7224 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7225 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7226 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7227 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7228 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7229 ) , + .clk_1_W_in ( clk_1_wires[190] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7230 ) , + .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7231 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7232 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7233 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7234 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7235 } ) , + .chanx_left_in ( sb_1__1__95_chanx_right_out ) , + .chanx_right_in ( sb_1__1__106_chanx_left_out ) , + .ccff_head ( sb_1__1__106_ccff_tail ) , + .chanx_left_out ( cbx_1__1__106_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__106_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7236 ) , + .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[106] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[106] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7237 ) , + .pReset_W_in ( pResetWires[441] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7238 ) , + .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7239 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7240 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7241 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7242 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7243 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7245 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7246 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7248 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7250 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7251 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7252 } ) , + .chanx_left_in ( sb_1__1__96_chanx_right_out ) , + .chanx_right_in ( sb_1__1__107_chanx_left_out ) , + .ccff_head ( sb_1__1__107_ccff_tail ) , + .chanx_left_out ( cbx_1__1__107_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__107_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7253 ) , + .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[107] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[107] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7254 ) , + .pReset_W_in ( pResetWires[490] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7255 ) , + .pReset_S_out ( pResetWires[492] ) , .pReset_E_out ( pResetWires[491] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[394] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7256 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7257 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7258 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7259 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7260 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7261 ) , + .clk_1_W_in ( clk_1_wires[197] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7262 ) , + .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7263 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7264 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7265 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7266 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7267 } ) , + .chanx_left_in ( sb_1__1__97_chanx_right_out ) , + .chanx_right_in ( sb_1__1__108_chanx_left_out ) , + .ccff_head ( sb_1__1__108_ccff_tail ) , + .chanx_left_out ( cbx_1__1__108_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__108_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7268 ) , + .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[108] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[108] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7269 ) , + .pReset_W_in ( pResetWires[539] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7270 ) , + .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7271 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7272 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7273 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7274 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7275 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7276 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7277 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7278 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7283 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7284 } ) , + .chanx_left_in ( sb_1__1__98_chanx_right_out ) , + .chanx_right_in ( sb_1__1__109_chanx_left_out ) , + .ccff_head ( sb_1__1__109_ccff_tail ) , + .chanx_left_out ( cbx_1__1__109_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__109_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7285 ) , + .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[109] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[109] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7286 ) , + .pReset_W_in ( pResetWires[588] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7287 ) , + .pReset_S_out ( pResetWires[590] ) , .pReset_E_out ( pResetWires[589] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[400] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7288 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7289 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7290 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7291 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7292 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7293 ) , + .clk_1_W_in ( clk_1_wires[204] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7294 ) , + .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7295 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7296 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7297 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7298 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7299 } ) , + .chanx_left_in ( sb_1__1__99_chanx_right_out ) , + .chanx_right_in ( sb_1__1__110_chanx_left_out ) , + .ccff_head ( sb_1__1__110_ccff_tail ) , + .chanx_left_out ( cbx_1__1__110_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__110_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7300 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[110] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[110] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7301 ) , + .pReset_W_in ( pResetWires[102] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7302 ) , + .pReset_S_out ( pResetWires[104] ) , .pReset_E_out ( pResetWires[103] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[408] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7303 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7304 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7305 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7306 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7307 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7308 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7309 ) , + .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7310 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7311 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7312 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7313 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7314 } ) , + .chanx_left_in ( sb_1__1__100_chanx_right_out ) , + .chanx_right_in ( sb_1__1__111_chanx_left_out ) , + .ccff_head ( sb_1__1__111_ccff_tail ) , + .chanx_left_out ( cbx_1__1__111_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__111_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7315 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[111] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[111] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7316 ) , + .pReset_W_in ( pResetWires[151] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7317 ) , + .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7318 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7319 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7320 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7321 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7322 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7323 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7325 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7326 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7327 ) , + .clk_2_W_in ( clk_2_wires[114] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7328 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7329 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7330 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7331 } ) , + .chanx_left_in ( sb_1__1__101_chanx_right_out ) , + .chanx_right_in ( sb_1__1__112_chanx_left_out ) , + .ccff_head ( sb_1__1__112_ccff_tail ) , + .chanx_left_out ( cbx_1__1__112_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__112_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7332 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[112] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[112] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7333 ) , + .pReset_W_in ( pResetWires[200] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7334 ) , + .pReset_S_out ( pResetWires[202] ) , .pReset_E_out ( pResetWires[201] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[414] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7335 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7336 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7337 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7338 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7339 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7340 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7341 ) , + .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7342 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7343 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7345 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7346 } ) , + .chanx_left_in ( sb_1__1__102_chanx_right_out ) , + .chanx_right_in ( sb_1__1__113_chanx_left_out ) , + .ccff_head ( sb_1__1__113_ccff_tail ) , + .chanx_left_out ( cbx_1__1__113_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__113_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7347 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[113] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[113] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7348 ) , + .pReset_W_in ( pResetWires[249] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7349 ) , + .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7350 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7351 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7352 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7353 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7354 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7355 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7356 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7357 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7358 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7359 ) , + .clk_2_W_in ( clk_2_wires[119] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7360 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7361 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7362 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7363 } ) , + .chanx_left_in ( sb_1__1__103_chanx_right_out ) , + .chanx_right_in ( sb_1__1__114_chanx_left_out ) , + .ccff_head ( sb_1__1__114_ccff_tail ) , + .chanx_left_out ( cbx_1__1__114_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__114_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7364 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[114] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[114] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7365 ) , + .pReset_W_in ( pResetWires[298] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7366 ) , + .pReset_S_out ( pResetWires[300] ) , .pReset_E_out ( pResetWires[299] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[420] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7367 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7368 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7369 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7370 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7371 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7372 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7373 ) , + .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7374 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7375 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7377 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7378 } ) , + .chanx_left_in ( sb_1__1__104_chanx_right_out ) , + .chanx_right_in ( sb_1__1__115_chanx_left_out ) , + .ccff_head ( sb_1__1__115_ccff_tail ) , + .chanx_left_out ( cbx_1__1__115_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__115_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7379 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[115] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[115] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7380 ) , + .pReset_W_in ( pResetWires[347] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7381 ) , + .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7382 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7383 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7384 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7385 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7386 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7387 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7388 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7389 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7393 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7394 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7395 } ) , + .chanx_left_in ( sb_1__1__105_chanx_right_out ) , + .chanx_right_in ( sb_1__1__116_chanx_left_out ) , + .ccff_head ( sb_1__1__116_ccff_tail ) , + .chanx_left_out ( cbx_1__1__116_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__116_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7396 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[116] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[116] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7397 ) , + .pReset_W_in ( pResetWires[396] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7398 ) , + .pReset_S_out ( pResetWires[398] ) , .pReset_E_out ( pResetWires[397] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[426] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7399 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7400 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7401 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7402 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7403 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7404 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7405 ) , + .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7407 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7408 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7409 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7410 } ) , + .chanx_left_in ( sb_1__1__106_chanx_right_out ) , + .chanx_right_in ( sb_1__1__117_chanx_left_out ) , + .ccff_head ( sb_1__1__117_ccff_tail ) , + .chanx_left_out ( cbx_1__1__117_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__117_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7411 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[117] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[117] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7412 ) , + .pReset_W_in ( pResetWires[445] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7413 ) , + .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7414 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7415 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7416 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7417 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7418 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7419 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7420 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7421 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7422 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7423 ) , + .clk_2_W_in ( clk_2_wires[126] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7424 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7425 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7426 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7427 } ) , + .chanx_left_in ( sb_1__1__107_chanx_right_out ) , + .chanx_right_in ( sb_1__1__118_chanx_left_out ) , + .ccff_head ( sb_1__1__118_ccff_tail ) , + .chanx_left_out ( cbx_1__1__118_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__118_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7428 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[118] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[118] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7429 ) , + .pReset_W_in ( pResetWires[494] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7430 ) , + .pReset_S_out ( pResetWires[496] ) , .pReset_E_out ( pResetWires[495] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[432] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7431 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7432 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7433 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7434 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7436 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7437 ) , + .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7438 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7439 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7440 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7441 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7442 } ) , + .chanx_left_in ( sb_1__1__108_chanx_right_out ) , + .chanx_right_in ( sb_1__1__119_chanx_left_out ) , + .ccff_head ( sb_1__1__119_ccff_tail ) , + .chanx_left_out ( cbx_1__1__119_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__119_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7443 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[119] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[119] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7444 ) , + .pReset_W_in ( pResetWires[543] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7445 ) , + .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7446 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7447 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7448 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7449 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7450 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7451 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7453 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7454 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7455 ) , + .clk_2_W_in ( clk_2_wires[133] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7456 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7457 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7458 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7459 } ) , + .chanx_left_in ( sb_1__1__109_chanx_right_out ) , + .chanx_right_in ( sb_1__1__120_chanx_left_out ) , + .ccff_head ( sb_1__1__120_ccff_tail ) , + .chanx_left_out ( cbx_1__1__120_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__120_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7460 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[120] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[120] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7461 ) , + .pReset_W_in ( pResetWires[592] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7462 ) , + .pReset_S_out ( pResetWires[594] ) , .pReset_E_out ( pResetWires[593] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[438] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7463 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7464 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7465 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7466 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7467 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7468 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7469 ) , + .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7470 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7471 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7472 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7473 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7474 } ) , + .chanx_left_in ( sb_1__1__110_chanx_right_out ) , + .chanx_right_in ( sb_12__1__0_chanx_left_out ) , + .ccff_head ( sb_12__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__121_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__121_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7475 ) , + .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[121] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[121] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7476 ) , + .pReset_W_in ( pResetWires[106] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7477 ) , + .pReset_S_out ( pResetWires[108] ) , .pReset_E_out ( pResetWires[107] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[446] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7478 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7479 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7480 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7481 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7482 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7483 ) , + .clk_1_W_in ( clk_1_wires[211] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7484 ) , + .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7485 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7487 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7488 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7489 } ) , + .chanx_left_in ( sb_1__1__111_chanx_right_out ) , + .chanx_right_in ( sb_12__1__1_chanx_left_out ) , + .ccff_head ( sb_12__1__1_ccff_tail ) , + .chanx_left_out ( cbx_1__1__122_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__122_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7490 ) , + .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[122] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[122] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7491 ) , + .pReset_W_in ( pResetWires[155] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7492 ) , + .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7493 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7494 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7495 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7496 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7497 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7498 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7499 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7500 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7502 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7504 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7505 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7506 } ) , + .chanx_left_in ( sb_1__1__112_chanx_right_out ) , + .chanx_right_in ( sb_12__1__2_chanx_left_out ) , + .ccff_head ( sb_12__1__2_ccff_tail ) , + .chanx_left_out ( cbx_1__1__123_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__123_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7507 ) , + .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[123] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[123] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7508 ) , + .pReset_W_in ( pResetWires[204] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7509 ) , + .pReset_S_out ( pResetWires[206] ) , .pReset_E_out ( pResetWires[205] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[452] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7510 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7511 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7512 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7513 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7514 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7515 ) , + .clk_1_W_in ( clk_1_wires[218] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7516 ) , + .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7518 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7519 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7520 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7521 } ) , + .chanx_left_in ( sb_1__1__113_chanx_right_out ) , + .chanx_right_in ( sb_12__1__3_chanx_left_out ) , + .ccff_head ( sb_12__1__3_ccff_tail ) , + .chanx_left_out ( cbx_1__1__124_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__124_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7522 ) , + .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[124] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[124] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7523 ) , + .pReset_W_in ( pResetWires[253] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7524 ) , + .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7525 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7526 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7527 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7528 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7529 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7530 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7531 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7532 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7537 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7538 } ) , + .chanx_left_in ( sb_1__1__114_chanx_right_out ) , + .chanx_right_in ( sb_12__1__4_chanx_left_out ) , + .ccff_head ( sb_12__1__4_ccff_tail ) , + .chanx_left_out ( cbx_1__1__125_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__125_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7539 ) , + .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[125] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[125] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7540 ) , + .pReset_W_in ( pResetWires[302] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7541 ) , + .pReset_S_out ( pResetWires[304] ) , .pReset_E_out ( pResetWires[303] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[458] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7542 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7543 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7544 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7545 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7546 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7547 ) , + .clk_1_W_in ( clk_1_wires[225] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7548 ) , + .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7549 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7551 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7552 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7553 } ) , + .chanx_left_in ( sb_1__1__115_chanx_right_out ) , + .chanx_right_in ( sb_12__1__5_chanx_left_out ) , + .ccff_head ( sb_12__1__5_ccff_tail ) , + .chanx_left_out ( cbx_1__1__126_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__126_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7554 ) , + .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[126] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[126] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7555 ) , + .pReset_W_in ( pResetWires[351] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7556 ) , + .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7557 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7558 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7559 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7560 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7561 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7562 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7563 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7564 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7568 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7569 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7570 } ) , + .chanx_left_in ( sb_1__1__116_chanx_right_out ) , + .chanx_right_in ( sb_12__1__6_chanx_left_out ) , + .ccff_head ( sb_12__1__6_ccff_tail ) , + .chanx_left_out ( cbx_1__1__127_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__127_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7571 ) , + .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[127] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[127] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7572 ) , + .pReset_W_in ( pResetWires[400] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7573 ) , + .pReset_S_out ( pResetWires[402] ) , .pReset_E_out ( pResetWires[401] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[464] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7574 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7575 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7576 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7577 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7578 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7579 ) , + .clk_1_W_in ( clk_1_wires[232] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7580 ) , + .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7582 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7583 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7584 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7585 } ) , + .chanx_left_in ( sb_1__1__117_chanx_right_out ) , + .chanx_right_in ( sb_12__1__7_chanx_left_out ) , + .ccff_head ( sb_12__1__7_ccff_tail ) , + .chanx_left_out ( cbx_1__1__128_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__128_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7586 ) , + .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[128] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[128] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7587 ) , + .pReset_W_in ( pResetWires[449] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7588 ) , + .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7589 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7590 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7591 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7592 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7593 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7594 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7595 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7596 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7601 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7602 } ) , + .chanx_left_in ( sb_1__1__118_chanx_right_out ) , + .chanx_right_in ( sb_12__1__8_chanx_left_out ) , + .ccff_head ( sb_12__1__8_ccff_tail ) , + .chanx_left_out ( cbx_1__1__129_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__129_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7603 ) , + .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[129] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[129] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7604 ) , + .pReset_W_in ( pResetWires[498] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7605 ) , + .pReset_S_out ( pResetWires[500] ) , .pReset_E_out ( pResetWires[499] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[470] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7606 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7607 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7608 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7609 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7610 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7611 ) , + .clk_1_W_in ( clk_1_wires[239] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7612 ) , + .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7613 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7615 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7616 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7617 } ) , + .chanx_left_in ( sb_1__1__119_chanx_right_out ) , + .chanx_right_in ( sb_12__1__9_chanx_left_out ) , + .ccff_head ( sb_12__1__9_ccff_tail ) , + .chanx_left_out ( cbx_1__1__130_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__130_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7618 ) , + .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[130] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[130] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7619 ) , + .pReset_W_in ( pResetWires[547] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7620 ) , + .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7621 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7622 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7623 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7624 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7625 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7626 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7627 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7628 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7632 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7633 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__1_ cbx_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7634 } ) , + .chanx_left_in ( sb_1__1__120_chanx_right_out ) , + .chanx_right_in ( sb_12__1__10_chanx_left_out ) , + .ccff_head ( sb_12__1__10_ccff_tail ) , + .chanx_left_out ( cbx_1__1__131_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__131_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7635 ) , + .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[131] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[131] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7636 ) , + .pReset_W_in ( pResetWires[596] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7637 ) , + .pReset_S_out ( pResetWires[598] ) , .pReset_E_out ( pResetWires[597] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[476] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7638 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7639 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7640 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7641 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7642 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7643 ) , + .clk_1_W_in ( clk_1_wires[246] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7644 ) , + .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7645 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7646 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7647 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7648 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2_ cbx_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7649 } ) , + .chanx_left_in ( sb_0__12__0_chanx_right_out ) , + .chanx_right_in ( sb_1__12__0_chanx_left_out ) , + .ccff_head ( sb_1__12__0_ccff_tail ) , + .chanx_left_out ( cbx_1__12__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__0_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7650 ) , + .pReset_E_in ( pResetWires[601] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7651 ) , + .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7652 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[59] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[62] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cbx_1__2_ cbx_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7653 } ) , + .chanx_left_in ( sb_1__12__0_chanx_right_out ) , + .chanx_right_in ( sb_1__12__1_chanx_left_out ) , + .ccff_head ( sb_1__12__1_ccff_tail ) , + .chanx_left_out ( cbx_1__12__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__1_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7654 ) , + .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , + .pReset_E_in ( pResetWires[605] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7655 ) , + .pReset_W_out ( pResetWires[604] ) , .pReset_S_out ( pResetWires[606] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7656 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[99] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7657 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7658 } ) , + .chanx_left_in ( sb_1__12__1_chanx_right_out ) , + .chanx_right_in ( sb_1__12__2_chanx_left_out ) , + .ccff_head ( sb_1__12__2_ccff_tail ) , + .chanx_left_out ( cbx_1__12__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__2_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7659 ) , + .pReset_E_in ( pResetWires[608] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7660 ) , + .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7661 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[137] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7662 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7663 } ) , + .chanx_left_in ( sb_1__12__2_chanx_right_out ) , + .chanx_right_in ( sb_1__12__3_chanx_left_out ) , + .ccff_head ( sb_1__12__3_ccff_tail ) , + .chanx_left_out ( cbx_1__12__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__3_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7664 ) , + .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , + .pReset_E_in ( pResetWires[611] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7665 ) , + .pReset_W_out ( pResetWires[610] ) , .pReset_S_out ( pResetWires[612] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7666 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[175] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7667 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7668 } ) , + .chanx_left_in ( sb_1__12__3_chanx_right_out ) , + .chanx_right_in ( sb_1__12__4_chanx_left_out ) , + .ccff_head ( sb_1__12__4_ccff_tail ) , + .chanx_left_out ( cbx_1__12__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__4_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7669 ) , + .pReset_E_in ( pResetWires[614] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7670 ) , + .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7671 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[213] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7672 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7673 } ) , + .chanx_left_in ( sb_1__12__4_chanx_right_out ) , + .chanx_right_in ( sb_1__12__5_chanx_left_out ) , + .ccff_head ( sb_1__12__5_ccff_tail ) , + .chanx_left_out ( cbx_1__12__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__5_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7674 ) , + .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , + .pReset_E_in ( pResetWires[617] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7675 ) , + .pReset_W_out ( pResetWires[616] ) , .pReset_S_out ( pResetWires[618] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7676 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[251] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7677 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7678 } ) , + .chanx_left_in ( sb_1__12__5_chanx_right_out ) , + .chanx_right_in ( sb_1__12__6_chanx_left_out ) , + .ccff_head ( sb_1__12__6_ccff_tail ) , + .chanx_left_out ( cbx_1__12__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__6_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7679 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7680 ) , + .pReset_W_in ( pResetWires[619] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7681 ) , + .pReset_S_out ( pResetWires[621] ) , .pReset_E_out ( pResetWires[620] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[289] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7682 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7683 } ) , + .chanx_left_in ( sb_1__12__6_chanx_right_out ) , + .chanx_right_in ( sb_1__12__7_chanx_left_out ) , + .ccff_head ( sb_1__12__7_ccff_tail ) , + .chanx_left_out ( cbx_1__12__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__7_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7684 ) , + .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7685 ) , + .pReset_W_in ( pResetWires[622] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7686 ) , + .pReset_S_out ( pResetWires[624] ) , .pReset_E_out ( pResetWires[623] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[327] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7687 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7688 } ) , + .chanx_left_in ( sb_1__12__7_chanx_right_out ) , + .chanx_right_in ( sb_1__12__8_chanx_left_out ) , + .ccff_head ( sb_1__12__8_ccff_tail ) , + .chanx_left_out ( cbx_1__12__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__8_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7689 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7690 ) , + .pReset_W_in ( pResetWires[625] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7691 ) , + .pReset_S_out ( pResetWires[627] ) , .pReset_E_out ( pResetWires[626] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[365] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7692 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7693 } ) , + .chanx_left_in ( sb_1__12__8_chanx_right_out ) , + .chanx_right_in ( sb_1__12__9_chanx_left_out ) , + .ccff_head ( sb_1__12__9_ccff_tail ) , + .chanx_left_out ( cbx_1__12__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__9_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7694 ) , + .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7695 ) , + .pReset_W_in ( pResetWires[628] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7696 ) , + .pReset_S_out ( pResetWires[630] ) , .pReset_E_out ( pResetWires[629] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[403] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7697 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7698 } ) , + .chanx_left_in ( sb_1__12__9_chanx_right_out ) , + .chanx_right_in ( sb_1__12__10_chanx_left_out ) , + .ccff_head ( sb_1__12__10_ccff_tail ) , + .chanx_left_out ( cbx_1__12__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__10_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7699 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7700 ) , + .pReset_W_in ( pResetWires[631] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7701 ) , + .pReset_S_out ( pResetWires[633] ) , .pReset_E_out ( pResetWires[632] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[441] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7702 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__2_ cbx_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7703 } ) , + .chanx_left_in ( sb_1__12__10_chanx_right_out ) , + .chanx_right_in ( sb_12__12__0_chanx_left_out ) , + .ccff_head ( sb_12__12__0_ccff_tail ) , + .chanx_left_out ( cbx_1__12__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__11_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7704 ) , + .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7705 ) , + .pReset_W_in ( pResetWires[634] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7706 ) , + .pReset_S_out ( pResetWires[636] ) , .pReset_E_out ( pResetWires[635] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[479] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7707 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_0__1_ cby_0__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7708 } ) , + .chany_bottom_in ( sb_0__0__0_chany_top_out ) , + .chany_top_in ( sb_0__1__0_chany_bottom_out ) , + .ccff_head ( sb_0__1__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , + .chany_top_out ( cby_0__1__0_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[64] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[3] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7709 } ) , + .chany_bottom_in ( sb_0__1__0_chany_top_out ) , + .chany_top_in ( sb_0__1__1_chany_bottom_out ) , + .ccff_head ( sb_0__1__1_ccff_tail ) , + .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , + .chany_top_out ( cby_0__1__1_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[113] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[9] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7710 } ) , + .chany_bottom_in ( sb_0__1__1_chany_top_out ) , + .chany_top_in ( sb_0__1__2_chany_bottom_out ) , + .ccff_head ( sb_0__1__2_ccff_tail ) , + .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) , + .chany_top_out ( cby_0__1__2_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[162] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[14] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7711 } ) , + .chany_bottom_in ( sb_0__1__2_chany_top_out ) , + .chany_top_in ( sb_0__1__3_chany_bottom_out ) , + .ccff_head ( sb_0__1__3_ccff_tail ) , + .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) , + .chany_top_out ( cby_0__1__3_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[211] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[19] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7712 } ) , + .chany_bottom_in ( sb_0__1__3_chany_top_out ) , + .chany_top_in ( sb_0__1__4_chany_bottom_out ) , + .ccff_head ( sb_0__1__4_ccff_tail ) , + .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) , + .chany_top_out ( cby_0__1__4_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[260] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[24] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7713 } ) , + .chany_bottom_in ( sb_0__1__4_chany_top_out ) , + .chany_top_in ( sb_0__1__5_chany_bottom_out ) , + .ccff_head ( sb_0__1__5_ccff_tail ) , + .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) , + .chany_top_out ( cby_0__1__5_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[309] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[29] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7714 } ) , + .chany_bottom_in ( sb_0__1__5_chany_top_out ) , + .chany_top_in ( sb_0__1__6_chany_bottom_out ) , + .ccff_head ( sb_0__1__6_ccff_tail ) , + .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) , + .chany_top_out ( cby_0__1__6_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[358] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[34] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7715 } ) , + .chany_bottom_in ( sb_0__1__6_chany_top_out ) , + .chany_top_in ( sb_0__1__7_chany_bottom_out ) , + .ccff_head ( sb_0__1__7_ccff_tail ) , + .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) , + .chany_top_out ( cby_0__1__7_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[407] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[39] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7716 } ) , + .chany_bottom_in ( sb_0__1__7_chany_top_out ) , + .chany_top_in ( sb_0__1__8_chany_bottom_out ) , + .ccff_head ( sb_0__1__8_ccff_tail ) , + .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) , + .chany_top_out ( cby_0__1__8_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[456] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[44] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7717 } ) , + .chany_bottom_in ( sb_0__1__8_chany_top_out ) , + .chany_top_in ( sb_0__1__9_chany_bottom_out ) , + .ccff_head ( sb_0__1__9_ccff_tail ) , + .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) , + .chany_top_out ( cby_0__1__9_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[505] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[49] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7718 } ) , + .chany_bottom_in ( sb_0__1__9_chany_top_out ) , + .chany_top_in ( sb_0__1__10_chany_bottom_out ) , + .ccff_head ( sb_0__1__10_ccff_tail ) , + .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) , + .chany_top_out ( cby_0__1__10_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[554] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[54] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_0__1_ cby_0__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7719 } ) , + .chany_bottom_in ( sb_0__1__10_chany_top_out ) , + .chany_top_in ( sb_0__12__0_chany_bottom_out ) , + .ccff_head ( sb_0__12__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) , + .chany_top_out ( cby_0__1__11_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[603] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[61] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7720 } ) , + .chany_bottom_in ( sb_1__0__0_chany_top_out ) , + .chany_top_in ( sb_1__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_0_ccff_tail ) , + .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , + .chany_top_out ( cby_1__1__0_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7721 ) , + .Test_en_E_in ( Test_enWires[26] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7722 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7723 ) , + .Test_en_W_out ( Test_enWires[24] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7724 ) , + .pReset_S_in ( pResetWires[27] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7725 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7726 ) , + .Reset_E_in ( ResetWires[26] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7727 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7728 ) , + .Reset_W_out ( ResetWires[24] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7729 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7730 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7731 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7732 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7733 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7734 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7735 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7737 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7738 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7739 } ) , + .chany_bottom_in ( sb_1__1__0_chany_top_out ) , + .chany_top_in ( sb_1__1__1_chany_bottom_out ) , + .ccff_head ( grid_clb_1_ccff_tail ) , + .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , + .chany_top_out ( cby_1__1__1_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7740 ) , + .Test_en_E_in ( Test_enWires[48] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7741 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7742 ) , + .Test_en_W_out ( Test_enWires[46] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7743 ) , + .pReset_S_in ( pResetWires[65] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7744 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7745 ) , + .Reset_E_in ( ResetWires[48] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7746 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7747 ) , + .Reset_W_out ( ResetWires[46] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7748 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[7] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[8] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7749 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[3] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7750 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7751 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7752 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7753 ) , + .clk_2_N_in ( clk_2_wires[3] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7754 ) , + .clk_2_S_out ( clk_2_wires[4] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7755 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7756 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7757 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7758 } ) , + .chany_bottom_in ( sb_1__1__1_chany_top_out ) , + .chany_top_in ( sb_1__1__2_chany_bottom_out ) , + .ccff_head ( grid_clb_2_ccff_tail ) , + .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , + .chany_top_out ( cby_1__1__2_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__2_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7759 ) , + .Test_en_E_in ( Test_enWires[70] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7760 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7761 ) , + .Test_en_W_out ( Test_enWires[68] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7762 ) , + .pReset_S_in ( pResetWires[114] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7763 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7764 ) , + .Reset_E_in ( ResetWires[70] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7765 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7766 ) , + .Reset_W_out ( ResetWires[68] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7767 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7768 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7769 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7770 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7771 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7772 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7773 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7775 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7776 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7777 } ) , + .chany_bottom_in ( sb_1__1__2_chany_top_out ) , + .chany_top_in ( sb_1__1__3_chany_bottom_out ) , + .ccff_head ( grid_clb_3_ccff_tail ) , + .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , + .chany_top_out ( cby_1__1__3_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__3_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7778 ) , + .Test_en_E_in ( Test_enWires[92] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7779 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7780 ) , + .Test_en_W_out ( Test_enWires[90] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7781 ) , + .pReset_S_in ( pResetWires[163] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7782 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7783 ) , + .Reset_E_in ( ResetWires[92] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7784 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7785 ) , + .Reset_W_out ( ResetWires[90] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7786 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[17] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[18] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7787 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[10] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7788 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7789 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7790 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7791 ) , + .clk_2_N_in ( clk_2_wires[10] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7792 ) , + .clk_2_S_out ( clk_2_wires[11] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7793 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7794 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7795 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7796 } ) , + .chany_bottom_in ( sb_1__1__3_chany_top_out ) , + .chany_top_in ( sb_1__1__4_chany_bottom_out ) , + .ccff_head ( grid_clb_4_ccff_tail ) , + .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) , + .chany_top_out ( cby_1__1__4_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__4_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7797 ) , + .Test_en_E_in ( Test_enWires[114] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7798 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7799 ) , + .Test_en_W_out ( Test_enWires[112] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7800 ) , + .pReset_S_in ( pResetWires[212] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7801 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7802 ) , + .Reset_E_in ( ResetWires[114] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7803 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7804 ) , + .Reset_W_out ( ResetWires[112] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7805 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[22] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[23] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7806 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7807 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7808 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7809 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7810 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7811 ) , + .clk_2_S_in ( clk_2_wires[8] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7812 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7813 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7814 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7815 } ) , + .chany_bottom_in ( sb_1__1__4_chany_top_out ) , + .chany_top_in ( sb_1__1__5_chany_bottom_out ) , + .ccff_head ( grid_clb_5_ccff_tail ) , + .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) , + .chany_top_out ( cby_1__1__5_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__5_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7816 ) , + .Test_en_E_in ( Test_enWires[136] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7817 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7818 ) , + .Test_en_W_out ( Test_enWires[134] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7819 ) , + .pReset_S_in ( pResetWires[261] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7820 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7821 ) , + .Reset_E_in ( ResetWires[136] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7822 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7823 ) , + .Reset_W_out ( ResetWires[134] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7824 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7825 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7826 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7827 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7828 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7829 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7830 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7832 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7833 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7834 } ) , + .chany_bottom_in ( sb_1__1__5_chany_top_out ) , + .chany_top_in ( sb_1__1__6_chany_bottom_out ) , + .ccff_head ( grid_clb_6_ccff_tail ) , + .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) , + .chany_top_out ( cby_1__1__6_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__6_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7835 ) , + .Test_en_E_in ( Test_enWires[158] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7836 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7837 ) , + .Test_en_W_out ( Test_enWires[156] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7838 ) , + .pReset_S_in ( pResetWires[310] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7839 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7840 ) , + .Reset_E_in ( ResetWires[158] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7841 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7842 ) , + .Reset_W_out ( ResetWires[156] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7843 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7844 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7845 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7846 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7847 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7848 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7849 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7851 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7852 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7853 } ) , + .chany_bottom_in ( sb_1__1__6_chany_top_out ) , + .chany_top_in ( sb_1__1__7_chany_bottom_out ) , + .ccff_head ( grid_clb_7_ccff_tail ) , + .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) , + .chany_top_out ( cby_1__1__7_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__7_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7854 ) , + .Test_en_E_in ( Test_enWires[180] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7855 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7856 ) , + .Test_en_W_out ( Test_enWires[178] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7857 ) , + .pReset_S_in ( pResetWires[359] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7858 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7859 ) , + .Reset_E_in ( ResetWires[180] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7860 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7861 ) , + .Reset_W_out ( ResetWires[178] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7862 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[37] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[38] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7863 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[17] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7864 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7865 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7866 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7867 ) , + .clk_2_N_in ( clk_2_wires[17] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7868 ) , + .clk_2_S_out ( clk_2_wires[18] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7869 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7870 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7871 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7872 } ) , + .chany_bottom_in ( sb_1__1__7_chany_top_out ) , + .chany_top_in ( sb_1__1__8_chany_bottom_out ) , + .ccff_head ( grid_clb_8_ccff_tail ) , + .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) , + .chany_top_out ( cby_1__1__8_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__8_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7873 ) , + .Test_en_E_in ( Test_enWires[202] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7874 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7875 ) , + .Test_en_W_out ( Test_enWires[200] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7876 ) , + .pReset_S_in ( pResetWires[408] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7877 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7878 ) , + .Reset_E_in ( ResetWires[202] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7879 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7880 ) , + .Reset_W_out ( ResetWires[200] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7881 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[42] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[43] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7882 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7883 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7884 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7885 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7886 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7887 ) , + .clk_2_S_in ( clk_2_wires[15] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7888 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7889 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7890 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7891 } ) , + .chany_bottom_in ( sb_1__1__8_chany_top_out ) , + .chany_top_in ( sb_1__1__9_chany_bottom_out ) , + .ccff_head ( grid_clb_9_ccff_tail ) , + .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) , + .chany_top_out ( cby_1__1__9_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__9_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7892 ) , + .Test_en_E_in ( Test_enWires[224] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7893 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7894 ) , + .Test_en_W_out ( Test_enWires[222] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7895 ) , + .pReset_S_in ( pResetWires[457] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7896 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7897 ) , + .Reset_E_in ( ResetWires[224] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7898 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7899 ) , + .Reset_W_out ( ResetWires[222] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7900 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7901 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7902 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7903 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7904 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7905 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7906 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7908 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7909 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7910 } ) , + .chany_bottom_in ( sb_1__1__9_chany_top_out ) , + .chany_top_in ( sb_1__1__10_chany_bottom_out ) , + .ccff_head ( grid_clb_10_ccff_tail ) , + .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) , + .chany_top_out ( cby_1__1__10_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__10_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7911 ) , + .Test_en_E_in ( Test_enWires[246] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7912 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7913 ) , + .Test_en_W_out ( Test_enWires[244] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7914 ) , + .pReset_S_in ( pResetWires[506] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7915 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7916 ) , + .Reset_E_in ( ResetWires[246] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7917 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7918 ) , + .Reset_W_out ( ResetWires[244] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7919 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[52] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[53] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7920 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7921 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7922 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7924 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7925 ) , + .clk_2_S_in ( clk_2_wires[22] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7926 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7927 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7928 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7929 } ) , + .chany_bottom_in ( sb_1__1__10_chany_top_out ) , + .chany_top_in ( sb_1__12__0_chany_bottom_out ) , + .ccff_head ( grid_clb_11_ccff_tail ) , + .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) , + .chany_top_out ( cby_1__1__11_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__11_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7930 ) , + .Test_en_E_in ( Test_enWires[268] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7931 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7932 ) , + .Test_en_W_out ( Test_enWires[266] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7933 ) , + .pReset_S_in ( pResetWires[555] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7934 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7935 ) , + .Reset_E_in ( ResetWires[268] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7936 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7937 ) , + .Reset_W_out ( ResetWires[266] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7938 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7939 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7940 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7941 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7942 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7943 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7945 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7946 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7947 } ) , + .chany_bottom_in ( sb_1__0__1_chany_top_out ) , + .chany_top_in ( sb_1__1__11_chany_bottom_out ) , + .ccff_head ( grid_clb_12_ccff_tail ) , + .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) , + .chany_top_out ( cby_1__1__12_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__12_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7948 ) , + .Test_en_E_in ( Test_enWires[28] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7949 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7950 ) , + .Test_en_W_out ( Test_enWires[25] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7951 ) , + .pReset_S_in ( pResetWires[30] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7952 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7953 ) , + .Reset_E_in ( ResetWires[28] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7954 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7955 ) , + .Reset_W_out ( ResetWires[25] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7956 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7957 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7958 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7959 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7960 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7961 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7962 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7964 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7965 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7966 } ) , + .chany_bottom_in ( sb_1__1__11_chany_top_out ) , + .chany_top_in ( sb_1__1__12_chany_bottom_out ) , + .ccff_head ( grid_clb_13_ccff_tail ) , + .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) , + .chany_top_out ( cby_1__1__13_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__13_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7967 ) , + .Test_en_E_in ( Test_enWires[50] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7968 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7969 ) , + .Test_en_W_out ( Test_enWires[47] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7970 ) , + .pReset_S_in ( pResetWires[69] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7971 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7972 ) , + .Reset_E_in ( ResetWires[50] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7973 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7974 ) , + .Reset_W_out ( ResetWires[47] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7975 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7976 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7977 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7978 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7979 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7980 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7981 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7983 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7984 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7985 } ) , + .chany_bottom_in ( sb_1__1__12_chany_top_out ) , + .chany_top_in ( sb_1__1__13_chany_bottom_out ) , + .ccff_head ( grid_clb_14_ccff_tail ) , + .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) , + .chany_top_out ( cby_1__1__14_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__14_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7986 ) , + .Test_en_E_in ( Test_enWires[72] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7987 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7988 ) , + .Test_en_W_out ( Test_enWires[69] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7989 ) , + .pReset_S_in ( pResetWires[118] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7990 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7991 ) , + .Reset_E_in ( ResetWires[72] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7992 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7993 ) , + .Reset_W_out ( ResetWires[69] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7994 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7995 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7996 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7997 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7998 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7999 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8000 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8001 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8002 ) , + .clk_3_N_in ( clk_3_wires[68] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8003 ) , + .clk_3_S_out ( clk_3_wires[69] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8004 } ) , + .chany_bottom_in ( sb_1__1__13_chany_top_out ) , + .chany_top_in ( sb_1__1__14_chany_bottom_out ) , + .ccff_head ( grid_clb_15_ccff_tail ) , + .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) , + .chany_top_out ( cby_1__1__15_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__15_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8005 ) , + .Test_en_E_in ( Test_enWires[94] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8006 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8007 ) , + .Test_en_W_out ( Test_enWires[91] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8008 ) , + .pReset_S_in ( pResetWires[167] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8009 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8010 ) , + .Reset_E_in ( ResetWires[94] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8011 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8012 ) , + .Reset_W_out ( ResetWires[91] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8013 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8014 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8015 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8016 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8017 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8018 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8019 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8020 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8021 ) , + .clk_3_N_in ( clk_3_wires[64] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8022 ) , + .clk_3_S_out ( clk_3_wires[65] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8023 } ) , + .chany_bottom_in ( sb_1__1__14_chany_top_out ) , + .chany_top_in ( sb_1__1__15_chany_bottom_out ) , + .ccff_head ( grid_clb_16_ccff_tail ) , + .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) , + .chany_top_out ( cby_1__1__16_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__16_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8024 ) , + .Test_en_E_in ( Test_enWires[116] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8025 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8026 ) , + .Test_en_W_out ( Test_enWires[113] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8027 ) , + .pReset_S_in ( pResetWires[216] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8028 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8029 ) , + .Reset_E_in ( ResetWires[116] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8030 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8031 ) , + .Reset_W_out ( ResetWires[113] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8032 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8033 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8034 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8035 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8036 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8037 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8038 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8039 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8040 ) , + .clk_3_N_in ( clk_3_wires[58] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8041 ) , + .clk_3_S_out ( clk_3_wires[59] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8042 } ) , + .chany_bottom_in ( sb_1__1__15_chany_top_out ) , + .chany_top_in ( sb_1__1__16_chany_bottom_out ) , + .ccff_head ( grid_clb_17_ccff_tail ) , + .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) , + .chany_top_out ( cby_1__1__17_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__17_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8043 ) , + .Test_en_E_in ( Test_enWires[138] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8044 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8045 ) , + .Test_en_W_out ( Test_enWires[135] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8046 ) , + .pReset_S_in ( pResetWires[265] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8047 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8048 ) , + .Reset_E_in ( ResetWires[138] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8049 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8050 ) , + .Reset_W_out ( ResetWires[135] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8051 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8052 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8053 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8054 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8055 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8056 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8057 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8058 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8059 ) , + .clk_3_N_in ( clk_3_wires[54] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8060 ) , + .clk_3_S_out ( clk_3_wires[55] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8061 } ) , + .chany_bottom_in ( sb_1__1__16_chany_top_out ) , + .chany_top_in ( sb_1__1__17_chany_bottom_out ) , + .ccff_head ( grid_clb_18_ccff_tail ) , + .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) , + .chany_top_out ( cby_1__1__18_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__18_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8062 ) , + .Test_en_E_in ( Test_enWires[160] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8063 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8064 ) , + .Test_en_W_out ( Test_enWires[157] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8065 ) , + .pReset_S_in ( pResetWires[314] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8066 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8067 ) , + .Reset_E_in ( ResetWires[160] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8068 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8069 ) , + .Reset_W_out ( ResetWires[157] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8070 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8071 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8072 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8073 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8074 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8075 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8076 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8077 ) , + .clk_3_S_in ( clk_3_wires[52] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8078 ) , + .clk_3_N_out ( clk_3_wires[53] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8079 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8080 } ) , + .chany_bottom_in ( sb_1__1__17_chany_top_out ) , + .chany_top_in ( sb_1__1__18_chany_bottom_out ) , + .ccff_head ( grid_clb_19_ccff_tail ) , + .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) , + .chany_top_out ( cby_1__1__19_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__19_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8081 ) , + .Test_en_E_in ( Test_enWires[182] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8082 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8083 ) , + .Test_en_W_out ( Test_enWires[179] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8084 ) , + .pReset_S_in ( pResetWires[363] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8085 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8086 ) , + .Reset_E_in ( ResetWires[182] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8087 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8088 ) , + .Reset_W_out ( ResetWires[179] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8089 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8090 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8091 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8092 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8093 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8094 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8095 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8096 ) , + .clk_3_S_in ( clk_3_wires[56] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8097 ) , + .clk_3_N_out ( clk_3_wires[57] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8098 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8099 } ) , + .chany_bottom_in ( sb_1__1__18_chany_top_out ) , + .chany_top_in ( sb_1__1__19_chany_bottom_out ) , + .ccff_head ( grid_clb_20_ccff_tail ) , + .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) , + .chany_top_out ( cby_1__1__20_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__20_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8100 ) , + .Test_en_E_in ( Test_enWires[204] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8101 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8102 ) , + .Test_en_W_out ( Test_enWires[201] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8103 ) , + .pReset_S_in ( pResetWires[412] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8104 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8105 ) , + .Reset_E_in ( ResetWires[204] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8106 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8107 ) , + .Reset_W_out ( ResetWires[201] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8108 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8109 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8110 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8111 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8112 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8113 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8114 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8115 ) , + .clk_3_S_in ( clk_3_wires[62] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8116 ) , + .clk_3_N_out ( clk_3_wires[63] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8117 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8118 } ) , + .chany_bottom_in ( sb_1__1__19_chany_top_out ) , + .chany_top_in ( sb_1__1__20_chany_bottom_out ) , + .ccff_head ( grid_clb_21_ccff_tail ) , + .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) , + .chany_top_out ( cby_1__1__21_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__21_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8119 ) , + .Test_en_E_in ( Test_enWires[226] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8120 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8121 ) , + .Test_en_W_out ( Test_enWires[223] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8122 ) , + .pReset_S_in ( pResetWires[461] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8123 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8124 ) , + .Reset_E_in ( ResetWires[226] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8125 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8126 ) , + .Reset_W_out ( ResetWires[223] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8127 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8128 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8129 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8130 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8131 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8132 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8133 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8134 ) , + .clk_3_S_in ( clk_3_wires[66] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8135 ) , + .clk_3_N_out ( clk_3_wires[67] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8136 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8137 } ) , + .chany_bottom_in ( sb_1__1__20_chany_top_out ) , + .chany_top_in ( sb_1__1__21_chany_bottom_out ) , + .ccff_head ( grid_clb_22_ccff_tail ) , + .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) , + .chany_top_out ( cby_1__1__22_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__22_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8138 ) , + .Test_en_E_in ( Test_enWires[248] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8139 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8140 ) , + .Test_en_W_out ( Test_enWires[245] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8141 ) , + .pReset_S_in ( pResetWires[510] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8142 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8143 ) , + .Reset_E_in ( ResetWires[248] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8144 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8145 ) , + .Reset_W_out ( ResetWires[245] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8146 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8147 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8148 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8150 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8151 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8152 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8155 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8156 } ) , + .chany_bottom_in ( sb_1__1__21_chany_top_out ) , + .chany_top_in ( sb_1__12__1_chany_bottom_out ) , + .ccff_head ( grid_clb_23_ccff_tail ) , + .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) , + .chany_top_out ( cby_1__1__23_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__23_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8157 ) , + .Test_en_E_in ( Test_enWires[270] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8158 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8159 ) , + .Test_en_W_out ( Test_enWires[267] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8160 ) , + .pReset_S_in ( pResetWires[559] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8161 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8162 ) , + .Reset_E_in ( ResetWires[270] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8163 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8164 ) , + .Reset_W_out ( ResetWires[267] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8165 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8166 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8167 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8168 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8169 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8170 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8172 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8173 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8174 } ) , + .chany_bottom_in ( sb_1__0__2_chany_top_out ) , + .chany_top_in ( sb_1__1__22_chany_bottom_out ) , + .ccff_head ( grid_clb_24_ccff_tail ) , + .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) , + .chany_top_out ( cby_1__1__24_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__24_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8175 ) , + .Test_en_E_in ( Test_enWires[30] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8176 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8177 ) , + .Test_en_W_out ( Test_enWires[27] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8178 ) , + .pReset_S_in ( pResetWires[33] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8179 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8180 ) , + .Reset_E_in ( ResetWires[30] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8181 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8182 ) , + .Reset_W_out ( ResetWires[27] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8183 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8184 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8185 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8186 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8187 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8188 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8189 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8192 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8193 } ) , + .chany_bottom_in ( sb_1__1__22_chany_top_out ) , + .chany_top_in ( sb_1__1__23_chany_bottom_out ) , + .ccff_head ( grid_clb_25_ccff_tail ) , + .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) , + .chany_top_out ( cby_1__1__25_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__25_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8194 ) , + .Test_en_E_in ( Test_enWires[52] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8195 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8196 ) , + .Test_en_W_out ( Test_enWires[49] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8197 ) , + .pReset_S_in ( pResetWires[73] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8198 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8199 ) , + .Reset_E_in ( ResetWires[52] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8200 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8201 ) , + .Reset_W_out ( ResetWires[49] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8202 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[105] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[106] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8203 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[29] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8204 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8205 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8206 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8207 ) , + .clk_2_N_in ( clk_2_wires[29] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8208 ) , + .clk_2_S_out ( clk_2_wires[30] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8209 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8210 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8211 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8212 } ) , + .chany_bottom_in ( sb_1__1__23_chany_top_out ) , + .chany_top_in ( sb_1__1__24_chany_bottom_out ) , + .ccff_head ( grid_clb_26_ccff_tail ) , + .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) , + .chany_top_out ( cby_1__1__26_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__26_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8213 ) , + .Test_en_E_in ( Test_enWires[74] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8214 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8215 ) , + .Test_en_W_out ( Test_enWires[71] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8216 ) , + .pReset_S_in ( pResetWires[122] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8217 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8218 ) , + .Reset_E_in ( ResetWires[74] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8219 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8220 ) , + .Reset_W_out ( ResetWires[71] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8221 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8222 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8223 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8224 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8225 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8226 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8227 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8229 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8230 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8231 } ) , + .chany_bottom_in ( sb_1__1__24_chany_top_out ) , + .chany_top_in ( sb_1__1__25_chany_bottom_out ) , + .ccff_head ( grid_clb_27_ccff_tail ) , + .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) , + .chany_top_out ( cby_1__1__27_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__27_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8232 ) , + .Test_en_E_in ( Test_enWires[96] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8233 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8234 ) , + .Test_en_W_out ( Test_enWires[93] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8235 ) , + .pReset_S_in ( pResetWires[171] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8236 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8237 ) , + .Reset_E_in ( ResetWires[96] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8238 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8239 ) , + .Reset_W_out ( ResetWires[93] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8240 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[111] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[112] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8241 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[40] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8242 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8243 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8244 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8245 ) , + .clk_2_N_in ( clk_2_wires[40] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8246 ) , + .clk_2_S_out ( clk_2_wires[41] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8247 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8248 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8249 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8250 } ) , + .chany_bottom_in ( sb_1__1__25_chany_top_out ) , + .chany_top_in ( sb_1__1__26_chany_bottom_out ) , + .ccff_head ( grid_clb_28_ccff_tail ) , + .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) , + .chany_top_out ( cby_1__1__28_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__28_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8251 ) , + .Test_en_E_in ( Test_enWires[118] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8252 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8253 ) , + .Test_en_W_out ( Test_enWires[115] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8254 ) , + .pReset_S_in ( pResetWires[220] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8255 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8256 ) , + .Reset_E_in ( ResetWires[118] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8257 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8258 ) , + .Reset_W_out ( ResetWires[115] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8259 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[114] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[115] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8260 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8261 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8262 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8263 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8264 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8265 ) , + .clk_2_S_in ( clk_2_wires[38] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8266 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8267 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8268 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8269 } ) , + .chany_bottom_in ( sb_1__1__26_chany_top_out ) , + .chany_top_in ( sb_1__1__27_chany_bottom_out ) , + .ccff_head ( grid_clb_29_ccff_tail ) , + .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) , + .chany_top_out ( cby_1__1__29_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__29_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8270 ) , + .Test_en_E_in ( Test_enWires[140] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8271 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8272 ) , + .Test_en_W_out ( Test_enWires[137] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8273 ) , + .pReset_S_in ( pResetWires[269] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8274 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8275 ) , + .Reset_E_in ( ResetWires[140] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8276 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8277 ) , + .Reset_W_out ( ResetWires[137] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8278 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8279 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8280 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8281 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8282 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8283 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8284 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8286 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8287 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8288 } ) , + .chany_bottom_in ( sb_1__1__27_chany_top_out ) , + .chany_top_in ( sb_1__1__28_chany_bottom_out ) , + .ccff_head ( grid_clb_30_ccff_tail ) , + .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) , + .chany_top_out ( cby_1__1__30_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__30_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8289 ) , + .Test_en_E_in ( Test_enWires[162] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8290 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8291 ) , + .Test_en_W_out ( Test_enWires[159] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8292 ) , + .pReset_S_in ( pResetWires[318] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8293 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8294 ) , + .Reset_E_in ( ResetWires[162] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8295 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8296 ) , + .Reset_W_out ( ResetWires[159] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8297 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8298 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8299 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8300 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8301 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8302 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8303 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8305 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8306 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8307 } ) , + .chany_bottom_in ( sb_1__1__28_chany_top_out ) , + .chany_top_in ( sb_1__1__29_chany_bottom_out ) , + .ccff_head ( grid_clb_31_ccff_tail ) , + .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) , + .chany_top_out ( cby_1__1__31_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__31_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8308 ) , + .Test_en_E_in ( Test_enWires[184] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8309 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8310 ) , + .Test_en_W_out ( Test_enWires[181] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8311 ) , + .pReset_S_in ( pResetWires[367] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8312 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8313 ) , + .Reset_E_in ( ResetWires[184] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8314 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8315 ) , + .Reset_W_out ( ResetWires[181] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8316 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[123] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[124] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8317 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[53] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8318 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8319 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8320 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8321 ) , + .clk_2_N_in ( clk_2_wires[53] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8322 ) , + .clk_2_S_out ( clk_2_wires[54] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8323 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8324 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8325 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8326 } ) , + .chany_bottom_in ( sb_1__1__29_chany_top_out ) , + .chany_top_in ( sb_1__1__30_chany_bottom_out ) , + .ccff_head ( grid_clb_32_ccff_tail ) , + .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) , + .chany_top_out ( cby_1__1__32_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__32_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8327 ) , + .Test_en_E_in ( Test_enWires[206] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8328 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8329 ) , + .Test_en_W_out ( Test_enWires[203] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8330 ) , + .pReset_S_in ( pResetWires[416] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8331 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8332 ) , + .Reset_E_in ( ResetWires[206] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8333 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8334 ) , + .Reset_W_out ( ResetWires[203] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8335 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[126] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[127] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8336 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8337 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8338 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8339 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8340 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8341 ) , + .clk_2_S_in ( clk_2_wires[51] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8342 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8343 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8344 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8345 } ) , + .chany_bottom_in ( sb_1__1__30_chany_top_out ) , + .chany_top_in ( sb_1__1__31_chany_bottom_out ) , + .ccff_head ( grid_clb_33_ccff_tail ) , + .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) , + .chany_top_out ( cby_1__1__33_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__33_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8346 ) , + .Test_en_E_in ( Test_enWires[228] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8347 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8348 ) , + .Test_en_W_out ( Test_enWires[225] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8349 ) , + .pReset_S_in ( pResetWires[465] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8350 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8351 ) , + .Reset_E_in ( ResetWires[228] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8352 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8353 ) , + .Reset_W_out ( ResetWires[225] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8354 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8355 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8356 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8357 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8358 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8359 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8360 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8362 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8363 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8364 } ) , + .chany_bottom_in ( sb_1__1__31_chany_top_out ) , + .chany_top_in ( sb_1__1__32_chany_bottom_out ) , + .ccff_head ( grid_clb_34_ccff_tail ) , + .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) , + .chany_top_out ( cby_1__1__34_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__34_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8365 ) , + .Test_en_E_in ( Test_enWires[250] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8366 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8367 ) , + .Test_en_W_out ( Test_enWires[247] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8368 ) , + .pReset_S_in ( pResetWires[514] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8369 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8370 ) , + .Reset_E_in ( ResetWires[250] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8371 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8372 ) , + .Reset_W_out ( ResetWires[247] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8373 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[132] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[133] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8374 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8375 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8376 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8377 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8378 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8379 ) , + .clk_2_S_in ( clk_2_wires[64] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8380 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8381 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8382 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8383 } ) , + .chany_bottom_in ( sb_1__1__32_chany_top_out ) , + .chany_top_in ( sb_1__12__2_chany_bottom_out ) , + .ccff_head ( grid_clb_35_ccff_tail ) , + .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) , + .chany_top_out ( cby_1__1__35_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__35_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8384 ) , + .Test_en_E_in ( Test_enWires[272] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8385 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8386 ) , + .Test_en_W_out ( Test_enWires[269] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8387 ) , + .pReset_S_in ( pResetWires[563] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8388 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8389 ) , + .Reset_E_in ( ResetWires[272] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8390 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8391 ) , + .Reset_W_out ( ResetWires[269] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8392 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8393 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8394 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8395 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8396 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8397 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8399 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8400 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8401 } ) , + .chany_bottom_in ( sb_1__0__3_chany_top_out ) , + .chany_top_in ( sb_1__1__33_chany_bottom_out ) , + .ccff_head ( grid_clb_36_ccff_tail ) , + .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) , + .chany_top_out ( cby_1__1__36_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__36_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8402 ) , + .Test_en_E_in ( Test_enWires[32] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8403 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8404 ) , + .Test_en_W_out ( Test_enWires[29] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8405 ) , + .pReset_S_in ( pResetWires[36] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8406 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8407 ) , + .Reset_E_in ( ResetWires[32] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8408 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8409 ) , + .Reset_W_out ( ResetWires[29] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8410 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8411 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8412 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8413 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8414 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8415 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8416 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8419 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8420 } ) , + .chany_bottom_in ( sb_1__1__33_chany_top_out ) , + .chany_top_in ( sb_1__1__34_chany_bottom_out ) , + .ccff_head ( grid_clb_37_ccff_tail ) , + .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) , + .chany_top_out ( cby_1__1__37_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__37_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8421 ) , + .Test_en_E_in ( Test_enWires[54] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8422 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8423 ) , + .Test_en_W_out ( Test_enWires[51] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8424 ) , + .pReset_S_in ( pResetWires[77] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8425 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8426 ) , + .Reset_E_in ( ResetWires[54] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8427 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8428 ) , + .Reset_W_out ( ResetWires[51] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8429 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8430 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8431 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8433 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8434 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8435 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8437 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8438 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8439 } ) , + .chany_bottom_in ( sb_1__1__34_chany_top_out ) , + .chany_top_in ( sb_1__1__35_chany_bottom_out ) , + .ccff_head ( grid_clb_38_ccff_tail ) , + .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) , + .chany_top_out ( cby_1__1__38_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__38_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8440 ) , + .Test_en_E_in ( Test_enWires[76] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8441 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8442 ) , + .Test_en_W_out ( Test_enWires[73] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8443 ) , + .pReset_S_in ( pResetWires[126] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8444 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8445 ) , + .Reset_E_in ( ResetWires[76] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8446 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8447 ) , + .Reset_W_out ( ResetWires[73] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8448 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8449 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8450 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8451 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8452 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8453 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8454 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8455 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8456 ) , + .clk_3_N_in ( clk_3_wires[24] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8457 ) , + .clk_3_S_out ( clk_3_wires[25] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8458 } ) , + .chany_bottom_in ( sb_1__1__35_chany_top_out ) , + .chany_top_in ( sb_1__1__36_chany_bottom_out ) , + .ccff_head ( grid_clb_39_ccff_tail ) , + .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) , + .chany_top_out ( cby_1__1__39_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__39_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8459 ) , + .Test_en_E_in ( Test_enWires[98] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8460 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8461 ) , + .Test_en_W_out ( Test_enWires[95] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8462 ) , + .pReset_S_in ( pResetWires[175] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8463 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8464 ) , + .Reset_E_in ( ResetWires[98] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8465 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8466 ) , + .Reset_W_out ( ResetWires[95] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8467 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8468 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8469 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8470 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8471 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8472 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8473 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8474 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8475 ) , + .clk_3_N_in ( clk_3_wires[20] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8476 ) , + .clk_3_S_out ( clk_3_wires[21] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8477 } ) , + .chany_bottom_in ( sb_1__1__36_chany_top_out ) , + .chany_top_in ( sb_1__1__37_chany_bottom_out ) , + .ccff_head ( grid_clb_40_ccff_tail ) , + .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) , + .chany_top_out ( cby_1__1__40_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__40_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8478 ) , + .Test_en_E_in ( Test_enWires[120] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8479 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8480 ) , + .Test_en_W_out ( Test_enWires[117] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8481 ) , + .pReset_S_in ( pResetWires[224] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8482 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8483 ) , + .Reset_E_in ( ResetWires[120] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8484 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8485 ) , + .Reset_W_out ( ResetWires[117] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8486 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8487 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8488 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8489 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8490 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8491 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8492 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8493 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8494 ) , + .clk_3_N_in ( clk_3_wires[14] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8495 ) , + .clk_3_S_out ( clk_3_wires[15] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8496 } ) , + .chany_bottom_in ( sb_1__1__37_chany_top_out ) , + .chany_top_in ( sb_1__1__38_chany_bottom_out ) , + .ccff_head ( grid_clb_41_ccff_tail ) , + .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) , + .chany_top_out ( cby_1__1__41_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__41_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8497 ) , + .Test_en_E_in ( Test_enWires[142] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8498 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8499 ) , + .Test_en_W_out ( Test_enWires[139] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8500 ) , + .pReset_S_in ( pResetWires[273] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8501 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8502 ) , + .Reset_E_in ( ResetWires[142] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8503 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8504 ) , + .Reset_W_out ( ResetWires[139] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8505 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8506 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8507 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8508 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8509 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8510 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8511 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8512 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8513 ) , + .clk_3_N_in ( clk_3_wires[10] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8514 ) , + .clk_3_S_out ( clk_3_wires[11] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8515 } ) , + .chany_bottom_in ( sb_1__1__38_chany_top_out ) , + .chany_top_in ( sb_1__1__39_chany_bottom_out ) , + .ccff_head ( grid_clb_42_ccff_tail ) , + .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) , + .chany_top_out ( cby_1__1__42_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__42_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8516 ) , + .Test_en_E_in ( Test_enWires[164] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8517 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8518 ) , + .Test_en_W_out ( Test_enWires[161] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8519 ) , + .pReset_S_in ( pResetWires[322] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8520 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8521 ) , + .Reset_E_in ( ResetWires[164] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8522 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8523 ) , + .Reset_W_out ( ResetWires[161] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8524 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8525 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8526 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8527 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8528 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8529 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8530 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8531 ) , + .clk_3_S_in ( clk_3_wires[8] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8532 ) , + .clk_3_N_out ( clk_3_wires[9] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8533 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8534 } ) , + .chany_bottom_in ( sb_1__1__39_chany_top_out ) , + .chany_top_in ( sb_1__1__40_chany_bottom_out ) , + .ccff_head ( grid_clb_43_ccff_tail ) , + .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) , + .chany_top_out ( cby_1__1__43_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__43_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8535 ) , + .Test_en_E_in ( Test_enWires[186] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8536 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8537 ) , + .Test_en_W_out ( Test_enWires[183] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8538 ) , + .pReset_S_in ( pResetWires[371] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8539 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8540 ) , + .Reset_E_in ( ResetWires[186] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8541 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8542 ) , + .Reset_W_out ( ResetWires[183] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8543 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8544 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8545 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8546 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8547 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8548 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8549 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8550 ) , + .clk_3_S_in ( clk_3_wires[12] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8551 ) , + .clk_3_N_out ( clk_3_wires[13] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8552 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8553 } ) , + .chany_bottom_in ( sb_1__1__40_chany_top_out ) , + .chany_top_in ( sb_1__1__41_chany_bottom_out ) , + .ccff_head ( grid_clb_44_ccff_tail ) , + .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) , + .chany_top_out ( cby_1__1__44_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__44_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8554 ) , + .Test_en_E_in ( Test_enWires[208] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8555 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8556 ) , + .Test_en_W_out ( Test_enWires[205] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8557 ) , + .pReset_S_in ( pResetWires[420] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8558 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8559 ) , + .Reset_E_in ( ResetWires[208] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8560 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8561 ) , + .Reset_W_out ( ResetWires[205] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8562 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8563 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8564 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8565 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8566 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8567 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8568 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8569 ) , + .clk_3_S_in ( clk_3_wires[18] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8570 ) , + .clk_3_N_out ( clk_3_wires[19] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8571 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8572 } ) , + .chany_bottom_in ( sb_1__1__41_chany_top_out ) , + .chany_top_in ( sb_1__1__42_chany_bottom_out ) , + .ccff_head ( grid_clb_45_ccff_tail ) , + .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) , + .chany_top_out ( cby_1__1__45_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__45_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8573 ) , + .Test_en_E_in ( Test_enWires[230] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8574 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8575 ) , + .Test_en_W_out ( Test_enWires[227] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8576 ) , + .pReset_S_in ( pResetWires[469] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8577 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8578 ) , + .Reset_E_in ( ResetWires[230] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8579 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8580 ) , + .Reset_W_out ( ResetWires[227] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8581 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8582 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8583 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8584 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8585 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8586 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8587 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8588 ) , + .clk_3_S_in ( clk_3_wires[22] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8589 ) , + .clk_3_N_out ( clk_3_wires[23] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8590 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8591 } ) , + .chany_bottom_in ( sb_1__1__42_chany_top_out ) , + .chany_top_in ( sb_1__1__43_chany_bottom_out ) , + .ccff_head ( grid_clb_46_ccff_tail ) , + .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) , + .chany_top_out ( cby_1__1__46_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__46_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8592 ) , + .Test_en_E_in ( Test_enWires[252] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8593 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8594 ) , + .Test_en_W_out ( Test_enWires[249] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8595 ) , + .pReset_S_in ( pResetWires[518] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8596 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8597 ) , + .Reset_E_in ( ResetWires[252] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8598 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8599 ) , + .Reset_W_out ( ResetWires[249] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8600 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8601 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8602 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8604 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8605 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8606 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8608 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8609 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8610 } ) , + .chany_bottom_in ( sb_1__1__43_chany_top_out ) , + .chany_top_in ( sb_1__12__3_chany_bottom_out ) , + .ccff_head ( grid_clb_47_ccff_tail ) , + .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) , + .chany_top_out ( cby_1__1__47_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__47_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8611 ) , + .Test_en_E_in ( Test_enWires[274] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8612 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8613 ) , + .Test_en_W_out ( Test_enWires[271] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8614 ) , + .pReset_S_in ( pResetWires[567] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8615 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8616 ) , + .Reset_E_in ( ResetWires[274] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8617 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8618 ) , + .Reset_W_out ( ResetWires[271] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8619 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8620 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8621 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8622 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8623 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8624 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8626 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8627 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8628 } ) , + .chany_bottom_in ( sb_1__0__4_chany_top_out ) , + .chany_top_in ( sb_1__1__44_chany_bottom_out ) , + .ccff_head ( grid_clb_48_ccff_tail ) , + .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) , + .chany_top_out ( cby_1__1__48_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__48_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8629 ) , + .Test_en_E_in ( Test_enWires[34] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8630 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8631 ) , + .Test_en_W_out ( Test_enWires[31] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8632 ) , + .pReset_S_in ( pResetWires[39] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8633 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8634 ) , + .Reset_E_in ( ResetWires[34] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8635 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8636 ) , + .Reset_W_out ( ResetWires[31] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8637 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8638 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8639 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8640 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8641 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8642 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8643 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8645 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8646 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8647 } ) , + .chany_bottom_in ( sb_1__1__44_chany_top_out ) , + .chany_top_in ( sb_1__1__45_chany_bottom_out ) , + .ccff_head ( grid_clb_49_ccff_tail ) , + .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) , + .chany_top_out ( cby_1__1__49_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__49_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8648 ) , + .Test_en_E_in ( Test_enWires[56] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8649 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8650 ) , + .Test_en_W_out ( Test_enWires[53] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8651 ) , + .pReset_S_in ( pResetWires[81] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8652 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8653 ) , + .Reset_E_in ( ResetWires[56] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8654 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8655 ) , + .Reset_W_out ( ResetWires[53] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8656 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[181] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[182] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8657 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[31] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8658 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8659 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8660 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8661 ) , + .clk_2_N_in ( clk_2_wires[31] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8662 ) , + .clk_2_S_out ( clk_2_wires[32] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8663 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8664 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8665 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8666 } ) , + .chany_bottom_in ( sb_1__1__45_chany_top_out ) , + .chany_top_in ( sb_1__1__46_chany_bottom_out ) , + .ccff_head ( grid_clb_50_ccff_tail ) , + .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) , + .chany_top_out ( cby_1__1__50_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__50_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8667 ) , + .Test_en_E_in ( Test_enWires[78] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8668 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8669 ) , + .Test_en_W_out ( Test_enWires[75] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8670 ) , + .pReset_S_in ( pResetWires[130] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8671 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8672 ) , + .Reset_E_in ( ResetWires[78] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8673 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8674 ) , + .Reset_W_out ( ResetWires[75] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8675 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8676 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8677 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8678 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8679 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8680 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8681 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8683 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8684 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8685 } ) , + .chany_bottom_in ( sb_1__1__46_chany_top_out ) , + .chany_top_in ( sb_1__1__47_chany_bottom_out ) , + .ccff_head ( grid_clb_51_ccff_tail ) , + .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) , + .chany_top_out ( cby_1__1__51_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__51_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8686 ) , + .Test_en_E_in ( Test_enWires[100] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8687 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8688 ) , + .Test_en_W_out ( Test_enWires[97] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8689 ) , + .pReset_S_in ( pResetWires[179] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8690 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8691 ) , + .Reset_E_in ( ResetWires[100] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8692 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8693 ) , + .Reset_W_out ( ResetWires[97] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8694 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[187] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[188] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8695 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[44] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8696 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8697 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8698 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8699 ) , + .clk_2_N_in ( clk_2_wires[44] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8700 ) , + .clk_2_S_out ( clk_2_wires[45] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8701 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8702 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8703 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8704 } ) , + .chany_bottom_in ( sb_1__1__47_chany_top_out ) , + .chany_top_in ( sb_1__1__48_chany_bottom_out ) , + .ccff_head ( grid_clb_52_ccff_tail ) , + .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) , + .chany_top_out ( cby_1__1__52_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__52_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8705 ) , + .Test_en_E_in ( Test_enWires[122] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8706 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8707 ) , + .Test_en_W_out ( Test_enWires[119] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8708 ) , + .pReset_S_in ( pResetWires[228] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8709 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8710 ) , + .Reset_E_in ( ResetWires[122] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8711 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8712 ) , + .Reset_W_out ( ResetWires[119] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8713 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[190] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[191] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8714 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8715 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8716 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8717 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8718 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8719 ) , + .clk_2_S_in ( clk_2_wires[42] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8720 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8721 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8722 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8723 } ) , + .chany_bottom_in ( sb_1__1__48_chany_top_out ) , + .chany_top_in ( sb_1__1__49_chany_bottom_out ) , + .ccff_head ( grid_clb_53_ccff_tail ) , + .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) , + .chany_top_out ( cby_1__1__53_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__53_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8724 ) , + .Test_en_E_in ( Test_enWires[144] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8725 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8726 ) , + .Test_en_W_out ( Test_enWires[141] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8727 ) , + .pReset_S_in ( pResetWires[277] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8728 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8729 ) , + .Reset_E_in ( ResetWires[144] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8730 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8731 ) , + .Reset_W_out ( ResetWires[141] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8732 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8733 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8734 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8735 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8736 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8737 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8738 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8740 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8741 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8742 } ) , + .chany_bottom_in ( sb_1__1__49_chany_top_out ) , + .chany_top_in ( sb_1__1__50_chany_bottom_out ) , + .ccff_head ( grid_clb_54_ccff_tail ) , + .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) , + .chany_top_out ( cby_1__1__54_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__54_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8743 ) , + .Test_en_E_in ( Test_enWires[166] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8744 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8745 ) , + .Test_en_W_out ( Test_enWires[163] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8746 ) , + .pReset_S_in ( pResetWires[326] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8747 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8748 ) , + .Reset_E_in ( ResetWires[166] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8749 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8750 ) , + .Reset_W_out ( ResetWires[163] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8751 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8752 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8753 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8754 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8755 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8756 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8757 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8759 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8760 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8761 } ) , + .chany_bottom_in ( sb_1__1__50_chany_top_out ) , + .chany_top_in ( sb_1__1__51_chany_bottom_out ) , + .ccff_head ( grid_clb_55_ccff_tail ) , + .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) , + .chany_top_out ( cby_1__1__55_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__55_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8762 ) , + .Test_en_E_in ( Test_enWires[188] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8763 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8764 ) , + .Test_en_W_out ( Test_enWires[185] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8765 ) , + .pReset_S_in ( pResetWires[375] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8766 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8767 ) , + .Reset_E_in ( ResetWires[188] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8768 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8769 ) , + .Reset_W_out ( ResetWires[185] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8770 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[199] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[200] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8771 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[57] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8772 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8773 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8774 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8775 ) , + .clk_2_N_in ( clk_2_wires[57] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8776 ) , + .clk_2_S_out ( clk_2_wires[58] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8777 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8778 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8779 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8780 } ) , + .chany_bottom_in ( sb_1__1__51_chany_top_out ) , + .chany_top_in ( sb_1__1__52_chany_bottom_out ) , + .ccff_head ( grid_clb_56_ccff_tail ) , + .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) , + .chany_top_out ( cby_1__1__56_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__56_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8781 ) , + .Test_en_E_in ( Test_enWires[210] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8782 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8783 ) , + .Test_en_W_out ( Test_enWires[207] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8784 ) , + .pReset_S_in ( pResetWires[424] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8785 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8786 ) , + .Reset_E_in ( ResetWires[210] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8787 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8788 ) , + .Reset_W_out ( ResetWires[207] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8789 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[202] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[203] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8790 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8791 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8792 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8793 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8794 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8795 ) , + .clk_2_S_in ( clk_2_wires[55] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8796 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8797 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8798 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8799 } ) , + .chany_bottom_in ( sb_1__1__52_chany_top_out ) , + .chany_top_in ( sb_1__1__53_chany_bottom_out ) , + .ccff_head ( grid_clb_57_ccff_tail ) , + .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) , + .chany_top_out ( cby_1__1__57_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__57_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8800 ) , + .Test_en_E_in ( Test_enWires[232] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8801 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8802 ) , + .Test_en_W_out ( Test_enWires[229] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8803 ) , + .pReset_S_in ( pResetWires[473] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8804 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8805 ) , + .Reset_E_in ( ResetWires[232] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8806 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8807 ) , + .Reset_W_out ( ResetWires[229] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8808 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8809 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8810 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8811 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8812 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8813 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8814 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8816 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8817 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8818 } ) , + .chany_bottom_in ( sb_1__1__53_chany_top_out ) , + .chany_top_in ( sb_1__1__54_chany_bottom_out ) , + .ccff_head ( grid_clb_58_ccff_tail ) , + .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) , + .chany_top_out ( cby_1__1__58_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__58_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8819 ) , + .Test_en_E_in ( Test_enWires[254] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8820 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8821 ) , + .Test_en_W_out ( Test_enWires[251] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8822 ) , + .pReset_S_in ( pResetWires[522] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8823 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8824 ) , + .Reset_E_in ( ResetWires[254] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8825 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8826 ) , + .Reset_W_out ( ResetWires[251] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8827 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[208] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[209] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8828 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8829 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8830 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8831 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8832 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8833 ) , + .clk_2_S_in ( clk_2_wires[66] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8834 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8835 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8836 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8837 } ) , + .chany_bottom_in ( sb_1__1__54_chany_top_out ) , + .chany_top_in ( sb_1__12__4_chany_bottom_out ) , + .ccff_head ( grid_clb_59_ccff_tail ) , + .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) , + .chany_top_out ( cby_1__1__59_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__59_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8838 ) , + .Test_en_E_in ( Test_enWires[276] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8839 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8840 ) , + .Test_en_W_out ( Test_enWires[273] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8841 ) , + .pReset_S_in ( pResetWires[571] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8842 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8843 ) , + .Reset_E_in ( ResetWires[276] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8844 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8845 ) , + .Reset_W_out ( ResetWires[273] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8846 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8847 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8848 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8849 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8850 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8853 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8854 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8855 } ) , + .chany_bottom_in ( sb_1__0__5_chany_top_out ) , + .chany_top_in ( sb_1__1__55_chany_bottom_out ) , + .ccff_head ( grid_clb_60_ccff_tail ) , + .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) , + .chany_top_out ( cby_1__1__60_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__60_ccff_tail ) , + .Test_en_S_in ( Test_enWires[1] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8856 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8857 ) , + .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) , + .Test_en_E_out ( Test_enWires[35] ) , .pReset_S_in ( pResetWires[42] ) , + .pReset_N_out ( pResetWires[2] ) , .Reset_S_in ( ResetWires[1] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8858 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8859 ) , + .Reset_N_out ( ResetWires[2] ) , .Reset_W_out ( ResetWires[33] ) , + .Reset_E_out ( ResetWires[35] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8860 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8861 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8862 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8863 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8864 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8865 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8866 ) , + .clk_3_S_in ( clk_3_wires[90] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8867 ) , + .clk_3_N_out ( clk_3_wires[89] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8868 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8869 } ) , + .chany_bottom_in ( sb_1__1__55_chany_top_out ) , + .chany_top_in ( sb_1__1__56_chany_bottom_out ) , + .ccff_head ( grid_clb_61_ccff_tail ) , + .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) , + .chany_top_out ( cby_1__1__61_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__61_ccff_tail ) , + .Test_en_S_in ( Test_enWires[3] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8870 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8871 ) , + .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) , + .Test_en_E_out ( Test_enWires[57] ) , .pReset_S_in ( pResetWires[85] ) , + .pReset_N_out ( pResetWires[4] ) , .Reset_S_in ( ResetWires[3] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8872 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8873 ) , + .Reset_N_out ( ResetWires[4] ) , .Reset_W_out ( ResetWires[55] ) , + .Reset_E_out ( ResetWires[57] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8874 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8875 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8876 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8877 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8878 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8879 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8880 ) , + .clk_3_S_in ( clk_3_wires[92] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8881 ) , + .clk_3_N_out ( clk_3_wires[91] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8882 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8883 } ) , + .chany_bottom_in ( sb_1__1__56_chany_top_out ) , + .chany_top_in ( sb_1__1__57_chany_bottom_out ) , + .ccff_head ( grid_clb_62_ccff_tail ) , + .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) , + .chany_top_out ( cby_1__1__62_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__62_ccff_tail ) , + .Test_en_S_in ( Test_enWires[5] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8884 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8885 ) , + .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) , + .Test_en_E_out ( Test_enWires[79] ) , .pReset_S_in ( pResetWires[134] ) , + .pReset_N_out ( pResetWires[6] ) , .Reset_S_in ( ResetWires[5] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8886 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8887 ) , + .Reset_N_out ( ResetWires[6] ) , .Reset_W_out ( ResetWires[77] ) , + .Reset_E_out ( ResetWires[79] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8888 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8889 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8891 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8892 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8893 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8894 ) , + .clk_3_S_in ( clk_3_wires[94] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8895 ) , + .clk_3_N_out ( clk_3_wires[93] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8896 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8897 } ) , + .chany_bottom_in ( sb_1__1__57_chany_top_out ) , + .chany_top_in ( sb_1__1__58_chany_bottom_out ) , + .ccff_head ( grid_clb_63_ccff_tail ) , + .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) , + .chany_top_out ( cby_1__1__63_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__63_ccff_tail ) , + .Test_en_S_in ( Test_enWires[7] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8898 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8899 ) , + .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) , + .Test_en_E_out ( Test_enWires[101] ) , .pReset_S_in ( pResetWires[183] ) , + .pReset_N_out ( pResetWires[8] ) , .Reset_S_in ( ResetWires[7] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8900 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8901 ) , + .Reset_N_out ( ResetWires[8] ) , .Reset_W_out ( ResetWires[99] ) , + .Reset_E_out ( ResetWires[101] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8902 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8903 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8904 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8905 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8906 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8907 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8908 ) , + .clk_3_S_in ( clk_3_wires[96] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8909 ) , + .clk_3_N_out ( clk_3_wires[95] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8910 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8911 } ) , + .chany_bottom_in ( sb_1__1__58_chany_top_out ) , + .chany_top_in ( sb_1__1__59_chany_bottom_out ) , + .ccff_head ( grid_clb_64_ccff_tail ) , + .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) , + .chany_top_out ( cby_1__1__64_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__64_ccff_tail ) , + .Test_en_S_in ( Test_enWires[9] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8912 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8913 ) , + .Test_en_N_out ( Test_enWires[10] ) , + .Test_en_W_out ( Test_enWires[121] ) , + .Test_en_E_out ( Test_enWires[123] ) , .pReset_S_in ( pResetWires[232] ) , + .pReset_N_out ( pResetWires[10] ) , .Reset_S_in ( ResetWires[9] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8914 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8915 ) , + .Reset_N_out ( ResetWires[10] ) , .Reset_W_out ( ResetWires[121] ) , + .Reset_E_out ( ResetWires[123] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8916 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8917 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8918 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8919 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8920 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8921 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8922 ) , + .clk_3_S_in ( clk_3_wires[98] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8923 ) , + .clk_3_N_out ( clk_3_wires[97] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8924 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8925 } ) , + .chany_bottom_in ( sb_1__1__59_chany_top_out ) , + .chany_top_in ( sb_1__1__60_chany_bottom_out ) , + .ccff_head ( grid_clb_65_ccff_tail ) , + .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) , + .chany_top_out ( cby_1__1__65_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__65_ccff_tail ) , + .Test_en_S_in ( Test_enWires[11] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8926 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8927 ) , + .Test_en_N_out ( Test_enWires[12] ) , + .Test_en_W_out ( Test_enWires[143] ) , + .Test_en_E_out ( Test_enWires[145] ) , .pReset_S_in ( pResetWires[281] ) , + .pReset_N_out ( pResetWires[12] ) , .Reset_S_in ( ResetWires[11] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8928 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8929 ) , + .Reset_N_out ( ResetWires[12] ) , .Reset_W_out ( ResetWires[143] ) , + .Reset_E_out ( ResetWires[145] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8930 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8931 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8932 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8933 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8934 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8935 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8936 ) , + .clk_3_S_in ( clk_3_wires[100] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8937 ) , + .clk_3_N_out ( clk_3_wires[99] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8938 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8939 } ) , + .chany_bottom_in ( sb_1__1__60_chany_top_out ) , + .chany_top_in ( sb_1__1__61_chany_bottom_out ) , + .ccff_head ( grid_clb_66_ccff_tail ) , + .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) , + .chany_top_out ( cby_1__1__66_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__66_ccff_tail ) , + .Test_en_S_in ( Test_enWires[13] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8940 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8941 ) , + .Test_en_N_out ( Test_enWires[14] ) , + .Test_en_W_out ( Test_enWires[165] ) , + .Test_en_E_out ( Test_enWires[167] ) , .pReset_S_in ( pResetWires[330] ) , + .pReset_N_out ( pResetWires[14] ) , .Reset_S_in ( ResetWires[13] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8942 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8943 ) , + .Reset_N_out ( ResetWires[14] ) , .Reset_W_out ( ResetWires[165] ) , + .Reset_E_out ( ResetWires[167] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8944 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8945 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8946 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8947 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8948 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8949 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8951 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8952 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8953 } ) , + .chany_bottom_in ( sb_1__1__61_chany_top_out ) , + .chany_top_in ( sb_1__1__62_chany_bottom_out ) , + .ccff_head ( grid_clb_67_ccff_tail ) , + .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) , + .chany_top_out ( cby_1__1__67_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__67_ccff_tail ) , + .Test_en_S_in ( Test_enWires[15] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8954 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8955 ) , + .Test_en_N_out ( Test_enWires[16] ) , + .Test_en_W_out ( Test_enWires[187] ) , + .Test_en_E_out ( Test_enWires[189] ) , .pReset_S_in ( pResetWires[379] ) , + .pReset_N_out ( pResetWires[16] ) , .Reset_S_in ( ResetWires[15] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8956 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8957 ) , + .Reset_N_out ( ResetWires[16] ) , .Reset_W_out ( ResetWires[187] ) , + .Reset_E_out ( ResetWires[189] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8958 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8959 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8960 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8961 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8962 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8963 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8965 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8966 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8967 } ) , + .chany_bottom_in ( sb_1__1__62_chany_top_out ) , + .chany_top_in ( sb_1__1__63_chany_bottom_out ) , + .ccff_head ( grid_clb_68_ccff_tail ) , + .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) , + .chany_top_out ( cby_1__1__68_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__68_ccff_tail ) , + .Test_en_S_in ( Test_enWires[17] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8968 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8969 ) , + .Test_en_N_out ( Test_enWires[18] ) , + .Test_en_W_out ( Test_enWires[209] ) , + .Test_en_E_out ( Test_enWires[211] ) , .pReset_S_in ( pResetWires[428] ) , + .pReset_N_out ( pResetWires[18] ) , .Reset_S_in ( ResetWires[17] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8970 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8971 ) , + .Reset_N_out ( ResetWires[18] ) , .Reset_W_out ( ResetWires[209] ) , + .Reset_E_out ( ResetWires[211] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8972 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8973 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8974 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8975 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8976 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8977 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8979 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8980 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8981 } ) , + .chany_bottom_in ( sb_1__1__63_chany_top_out ) , + .chany_top_in ( sb_1__1__64_chany_bottom_out ) , + .ccff_head ( grid_clb_69_ccff_tail ) , + .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) , + .chany_top_out ( cby_1__1__69_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__69_ccff_tail ) , + .Test_en_S_in ( Test_enWires[19] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8982 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8983 ) , + .Test_en_N_out ( Test_enWires[20] ) , + .Test_en_W_out ( Test_enWires[231] ) , + .Test_en_E_out ( Test_enWires[233] ) , .pReset_S_in ( pResetWires[477] ) , + .pReset_N_out ( pResetWires[20] ) , .Reset_S_in ( ResetWires[19] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8984 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8985 ) , + .Reset_N_out ( ResetWires[20] ) , .Reset_W_out ( ResetWires[231] ) , + .Reset_E_out ( ResetWires[233] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8986 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8987 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8988 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8989 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8990 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8991 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8993 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8994 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8995 } ) , + .chany_bottom_in ( sb_1__1__64_chany_top_out ) , + .chany_top_in ( sb_1__1__65_chany_bottom_out ) , + .ccff_head ( grid_clb_70_ccff_tail ) , + .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) , + .chany_top_out ( cby_1__1__70_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__70_ccff_tail ) , + .Test_en_S_in ( Test_enWires[21] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8996 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8997 ) , + .Test_en_N_out ( Test_enWires[22] ) , + .Test_en_W_out ( Test_enWires[253] ) , + .Test_en_E_out ( Test_enWires[255] ) , .pReset_S_in ( pResetWires[526] ) , + .pReset_N_out ( pResetWires[22] ) , .Reset_S_in ( ResetWires[21] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8998 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8999 ) , + .Reset_N_out ( ResetWires[22] ) , .Reset_W_out ( ResetWires[253] ) , + .Reset_E_out ( ResetWires[255] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9000 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9001 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9002 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9003 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9004 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9005 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9007 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9008 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9009 } ) , + .chany_bottom_in ( sb_1__1__65_chany_top_out ) , + .chany_top_in ( sb_1__12__5_chany_bottom_out ) , + .ccff_head ( grid_clb_71_ccff_tail ) , + .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) , + .chany_top_out ( cby_1__1__71_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__71_ccff_tail ) , + .Test_en_S_in ( Test_enWires[23] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9010 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9011 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9012 ) , + .Test_en_W_out ( Test_enWires[275] ) , + .Test_en_E_out ( Test_enWires[277] ) , .pReset_S_in ( pResetWires[575] ) , + .pReset_N_out ( pResetWires[24] ) , .Reset_S_in ( ResetWires[23] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9013 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_9014 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9015 ) , + .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9016 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9017 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9018 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9019 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9020 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9022 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9023 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9024 } ) , + .chany_bottom_in ( sb_1__0__6_chany_top_out ) , + .chany_top_in ( sb_1__1__66_chany_bottom_out ) , + .ccff_head ( grid_clb_72_ccff_tail ) , + .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) , + .chany_top_out ( cby_1__1__72_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__72_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9025 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9026 ) , + .Test_en_W_in ( Test_enWires[36] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9027 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9028 ) , + .Test_en_E_out ( Test_enWires[37] ) , .pReset_S_in ( pResetWires[45] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9029 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9030 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9031 ) , + .Reset_W_in ( ResetWires[36] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9032 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9033 ) , + .Reset_E_out ( ResetWires[37] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9034 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9035 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9036 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9037 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9038 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9039 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9041 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9042 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9043 } ) , + .chany_bottom_in ( sb_1__1__66_chany_top_out ) , + .chany_top_in ( sb_1__1__67_chany_bottom_out ) , + .ccff_head ( grid_clb_73_ccff_tail ) , + .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) , + .chany_top_out ( cby_1__1__73_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__73_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9044 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9045 ) , + .Test_en_W_in ( Test_enWires[58] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9046 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9047 ) , + .Test_en_E_out ( Test_enWires[59] ) , .pReset_S_in ( pResetWires[89] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9048 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9049 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9050 ) , + .Reset_W_in ( ResetWires[58] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9051 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9052 ) , + .Reset_E_out ( ResetWires[59] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[257] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[258] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9053 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[73] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9054 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9055 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9056 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9057 ) , + .clk_2_N_in ( clk_2_wires[73] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9058 ) , + .clk_2_S_out ( clk_2_wires[74] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9059 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9060 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9061 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9062 } ) , + .chany_bottom_in ( sb_1__1__67_chany_top_out ) , + .chany_top_in ( sb_1__1__68_chany_bottom_out ) , + .ccff_head ( grid_clb_74_ccff_tail ) , + .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) , + .chany_top_out ( cby_1__1__74_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__74_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9063 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9064 ) , + .Test_en_W_in ( Test_enWires[80] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9065 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9066 ) , + .Test_en_E_out ( Test_enWires[81] ) , .pReset_S_in ( pResetWires[138] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9067 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9068 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9069 ) , + .Reset_W_in ( ResetWires[80] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9070 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9071 ) , + .Reset_E_out ( ResetWires[81] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9072 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9073 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9074 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9075 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9076 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9077 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9079 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9080 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9081 } ) , + .chany_bottom_in ( sb_1__1__68_chany_top_out ) , + .chany_top_in ( sb_1__1__69_chany_bottom_out ) , + .ccff_head ( grid_clb_75_ccff_tail ) , + .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) , + .chany_top_out ( cby_1__1__75_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__75_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9082 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9083 ) , + .Test_en_W_in ( Test_enWires[102] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9084 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9085 ) , + .Test_en_E_out ( Test_enWires[103] ) , .pReset_S_in ( pResetWires[187] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9086 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9087 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9088 ) , + .Reset_W_in ( ResetWires[102] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9089 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9090 ) , + .Reset_E_out ( ResetWires[103] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[263] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[264] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9091 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[84] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9092 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9093 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9094 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9095 ) , + .clk_2_N_in ( clk_2_wires[84] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9096 ) , + .clk_2_S_out ( clk_2_wires[85] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9097 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9098 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9099 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9100 } ) , + .chany_bottom_in ( sb_1__1__69_chany_top_out ) , + .chany_top_in ( sb_1__1__70_chany_bottom_out ) , + .ccff_head ( grid_clb_76_ccff_tail ) , + .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) , + .chany_top_out ( cby_1__1__76_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__76_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9101 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9102 ) , + .Test_en_W_in ( Test_enWires[124] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9103 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9104 ) , + .Test_en_E_out ( Test_enWires[125] ) , .pReset_S_in ( pResetWires[236] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9105 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9106 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9107 ) , + .Reset_W_in ( ResetWires[124] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9108 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9109 ) , + .Reset_E_out ( ResetWires[125] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[266] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[267] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9110 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9111 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9112 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9113 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9115 ) , + .clk_2_S_in ( clk_2_wires[82] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9116 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9117 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9118 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9119 } ) , + .chany_bottom_in ( sb_1__1__70_chany_top_out ) , + .chany_top_in ( sb_1__1__71_chany_bottom_out ) , + .ccff_head ( grid_clb_77_ccff_tail ) , + .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) , + .chany_top_out ( cby_1__1__77_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__77_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9120 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9121 ) , + .Test_en_W_in ( Test_enWires[146] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9122 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9123 ) , + .Test_en_E_out ( Test_enWires[147] ) , .pReset_S_in ( pResetWires[285] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9124 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9125 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9126 ) , + .Reset_W_in ( ResetWires[146] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9127 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9128 ) , + .Reset_E_out ( ResetWires[147] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9129 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9130 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9131 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9132 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9133 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9134 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9136 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9137 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9138 } ) , + .chany_bottom_in ( sb_1__1__71_chany_top_out ) , + .chany_top_in ( sb_1__1__72_chany_bottom_out ) , + .ccff_head ( grid_clb_78_ccff_tail ) , + .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) , + .chany_top_out ( cby_1__1__78_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__78_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9139 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9140 ) , + .Test_en_W_in ( Test_enWires[168] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9141 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9142 ) , + .Test_en_E_out ( Test_enWires[169] ) , .pReset_S_in ( pResetWires[334] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9143 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9144 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9145 ) , + .Reset_W_in ( ResetWires[168] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9146 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9147 ) , + .Reset_E_out ( ResetWires[169] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9148 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9149 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9150 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9151 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9152 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9153 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9155 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9156 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9157 } ) , + .chany_bottom_in ( sb_1__1__72_chany_top_out ) , + .chany_top_in ( sb_1__1__73_chany_bottom_out ) , + .ccff_head ( grid_clb_79_ccff_tail ) , + .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) , + .chany_top_out ( cby_1__1__79_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__79_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9158 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9159 ) , + .Test_en_W_in ( Test_enWires[190] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9160 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9161 ) , + .Test_en_E_out ( Test_enWires[191] ) , .pReset_S_in ( pResetWires[383] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9162 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9163 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9164 ) , + .Reset_W_in ( ResetWires[190] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9165 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9166 ) , + .Reset_E_out ( ResetWires[191] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[275] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[276] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9167 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[97] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9168 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9169 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9170 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9171 ) , + .clk_2_N_in ( clk_2_wires[97] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9172 ) , + .clk_2_S_out ( clk_2_wires[98] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9173 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9174 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9175 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9176 } ) , + .chany_bottom_in ( sb_1__1__73_chany_top_out ) , + .chany_top_in ( sb_1__1__74_chany_bottom_out ) , + .ccff_head ( grid_clb_80_ccff_tail ) , + .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) , + .chany_top_out ( cby_1__1__80_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__80_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9177 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9178 ) , + .Test_en_W_in ( Test_enWires[212] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9179 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9180 ) , + .Test_en_E_out ( Test_enWires[213] ) , .pReset_S_in ( pResetWires[432] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9181 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9182 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9183 ) , + .Reset_W_in ( ResetWires[212] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9184 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9185 ) , + .Reset_E_out ( ResetWires[213] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[278] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[279] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9186 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9187 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9188 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9189 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9191 ) , + .clk_2_S_in ( clk_2_wires[95] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9192 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9193 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9194 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9195 } ) , + .chany_bottom_in ( sb_1__1__74_chany_top_out ) , + .chany_top_in ( sb_1__1__75_chany_bottom_out ) , + .ccff_head ( grid_clb_81_ccff_tail ) , + .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) , + .chany_top_out ( cby_1__1__81_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__81_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9196 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9197 ) , + .Test_en_W_in ( Test_enWires[234] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9198 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9199 ) , + .Test_en_E_out ( Test_enWires[235] ) , .pReset_S_in ( pResetWires[481] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9200 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9201 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9202 ) , + .Reset_W_in ( ResetWires[234] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9203 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9204 ) , + .Reset_E_out ( ResetWires[235] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9205 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9206 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9207 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9208 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9209 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9210 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9212 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9213 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9214 } ) , + .chany_bottom_in ( sb_1__1__75_chany_top_out ) , + .chany_top_in ( sb_1__1__76_chany_bottom_out ) , + .ccff_head ( grid_clb_82_ccff_tail ) , + .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) , + .chany_top_out ( cby_1__1__82_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__82_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9215 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9216 ) , + .Test_en_W_in ( Test_enWires[256] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9217 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9218 ) , + .Test_en_E_out ( Test_enWires[257] ) , .pReset_S_in ( pResetWires[530] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9219 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9220 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9221 ) , + .Reset_W_in ( ResetWires[256] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9222 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9223 ) , + .Reset_E_out ( ResetWires[257] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[284] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[285] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9224 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9225 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9226 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9227 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9229 ) , + .clk_2_S_in ( clk_2_wires[108] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9230 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9231 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9232 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9233 } ) , + .chany_bottom_in ( sb_1__1__76_chany_top_out ) , + .chany_top_in ( sb_1__12__6_chany_bottom_out ) , + .ccff_head ( grid_clb_83_ccff_tail ) , + .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) , + .chany_top_out ( cby_1__1__83_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__83_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9234 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9235 ) , + .Test_en_W_in ( Test_enWires[278] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9236 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9237 ) , + .Test_en_E_out ( Test_enWires[279] ) , .pReset_S_in ( pResetWires[579] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9238 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9239 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9240 ) , + .Reset_W_in ( ResetWires[278] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9241 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9242 ) , + .Reset_E_out ( ResetWires[279] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9243 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9244 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9245 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9246 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9247 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9249 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9250 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9251 } ) , + .chany_bottom_in ( sb_1__0__7_chany_top_out ) , + .chany_top_in ( sb_1__1__77_chany_bottom_out ) , + .ccff_head ( grid_clb_84_ccff_tail ) , + .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) , + .chany_top_out ( cby_1__1__84_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__84_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9252 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9253 ) , + .Test_en_W_in ( Test_enWires[38] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9254 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9255 ) , + .Test_en_E_out ( Test_enWires[39] ) , .pReset_S_in ( pResetWires[48] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9256 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9257 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9258 ) , + .Reset_W_in ( ResetWires[38] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9259 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9260 ) , + .Reset_E_out ( ResetWires[39] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9261 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9262 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9264 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9265 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9266 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9268 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9269 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9270 } ) , + .chany_bottom_in ( sb_1__1__77_chany_top_out ) , + .chany_top_in ( sb_1__1__78_chany_bottom_out ) , + .ccff_head ( grid_clb_85_ccff_tail ) , + .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) , + .chany_top_out ( cby_1__1__85_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__85_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9272 ) , + .Test_en_W_in ( Test_enWires[60] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9273 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9274 ) , + .Test_en_E_out ( Test_enWires[61] ) , .pReset_S_in ( pResetWires[93] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9275 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9276 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9277 ) , + .Reset_W_in ( ResetWires[60] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9278 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9279 ) , + .Reset_E_out ( ResetWires[61] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9280 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9281 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9282 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9283 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9284 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9285 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9287 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9288 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9289 } ) , + .chany_bottom_in ( sb_1__1__78_chany_top_out ) , + .chany_top_in ( sb_1__1__79_chany_bottom_out ) , + .ccff_head ( grid_clb_86_ccff_tail ) , + .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) , + .chany_top_out ( cby_1__1__86_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__86_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9290 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9291 ) , + .Test_en_W_in ( Test_enWires[82] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9292 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9293 ) , + .Test_en_E_out ( Test_enWires[83] ) , .pReset_S_in ( pResetWires[142] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9294 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9295 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9296 ) , + .Reset_W_in ( ResetWires[82] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9297 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9298 ) , + .Reset_E_out ( ResetWires[83] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9299 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9300 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9301 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9302 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9303 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9304 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9305 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9306 ) , + .clk_3_N_in ( clk_3_wires[42] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , + .clk_3_S_out ( clk_3_wires[43] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9308 } ) , + .chany_bottom_in ( sb_1__1__79_chany_top_out ) , + .chany_top_in ( sb_1__1__80_chany_bottom_out ) , + .ccff_head ( grid_clb_87_ccff_tail ) , + .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) , + .chany_top_out ( cby_1__1__87_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__87_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9309 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9310 ) , + .Test_en_W_in ( Test_enWires[104] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9311 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9312 ) , + .Test_en_E_out ( Test_enWires[105] ) , .pReset_S_in ( pResetWires[191] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9313 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9314 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9315 ) , + .Reset_W_in ( ResetWires[104] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9316 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9317 ) , + .Reset_E_out ( ResetWires[105] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9318 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9319 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9321 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9322 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9323 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9324 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9325 ) , + .clk_3_N_in ( clk_3_wires[38] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9326 ) , + .clk_3_S_out ( clk_3_wires[39] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9327 } ) , + .chany_bottom_in ( sb_1__1__80_chany_top_out ) , + .chany_top_in ( sb_1__1__81_chany_bottom_out ) , + .ccff_head ( grid_clb_88_ccff_tail ) , + .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) , + .chany_top_out ( cby_1__1__88_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__88_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9328 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9329 ) , + .Test_en_W_in ( Test_enWires[126] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9330 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9331 ) , + .Test_en_E_out ( Test_enWires[127] ) , .pReset_S_in ( pResetWires[240] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9332 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9333 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9334 ) , + .Reset_W_in ( ResetWires[126] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9335 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9336 ) , + .Reset_E_out ( ResetWires[127] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9337 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9338 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9339 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9340 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9342 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9344 ) , + .clk_3_N_in ( clk_3_wires[32] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9345 ) , + .clk_3_S_out ( clk_3_wires[33] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9346 } ) , + .chany_bottom_in ( sb_1__1__81_chany_top_out ) , + .chany_top_in ( sb_1__1__82_chany_bottom_out ) , + .ccff_head ( grid_clb_89_ccff_tail ) , + .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) , + .chany_top_out ( cby_1__1__89_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__89_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9347 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9348 ) , + .Test_en_W_in ( Test_enWires[148] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9349 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9350 ) , + .Test_en_E_out ( Test_enWires[149] ) , .pReset_S_in ( pResetWires[289] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9351 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9352 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9353 ) , + .Reset_W_in ( ResetWires[148] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9354 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9355 ) , + .Reset_E_out ( ResetWires[149] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9356 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9357 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9359 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9361 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9362 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9363 ) , + .clk_3_N_in ( clk_3_wires[28] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , + .clk_3_S_out ( clk_3_wires[29] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9365 } ) , + .chany_bottom_in ( sb_1__1__82_chany_top_out ) , + .chany_top_in ( sb_1__1__83_chany_bottom_out ) , + .ccff_head ( grid_clb_90_ccff_tail ) , + .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) , + .chany_top_out ( cby_1__1__90_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__90_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9366 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9367 ) , + .Test_en_W_in ( Test_enWires[170] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9368 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9369 ) , + .Test_en_E_out ( Test_enWires[171] ) , .pReset_S_in ( pResetWires[338] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9370 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9371 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9372 ) , + .Reset_W_in ( ResetWires[170] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9373 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9374 ) , + .Reset_E_out ( ResetWires[171] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9375 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9376 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9378 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9379 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9380 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9381 ) , + .clk_3_S_in ( clk_3_wires[26] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9382 ) , + .clk_3_N_out ( clk_3_wires[27] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9383 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9384 } ) , + .chany_bottom_in ( sb_1__1__83_chany_top_out ) , + .chany_top_in ( sb_1__1__84_chany_bottom_out ) , + .ccff_head ( grid_clb_91_ccff_tail ) , + .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) , + .chany_top_out ( cby_1__1__91_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__91_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9385 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9386 ) , + .Test_en_W_in ( Test_enWires[192] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9387 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9388 ) , + .Test_en_E_out ( Test_enWires[193] ) , .pReset_S_in ( pResetWires[387] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9389 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9390 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9391 ) , + .Reset_W_in ( ResetWires[192] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9392 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9393 ) , + .Reset_E_out ( ResetWires[193] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9394 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9395 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9396 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9397 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9398 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9399 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9400 ) , + .clk_3_S_in ( clk_3_wires[30] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9401 ) , + .clk_3_N_out ( clk_3_wires[31] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9402 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9403 } ) , + .chany_bottom_in ( sb_1__1__84_chany_top_out ) , + .chany_top_in ( sb_1__1__85_chany_bottom_out ) , + .ccff_head ( grid_clb_92_ccff_tail ) , + .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) , + .chany_top_out ( cby_1__1__92_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__92_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9404 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9405 ) , + .Test_en_W_in ( Test_enWires[214] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9406 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9407 ) , + .Test_en_E_out ( Test_enWires[215] ) , .pReset_S_in ( pResetWires[436] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9408 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9409 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9410 ) , + .Reset_W_in ( ResetWires[214] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9411 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9412 ) , + .Reset_E_out ( ResetWires[215] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9413 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9414 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9416 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9417 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9418 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9419 ) , + .clk_3_S_in ( clk_3_wires[36] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9420 ) , + .clk_3_N_out ( clk_3_wires[37] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9421 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9422 } ) , + .chany_bottom_in ( sb_1__1__85_chany_top_out ) , + .chany_top_in ( sb_1__1__86_chany_bottom_out ) , + .ccff_head ( grid_clb_93_ccff_tail ) , + .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) , + .chany_top_out ( cby_1__1__93_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__93_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9423 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9424 ) , + .Test_en_W_in ( Test_enWires[236] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9425 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9426 ) , + .Test_en_E_out ( Test_enWires[237] ) , .pReset_S_in ( pResetWires[485] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9427 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9428 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9429 ) , + .Reset_W_in ( ResetWires[236] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9430 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9431 ) , + .Reset_E_out ( ResetWires[237] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9432 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9433 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9434 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9435 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9436 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9438 ) , + .clk_3_S_in ( clk_3_wires[40] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9439 ) , + .clk_3_N_out ( clk_3_wires[41] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9440 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9441 } ) , + .chany_bottom_in ( sb_1__1__86_chany_top_out ) , + .chany_top_in ( sb_1__1__87_chany_bottom_out ) , + .ccff_head ( grid_clb_94_ccff_tail ) , + .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) , + .chany_top_out ( cby_1__1__94_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__94_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9442 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9443 ) , + .Test_en_W_in ( Test_enWires[258] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9444 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9445 ) , + .Test_en_E_out ( Test_enWires[259] ) , .pReset_S_in ( pResetWires[534] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9446 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9447 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9448 ) , + .Reset_W_in ( ResetWires[258] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9449 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9450 ) , + .Reset_E_out ( ResetWires[259] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9451 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9452 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9453 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9454 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9455 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9456 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9458 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9459 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9460 } ) , + .chany_bottom_in ( sb_1__1__87_chany_top_out ) , + .chany_top_in ( sb_1__12__7_chany_bottom_out ) , + .ccff_head ( grid_clb_95_ccff_tail ) , + .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) , + .chany_top_out ( cby_1__1__95_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__95_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9461 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9462 ) , + .Test_en_W_in ( Test_enWires[280] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9463 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9464 ) , + .Test_en_E_out ( Test_enWires[281] ) , .pReset_S_in ( pResetWires[583] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9465 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9466 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9467 ) , + .Reset_W_in ( ResetWires[280] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9468 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9469 ) , + .Reset_E_out ( ResetWires[281] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9470 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9471 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9472 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9473 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9474 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9476 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9477 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9478 } ) , + .chany_bottom_in ( sb_1__0__8_chany_top_out ) , + .chany_top_in ( sb_1__1__88_chany_bottom_out ) , + .ccff_head ( grid_clb_96_ccff_tail ) , + .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) , + .chany_top_out ( cby_1__1__96_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__96_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9479 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9480 ) , + .Test_en_W_in ( Test_enWires[40] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9481 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9482 ) , + .Test_en_E_out ( Test_enWires[41] ) , .pReset_S_in ( pResetWires[51] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9483 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9484 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9485 ) , + .Reset_W_in ( ResetWires[40] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9486 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9487 ) , + .Reset_E_out ( ResetWires[41] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9488 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9489 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9490 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9491 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9492 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9493 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9495 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9496 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9497 } ) , + .chany_bottom_in ( sb_1__1__88_chany_top_out ) , + .chany_top_in ( sb_1__1__89_chany_bottom_out ) , + .ccff_head ( grid_clb_97_ccff_tail ) , + .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) , + .chany_top_out ( cby_1__1__97_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__97_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9498 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9499 ) , + .Test_en_W_in ( Test_enWires[62] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9500 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9501 ) , + .Test_en_E_out ( Test_enWires[63] ) , .pReset_S_in ( pResetWires[97] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9502 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9503 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9504 ) , + .Reset_W_in ( ResetWires[62] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9505 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9506 ) , + .Reset_E_out ( ResetWires[63] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[333] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[334] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9507 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[75] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9508 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9509 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9510 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9511 ) , + .clk_2_N_in ( clk_2_wires[75] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9512 ) , + .clk_2_S_out ( clk_2_wires[76] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9513 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9514 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9515 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9516 } ) , + .chany_bottom_in ( sb_1__1__89_chany_top_out ) , + .chany_top_in ( sb_1__1__90_chany_bottom_out ) , + .ccff_head ( grid_clb_98_ccff_tail ) , + .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) , + .chany_top_out ( cby_1__1__98_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__98_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9517 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9518 ) , + .Test_en_W_in ( Test_enWires[84] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9519 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9520 ) , + .Test_en_E_out ( Test_enWires[85] ) , .pReset_S_in ( pResetWires[146] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9521 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9522 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9523 ) , + .Reset_W_in ( ResetWires[84] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9524 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9525 ) , + .Reset_E_out ( ResetWires[85] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9526 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9527 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9528 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9529 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9530 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9531 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9534 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9535 } ) , + .chany_bottom_in ( sb_1__1__90_chany_top_out ) , + .chany_top_in ( sb_1__1__91_chany_bottom_out ) , + .ccff_head ( grid_clb_99_ccff_tail ) , + .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) , + .chany_top_out ( cby_1__1__99_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__99_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9536 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9537 ) , + .Test_en_W_in ( Test_enWires[106] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9538 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9539 ) , + .Test_en_E_out ( Test_enWires[107] ) , .pReset_S_in ( pResetWires[195] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9540 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9541 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9542 ) , + .Reset_W_in ( ResetWires[106] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9543 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9544 ) , + .Reset_E_out ( ResetWires[107] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[339] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[340] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9545 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[88] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9546 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9547 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9548 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9549 ) , + .clk_2_N_in ( clk_2_wires[88] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9550 ) , + .clk_2_S_out ( clk_2_wires[89] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9551 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9552 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9553 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9554 } ) , + .chany_bottom_in ( sb_1__1__91_chany_top_out ) , + .chany_top_in ( sb_1__1__92_chany_bottom_out ) , + .ccff_head ( grid_clb_100_ccff_tail ) , + .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) , + .chany_top_out ( cby_1__1__100_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__100_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9555 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9556 ) , + .Test_en_W_in ( Test_enWires[128] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9557 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9558 ) , + .Test_en_E_out ( Test_enWires[129] ) , .pReset_S_in ( pResetWires[244] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9559 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9560 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9561 ) , + .Reset_W_in ( ResetWires[128] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9562 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9563 ) , + .Reset_E_out ( ResetWires[129] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[342] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[343] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9564 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9565 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9566 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9567 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9568 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9569 ) , + .clk_2_S_in ( clk_2_wires[86] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9570 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9571 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9572 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9573 } ) , + .chany_bottom_in ( sb_1__1__92_chany_top_out ) , + .chany_top_in ( sb_1__1__93_chany_bottom_out ) , + .ccff_head ( grid_clb_101_ccff_tail ) , + .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) , + .chany_top_out ( cby_1__1__101_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__101_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9574 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9575 ) , + .Test_en_W_in ( Test_enWires[150] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9576 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9577 ) , + .Test_en_E_out ( Test_enWires[151] ) , .pReset_S_in ( pResetWires[293] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9578 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9579 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9580 ) , + .Reset_W_in ( ResetWires[150] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9581 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9582 ) , + .Reset_E_out ( ResetWires[151] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9583 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9584 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9585 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9586 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9587 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9588 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9590 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9591 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9592 } ) , + .chany_bottom_in ( sb_1__1__93_chany_top_out ) , + .chany_top_in ( sb_1__1__94_chany_bottom_out ) , + .ccff_head ( grid_clb_102_ccff_tail ) , + .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) , + .chany_top_out ( cby_1__1__102_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__102_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9593 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9594 ) , + .Test_en_W_in ( Test_enWires[172] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9595 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9596 ) , + .Test_en_E_out ( Test_enWires[173] ) , .pReset_S_in ( pResetWires[342] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9597 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9598 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9599 ) , + .Reset_W_in ( ResetWires[172] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9600 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9601 ) , + .Reset_E_out ( ResetWires[173] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9602 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9603 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9604 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9605 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9606 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9607 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9609 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9610 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9611 } ) , + .chany_bottom_in ( sb_1__1__94_chany_top_out ) , + .chany_top_in ( sb_1__1__95_chany_bottom_out ) , + .ccff_head ( grid_clb_103_ccff_tail ) , + .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) , + .chany_top_out ( cby_1__1__103_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__103_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9612 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9613 ) , + .Test_en_W_in ( Test_enWires[194] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9614 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9615 ) , + .Test_en_E_out ( Test_enWires[195] ) , .pReset_S_in ( pResetWires[391] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9616 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9617 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9618 ) , + .Reset_W_in ( ResetWires[194] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9619 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9620 ) , + .Reset_E_out ( ResetWires[195] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[351] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[352] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9621 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[101] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9622 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9623 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9624 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9625 ) , + .clk_2_N_in ( clk_2_wires[101] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9626 ) , + .clk_2_S_out ( clk_2_wires[102] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9627 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9628 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9629 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9630 } ) , + .chany_bottom_in ( sb_1__1__95_chany_top_out ) , + .chany_top_in ( sb_1__1__96_chany_bottom_out ) , + .ccff_head ( grid_clb_104_ccff_tail ) , + .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) , + .chany_top_out ( cby_1__1__104_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__104_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9631 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9632 ) , + .Test_en_W_in ( Test_enWires[216] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9633 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9634 ) , + .Test_en_E_out ( Test_enWires[217] ) , .pReset_S_in ( pResetWires[440] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9635 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9636 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9637 ) , + .Reset_W_in ( ResetWires[216] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9638 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9639 ) , + .Reset_E_out ( ResetWires[217] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[354] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[355] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9640 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9641 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9642 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9643 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9644 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9645 ) , + .clk_2_S_in ( clk_2_wires[99] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9646 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9647 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9648 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9649 } ) , + .chany_bottom_in ( sb_1__1__96_chany_top_out ) , + .chany_top_in ( sb_1__1__97_chany_bottom_out ) , + .ccff_head ( grid_clb_105_ccff_tail ) , + .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) , + .chany_top_out ( cby_1__1__105_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__105_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9650 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9651 ) , + .Test_en_W_in ( Test_enWires[238] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9652 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9653 ) , + .Test_en_E_out ( Test_enWires[239] ) , .pReset_S_in ( pResetWires[489] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9654 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9655 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9656 ) , + .Reset_W_in ( ResetWires[238] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9657 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9658 ) , + .Reset_E_out ( ResetWires[239] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9659 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9660 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9661 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9662 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9663 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9664 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9666 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9667 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9668 } ) , + .chany_bottom_in ( sb_1__1__97_chany_top_out ) , + .chany_top_in ( sb_1__1__98_chany_bottom_out ) , + .ccff_head ( grid_clb_106_ccff_tail ) , + .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) , + .chany_top_out ( cby_1__1__106_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__106_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9669 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9670 ) , + .Test_en_W_in ( Test_enWires[260] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9671 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9672 ) , + .Test_en_E_out ( Test_enWires[261] ) , .pReset_S_in ( pResetWires[538] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9673 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9674 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9675 ) , + .Reset_W_in ( ResetWires[260] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9676 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9677 ) , + .Reset_E_out ( ResetWires[261] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[360] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[361] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9678 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9679 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9680 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9682 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9683 ) , + .clk_2_S_in ( clk_2_wires[110] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9684 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9685 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9686 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9687 } ) , + .chany_bottom_in ( sb_1__1__98_chany_top_out ) , + .chany_top_in ( sb_1__12__8_chany_bottom_out ) , + .ccff_head ( grid_clb_107_ccff_tail ) , + .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) , + .chany_top_out ( cby_1__1__107_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__107_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9688 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9689 ) , + .Test_en_W_in ( Test_enWires[282] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9690 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9691 ) , + .Test_en_E_out ( Test_enWires[283] ) , .pReset_S_in ( pResetWires[587] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9692 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9693 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9694 ) , + .Reset_W_in ( ResetWires[282] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9695 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9696 ) , + .Reset_E_out ( ResetWires[283] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9697 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9698 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9699 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9700 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9701 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9704 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9705 } ) , + .chany_bottom_in ( sb_1__0__9_chany_top_out ) , + .chany_top_in ( sb_1__1__99_chany_bottom_out ) , + .ccff_head ( grid_clb_108_ccff_tail ) , + .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) , + .chany_top_out ( cby_1__1__108_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__108_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9706 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9707 ) , + .Test_en_W_in ( Test_enWires[42] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9708 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9709 ) , + .Test_en_E_out ( Test_enWires[43] ) , .pReset_S_in ( pResetWires[54] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9710 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9711 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9712 ) , + .Reset_W_in ( ResetWires[42] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9713 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9714 ) , + .Reset_E_out ( ResetWires[43] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9715 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9716 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9717 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9719 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9720 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9722 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9723 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9724 } ) , + .chany_bottom_in ( sb_1__1__99_chany_top_out ) , + .chany_top_in ( sb_1__1__100_chany_bottom_out ) , + .ccff_head ( grid_clb_109_ccff_tail ) , + .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) , + .chany_top_out ( cby_1__1__109_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__109_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9725 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9726 ) , + .Test_en_W_in ( Test_enWires[64] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9727 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9728 ) , + .Test_en_E_out ( Test_enWires[65] ) , .pReset_S_in ( pResetWires[101] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9729 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9730 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9731 ) , + .Reset_W_in ( ResetWires[64] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9732 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9733 ) , + .Reset_E_out ( ResetWires[65] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9734 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9735 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9736 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9737 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9738 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9739 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9741 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9742 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9743 } ) , + .chany_bottom_in ( sb_1__1__100_chany_top_out ) , + .chany_top_in ( sb_1__1__101_chany_bottom_out ) , + .ccff_head ( grid_clb_110_ccff_tail ) , + .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) , + .chany_top_out ( cby_1__1__110_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__110_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9744 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9745 ) , + .Test_en_W_in ( Test_enWires[86] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9746 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9747 ) , + .Test_en_E_out ( Test_enWires[87] ) , .pReset_S_in ( pResetWires[150] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9748 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9749 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9750 ) , + .Reset_W_in ( ResetWires[86] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9751 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9752 ) , + .Reset_E_out ( ResetWires[87] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9753 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9754 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9755 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9756 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9757 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9758 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9759 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9760 ) , + .clk_3_N_in ( clk_3_wires[86] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9761 ) , + .clk_3_S_out ( clk_3_wires[87] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9762 } ) , + .chany_bottom_in ( sb_1__1__101_chany_top_out ) , + .chany_top_in ( sb_1__1__102_chany_bottom_out ) , + .ccff_head ( grid_clb_111_ccff_tail ) , + .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) , + .chany_top_out ( cby_1__1__111_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__111_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9763 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9764 ) , + .Test_en_W_in ( Test_enWires[108] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9765 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9766 ) , + .Test_en_E_out ( Test_enWires[109] ) , .pReset_S_in ( pResetWires[199] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9767 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9768 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9769 ) , + .Reset_W_in ( ResetWires[108] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9770 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9771 ) , + .Reset_E_out ( ResetWires[109] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9772 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9773 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9775 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9776 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9777 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9778 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9779 ) , + .clk_3_N_in ( clk_3_wires[82] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9780 ) , + .clk_3_S_out ( clk_3_wires[83] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9781 } ) , + .chany_bottom_in ( sb_1__1__102_chany_top_out ) , + .chany_top_in ( sb_1__1__103_chany_bottom_out ) , + .ccff_head ( grid_clb_112_ccff_tail ) , + .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) , + .chany_top_out ( cby_1__1__112_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__112_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9782 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9783 ) , + .Test_en_W_in ( Test_enWires[130] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9784 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9785 ) , + .Test_en_E_out ( Test_enWires[131] ) , .pReset_S_in ( pResetWires[248] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9786 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9787 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9788 ) , + .Reset_W_in ( ResetWires[130] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9789 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9790 ) , + .Reset_E_out ( ResetWires[131] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9791 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9792 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9794 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9797 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9798 ) , + .clk_3_N_in ( clk_3_wires[76] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9799 ) , + .clk_3_S_out ( clk_3_wires[77] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9800 } ) , + .chany_bottom_in ( sb_1__1__103_chany_top_out ) , + .chany_top_in ( sb_1__1__104_chany_bottom_out ) , + .ccff_head ( grid_clb_113_ccff_tail ) , + .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) , + .chany_top_out ( cby_1__1__113_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__113_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9801 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9802 ) , + .Test_en_W_in ( Test_enWires[152] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9803 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9804 ) , + .Test_en_E_out ( Test_enWires[153] ) , .pReset_S_in ( pResetWires[297] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9805 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9806 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9807 ) , + .Reset_W_in ( ResetWires[152] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9808 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9809 ) , + .Reset_E_out ( ResetWires[153] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9810 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9811 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9813 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9814 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9815 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9816 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9817 ) , + .clk_3_N_in ( clk_3_wires[72] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9818 ) , + .clk_3_S_out ( clk_3_wires[73] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9819 } ) , + .chany_bottom_in ( sb_1__1__104_chany_top_out ) , + .chany_top_in ( sb_1__1__105_chany_bottom_out ) , + .ccff_head ( grid_clb_114_ccff_tail ) , + .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) , + .chany_top_out ( cby_1__1__114_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__114_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9820 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9821 ) , + .Test_en_W_in ( Test_enWires[174] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9822 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9823 ) , + .Test_en_E_out ( Test_enWires[175] ) , .pReset_S_in ( pResetWires[346] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9824 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9825 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9826 ) , + .Reset_W_in ( ResetWires[174] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9827 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9828 ) , + .Reset_E_out ( ResetWires[175] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9829 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9830 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9831 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9832 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9833 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9834 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9835 ) , + .clk_3_S_in ( clk_3_wires[70] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9836 ) , + .clk_3_N_out ( clk_3_wires[71] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9837 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9838 } ) , + .chany_bottom_in ( sb_1__1__105_chany_top_out ) , + .chany_top_in ( sb_1__1__106_chany_bottom_out ) , + .ccff_head ( grid_clb_115_ccff_tail ) , + .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) , + .chany_top_out ( cby_1__1__115_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__115_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9839 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9840 ) , + .Test_en_W_in ( Test_enWires[196] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9841 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9842 ) , + .Test_en_E_out ( Test_enWires[197] ) , .pReset_S_in ( pResetWires[395] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9843 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9844 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9845 ) , + .Reset_W_in ( ResetWires[196] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9846 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9847 ) , + .Reset_E_out ( ResetWires[197] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9848 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9849 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9850 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9851 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9852 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9854 ) , + .clk_3_S_in ( clk_3_wires[74] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9855 ) , + .clk_3_N_out ( clk_3_wires[75] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9856 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9857 } ) , + .chany_bottom_in ( sb_1__1__106_chany_top_out ) , + .chany_top_in ( sb_1__1__107_chany_bottom_out ) , + .ccff_head ( grid_clb_116_ccff_tail ) , + .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) , + .chany_top_out ( cby_1__1__116_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__116_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9858 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9859 ) , + .Test_en_W_in ( Test_enWires[218] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9860 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9861 ) , + .Test_en_E_out ( Test_enWires[219] ) , .pReset_S_in ( pResetWires[444] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9862 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9863 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9864 ) , + .Reset_W_in ( ResetWires[218] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9865 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9866 ) , + .Reset_E_out ( ResetWires[219] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9867 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9869 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9870 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9871 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9872 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9873 ) , + .clk_3_S_in ( clk_3_wires[80] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9874 ) , + .clk_3_N_out ( clk_3_wires[81] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9875 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9876 } ) , + .chany_bottom_in ( sb_1__1__107_chany_top_out ) , + .chany_top_in ( sb_1__1__108_chany_bottom_out ) , + .ccff_head ( grid_clb_117_ccff_tail ) , + .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) , + .chany_top_out ( cby_1__1__117_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__117_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9877 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9878 ) , + .Test_en_W_in ( Test_enWires[240] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9879 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9880 ) , + .Test_en_E_out ( Test_enWires[241] ) , .pReset_S_in ( pResetWires[493] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9881 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9882 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9883 ) , + .Reset_W_in ( ResetWires[240] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9884 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9885 ) , + .Reset_E_out ( ResetWires[241] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9886 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9887 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9888 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9889 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9890 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9891 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9892 ) , + .clk_3_S_in ( clk_3_wires[84] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9893 ) , + .clk_3_N_out ( clk_3_wires[85] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9894 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9895 } ) , + .chany_bottom_in ( sb_1__1__108_chany_top_out ) , + .chany_top_in ( sb_1__1__109_chany_bottom_out ) , + .ccff_head ( grid_clb_118_ccff_tail ) , + .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) , + .chany_top_out ( cby_1__1__118_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__118_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9896 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9897 ) , + .Test_en_W_in ( Test_enWires[262] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9898 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9899 ) , + .Test_en_E_out ( Test_enWires[263] ) , .pReset_S_in ( pResetWires[542] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9900 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9901 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9902 ) , + .Reset_W_in ( ResetWires[262] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9903 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9904 ) , + .Reset_E_out ( ResetWires[263] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9905 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9906 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9907 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9908 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9909 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9910 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9913 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9914 } ) , + .chany_bottom_in ( sb_1__1__109_chany_top_out ) , + .chany_top_in ( sb_1__12__9_chany_bottom_out ) , + .ccff_head ( grid_clb_119_ccff_tail ) , + .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) , + .chany_top_out ( cby_1__1__119_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__119_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9915 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9916 ) , + .Test_en_W_in ( Test_enWires[284] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9917 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9918 ) , + .Test_en_E_out ( Test_enWires[285] ) , .pReset_S_in ( pResetWires[591] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9919 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9920 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9921 ) , + .Reset_W_in ( ResetWires[284] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9922 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9923 ) , + .Reset_E_out ( ResetWires[285] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9924 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9925 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9926 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9927 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9928 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9930 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9931 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9932 } ) , + .chany_bottom_in ( sb_1__0__10_chany_top_out ) , + .chany_top_in ( sb_1__1__110_chany_bottom_out ) , + .ccff_head ( grid_clb_120_ccff_tail ) , + .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) , + .chany_top_out ( cby_1__1__120_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__120_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9933 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9934 ) , + .Test_en_W_in ( Test_enWires[44] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9935 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9936 ) , + .Test_en_E_out ( Test_enWires[45] ) , .pReset_S_in ( pResetWires[57] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9937 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9938 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9939 ) , + .Reset_W_in ( ResetWires[44] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9940 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9941 ) , + .Reset_E_out ( ResetWires[45] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9942 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9943 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9944 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9945 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9946 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9947 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9949 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9950 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9951 } ) , + .chany_bottom_in ( sb_1__1__110_chany_top_out ) , + .chany_top_in ( sb_1__1__111_chany_bottom_out ) , + .ccff_head ( grid_clb_121_ccff_tail ) , + .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) , + .chany_top_out ( cby_1__1__121_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__121_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9952 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9953 ) , + .Test_en_W_in ( Test_enWires[66] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9954 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9955 ) , + .Test_en_E_out ( Test_enWires[67] ) , .pReset_S_in ( pResetWires[105] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9956 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9957 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9958 ) , + .Reset_W_in ( ResetWires[66] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9959 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9960 ) , + .Reset_E_out ( ResetWires[67] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[409] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[410] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9961 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[115] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9962 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9963 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9964 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9965 ) , + .clk_2_N_in ( clk_2_wires[115] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9966 ) , + .clk_2_S_out ( clk_2_wires[116] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9967 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9968 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9969 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9970 } ) , + .chany_bottom_in ( sb_1__1__111_chany_top_out ) , + .chany_top_in ( sb_1__1__112_chany_bottom_out ) , + .ccff_head ( grid_clb_122_ccff_tail ) , + .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) , + .chany_top_out ( cby_1__1__122_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__122_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9971 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9972 ) , + .Test_en_W_in ( Test_enWires[88] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9973 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9974 ) , + .Test_en_E_out ( Test_enWires[89] ) , .pReset_S_in ( pResetWires[154] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9975 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9976 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9977 ) , + .Reset_W_in ( ResetWires[88] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9978 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9979 ) , + .Reset_E_out ( ResetWires[89] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9980 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9981 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9982 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9983 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9984 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9985 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9988 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +cby_1__1_ cby_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9989 } ) , + .chany_bottom_in ( sb_1__1__112_chany_top_out ) , + .chany_top_in ( sb_1__1__113_chany_bottom_out ) , + .ccff_head ( grid_clb_123_ccff_tail ) , + .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) , + .chany_top_out ( cby_1__1__123_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__123_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9990 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9991 ) , + .Test_en_W_in ( Test_enWires[110] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9992 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9993 ) , + .Test_en_E_out ( Test_enWires[111] ) , .pReset_S_in ( pResetWires[203] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9994 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9995 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9996 ) , + .Reset_W_in ( ResetWires[110] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9997 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9998 ) , + .Reset_E_out ( ResetWires[111] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[415] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[416] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9999 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[122] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10000 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10001 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10002 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10003 ) , + .clk_2_N_in ( clk_2_wires[122] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10004 ) , + .clk_2_S_out ( clk_2_wires[123] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10005 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10006 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10007 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10008 } ) , + .chany_bottom_in ( sb_1__1__113_chany_top_out ) , + .chany_top_in ( sb_1__1__114_chany_bottom_out ) , + .ccff_head ( grid_clb_124_ccff_tail ) , + .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) , + .chany_top_out ( cby_1__1__124_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__124_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10009 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10010 ) , + .Test_en_W_in ( Test_enWires[132] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10011 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10012 ) , + .Test_en_E_out ( Test_enWires[133] ) , .pReset_S_in ( pResetWires[252] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10013 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10014 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10015 ) , + .Reset_W_in ( ResetWires[132] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10016 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10017 ) , + .Reset_E_out ( ResetWires[133] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[418] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[419] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10018 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10019 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10020 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10021 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10022 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10023 ) , + .clk_2_S_in ( clk_2_wires[120] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10024 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10025 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10026 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10027 } ) , + .chany_bottom_in ( sb_1__1__114_chany_top_out ) , + .chany_top_in ( sb_1__1__115_chany_bottom_out ) , + .ccff_head ( grid_clb_125_ccff_tail ) , + .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) , + .chany_top_out ( cby_1__1__125_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__125_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10028 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10029 ) , + .Test_en_W_in ( Test_enWires[154] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10030 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10031 ) , + .Test_en_E_out ( Test_enWires[155] ) , .pReset_S_in ( pResetWires[301] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10032 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10033 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10034 ) , + .Reset_W_in ( ResetWires[154] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10035 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10036 ) , + .Reset_E_out ( ResetWires[155] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10037 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10038 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10039 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10040 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10041 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10042 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10044 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10045 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10046 } ) , + .chany_bottom_in ( sb_1__1__115_chany_top_out ) , + .chany_top_in ( sb_1__1__116_chany_bottom_out ) , + .ccff_head ( grid_clb_126_ccff_tail ) , + .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) , + .chany_top_out ( cby_1__1__126_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__126_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10047 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10048 ) , + .Test_en_W_in ( Test_enWires[176] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10049 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10050 ) , + .Test_en_E_out ( Test_enWires[177] ) , .pReset_S_in ( pResetWires[350] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10051 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10052 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10053 ) , + .Reset_W_in ( ResetWires[176] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10054 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10055 ) , + .Reset_E_out ( ResetWires[177] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10056 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10057 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10058 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10059 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10060 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10061 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10063 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10064 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10065 } ) , + .chany_bottom_in ( sb_1__1__116_chany_top_out ) , + .chany_top_in ( sb_1__1__117_chany_bottom_out ) , + .ccff_head ( grid_clb_127_ccff_tail ) , + .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) , + .chany_top_out ( cby_1__1__127_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__127_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10066 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10067 ) , + .Test_en_W_in ( Test_enWires[198] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10068 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10069 ) , + .Test_en_E_out ( Test_enWires[199] ) , .pReset_S_in ( pResetWires[399] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10070 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10071 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10072 ) , + .Reset_W_in ( ResetWires[198] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10073 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10074 ) , + .Reset_E_out ( ResetWires[199] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[427] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[428] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10075 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[129] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10076 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10077 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10078 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10079 ) , + .clk_2_N_in ( clk_2_wires[129] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10080 ) , + .clk_2_S_out ( clk_2_wires[130] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10081 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10082 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10083 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10084 } ) , + .chany_bottom_in ( sb_1__1__117_chany_top_out ) , + .chany_top_in ( sb_1__1__118_chany_bottom_out ) , + .ccff_head ( grid_clb_128_ccff_tail ) , + .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) , + .chany_top_out ( cby_1__1__128_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__128_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10085 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10086 ) , + .Test_en_W_in ( Test_enWires[220] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10087 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10088 ) , + .Test_en_E_out ( Test_enWires[221] ) , .pReset_S_in ( pResetWires[448] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10089 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10090 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10091 ) , + .Reset_W_in ( ResetWires[220] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10092 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10093 ) , + .Reset_E_out ( ResetWires[221] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[430] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[431] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10094 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10095 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10096 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10097 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10098 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10099 ) , + .clk_2_S_in ( clk_2_wires[127] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10100 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10101 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10102 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10103 } ) , + .chany_bottom_in ( sb_1__1__118_chany_top_out ) , + .chany_top_in ( sb_1__1__119_chany_bottom_out ) , + .ccff_head ( grid_clb_129_ccff_tail ) , + .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) , + .chany_top_out ( cby_1__1__129_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__129_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10104 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10105 ) , + .Test_en_W_in ( Test_enWires[242] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10106 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10107 ) , + .Test_en_E_out ( Test_enWires[243] ) , .pReset_S_in ( pResetWires[497] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10108 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10109 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10110 ) , + .Reset_W_in ( ResetWires[242] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10111 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10112 ) , + .Reset_E_out ( ResetWires[243] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10113 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10114 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10115 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10117 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10118 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10120 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10121 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10122 } ) , + .chany_bottom_in ( sb_1__1__119_chany_top_out ) , + .chany_top_in ( sb_1__1__120_chany_bottom_out ) , + .ccff_head ( grid_clb_130_ccff_tail ) , + .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) , + .chany_top_out ( cby_1__1__130_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__130_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10123 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10124 ) , + .Test_en_W_in ( Test_enWires[264] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10125 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10126 ) , + .Test_en_E_out ( Test_enWires[265] ) , .pReset_S_in ( pResetWires[546] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10127 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10128 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10129 ) , + .Reset_W_in ( ResetWires[264] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10130 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10131 ) , + .Reset_E_out ( ResetWires[265] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[436] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[437] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10132 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10133 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10134 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10136 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10137 ) , + .clk_2_S_in ( clk_2_wires[134] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10138 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10139 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10140 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_1__1_ cby_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10141 } ) , + .chany_bottom_in ( sb_1__1__120_chany_top_out ) , + .chany_top_in ( sb_1__12__10_chany_bottom_out ) , + .ccff_head ( grid_clb_131_ccff_tail ) , + .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) , + .chany_top_out ( cby_1__1__131_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__131_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10142 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10143 ) , + .Test_en_W_in ( Test_enWires[286] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10144 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10145 ) , + .Test_en_E_out ( Test_enWires[287] ) , .pReset_S_in ( pResetWires[595] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10146 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10147 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10148 ) , + .Reset_W_in ( ResetWires[286] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10149 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10150 ) , + .Reset_E_out ( ResetWires[287] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10151 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10152 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10154 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10155 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10157 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10158 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10159 } ) , + .chany_bottom_in ( sb_12__0__0_chany_top_out ) , + .chany_top_in ( sb_12__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_132_ccff_tail ) , + .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) , + .chany_top_out ( cby_12__1__0_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[60] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[444] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[445] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10160 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) , + .chany_bottom_in ( sb_12__1__0_chany_top_out ) , + .chany_top_in ( sb_12__1__1_chany_bottom_out ) , + .ccff_head ( grid_clb_133_ccff_tail ) , + .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) , + .chany_top_out ( cby_12__1__1_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[109] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[447] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[448] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10163 } ) , + .chany_bottom_in ( sb_12__1__1_chany_top_out ) , + .chany_top_in ( sb_12__1__2_chany_bottom_out ) , + .ccff_head ( grid_clb_134_ccff_tail ) , + .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) , + .chany_top_out ( cby_12__1__2_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[158] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[450] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[451] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10165 } ) , + .chany_bottom_in ( sb_12__1__2_chany_top_out ) , + .chany_top_in ( sb_12__1__3_chany_bottom_out ) , + .ccff_head ( grid_clb_135_ccff_tail ) , + .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) , + .chany_top_out ( cby_12__1__3_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[207] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[453] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[454] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10167 } ) , + .chany_bottom_in ( sb_12__1__3_chany_top_out ) , + .chany_top_in ( sb_12__1__4_chany_bottom_out ) , + .ccff_head ( grid_clb_136_ccff_tail ) , + .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) , + .chany_top_out ( cby_12__1__4_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[256] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[456] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[457] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10169 } ) , + .chany_bottom_in ( sb_12__1__4_chany_top_out ) , + .chany_top_in ( sb_12__1__5_chany_bottom_out ) , + .ccff_head ( grid_clb_137_ccff_tail ) , + .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) , + .chany_top_out ( cby_12__1__5_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[305] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[459] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[460] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10171 } ) , + .chany_bottom_in ( sb_12__1__5_chany_top_out ) , + .chany_top_in ( sb_12__1__6_chany_bottom_out ) , + .ccff_head ( grid_clb_138_ccff_tail ) , + .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) , + .chany_top_out ( cby_12__1__6_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[354] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[462] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[463] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10173 } ) , + .chany_bottom_in ( sb_12__1__6_chany_top_out ) , + .chany_top_in ( sb_12__1__7_chany_bottom_out ) , + .ccff_head ( grid_clb_139_ccff_tail ) , + .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) , + .chany_top_out ( cby_12__1__7_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[403] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[465] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[466] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10175 } ) , + .chany_bottom_in ( sb_12__1__7_chany_top_out ) , + .chany_top_in ( sb_12__1__8_chany_bottom_out ) , + .ccff_head ( grid_clb_140_ccff_tail ) , + .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) , + .chany_top_out ( cby_12__1__8_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[452] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[468] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[469] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10177 } ) , + .chany_bottom_in ( sb_12__1__8_chany_top_out ) , + .chany_top_in ( sb_12__1__9_chany_bottom_out ) , + .ccff_head ( grid_clb_141_ccff_tail ) , + .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) , + .chany_top_out ( cby_12__1__9_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[501] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[471] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[472] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10179 } ) , + .chany_bottom_in ( sb_12__1__9_chany_top_out ) , + .chany_top_in ( sb_12__1__10_chany_bottom_out ) , + .ccff_head ( grid_clb_142_ccff_tail ) , + .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) , + .chany_top_out ( cby_12__1__10_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[550] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[474] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[475] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1_ cby_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10181 } ) , + .chany_bottom_in ( sb_12__1__10_chany_top_out ) , + .chany_top_in ( sb_12__12__0_chany_bottom_out ) , + .ccff_head ( grid_clb_143_ccff_tail ) , + .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) , + .chany_top_out ( cby_12__1__11_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[599] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[477] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[478] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[480] ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , + vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , + wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , + la_data_out , la_oen , io_in , io_out , io_oeb , VDD , VSS , + analog_io_0_ , analog_io_10_ , analog_io_11_ , analog_io_12_ , + analog_io_13_ , analog_io_14_ , analog_io_15_ , analog_io_16_ , + analog_io_17_ , analog_io_18_ , analog_io_19_ , analog_io_1_ , + analog_io_20_ , analog_io_21_ , analog_io_22_ , analog_io_23_ , + analog_io_24_ , analog_io_25_ , analog_io_26_ , analog_io_27_ , + analog_io_28_ , analog_io_29_ , analog_io_2_ , analog_io_30_ , + analog_io_3_ , analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , + analog_io_8_ , analog_io_9_ , user_clock2 ) ; +inout vdda1 ; +inout vdda2 ; +inout vssa1 ; +inout vssa2 ; +inout vccd1 ; +inout vccd2 ; +inout vssd1 ; +inout vssd2 ; +input wb_clk_i ; +input wb_rst_i ; +input wbs_stb_i ; +input wbs_cyc_i ; +input wbs_we_i ; +input [3:0] wbs_sel_i ; +input [31:0] wbs_dat_i ; +input [31:0] wbs_adr_i ; +output wbs_ack_o ; +output [31:0] wbs_dat_o ; +input [127:0] la_data_in ; +output [127:0] la_data_out ; +input [127:0] la_oen ; +input [37:0] io_in ; +output [37:0] io_out ; +output [37:0] io_oeb ; +input VDD ; +input VSS ; +inout analog_io_0_ ; +inout analog_io_10_ ; +inout analog_io_11_ ; +inout analog_io_12_ ; +inout analog_io_13_ ; +inout analog_io_14_ ; +inout analog_io_15_ ; +inout analog_io_16_ ; +inout analog_io_17_ ; +inout analog_io_18_ ; +inout analog_io_19_ ; +inout analog_io_1_ ; +inout analog_io_20_ ; +inout analog_io_21_ ; +inout analog_io_22_ ; +inout analog_io_23_ ; +inout analog_io_24_ ; +inout analog_io_25_ ; +inout analog_io_26_ ; +inout analog_io_27_ ; +inout analog_io_28_ ; +inout analog_io_29_ ; +inout analog_io_2_ ; +inout analog_io_30_ ; +inout analog_io_3_ ; +inout analog_io_4_ ; +inout analog_io_5_ ; +inout analog_io_6_ ; +inout analog_io_7_ ; +inout analog_io_8_ ; +inout analog_io_9_ ; +input user_clock2 ; + +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +wire ccff_head ; +wire sc_tail ; +wire pReset ; +wire Reset ; +wire IO_ISOL_N ; +wire Test_en ; +wire prog_clk ; +wire clk ; +wire ccff_tail ; +wire sc_head ; +wire wb_la_switch ; +supply1 VDD ; +supply0 VSS ; + +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ; +assign ccff_head = io_in[12] ; +assign sc_tail = io_out[11] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ; +assign pReset = io_in[3] ; +assign Reset = io_in[2] ; +assign IO_ISOL_N = io_in[1] ; +assign Test_en = io_in[0] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ; +assign prog_clk = io_in[37] ; +assign clk = io_in[36] ; +assign ccff_tail = io_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ; +assign sc_head = io_in[26] ; +assign wb_la_switch = io_in[25] ; + +sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) , + .Y ( wb_la_switch_b ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[116] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[115] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[114] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[113] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[112] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[111] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[110] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[109] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[108] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[107] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[106] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[105] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[104] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[103] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[102] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[101] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[100] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[99] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[98] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[97] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[96] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[95] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[94] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[93] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[92] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[91] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[90] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[89] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[88] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[87] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[30] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[86] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[31] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[85] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) , + .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) , + .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) , + .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) , + .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) , + .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) , + .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) , + .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) , + .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) , + .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) , + .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) , + .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) , + .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) , + .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) , + .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) , + .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) , + .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) , + .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) , + .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) , + .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) , + .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) , + .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) , + .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) , + .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) , + .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) , + .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) , + .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) , + .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) , + .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) , + .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) , + .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) , + .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) , + .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) , + .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) , + .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) , + .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) , + .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) , + .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) , + .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) , + .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) , + .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) , + .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) , + .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) , + .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) , + .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) , + .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) , + .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) , + .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) , + .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) , + .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) , + .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) , + .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) , + .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) , + .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) , + .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) , + .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) , + .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) , + .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) , + .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) , + .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) , + .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) , + .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) , + .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) , + .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) , + .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) , + .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) , + .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) , + .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) , + .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) , + .A1 ( wbs_we_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) , + .A1 ( wbs_stb_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) , + .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_ack_o ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) , + .A1 ( wb_rst_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) , + .A1 ( wb_clk_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , + .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) , + .Reset ( io_in[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] , + io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] , + io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] , + io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] , + la_data_in[127] , la_data_in[126] , la_data_in[125] , + la_data_in[124] , la_data_in[123] , la_data_in[122] , + la_data_in[121] , la_data_in[120] , la_data_in[119] , + la_data_in[118] , la_data_in[117] , la_data_in[116] , + la_data_in[115] , la_data_in[114] , la_data_in[113] , + la_data_in[112] , la_data_in[111] , la_data_in[110] , + la_data_in[109] , la_data_in[108] , la_data_in[107] , + la_data_in[106] , la_data_in[105] , la_data_in[104] , + la_data_in[103] , la_data_in[102] , la_data_in[101] , + la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] , + la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] , + la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] , + la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] , + io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] , + io_in[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] , + io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] , + io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] , + io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] , + io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] , + la_data_out[125] , la_data_out[124] , la_data_out[123] , + la_data_out[122] , la_data_out[121] , la_data_out[120] , + la_data_out[119] , la_data_out[118] , la_data_out[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] , + la_data_out[83] , la_data_out[82] , la_data_out[81] , + la_data_out[80] , la_data_out[79] , la_data_out[78] , + la_data_out[77] , la_data_out[76] , la_data_out[75] , + la_data_out[74] , la_data_out[73] , la_data_out[72] , + la_data_out[71] , la_data_out[70] , la_data_out[69] , + la_data_out[68] , la_data_out[67] , la_data_out[66] , + la_data_out[65] , la_data_out[64] , la_data_out[63] , + la_data_out[62] , la_data_out[61] , la_data_out[60] , + la_data_out[59] , la_data_out[58] , la_data_out[57] , + la_data_out[56] , la_data_out[55] , la_data_out[54] , + la_data_out[53] , la_data_out[52] , la_data_out[51] , + la_data_out[50] , la_data_out[49] , la_data_out[48] , + la_data_out[47] , la_data_out[46] , la_data_out[45] , + la_data_out[44] , la_data_out[43] , la_data_out[42] , + la_data_out[41] , la_data_out[40] , la_data_out[39] , + la_data_out[38] , la_data_out[37] , la_data_out[36] , + la_data_out[35] , la_data_out[34] , la_data_out[33] , + la_data_out[32] , la_data_out[31] , la_data_out[30] , + la_data_out[29] , la_data_out[28] , la_data_out[27] , + la_data_out[26] , la_data_out[25] , la_data_out[24] , + la_data_out[23] , la_data_out[22] , la_data_out[21] , + la_data_out[20] , la_data_out[19] , la_data_out[18] , + la_data_out[17] , la_data_out[16] , la_data_out[15] , + la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] , + la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] , + io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] , + io_out[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] , + io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] , + io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] , + io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] , + io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] , + io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] , + io_oeb[27] } ) , + .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) , + .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , .VDD ( VDD ) , + .VSS ( VSS ) , .h_incr0 ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( io_oeb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( io_oeb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( io_oeb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( io_oeb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( io_oeb[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( io_oeb[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( io_oeb[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( io_oeb[36] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , + .HI ( io_oeb[37] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) , + .HI ( SYNOPSYS_UNCONNECTED_10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) , + .HI ( SYNOPSYS_UNCONNECTED_11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) , + .HI ( SYNOPSYS_UNCONNECTED_12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) , + .HI ( SYNOPSYS_UNCONNECTED_13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) , + .HI ( SYNOPSYS_UNCONNECTED_14 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) , + .HI ( SYNOPSYS_UNCONNECTED_15 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) , + .HI ( SYNOPSYS_UNCONNECTED_16 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) , + .HI ( SYNOPSYS_UNCONNECTED_17 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) , + .HI ( SYNOPSYS_UNCONNECTED_18 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) , + .HI ( SYNOPSYS_UNCONNECTED_19 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , + .HI ( SYNOPSYS_UNCONNECTED_20 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef new file mode 100644 index 0000000..4fe5c42 --- /dev/null +++ b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:461a20568a95b16ee3befe52cf56fc0a17bb2f4b8f36ee9a34deda5b28a672f0 +size 35397128 diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v new file mode 100644 index 0000000..66c8054 --- /dev/null +++ b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v @@ -0,0 +1,96589 @@ +// +// +// +// +// +// +module cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_103 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1347 ( .A ( ropt_net_114 ) , + .X ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_106 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_103 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_104 ) , + .X ( ropt_net_114 ) ) ; +endmodule + + +module cby_2__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_79 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_79 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_79 ( .A ( BUF_net_81 ) , .Y ( BUF_net_79 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_81 ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_2__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_2__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_2__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_113 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ccff_head[0] ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_98 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_100 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_101 ) , + .X ( ropt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1345 ( .A ( ropt_net_111 ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( ropt_net_112 ) , + .X ( ropt_net_113 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ , + left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ , + left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ , + left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , + left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , + left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , + left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] right_grid_pin_0_ ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] left_width_0_height_0__pin_0_ ; +output [0:0] left_width_0_height_0__pin_1_upper ; +output [0:0] left_width_0_height_0__pin_1_lower ; +input pReset_S_in ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] , + chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_90 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] , + chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] , + chany_bottom_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_92 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_91 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_93 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( left_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_194 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_295 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( left_width_0_height_0__pin_1_lower[0] ) , + .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591232 ( .A ( ctsbuf_net_194 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641237 ( .A ( ctsbuf_net_295 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( mem_out[3] ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , + .X ( copt_net_120 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_130 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( ccff_head[0] ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1349 ( .A ( copt_net_111 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_112 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_116 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , + .X ( copt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , + .X ( copt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_131 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( copt_net_123 ) , + .X ( ropt_net_131 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_103 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ , + left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ , + left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , + left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , + left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in , + Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out , + Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in , + Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in , + prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in , + prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in , + prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in , + clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_16_ ; +output [0:0] left_grid_pin_17_ ; +output [0:0] left_grid_pin_18_ ; +output [0:0] left_grid_pin_19_ ; +output [0:0] left_grid_pin_20_ ; +output [0:0] left_grid_pin_21_ ; +output [0:0] left_grid_pin_22_ ; +output [0:0] left_grid_pin_23_ ; +output [0:0] left_grid_pin_24_ ; +output [0:0] left_grid_pin_25_ ; +output [0:0] left_grid_pin_26_ ; +output [0:0] left_grid_pin_27_ ; +output [0:0] left_grid_pin_28_ ; +output [0:0] left_grid_pin_29_ ; +output [0:0] left_grid_pin_30_ ; +output [0:0] left_grid_pin_31_ ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_N_out ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_S_in ; +output pReset_N_out ; +input Reset_S_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_N_out ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_W_in ; +output prog_clk_0_S_out ; +output prog_clk_0_N_out ; +input prog_clk_2_N_in ; +input prog_clk_2_S_in ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_2_N_in ; +input clk_2_S_in ; +output clk_2_S_out ; +output clk_2_N_out ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign Test_en_E_in = Test_en_S_in ; +assign Test_en_E_in = Test_en_W_in ; +assign Reset_E_in = Reset_S_in ; +assign Reset_E_in = Reset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_2_S_in = prog_clk_2_N_in ; +assign prog_clk_3_N_in = prog_clk_3_S_in ; +assign clk_2_S_in = clk_2_N_in ; +assign clk_3_N_in = clk_3_S_in ; + +cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] , + chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , + chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] , + chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] , + chany_bottom_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] , + chany_bottom_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] , + chany_bottom_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , + chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] , + chany_bottom_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] , + chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( + .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , + chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , + chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] , + chany_bottom_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( + .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , + chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] , + chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] , + chany_bottom_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] , + chany_bottom_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) , + .X ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ; +sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_1109 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , + .X ( ctsbuf_net_2110 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) , + .X ( ZBUF_4_f_0 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) , + .X ( prog_clk_3_S_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) , + .X ( clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) , + .X ( clk_3_S_out ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_21__20 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) , + .X ( prog_clk_2_S_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) , + .X ( prog_clk_2_N_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_78 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_78 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_78 ) , + .X ( copt_net_73 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_73 ) , + .X ( copt_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , + .X ( copt_net_75 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_75 ) , + .X ( copt_net_76 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , + .X ( copt_net_77 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) , + .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) , + .X ( copt_net_67 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) , + .X ( copt_net_68 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , + .X ( copt_net_69 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , + .X ( copt_net_70 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_70 ) , + .X ( copt_net_71 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_71 ) , + .X ( copt_net_72 ) ) ; +endmodule + + +module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head , + chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail , + IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , + right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:29] chany_top_in ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chany_top_out ; +output [0:0] left_grid_pin_0_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] right_width_0_height_0__pin_0_ ; +output [0:0] right_width_0_height_0__pin_1_upper ; +output [0:0] right_width_0_height_0__pin_1_lower ; +input pReset_N_in ; +input prog_clk_0_E_in ; + +wire ropt_net_134 ; +wire ropt_net_128 ; +wire ropt_net_129 ; +wire ropt_net_133 ; +wire ropt_net_127 ; +wire ropt_net_122 ; +wire ropt_net_124 ; +wire ropt_net_132 ; +wire ropt_net_123 ; +wire ropt_net_120 ; +wire ropt_net_138 ; +wire ropt_net_125 ; +wire ropt_net_137 ; +wire ropt_net_121 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; + +assign prog_clk_0 = prog_clk[0] ; + +cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 ( + .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , + chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , + chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] , + chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ; +cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( right_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( right_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( + .A ( right_width_0_height_0__pin_1_lower[0] ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_66 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_120 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_125 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_127 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_132 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[14] ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_108 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_108 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__or2b_4 ISOL_EN_GATE ( .A ( FPGA_DIR ) , .B_N ( IO_ISOL_N ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( BUF_net_83 ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( aps_rename_505_ ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__2__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__2__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__2__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_97 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_95 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +endmodule + + +module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper , + bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT , + SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] top_grid_pin_0_ ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] bottom_width_0_height_0__pin_0_ ; +output [0:0] bottom_width_0_height_0__pin_1_upper ; +output [0:0] bottom_width_0_height_0__pin_1_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] , + chanx_left_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .io_outpad ( bottom_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( bottom_width_0_height_0__pin_1_lower ) , + .ccff_tail ( ccff_tail ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1107 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( bottom_width_0_height_0__pin_1_lower[0] ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_107 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_101 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1327 ( .A ( ccff_head[0] ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1329 ( .A ( copt_net_102 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__buf_1 copt_h_inst_1333 ( .A ( copt_net_103 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_106 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_104 ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_105 ) , + .X ( copt_net_107 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , + REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH , + COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out , + pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out , + prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out , + prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out , + prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out , + clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in , + clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_E_out , clk_3_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input REGIN_FEEDTHROUGH ; +output REGOUT_FEEDTHROUGH ; +input CIN_FEEDTHROUGH ; +output COUT_FEEDTHROUGH ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_S_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; +input prog_clk_1_W_in ; +input prog_clk_1_E_in ; +output prog_clk_1_N_out ; +output prog_clk_1_S_out ; +input prog_clk_2_E_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +input clk_1_W_in ; +input clk_1_E_in ; +output clk_1_N_out ; +output clk_1_S_out ; +input clk_2_E_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +output clk_3_E_out ; +output clk_3_W_out ; + +wire ropt_net_130 ; +wire ropt_net_121 ; +wire ropt_net_132 ; +wire ropt_net_124 ; +wire ropt_net_125 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_E_in = prog_clk_1_W_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_E_in = prog_clk_3_W_in ; +assign clk_1_E_in = clk_1_W_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_E_in = clk_3_W_in ; + +cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_96 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] , + chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] , + chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] , + chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_95 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] , + chanx_left_out[22] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_93 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] , + chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_96 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] , + chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_94 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , + chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] , + chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_94 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_97 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { copt_net_108 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_198 ) ) ; +sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , + .X ( prog_clk_1_S_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , + .X ( prog_clk_3_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_N_out ) ) ; +sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_W_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( ZBUF_39_0 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , + .X ( REGOUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( clk_1_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1345 ( .A ( ZBUF_39_0 ) , + .X ( clk_3_W_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531232 ( .A ( ctsbuf_net_198 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( ropt_net_133 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__buf_2 copt_h_inst_1356 ( .A ( copt_net_108 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_110 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( ropt_net_135 ) , + .X ( copt_net_113 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_125 ) , + .X ( COUT_FEEDTHROUGH ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1377 ( .A ( ropt_net_130 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1379 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1380 ( .A ( copt_net_113 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1381 ( .A ( copt_net_112 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_121 ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1382 ( .A ( ropt_net_134 ) , + .X ( ropt_net_135 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +wire copt_net_113 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_113 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( copt_net_110 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_111 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_113 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_109 ) , + .X ( mem_out[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_898_f_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_898_f_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_898_f_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_898_f_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_898_f_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( ZBUF_898_f_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_208_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_208_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_208_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_208_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_7 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_7 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_7 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__7 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_208_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_208_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_208_0 ( ZBUF_208_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_96 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_96 ( .A ( net_net_96 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_6 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_6 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_6 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__6 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N , ZBUF_217_0 ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; +input ZBUF_217_0 ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( ZBUF_217_0 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( ZBUF_217_0 ) , .Z ( SOC_OUT ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_5 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_5 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_5 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__5 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , ZBUF_217_0 ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input ZBUF_217_0 ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .ZBUF_217_0 ( ZBUF_217_0 ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_95 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( net_net_95 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_4 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_4 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( BUF_net_93 ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( BUF_net_93 ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_94 ) , .Y ( SOC_DIR ) ) ; +sky130_fd_sc_hd__inv_4 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_3 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_3 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_91 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( net_net_91 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_2 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_2 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_90 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_90 ( .A ( net_net_90 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_1 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_1 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , + prog_clk , ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_HD_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +input IO_ISOL_N ; + +sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) , + .B ( IO_ISOL_N ) , .Y ( net_net_89 ) ) ; +sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( SOC_DIR ) , .Y ( SOC_DIR_N ) ) ; +sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , + .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; +sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , + .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( IO_ISOL_N , pReset , + prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , + iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; + +wire [0:0] EMBEDDED_IO_HD_0_en ; + +cbx_1__0__EMBEDDED_IO_HD_0 EMBEDDED_IO_HD_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ; +cbx_1__0__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem_0 EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( IO_ISOL_N , pReset , prog_clk , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail ) ; +input [0:0] IO_ISOL_N ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_7 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_123 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( ccff_head[0] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_116 ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_114 ) , + .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( copt_net_115 ) , + .X ( copt_net_117 ) ) ; +sky130_fd_sc_hd__bufbuf_16 copt_h_inst_1359 ( .A ( ropt_net_124 ) , + .X ( copt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_117 ) , + .X ( copt_net_119 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_118 ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_119 ) , + .X ( ropt_net_124 ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , + bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ , + bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ , + top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower , + top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower , + top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower , + top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower , + top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , + top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , + top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower , + top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower , + top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower , + SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in , + pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in , + prog_clk_0_W_out ) ; +input [0:0] pReset ; +input [0:29] chanx_left_in ; +input [0:29] chanx_right_in ; +input [0:0] ccff_head ; +output [0:29] chanx_left_out ; +output [0:29] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_16_ ; +output [0:0] ccff_tail ; +input [0:0] IO_ISOL_N ; +input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_16_ ; +output [0:0] top_width_0_height_0__pin_1_upper ; +output [0:0] top_width_0_height_0__pin_1_lower ; +output [0:0] top_width_0_height_0__pin_3_upper ; +output [0:0] top_width_0_height_0__pin_3_lower ; +output [0:0] top_width_0_height_0__pin_5_upper ; +output [0:0] top_width_0_height_0__pin_5_lower ; +output [0:0] top_width_0_height_0__pin_7_upper ; +output [0:0] top_width_0_height_0__pin_7_lower ; +output [0:0] top_width_0_height_0__pin_9_upper ; +output [0:0] top_width_0_height_0__pin_9_lower ; +output [0:0] top_width_0_height_0__pin_11_upper ; +output [0:0] top_width_0_height_0__pin_11_lower ; +output [0:0] top_width_0_height_0__pin_13_upper ; +output [0:0] top_width_0_height_0__pin_13_lower ; +output [0:0] top_width_0_height_0__pin_15_upper ; +output [0:0] top_width_0_height_0__pin_15_lower ; +output [0:0] top_width_0_height_0__pin_17_upper ; +output [0:0] top_width_0_height_0__pin_17_lower ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_N_in ; +output prog_clk_0_W_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:3] mux_tree_tapbuf_size12_8_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__0_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__1_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__2_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__3_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__4_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__5_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__6_ccff_tail ; +wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; + +assign pReset_W_in = pReset_E_in ; +assign prog_clk_0 = prog_clk[0] ; + +cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , + chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] , + chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , + chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] , + chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , + chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] , + chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 ( + .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , + chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , + chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] , + chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 ( + .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , + chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , + chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] , + chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 ( + .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , + chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , + chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] , + chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) , + .sram ( mux_tree_tapbuf_size12_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( { ccff_tail_mid } ) , + .mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ; +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .io_outpad ( top_width_0_height_0__pin_0_ ) , + .ccff_head ( { ccff_tail_mid } ) , + .io_inpad ( top_width_0_height_0__pin_1_lower ) , + .ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .io_outpad ( top_width_0_height_0__pin_2_ ) , + .ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_3_lower ) , + .ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .io_outpad ( top_width_0_height_0__pin_4_ ) , + .ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_5_lower ) , + .ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .io_outpad ( top_width_0_height_0__pin_6_ ) , + .ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_7_lower ) , + .ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .io_outpad ( top_width_0_height_0__pin_8_ ) , + .ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_9_lower ) , + .ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) , + .io_outpad ( top_width_0_height_0__pin_10_ ) , + .ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_11_lower ) , + .ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) , + .ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .io_outpad ( top_width_0_height_0__pin_12_ ) , + .ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_13_lower ) , + .ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ; +cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) , + .io_outpad ( top_width_0_height_0__pin_14_ ) , + .ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_15_lower ) , + .ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) , + .ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 ( + .IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) , + .io_outpad ( top_width_0_height_0__pin_16_ ) , + .ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) , + .io_inpad ( top_width_0_height_0__pin_17_lower ) , + .ccff_tail ( ccff_tail ) , + .ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , + .X ( ctsbuf_net_1106 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_12 FTB_39__38 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[22] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( + .A ( top_width_0_height_0__pin_1_lower[0] ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( + .A ( top_width_0_height_0__pin_3_lower[0] ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( + .A ( top_width_0_height_0__pin_5_lower[0] ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_82__81 ( + .A ( top_width_0_height_0__pin_7_lower[0] ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_83__82 ( + .A ( top_width_0_height_0__pin_9_lower[0] ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_84__83 ( + .A ( top_width_0_height_0__pin_11_lower[0] ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_85__84 ( + .A ( top_width_0_height_0__pin_13_lower[0] ) , + .X ( top_width_0_height_0__pin_13_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_86__85 ( + .A ( top_width_0_height_0__pin_15_lower[0] ) , + .X ( top_width_0_height_0__pin_15_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_87__86 ( + .A ( top_width_0_height_0__pin_17_lower[0] ) , + .X ( top_width_0_height_0__pin_17_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) , + .X ( prog_clk_0_W_out ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_172 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_172 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_172 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_35 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_150 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_150 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_146 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_104 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_102 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_207 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_166 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( ccff_head[0] ) , + .X ( copt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_161 ) , + .X ( copt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_162 ) , + .X ( copt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_163 ) , + .X ( copt_net_165 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_164 ) , + .X ( copt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1378 ( .A ( copt_net_165 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_205 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( ropt_net_203 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_204 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1382 ( .A ( ropt_net_206 ) , + .X ( ropt_net_207 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_144 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_144 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_68 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_2__2_ ( pReset , chany_bottom_in , bottom_right_grid_pin_1_ , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_bottom_out , chanx_left_out , + ccff_tail , SC_IN_BOT , SC_OUT_BOT , pReset_W_in , prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_W_in ; +input prog_clk_0_S_in ; + +wire ropt_net_182 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_36_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_35_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( + .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( + .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( + .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( + .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( + .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( + .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( + .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( + .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( + .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( + .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( + .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( + .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( + .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( + .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( + .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( + .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( + .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( + .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( + .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( + .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( + .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( + .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( + .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( + .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( + .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( + .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( + .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( + .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( + .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( + .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( + .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( + .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_36_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_bottom_track_51 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_23 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_24 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_25 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_26 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_27 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_28 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_29 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_30 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_31 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_32 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_33 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_34 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_35 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_35_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_36_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[15] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_155 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( + .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_154 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( + .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[19] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_124 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_125 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_126 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[29] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_109 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_166 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_149 ) , + .X ( copt_net_145 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_148 ) , + .X ( copt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , + .X ( copt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_168 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1337 ( .A ( copt_net_150 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( copt_net_158 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1339 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_93 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_91 ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_2__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chany_bottom_in , + bottom_right_grid_pin_1_ , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chany_bottom_out , + chanx_left_out , ccff_tail , pReset_W_in , pReset_N_out , + prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_right_grid_pin_1_ ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__1__mux_tree_tapbuf_size8_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_1 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[12] , + chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_2 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[2] , chanx_left_in[13] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[3] , chanx_left_in[14] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_2 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chany_top_out[7] , chany_top_out[21] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chany_top_out[8] , chany_top_out[23] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 , + SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chany_top_out[12] , chany_top_out[27] , chanx_left_in[6] , + chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 , + SYNOPSYS_UNCONNECTED_25 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[5] , + chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , + SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , + chany_top_out[15] , chany_top_out[29] , chanx_left_in[4] , + chanx_left_in[15] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_5 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[6] , chanx_left_in[17] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[7] , chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 , + SYNOPSYS_UNCONNECTED_37 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem mem_bottom_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + top_right_grid_pin_1_[0] , chany_top_out[9] , chany_top_out[24] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , + SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chany_top_out[11] , chany_top_out[25] , chanx_left_in[7] , + chanx_left_in[18] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , + SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chany_top_out[16] , chanx_left_in[3] , + chanx_left_in[14] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , + SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chany_top_out[17] , chanx_left_in[2] , + chanx_left_in[13] , chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chany_top_out[19] , chanx_left_in[1] , + chanx_left_in[12] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , bottom_left_grid_pin_48_[0] , + chanx_left_in[0] , chanx_left_in[11] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_4 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_in[1] , chany_top_out[8] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size5 mux_left_track_11 ( + .in ( { chany_bottom_out[12] , chany_bottom_in[5] , chany_top_out[12] , + left_bottom_grid_pin_38_[0] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem_4 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size5_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size10 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , + bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[4] , chanx_left_in[15] , + chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[8] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 , + SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_top_out[4] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 , + SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_2 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_in[0] , chany_top_out[7] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 , + SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_in[2] , chany_top_out[9] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( + .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 , + SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_2 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem_3 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , bottom_left_grid_pin_46_[0] , + chanx_left_in[9] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 , + SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , bottom_left_grid_pin_47_[0] , + chanx_left_in[10] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 , + SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_13 ( + .in ( { chany_bottom_out[13] , chany_bottom_in[9] , chany_top_out[13] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_3 mux_left_track_15 ( + .in ( { chany_bottom_out[15] , chany_bottom_in[13] , chany_top_out[15] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 , + SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_4 mux_left_track_17 ( + .in ( { chany_bottom_out[16] , chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 , + SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_5 mux_left_track_19 ( + .in ( { chany_bottom_out[17] , chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 , + SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_6 mux_left_track_21 ( + .in ( { chany_bottom_out[19] , chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_23 ( + .in ( { chany_bottom_out[20] , chany_top_out[20] , chany_bottom_in[29] , + chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_3 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_4 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_5 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem_6 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_25 ( + .in ( { chany_bottom_out[21] , chany_top_out[21] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_27 ( + .in ( { chany_bottom_out[23] , chany_top_out[23] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_29 ( + .in ( { chany_bottom_out[24] , chany_top_out[24] , + left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_31 ( + .in ( { chany_bottom_out[25] , chany_top_out[25] , + left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_4 mux_left_track_33 ( + .in ( { chany_bottom_out[27] , chany_top_out[27] , + left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_5 mux_left_track_35 ( + .in ( { chany_bottom_out[28] , chany_top_out[28] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_6 mux_left_track_37 ( + .in ( { chany_bottom_out[29] , chany_top_out[29] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_51 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_142 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_4 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_5 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_6 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_41 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_45 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_36_[0] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_47 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_37_[0] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_49 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_141 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_53 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_5 mux_left_track_55 ( + .in ( { chany_top_in[4] , chanx_left_out[19] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_137 , SYNOPSYS_UNCONNECTED_138 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_139 , SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_140 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_5 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_N_FTB01 ( .A ( pReset_W_in ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[25] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( left_bottom_grid_pin_41_[0] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , + .HI ( optlc_net_144 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_164 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_164 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_142 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_148 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_33 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_32 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_31 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_140 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_138 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_136 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_146 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_132 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_128 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_81 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_126 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_124 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_156 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_158 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( ccff_head[0] ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( ropt_net_192 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_157 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1393 ( .A ( ropt_net_196 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1394 ( .A ( copt_net_159 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_194 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1397 ( .A ( ropt_net_195 ) , + .X ( ropt_net_196 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_122 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_72 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_70 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_68 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_144 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out , + ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:0] top_right_grid_pin_1_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input pReset_W_in ; +output pReset_N_out ; +input prog_clk_0_N_in ; + +wire ropt_net_174 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_27_sram ; +wire [0:1] mux_tree_tapbuf_size2_28_sram ; +wire [0:1] mux_tree_tapbuf_size2_29_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_30_sram ; +wire [0:1] mux_tree_tapbuf_size2_31_sram ; +wire [0:1] mux_tree_tapbuf_size2_32_sram ; +wire [0:1] mux_tree_tapbuf_size2_33_sram ; +wire [0:1] mux_tree_tapbuf_size2_34_sram ; +wire [0:1] mux_tree_tapbuf_size2_35_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( + .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( + .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( + .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( + .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( + .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[24] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , + chanx_left_in[8] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( + .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( + .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( + .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( + .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( + .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( + .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( + .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( + .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( + .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( + .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( + .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( + .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( + .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( + .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( + .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_151 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( + .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( + .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( + .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_27_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( + .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_28_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( + .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_29_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_152 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( + .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_30_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( + .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_31_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_153 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( + .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_32_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( + .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_33_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( + .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_34_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( + .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_35_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_150 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( pReset_W_in ) , .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1337 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[29] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_135 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_104 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_146 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_146 ) , + .X ( copt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_147 ) , + .X ( copt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_150 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_148 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_149 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_151 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_182 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_183 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_184 ) , + .X ( ropt_net_185 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ , + bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ , + bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ , + bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in , + left_top_grid_pin_1_ , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT , + pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out , + prog_clk_0_S_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_top_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_BOT ; +output SC_OUT_BOT ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_W_out ; +output pReset_E_out ; +input prog_clk_0_S_in ; + +wire ropt_net_167 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; + +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[9] , + chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , + chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , + chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( + .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , + chany_bottom_in[21] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( + .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , + chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( + .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , + chany_bottom_in[16] , chany_bottom_in[27] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[7] , + chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( + .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , + SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( + .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , + SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[6] , + chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( + .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , + left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , + SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , + SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , + chany_bottom_in[14] , chany_bottom_in[25] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , + chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , + chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( + .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( + .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_49_[0] , chanx_right_out[12] , + chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( + .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , + chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] , + chany_bottom_in[21] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , + SYNOPSYS_UNCONNECTED_73 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( + .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , + chanx_right_out[13] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , + SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( + .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , + chanx_right_out[15] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( + .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , + chanx_right_out[16] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , + SYNOPSYS_UNCONNECTED_82 } ) , + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , + chanx_right_out[17] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , + SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( + .in ( { chanx_left_out[29] , chanx_right_in[29] , + bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , + SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( + .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( + .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , + SYNOPSYS_UNCONNECTED_94 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[1] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , + SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( + .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[2] , chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , + SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( + .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , + bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( + .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , + SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( + .in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( + .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( + .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( + .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( + .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( + .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( + .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( + .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( + .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( + .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_139 ) ) ; +sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( net_net_139 ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_505_ ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1349 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[29] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_150 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_148 ( .A ( BUF_net_149 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_149 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_149 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_146 ( .A ( BUF_net_147 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_147 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_147 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_154 ( .A ( BUF_net_155 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_155 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_155 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_141 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_140 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_138 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_136 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:11] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_134 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_128 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_152 ( .A ( BUF_net_153 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_153 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_153 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_176 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_172 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ropt_net_179 ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_173 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , + .X ( copt_net_176 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ccff_head[0] ) , + .X ( ropt_net_179 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_124 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .Y ( BUF_net_121 ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:10] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[10] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +endmodule + + +module sb_1__1_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_36_ , + right_bottom_grid_pin_37_ , right_bottom_grid_pin_38_ , + right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , + right_bottom_grid_pin_41_ , right_bottom_grid_pin_42_ , + right_bottom_grid_pin_43_ , chany_bottom_in , bottom_left_grid_pin_44_ , + bottom_left_grid_pin_45_ , bottom_left_grid_pin_46_ , + bottom_left_grid_pin_47_ , bottom_left_grid_pin_48_ , + bottom_left_grid_pin_49_ , bottom_left_grid_pin_50_ , + bottom_left_grid_pin_51_ , chanx_left_in , left_bottom_grid_pin_36_ , + left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , + left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , + left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ , + left_bottom_grid_pin_43_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , chanx_left_out , ccff_tail , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_1_N_in , prog_clk_1_S_in , prog_clk_1_E_out , prog_clk_1_W_out , + prog_clk_2_N_in , prog_clk_2_E_in , prog_clk_2_S_in , prog_clk_2_W_in , + prog_clk_2_W_out , prog_clk_2_S_out , prog_clk_2_N_out , + prog_clk_2_E_out , prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_S_in , + prog_clk_3_N_in , prog_clk_3_E_out , prog_clk_3_W_out , prog_clk_3_N_out , + prog_clk_3_S_out , clk_1_N_in , clk_1_S_in , clk_1_E_out , clk_1_W_out , + clk_2_N_in , clk_2_E_in , clk_2_S_in , clk_2_W_in , clk_2_W_out , + clk_2_S_out , clk_2_N_out , clk_2_E_out , clk_3_W_in , clk_3_E_in , + clk_3_S_in , clk_3_N_in , clk_3_E_out , clk_3_W_out , clk_3_N_out , + clk_3_S_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_44_ ; +input [0:0] bottom_left_grid_pin_45_ ; +input [0:0] bottom_left_grid_pin_46_ ; +input [0:0] bottom_left_grid_pin_47_ ; +input [0:0] bottom_left_grid_pin_48_ ; +input [0:0] bottom_left_grid_pin_49_ ; +input [0:0] bottom_left_grid_pin_50_ ; +input [0:0] bottom_left_grid_pin_51_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_36_ ; +input [0:0] left_bottom_grid_pin_37_ ; +input [0:0] left_bottom_grid_pin_38_ ; +input [0:0] left_bottom_grid_pin_39_ ; +input [0:0] left_bottom_grid_pin_40_ ; +input [0:0] left_bottom_grid_pin_41_ ; +input [0:0] left_bottom_grid_pin_42_ ; +input [0:0] left_bottom_grid_pin_43_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_1_N_in ; +input prog_clk_1_S_in ; +output prog_clk_1_E_out ; +output prog_clk_1_W_out ; +input prog_clk_2_N_in ; +input prog_clk_2_E_in ; +input prog_clk_2_S_in ; +input prog_clk_2_W_in ; +output prog_clk_2_W_out ; +output prog_clk_2_S_out ; +output prog_clk_2_N_out ; +output prog_clk_2_E_out ; +input prog_clk_3_W_in ; +input prog_clk_3_E_in ; +input prog_clk_3_S_in ; +input prog_clk_3_N_in ; +output prog_clk_3_E_out ; +output prog_clk_3_W_out ; +output prog_clk_3_N_out ; +output prog_clk_3_S_out ; +input clk_1_N_in ; +input clk_1_S_in ; +output clk_1_E_out ; +output clk_1_W_out ; +input clk_2_N_in ; +input clk_2_E_in ; +input clk_2_S_in ; +input clk_2_W_in ; +output clk_2_W_out ; +output clk_2_S_out ; +output clk_2_N_out ; +output clk_2_E_out ; +input clk_3_W_in ; +input clk_3_E_in ; +input clk_3_S_in ; +input clk_3_N_in ; +output clk_3_E_out ; +output clk_3_W_out ; +output clk_3_N_out ; +output clk_3_S_out ; + +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_10_sram ; +wire [0:3] mux_tree_tapbuf_size10_11_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_8_sram ; +wire [0:3] mux_tree_tapbuf_size10_9_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size11_0_sram ; +wire [0:3] mux_tree_tapbuf_size11_1_sram ; +wire [0:3] mux_tree_tapbuf_size11_2_sram ; +wire [0:3] mux_tree_tapbuf_size11_3_sram ; +wire [0:3] mux_tree_tapbuf_size11_4_sram ; +wire [0:3] mux_tree_tapbuf_size11_5_sram ; +wire [0:3] mux_tree_tapbuf_size11_6_sram ; +wire [0:3] mux_tree_tapbuf_size11_7_sram ; +wire [0:0] mux_tree_tapbuf_size11_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size11_mem_7_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size12_0_sram ; +wire [0:3] mux_tree_tapbuf_size12_1_sram ; +wire [0:3] mux_tree_tapbuf_size12_2_sram ; +wire [0:3] mux_tree_tapbuf_size12_3_sram ; +wire [0:3] mux_tree_tapbuf_size12_4_sram ; +wire [0:3] mux_tree_tapbuf_size12_5_sram ; +wire [0:3] mux_tree_tapbuf_size12_6_sram ; +wire [0:3] mux_tree_tapbuf_size12_7_sram ; +wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_10_sram ; +wire [0:2] mux_tree_tapbuf_size6_11_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:2] mux_tree_tapbuf_size6_8_sram ; +wire [0:2] mux_tree_tapbuf_size6_9_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:3] mux_tree_tapbuf_size9_3_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_3_ccff_tail ; + +assign prog_clk_1_E_out = prog_clk_1_S_in ; +assign prog_clk_1_W_out = prog_clk_1_S_in ; +assign prog_clk_2_W_out = prog_clk_2_E_in ; +assign prog_clk_2_S_out = prog_clk_2_E_in ; +assign prog_clk_2_N_out = prog_clk_2_E_in ; +assign prog_clk_2_E_out = prog_clk_2_E_in ; +assign prog_clk_3_E_out = prog_clk_3_E_in ; +assign prog_clk_3_W_out = prog_clk_3_E_in ; +assign prog_clk_3_N_out = prog_clk_3_E_in ; +assign prog_clk_3_S_out = prog_clk_3_E_in ; +assign clk_1_E_out = clk_1_S_in ; +assign clk_1_W_out = clk_1_S_in ; +assign clk_2_W_out = clk_2_E_in ; +assign clk_2_S_out = clk_2_E_in ; +assign clk_2_N_out = clk_2_E_in ; +assign clk_2_E_out = clk_2_E_in ; +assign clk_3_E_out = clk_3_E_in ; +assign clk_3_W_out = clk_3_E_in ; +assign clk_3_N_out = clk_3_E_in ; +assign clk_3_S_out = clk_3_E_in ; +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; +assign prog_clk_1_S_in = prog_clk_1_N_in ; +assign prog_clk_2_E_in = prog_clk_2_N_in ; +assign prog_clk_2_E_in = prog_clk_2_S_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_E_in = prog_clk_3_W_in ; +assign prog_clk_3_E_in = prog_clk_3_S_in ; +assign prog_clk_3_E_in = prog_clk_3_N_in ; +assign clk_1_S_in = clk_1_N_in ; +assign clk_2_E_in = clk_2_N_in ; +assign clk_2_E_in = clk_2_S_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_E_in = clk_3_W_in ; +assign clk_3_E_in = clk_3_S_in ; +assign clk_3_E_in = clk_3_N_in ; + +sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_out[20] , chany_top_out[4] , chany_top_out[20] , + chanx_left_in[0] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_1 mux_top_track_2 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_left_out[21] , chany_top_out[7] , chany_top_out[21] , + chanx_right_out[7] , chanx_right_out[21] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size11_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_2 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[4] , chany_top_out[20] , + chany_bottom_in[25] , chanx_right_out[4] , chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , chany_bottom_out[21] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] , chany_top_out[21] , + chany_bottom_in[21] , chanx_right_out[7] , chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_4 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_left_out[4] , + chanx_left_out[20] , chanx_right_in[25] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_50_[0] , chanx_left_in[1] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size11_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , + SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_5 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_left_out[7] , + chanx_left_out[21] , chanx_right_in[21] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , + bottom_left_grid_pin_51_[0] , chanx_left_in[2] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size11_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , + SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_6 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_bottom_out[4] , chany_bottom_out[20] , + chanx_left_out[4] , chanx_left_out[20] , chany_top_out[4] , + chany_top_out[20] , chany_bottom_in[29] , + left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size11_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11 mux_left_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chany_top_in[29] , + chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , + chany_top_out[7] , chany_top_out[21] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size11_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , + SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_1 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_2 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_4 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_5 mem_bottom_track_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem_6 mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size11_mem mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size11_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_left_out[23] , + chany_top_out[8] , chany_top_out[23] , chanx_right_out[8] , + chanx_right_out[23] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , + SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_50_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_left_out[27] , + chany_top_out[12] , chany_top_out[27] , chanx_right_out[12] , + chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_top_track_20 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_51_[0] , + chanx_left_out[13] , chanx_right_in[17] , chanx_left_out[28] , + chany_top_out[13] , chany_top_out[28] , chanx_left_in[9] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , + SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , chany_bottom_out[23] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] , chany_bottom_in[17] , chany_top_out[23] , + chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , + SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_right_track_12 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , chany_bottom_out[27] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , + chany_bottom_in[5] , chany_top_out[12] , chany_top_out[27] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_right_track_20 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] , chany_top_out[13] , chany_top_out[28] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_left_out[8] , + chanx_right_in[17] , chanx_left_out[23] , + bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , + chanx_left_in[4] , chanx_right_out[8] , chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , + SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[5] , + chanx_left_out[12] , chanx_left_out[27] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_50_[0] , + chanx_right_out[12] , chanx_left_in[13] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[4] , + chanx_left_out[13] , chanx_left_out[28] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_51_[0] , + chanx_right_out[13] , chanx_left_in[17] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size10_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chany_top_in[25] , + chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , + chany_top_out[8] , chany_top_out[23] , left_bottom_grid_pin_38_[0] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size10_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , + SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( { ropt_net_180 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( + .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , + chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , + chany_top_out[12] , chany_top_out[27] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size10_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size10 mux_left_track_21 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , chany_bottom_out[28] , + chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[9] , + chany_top_out[13] , chany_top_out[28] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size10_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , + SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_track_12 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_track_20 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_bottom_track_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size11_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_left_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_11_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , + top_left_grid_pin_48_[0] , top_left_grid_pin_50_[0] , + chanx_right_in[5] , chanx_left_out[9] , chanx_left_out[24] , + chany_top_out[9] , chany_top_out[24] , chanx_right_out[9] , + chanx_left_in[21] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 , + SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_49_[0] , top_left_grid_pin_51_[0] , + chanx_right_in[9] , chanx_left_out[11] , chanx_left_out[25] , + chany_top_out[11] , chany_top_out[25] , chanx_right_out[11] , + chanx_left_in[17] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , chany_bottom_out[24] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[9] , chany_bottom_in[13] , chany_top_out[24] , + chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , + SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_right_track_10 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , chany_bottom_out[25] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_41_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[9] , chany_top_out[11] , chany_top_out[25] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 , + SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_left_out[9] , + chanx_right_in[13] , chanx_left_out[24] , + bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , + bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , + chanx_left_in[5] , chanx_right_out[9] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size12_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 , + SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[9] , + chanx_left_out[11] , chanx_left_out[25] , + bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , + bottom_left_grid_pin_49_[0] , bottom_left_grid_pin_51_[0] , + chanx_left_in[9] , chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size12_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , + SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_156 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( + .in ( { chany_bottom_out[9] , chany_top_in[21] , chany_bottom_out[24] , + chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , + chany_top_out[9] , chany_top_out[24] , left_bottom_grid_pin_36_[0] , + left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] , + left_bottom_grid_pin_42_[0] } ) , + .sram ( mux_tree_tapbuf_size12_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , + SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( + .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , + chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , + chany_top_out[11] , chany_top_out[25] , left_bottom_grid_pin_37_[0] , + left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] , + left_bottom_grid_pin_43_[0] } ) , + .sram ( mux_tree_tapbuf_size12_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , + SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_track_10 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_0 mux_top_track_28 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[15] , + chanx_right_in[21] , chanx_left_out[29] , chany_top_out[15] , + chany_top_out[29] , chanx_left_in[5] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , + SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , chany_bottom_out[29] , + right_bottom_grid_pin_38_[0] , chany_bottom_in[2] , + chany_top_out[15] , chany_top_out[29] , chanx_right_out[15] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , + SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_2 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_left_out[15] , chanx_left_out[29] , + bottom_left_grid_pin_46_[0] , chanx_right_out[15] , + chanx_left_in[21] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , + SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size9 mux_left_track_29 ( + .in ( { chany_top_in[5] , chany_bottom_out[15] , chany_bottom_out[29] , + chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[13] , + chany_top_out[15] , chany_top_out[29] , left_bottom_grid_pin_38_[0] } ) , + .sram ( mux_tree_tapbuf_size9_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , + SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem_2 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size9_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_0 mux_top_track_36 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[16] , + chanx_right_in[25] , chany_top_out[16] , chanx_left_in[4] , + chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , + SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_1 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[17] , + chanx_right_in[29] , chany_top_out[17] , chanx_left_in[2] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_2 mux_top_track_52 ( + .in ( { top_left_grid_pin_49_[0] , chanx_right_in[0] , + chanx_left_out[19] , chany_top_out[19] , chanx_left_in[1] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 , + SYNOPSYS_UNCONNECTED_137 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_3 mux_right_track_36 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , + chany_top_out[16] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_138 , SYNOPSYS_UNCONNECTED_139 , + SYNOPSYS_UNCONNECTED_140 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_161 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , + chany_top_out[17] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , + SYNOPSYS_UNCONNECTED_143 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_41_[0] , chany_top_out[19] , + chany_bottom_in[29] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_144 , SYNOPSYS_UNCONNECTED_145 , + SYNOPSYS_UNCONNECTED_146 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_158 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_6 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_left_out[16] , + bottom_left_grid_pin_47_[0] , chanx_right_out[16] , + chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_147 , SYNOPSYS_UNCONNECTED_148 , + SYNOPSYS_UNCONNECTED_149 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_157 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_7 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_left_out[17] , + bottom_left_grid_pin_48_[0] , chanx_right_out[17] , + chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_150 , SYNOPSYS_UNCONNECTED_151 , + SYNOPSYS_UNCONNECTED_152 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_8 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_left_out[19] , chanx_right_in[29] , + bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size6_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_153 , SYNOPSYS_UNCONNECTED_154 , + SYNOPSYS_UNCONNECTED_155 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_9 mux_left_track_37 ( + .in ( { chany_top_in[4] , chany_bottom_out[16] , chanx_left_out[16] , + chany_top_out[16] , chany_bottom_in[17] , + left_bottom_grid_pin_39_[0] } ) , + .sram ( mux_tree_tapbuf_size6_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_156 , SYNOPSYS_UNCONNECTED_157 , + SYNOPSYS_UNCONNECTED_158 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_10 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_bottom_out[17] , chanx_left_out[17] , + chany_top_out[17] , chany_bottom_in[21] , + left_bottom_grid_pin_40_[0] } ) , + .sram ( mux_tree_tapbuf_size6_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_159 , SYNOPSYS_UNCONNECTED_160 , + SYNOPSYS_UNCONNECTED_161 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_160 ) ) ; +sb_1__1__mux_tree_tapbuf_size6 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_bottom_out[19] , chanx_left_out[19] , + chany_top_out[19] , chany_bottom_in[25] , + left_bottom_grid_pin_41_[0] } ) , + .sram ( mux_tree_tapbuf_size6_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_162 , SYNOPSYS_UNCONNECTED_163 , + SYNOPSYS_UNCONNECTED_164 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_159 ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_7 mem_bottom_track_45 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_8 mem_bottom_track_53 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_8_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_9 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_9_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; +sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( { copt_net_170 } ) , + .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; +sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , + .X ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( net_net_151 ) ) ; +sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 Reset_N_FTB01 ( .A ( Reset_S_in ) , + .X ( Reset_N_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_92__91 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_93__92 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_94__93 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_95__94 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_96__95 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_97__96 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_98__97 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_99__98 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_100__99 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_101__100 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_102__101 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_103__102 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_104__103 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_105__104 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_106__105 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_107__106 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_108__107 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_109__108 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_110__109 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_111__110 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_112__111 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_113__112 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_114__113 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_115__114 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_116__115 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_117__116 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_118__117 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_119__118 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_120__119 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_151 ( .A ( net_net_151 ) , + .X ( pReset_N_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_165 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_166 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_167 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_168 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , + .HI ( optlc_net_161 ) ) ; +sky130_fd_sc_hd__buf_8 copt_h_inst_1358 ( .A ( copt_net_170 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_180 ) , + .X ( chanx_left_out[2] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_145 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_129 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_127 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_112 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_106 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_97 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_155 ) , + .X ( copt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_157 ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_152 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( ccff_head[0] ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_153 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( copt_net_154 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_156 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( ropt_net_181 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_184 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_182 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_183 ) , + .X ( ropt_net_185 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_143 ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ , + top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ , + top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ , + top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ , + right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ , + right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ , + right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ , + right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in , + left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ , + left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ , + left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , + left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ , + left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in , + Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out , + pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in , + prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_44_ ; +input [0:0] top_left_grid_pin_45_ ; +input [0:0] top_left_grid_pin_46_ ; +input [0:0] top_left_grid_pin_47_ ; +input [0:0] top_left_grid_pin_48_ ; +input [0:0] top_left_grid_pin_49_ ; +input [0:0] top_left_grid_pin_50_ ; +input [0:0] top_left_grid_pin_51_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:29] chanx_left_in ; +input [0:0] left_bottom_grid_pin_1_ ; +input [0:0] left_bottom_grid_pin_3_ ; +input [0:0] left_bottom_grid_pin_5_ ; +input [0:0] left_bottom_grid_pin_7_ ; +input [0:0] left_bottom_grid_pin_9_ ; +input [0:0] left_bottom_grid_pin_11_ ; +input [0:0] left_bottom_grid_pin_13_ ; +input [0:0] left_bottom_grid_pin_15_ ; +input [0:0] left_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chanx_left_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_TOP ; +input Test_en_S_in ; +output Test_en_N_out ; +input pReset_S_in ; +input pReset_E_in ; +input pReset_W_in ; +output pReset_N_out ; +output pReset_W_out ; +output pReset_E_out ; +input Reset_S_in ; +output Reset_N_out ; +input prog_clk_0_N_in ; +input prog_clk_3_S_in ; +output prog_clk_3_N_out ; +input clk_3_S_in ; +output clk_3_N_out ; + +wire ropt_net_170 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size7_0_sram ; +wire [0:2] mux_tree_tapbuf_size7_1_sram ; +wire [0:2] mux_tree_tapbuf_size7_2_sram ; +wire [0:2] mux_tree_tapbuf_size7_3_sram ; +wire [0:2] mux_tree_tapbuf_size7_4_sram ; +wire [0:2] mux_tree_tapbuf_size7_5_sram ; +wire [0:2] mux_tree_tapbuf_size7_6_sram ; +wire [0:2] mux_tree_tapbuf_size7_7_sram ; +wire [0:2] mux_tree_tapbuf_size7_8_sram ; +wire [0:2] mux_tree_tapbuf_size7_9_sram ; +wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size9_0_sram ; +wire [0:3] mux_tree_tapbuf_size9_1_sram ; +wire [0:3] mux_tree_tapbuf_size9_2_sram ; +wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; + +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; +assign prog_clk_0 = prog_clk[0] ; + +sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] , + chanx_left_in[0] , chanx_right_out[4] } ) , + .sram ( mux_tree_tapbuf_size7_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( + .in ( { chany_top_in[10] , chany_top_in[21] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_13_[0] , chanx_right_out[4] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size7_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , + chanx_right_out[12] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size7_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[13] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size7_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , + chanx_right_out[15] , chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size7_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( + .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , + chanx_left_out[21] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( + .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , + chanx_left_out[23] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( + .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , + chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size7_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( + .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , + chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size7_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( + .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , + chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , + left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size7_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] , + chanx_right_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , + top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , + chanx_right_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( + .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , + top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , + chanx_right_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chany_top_out[4] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( + .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , + chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] , + chanx_right_in[17] , chanx_right_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( + .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , + chanx_right_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[7] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , + chanx_right_in[25] , chanx_right_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] , + chanx_right_in[29] , chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chany_top_out[9] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( + .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , + chanx_right_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( + .in ( { chany_top_in[9] , chany_top_in[20] , + right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] , + chanx_right_out[19] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , + chanx_right_out[20] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , + .out ( chany_top_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , + .out ( chany_top_out[13] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( + .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , + chanx_right_out[29] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( + .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( + .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , + .out ( chany_top_out[15] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( + .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , + .out ( chany_top_out[16] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( + .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_top_out[17] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( + .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , + .out ( chany_top_out[20] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( + .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , + .out ( chany_top_out[21] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( + .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( + .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , + .out ( chany_top_out[23] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( + .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , + .out ( chany_top_out[24] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( + .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , + .out ( chany_top_out[25] ) , .p0 ( optlc_net_149 ) ) ; +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( + .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , + .out ( chany_top_out[29] ) , .p0 ( optlc_net_150 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , + right_bottom_grid_pin_15_[0] , chanx_right_out[7] , + chanx_right_out[21] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , + SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , + right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[8] , + chanx_right_out[23] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , + SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_147 ) ) ; +sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( + .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , + chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , + SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , + right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] , + right_bottom_grid_pin_17_[0] , chanx_right_out[9] , + chanx_right_out[24] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , + SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( + .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , + right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] , + chanx_right_out[11] , chanx_right_out[25] } ) , + .sram ( mux_tree_tapbuf_size9_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , + SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_151 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( + .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , + chanx_left_out[24] , left_bottom_grid_pin_1_[0] , + left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] , + left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size9_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , + SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( + .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , + chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , + left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] , + left_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size9_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , + SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_148 ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ; +sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_W_out ) ) ; +sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_E_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) , + .X ( chanx_left_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) , + .X ( chanx_left_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) , + .X ( chanx_left_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) , + .X ( chanx_left_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) , + .X ( chanx_left_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) , + .X ( chanx_left_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) , + .X ( chanx_right_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) , + .X ( chanx_right_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) , + .X ( chanx_right_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , + .X ( chanx_right_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , + .X ( chanx_right_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , + .Y ( Test_en_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( Test_en_S_in ) , .Y ( BUF_net_133 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( Reset_S_in ) , .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , + .Y ( prog_clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_139 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_141 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_170 ) , + .X ( SC_OUT_TOP ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_102 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_101 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_103 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_25 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_73 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , + .X ( copt_net_94 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_98 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_99 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_95 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ , + right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out , + ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chanx_right_in ; +input [0:0] right_top_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +output SC_OUT_BOT ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_129 ; +wire ropt_net_127 ; +wire ropt_net_137 ; +wire ropt_net_128 ; +wire ropt_net_134 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_26_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] , + right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( + .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( + .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_93 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( + .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 ( + .in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( + .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( + .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( + .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size2_26_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_91 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 ( + .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[14] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ; +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_92 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , + .X ( chany_bottom_out[26] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[18] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_93 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_127 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_137 ) , + .X ( chany_bottom_out[20] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_146 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_143 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +wire copt_net_164 ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_164 ) , + .X ( mem_out[1] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_137 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_135 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_132 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_117 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_111 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_99 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:4] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( ccff_head[0] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1347 ( .A ( copt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1348 ( .A ( ropt_net_177 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1349 ( .A ( ropt_net_178 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1350 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( ropt_net_180 ) , + .X ( ropt_net_181 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ , + right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , + right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , + right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in , + bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , + chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out , + prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_36_ ; +input [0:0] right_bottom_grid_pin_37_ ; +input [0:0] right_bottom_grid_pin_38_ ; +input [0:0] right_bottom_grid_pin_39_ ; +input [0:0] right_bottom_grid_pin_40_ ; +input [0:0] right_bottom_grid_pin_41_ ; +input [0:0] right_bottom_grid_pin_42_ ; +input [0:0] right_bottom_grid_pin_43_ ; +input [0:29] chany_bottom_in ; +input [0:0] bottom_left_grid_pin_1_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:29] chany_bottom_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +output pReset_S_out ; +input prog_clk_0_E_in ; + +wire ropt_net_168 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:1] mux_tree_tapbuf_size3_3_sram ; +wire [0:1] mux_tree_tapbuf_size3_4_sram ; +wire [0:1] mux_tree_tapbuf_size3_5_sram ; +wire [0:1] mux_tree_tapbuf_size3_6_sram ; +wire [0:1] mux_tree_tapbuf_size3_7_sram ; +wire [0:1] mux_tree_tapbuf_size3_8_sram ; +wire [0:1] mux_tree_tapbuf_size3_9_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_10_sram ; +wire [0:2] mux_tree_tapbuf_size4_11_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:2] mux_tree_tapbuf_size4_6_sram ; +wire [0:2] mux_tree_tapbuf_size4_7_sram ; +wire [0:2] mux_tree_tapbuf_size4_8_sram ; +wire [0:2] mux_tree_tapbuf_size4_9_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size5_0_sram ; +wire [0:2] mux_tree_tapbuf_size5_10_sram ; +wire [0:2] mux_tree_tapbuf_size5_11_sram ; +wire [0:2] mux_tree_tapbuf_size5_1_sram ; +wire [0:2] mux_tree_tapbuf_size5_2_sram ; +wire [0:2] mux_tree_tapbuf_size5_3_sram ; +wire [0:2] mux_tree_tapbuf_size5_4_sram ; +wire [0:2] mux_tree_tapbuf_size5_5_sram ; +wire [0:2] mux_tree_tapbuf_size5_6_sram ; +wire [0:2] mux_tree_tapbuf_size5_7_sram ; +wire [0:2] mux_tree_tapbuf_size5_8_sram ; +wire [0:2] mux_tree_tapbuf_size5_9_sram ; +wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size6_0_sram ; +wire [0:2] mux_tree_tapbuf_size6_1_sram ; +wire [0:2] mux_tree_tapbuf_size6_2_sram ; +wire [0:2] mux_tree_tapbuf_size6_3_sram ; +wire [0:2] mux_tree_tapbuf_size6_4_sram ; +wire [0:2] mux_tree_tapbuf_size6_5_sram ; +wire [0:2] mux_tree_tapbuf_size6_6_sram ; +wire [0:2] mux_tree_tapbuf_size6_7_sram ; +wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size6_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , + chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size6_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , + SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , + chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size6_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( + .in ( { chany_top_in[0] , chany_bottom_out[7] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) , + .sram ( mux_tree_tapbuf_size6_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , + SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( + .in ( { chany_top_in[2] , chany_bottom_out[9] , + right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , + right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) , + .sram ( mux_tree_tapbuf_size6_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( + .in ( { chany_top_in[4] , chany_bottom_out[11] , + right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , + right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) , + .sram ( mux_tree_tapbuf_size6_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , + SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( + .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , + chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , + SYNOPSYS_UNCONNECTED_21 } ) , + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( + .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , + chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size6_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , + SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( + .in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] , + chany_top_out[7] , chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size5_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , + SYNOPSYS_UNCONNECTED_27 } ) , + .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( + .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , + chany_top_out[8] , ropt_net_168 } ) , + .sram ( mux_tree_tapbuf_size5_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , + SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( + .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , + chany_top_out[11] , chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size5_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , + SYNOPSYS_UNCONNECTED_33 } ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( + .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , + chany_top_out[13] , chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size5_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , + SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chany_top_out[10] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( + .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , + right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , + chany_top_out[4] } ) , + .sram ( mux_tree_tapbuf_size5_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , + SYNOPSYS_UNCONNECTED_39 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( + .in ( { chany_top_in[1] , chany_bottom_out[8] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[8] } ) , + .sram ( mux_tree_tapbuf_size5_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , + SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( + .in ( { chany_top_in[5] , chany_bottom_out[12] , + right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , + chany_top_out[12] } ) , + .sram ( mux_tree_tapbuf_size5_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , + SYNOPSYS_UNCONNECTED_45 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( + .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , + chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , + .sram ( mux_tree_tapbuf_size5_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , + SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( + .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , + chanx_right_in[18] , chanx_right_in[29] } ) , + .sram ( mux_tree_tapbuf_size5_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , + SYNOPSYS_UNCONNECTED_51 } ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( + .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , + chanx_right_in[16] , chanx_right_in[27] } ) , + .sram ( mux_tree_tapbuf_size5_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , + SYNOPSYS_UNCONNECTED_54 } ) , + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_152 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( + .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , + chanx_right_in[14] , chanx_right_in[25] } ) , + .sram ( mux_tree_tapbuf_size5_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , + SYNOPSYS_UNCONNECTED_57 } ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( + .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , + chanx_right_in[13] , chanx_right_in[24] } ) , + .sram ( mux_tree_tapbuf_size5_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , + SYNOPSYS_UNCONNECTED_60 } ) , + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( + .in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] , + chany_top_out[29] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , + SYNOPSYS_UNCONNECTED_63 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( + .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , + chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , + SYNOPSYS_UNCONNECTED_66 } ) , + .out ( chany_top_out[26] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( + .in ( { chany_top_in[9] , chany_bottom_out[13] , + right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , + SYNOPSYS_UNCONNECTED_69 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( + .in ( { chany_top_in[13] , chany_bottom_out[15] , + right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , + SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( + .in ( { chany_bottom_out[16] , chany_top_in[17] , + right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , + SYNOPSYS_UNCONNECTED_75 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( + .in ( { chany_bottom_out[17] , chany_top_in[21] , + right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , + SYNOPSYS_UNCONNECTED_78 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( + .in ( { chany_bottom_out[19] , chany_top_in[25] , + right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , + .sram ( mux_tree_tapbuf_size4_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , + SYNOPSYS_UNCONNECTED_81 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( + .in ( { chany_bottom_out[20] , chany_top_in[29] , + right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , + .sram ( mux_tree_tapbuf_size4_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , + SYNOPSYS_UNCONNECTED_84 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( + .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , + chany_top_out[29] , chany_bottom_in[29] } ) , + .sram ( mux_tree_tapbuf_size4_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , + SYNOPSYS_UNCONNECTED_87 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( + .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size4_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , + SYNOPSYS_UNCONNECTED_90 } ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( + .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , + chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size4_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , + SYNOPSYS_UNCONNECTED_93 } ) , + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( + .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , + chanx_right_in[22] } ) , + .sram ( mux_tree_tapbuf_size4_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , + SYNOPSYS_UNCONNECTED_96 } ) , + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( + .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , + .out ( chany_top_out[18] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( + .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( + .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , + chany_top_out[21] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( + .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , + ropt_net_168 } ) , + .sram ( mux_tree_tapbuf_size3_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( + .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , + chany_top_out[24] } ) , + .sram ( mux_tree_tapbuf_size3_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( + .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , + chany_top_out[25] } ) , + .sram ( mux_tree_tapbuf_size3_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_149 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( + .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , + chany_top_out[27] } ) , + .sram ( mux_tree_tapbuf_size3_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( + .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , + chany_top_out[28] } ) , + .sram ( mux_tree_tapbuf_size3_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( + .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , + chany_bottom_in[4] } ) , + .sram ( mux_tree_tapbuf_size3_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( + .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , + .sram ( mux_tree_tapbuf_size3_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( + .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( + .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( + .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( + .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( + .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( + .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_150 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , + .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) , + .X ( chany_bottom_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) , + .X ( chany_bottom_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) , + .X ( chany_bottom_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) , + .X ( chany_bottom_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) , + .X ( chany_bottom_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) , + .X ( chanx_right_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ropt_mt_inst_1340 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[23] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_96 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_94 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_100 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_116 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( mem_out[1] ) , + .X ( copt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_114 ) , + .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_115 ) , + .X ( copt_net_116 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_194 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( ccff_head[0] ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_108 ) , + .X ( copt_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_112 ) , + .X ( copt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_110 ) , + .X ( copt_net_111 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_109 ) , + .X ( copt_net_112 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( copt_net_111 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_192 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1358 ( .A ( ropt_net_193 ) , + .X ( ropt_net_194 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_75 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_71 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_69 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_67 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_65 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_62 ( .A ( BUF_net_63 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_63 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_63 ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_60 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_61 ) ) ; +endmodule + + +module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ , + chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ , + right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ , + right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ , + right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ , + right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out , + ccff_tail , pReset_E_in , prog_clk_0_E_in ) ; +input [0:0] pReset ; +input [0:29] chany_top_in ; +input [0:0] top_left_grid_pin_1_ ; +input [0:29] chanx_right_in ; +input [0:0] right_bottom_grid_pin_1_ ; +input [0:0] right_bottom_grid_pin_3_ ; +input [0:0] right_bottom_grid_pin_5_ ; +input [0:0] right_bottom_grid_pin_7_ ; +input [0:0] right_bottom_grid_pin_9_ ; +input [0:0] right_bottom_grid_pin_11_ ; +input [0:0] right_bottom_grid_pin_13_ ; +input [0:0] right_bottom_grid_pin_15_ ; +input [0:0] right_bottom_grid_pin_17_ ; +input [0:0] ccff_head ; +output [0:29] chany_top_out ; +output [0:29] chanx_right_out ; +output [0:0] ccff_tail ; +input pReset_E_in ; +input prog_clk_0_E_in ; + +wire ropt_net_139 ; +wire ropt_net_140 ; +wire [0:0] prog_clk ; +wire prog_clk_0 ; +wire [0:1] mux_tree_tapbuf_size2_0_sram ; +wire [0:1] mux_tree_tapbuf_size2_10_sram ; +wire [0:1] mux_tree_tapbuf_size2_11_sram ; +wire [0:1] mux_tree_tapbuf_size2_12_sram ; +wire [0:1] mux_tree_tapbuf_size2_13_sram ; +wire [0:1] mux_tree_tapbuf_size2_14_sram ; +wire [0:1] mux_tree_tapbuf_size2_15_sram ; +wire [0:1] mux_tree_tapbuf_size2_16_sram ; +wire [0:1] mux_tree_tapbuf_size2_17_sram ; +wire [0:1] mux_tree_tapbuf_size2_18_sram ; +wire [0:1] mux_tree_tapbuf_size2_19_sram ; +wire [0:1] mux_tree_tapbuf_size2_1_sram ; +wire [0:1] mux_tree_tapbuf_size2_20_sram ; +wire [0:1] mux_tree_tapbuf_size2_21_sram ; +wire [0:1] mux_tree_tapbuf_size2_22_sram ; +wire [0:1] mux_tree_tapbuf_size2_23_sram ; +wire [0:1] mux_tree_tapbuf_size2_24_sram ; +wire [0:1] mux_tree_tapbuf_size2_25_sram ; +wire [0:1] mux_tree_tapbuf_size2_2_sram ; +wire [0:1] mux_tree_tapbuf_size2_3_sram ; +wire [0:1] mux_tree_tapbuf_size2_4_sram ; +wire [0:1] mux_tree_tapbuf_size2_5_sram ; +wire [0:1] mux_tree_tapbuf_size2_6_sram ; +wire [0:1] mux_tree_tapbuf_size2_7_sram ; +wire [0:1] mux_tree_tapbuf_size2_8_sram ; +wire [0:1] mux_tree_tapbuf_size2_9_sram ; +wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ; +wire [0:1] mux_tree_tapbuf_size3_0_sram ; +wire [0:1] mux_tree_tapbuf_size3_1_sram ; +wire [0:1] mux_tree_tapbuf_size3_2_sram ; +wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ; +wire [0:2] mux_tree_tapbuf_size4_0_sram ; +wire [0:2] mux_tree_tapbuf_size4_1_sram ; +wire [0:2] mux_tree_tapbuf_size4_2_sram ; +wire [0:2] mux_tree_tapbuf_size4_3_sram ; +wire [0:2] mux_tree_tapbuf_size4_4_sram ; +wire [0:2] mux_tree_tapbuf_size4_5_sram ; +wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ; + +assign prog_clk_0 = prog_clk[0] ; + +sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , + .sram ( mux_tree_tapbuf_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , + .sram ( mux_tree_tapbuf_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , + .sram ( mux_tree_tapbuf_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( chany_top_out[6] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( chany_top_out[14] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( + .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , + .sram ( mux_tree_tapbuf_size2_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , + .out ( chany_top_out[22] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( + .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( + .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_6_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( + .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_7_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( + .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_8_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( + .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_9_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( + .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_10_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_11_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( + .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_12_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( + .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_13_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( + .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_14_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_15_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( + .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_16_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( + .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_17_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( + .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_18_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( + .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , + .sram ( mux_tree_tapbuf_size2_19_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( + .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , + .sram ( mux_tree_tapbuf_size2_20_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( + .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , + .sram ( mux_tree_tapbuf_size2_21_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( + .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , + .sram ( mux_tree_tapbuf_size2_22_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( + .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , + .sram ( mux_tree_tapbuf_size2_23_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( + .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size2_24_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( + .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size2_25_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( + .in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , + SYNOPSYS_UNCONNECTED_55 } ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , + SYNOPSYS_UNCONNECTED_58 } ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , + SYNOPSYS_UNCONNECTED_61 } ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( + .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , + .sram ( mux_tree_tapbuf_size4_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , + SYNOPSYS_UNCONNECTED_64 } ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , + right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , + .sram ( mux_tree_tapbuf_size4_4_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , + SYNOPSYS_UNCONNECTED_67 } ) , + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( + .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , + right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size4_5_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , + SYNOPSYS_UNCONNECTED_70 } ) , + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( + .in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( + .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( + .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , + right_bottom_grid_pin_17_[0] } ) , + .sram ( mux_tree_tapbuf_size3_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; +sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , + .X ( prog_clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[20] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) , + .X ( chany_top_out[21] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) , + .X ( chany_top_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) , + .X ( chany_top_out[25] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) , + .X ( chany_top_out[26] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , + .X ( chany_top_out[28] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_139 ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_140 ) , + .X ( chany_top_out[16] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1614 ( .A ( copt_net_198 ) , + .X ( copt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1615 ( .A ( copt_net_195 ) , + .X ( copt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1616 ( .A ( copt_net_199 ) , + .X ( copt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1617 ( .A ( copt_net_197 ) , + .X ( copt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1618 ( .A ( mem_out[1] ) , + .X ( copt_net_199 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_46 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_62__61 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_45 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_61__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_44 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_60__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_46 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_45 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_521_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_131 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_44 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_520_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_520_ ) , + .Y ( BUF_net_128 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk , p_abuf0 , p_abuf1 ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +output p_abuf0 ; +output p_abuf1 ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_43 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_59__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_42 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_58__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_43 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_42 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb22 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_57__56 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p0 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_43 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf2 , p_abuf3 , p0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; +grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_45 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_46 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_6 FTB_64__63 ( .A ( p_abuf1 ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , + .p0 ( p1 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_41 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_40 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_54__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_39 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_38 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_52__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_41 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_39 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_518_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_125 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_517_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_122 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_37 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_51__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_36 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_36 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb19 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_49__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p3 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_37 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p1 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p1 ) ) ; +grid_clb_mux_tree_size2_40 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_39 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_40 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_41 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_56__55 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; +input p3 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_35 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_47__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_34 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_46__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_33 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_45__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_32 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_35 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_33 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_516_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_119 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_32 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_515_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_116 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_31 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_43__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_30 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_31 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb16 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_41__40 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p3 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_31 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_32 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_33 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_34 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_35 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_48__47 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p3 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_29 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_39__38 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_28 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_38__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_27 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_37__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_26 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p3 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_514_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_113 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_513_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_110 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_25 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_35__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_24 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_34__33 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb13 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_33__32 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p0 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p0 ; +input p2 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_25 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p2 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p2 ; +input p3 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p0 ( p0 ) , .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_27 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_28 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_29 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p2 ; +input p3 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_23 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_31__30 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_22 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_30__29 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_21 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_29__28 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_20 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_28__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_512_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_107 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p_abuf0 , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_511_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_104 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_19 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_27__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_18 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_26__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb10 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_25__24 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_19 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_20 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_21 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_22 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_23 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_32__31 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_3 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p2 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p2 ( p2 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_17 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_23__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_16 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_22__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_15 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_21__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_14 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_20__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , + p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_510_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_101 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p_abuf0 , + p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_509_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_98 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_13 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_19__18 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_12 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb7 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_17__16 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p2 ; +input p4 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_13 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p1 , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p2 ; +input p4 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) , .p4 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_14 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_17 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_15 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_16 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_17 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_24__23 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p2 ; +input p4 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p1 ( p1 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_11 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_15__14 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_10 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_14__13 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_9 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_13__12 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_8 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_12__11 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_95 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_507_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_92 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_7 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_11__10 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_6 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_10__9 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb4 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_9__8 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p1 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_7 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p0 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_9 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_10 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_11 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_16__15 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_1 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; +input p1 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p0 ( p0 ) , .p1 ( p1 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_5 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_7__6 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_4 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_6__5 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_3 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_5__4 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_2 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_506_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( aps_rename_505_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + Test_en , ff_D , ff_DI , ff_reset , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +input [0:0] ff_reset ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , + .RESET_B ( ff_reset[0] ) , .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_1 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_3__2 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_0 ( pReset , prog_clk , ccff_head , + ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_2__1 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p4 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p4 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 ( A0 , A1 , S , X ) ; +input A0 ; +input A1 ; +input S ; +output X ; + +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( X_gOb1 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + carry_follower_a , carry_follower_b , carry_follower_cin , + carry_follower_cout ) ; +input [0:0] carry_follower_a ; +input [0:0] carry_follower_b ; +input [0:0] carry_follower_cin ; +output [0:0] carry_follower_cout ; + +grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( + .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , + .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 ( pReset , prog_clk , + ccff_head , ccff_tail , mem_out ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; + +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[4] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[5] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[6] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[7] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[8] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[9] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[10] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[11] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[12] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[13] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[14] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[15] ) ) ; +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1607 ( .A ( ccff_head[0] ) , + .X ( copt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1608 ( .A ( copt_net_191 ) , + .X ( copt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1609 ( .A ( copt_net_192 ) , + .X ( copt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1610 ( .A ( copt_net_190 ) , + .X ( copt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1611 ( .A ( copt_net_188 ) , + .X ( copt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1612 ( .A ( copt_net_189 ) , + .X ( copt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1619 ( .A ( copt_net_193 ) , + .X ( ropt_net_200 ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut2_out , lut3_out , + lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( lut2_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[2] ) , + .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( lut2_out[1] ) , + .A1 ( lut2_out[0] ) , .S ( sram[2] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( lut3_out[1] ) , + .A1 ( lut3_out[0] ) , .S ( sram[3] ) , .X ( lut4_out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , + lut2_out , lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut2_out ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { in[0] , in[1] , in[2] , sky130_fd_sc_hd__or2_1_0_X[0] } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .lut2_out ( lut2_out ) , .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + pReset , prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut2_out , + frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut2_out ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; + +grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , + SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 , + SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , + SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , + SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , + SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 , + SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , + SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_17 } ) , + .lut2_out ( frac_lut4_lut2_out ) , .lut3_out ( frac_lut4_lut3_out ) , + .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , + frac_logic_out , frac_logic_cout , ccff_tail , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] frac_logic_cin ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] frac_logic_cout ; +output [0:0] ccff_tail ; +input p1 ; +input p4 ; + +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:0] mux_tree_size2_1_out ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_lut4_in ( { frac_logic_in[0] , frac_logic_in[1] , + mux_tree_size2_1_out[0] , frac_logic_in[3] } ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut2_out ( { direct_interc_7_out[0] , direct_interc_5_out[0] } ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( + .carry_follower_a ( direct_interc_5_out ) , + .carry_follower_b ( frac_logic_cin ) , + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 ( + .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_1 mem_frac_lut4_0_in_2 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , + fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , + fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , + p_abuf1 , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fabric_in ; +input [0:0] fabric_reg_in ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_cin ; +input [0:0] fabric_reset ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_reg_out ; +output [0:0] fabric_sc_out ; +output [0:0] fabric_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p4 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:0] mux_tree_size2_3_out ; +wire [0:1] mux_tree_size2_3_sram ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +wire [0:0] mux_tree_size2_mem_2_ccff_tail ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , + .frac_logic_in ( fabric_in ) , + .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , + + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p1 ( p1 ) , .p4 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_3_out ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_reset ( fabric_reset ) , .ff_Q ( fabric_sc_out ) , + .ff_clk ( fabric_clk ) ) ; +grid_clb_mux_tree_size2_2 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_reg_in[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_5 mux_ff_1_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] + } ) , + .sram ( mux_tree_size2_3_sram ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) ) ; +grid_clb_mux_tree_size2_mem_3 mem_fabric_out_1 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) ) ; +grid_clb_mux_tree_size2_mem_4 mem_ff_0_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_2_ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) ) ; +grid_clb_mux_tree_size2_mem_5 mem_ff_1_D_0 ( .pReset ( pReset ) , + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_2_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_3_sram ) ) ; +sky130_fd_sc_hd__buf_1 FTB_8__7 ( .A ( fabric_sc_out[0] ) , + .X ( fabric_reg_out[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , + Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , + fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , + ccff_tail , p_abuf0 , p_abuf1 , p1 , p4 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:3] fle_in ; +input [0:0] fle_reg_in ; +input [0:0] fle_sc_in ; +input [0:0] fle_cin ; +input [0:0] fle_reset ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_reg_out ; +output [0:0] fle_sc_out ; +output [0:0] fle_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +input p1 ; +input p4 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , + .fabric_sc_in ( fle_sc_in ) , + .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p1 ( p1 ) , .p4 ( p4 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_clb_ ( pReset , prog_clk , Test_en , + clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , + clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , + clb_I7 , clb_I7i , clb_reg_in , clb_sc_in , clb_cin , clb_reset , + clb_clk , ccff_head , clb_O , clb_reg_out , clb_sc_out , clb_cout , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p_abuf5 , + p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , p_abuf12 , + p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , p4 , p5 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:1] clb_I0 ; +input [0:1] clb_I0i ; +input [0:1] clb_I1 ; +input [0:1] clb_I1i ; +input [0:1] clb_I2 ; +input [0:1] clb_I2i ; +input [0:1] clb_I3 ; +input [0:1] clb_I3i ; +input [0:1] clb_I4 ; +input [0:1] clb_I4i ; +input [0:1] clb_I5 ; +input [0:1] clb_I5i ; +input [0:1] clb_I6 ; +input [0:1] clb_I6i ; +input [0:1] clb_I7 ; +input [0:1] clb_I7i ; +input [0:0] clb_reg_in ; +input [0:0] clb_sc_in ; +input [0:0] clb_cin ; +input [0:0] clb_reset ; +input [0:0] clb_clk ; +input [0:0] ccff_head ; +output [0:15] clb_O ; +output [0:0] clb_reg_out ; +output [0:0] clb_sc_out ; +output [0:0] clb_cout ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +output p_abuf3 ; +output p_abuf4 ; +output p_abuf5 ; +output p_abuf6 ; +output p_abuf7 ; +output p_abuf8 ; +output p_abuf9 ; +output p_abuf10 ; +output p_abuf11 ; +output p_abuf12 ; +output p_abuf13 ; +output p_abuf14 ; +output p_abuf15 ; +output p_abuf16 ; +input p0 ; +input p1 ; +input p2 ; +input p3 ; +input p4 ; +input p5 ; + +wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_86_out ; +wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_1_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_5_fle_sc_out ; +wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; + +grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) , + .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( ccff_head ) , + .fle_out ( { clb_O[1] , clb_O[0] } ) , + .fle_reg_out ( direct_interc_32_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , + .fle_reg_in ( direct_interc_32_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , + .fle_reg_out ( direct_interc_41_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , + .fle_reg_in ( direct_interc_41_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , + .fle_out ( { clb_O[5] , clb_O[4] } ) , + .fle_reg_out ( direct_interc_50_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) , + .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , + .fle_reg_in ( direct_interc_50_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , + .fle_out ( { clb_O[7] , clb_O[6] } ) , + .fle_reg_out ( direct_interc_59_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , + .fle_reg_in ( direct_interc_59_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , + .fle_out ( { clb_O[9] , clb_O[8] } ) , + .fle_reg_out ( direct_interc_68_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , + .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , + .fle_reg_in ( direct_interc_68_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , + .fle_out ( { clb_O[11] , clb_O[10] } ) , + .fle_reg_out ( direct_interc_77_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , + .fle_reg_in ( direct_interc_77_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , + .fle_out ( { clb_O[13] , clb_O[12] } ) , + .fle_reg_out ( direct_interc_86_out ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , + .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , + .fle_reg_in ( direct_interc_86_out ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) , + .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , + .fle_out ( { clb_O[15] , clb_O[14] } ) , + .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , + .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p1 ( p1 ) ) ; +endmodule + + +module grid_clb ( pReset , top_width_0_height_0__pin_0_ , + top_width_0_height_0__pin_1_ , top_width_0_height_0__pin_2_ , + top_width_0_height_0__pin_3_ , top_width_0_height_0__pin_4_ , + top_width_0_height_0__pin_5_ , top_width_0_height_0__pin_6_ , + top_width_0_height_0__pin_7_ , top_width_0_height_0__pin_8_ , + top_width_0_height_0__pin_9_ , top_width_0_height_0__pin_10_ , + top_width_0_height_0__pin_11_ , top_width_0_height_0__pin_12_ , + top_width_0_height_0__pin_13_ , top_width_0_height_0__pin_14_ , + top_width_0_height_0__pin_15_ , top_width_0_height_0__pin_32_ , + top_width_0_height_0__pin_33_ , top_width_0_height_0__pin_34_ , + right_width_0_height_0__pin_16_ , right_width_0_height_0__pin_17_ , + right_width_0_height_0__pin_18_ , right_width_0_height_0__pin_19_ , + right_width_0_height_0__pin_20_ , right_width_0_height_0__pin_21_ , + right_width_0_height_0__pin_22_ , right_width_0_height_0__pin_23_ , + right_width_0_height_0__pin_24_ , right_width_0_height_0__pin_25_ , + right_width_0_height_0__pin_26_ , right_width_0_height_0__pin_27_ , + right_width_0_height_0__pin_28_ , right_width_0_height_0__pin_29_ , + right_width_0_height_0__pin_30_ , right_width_0_height_0__pin_31_ , + Reset , ccff_head , top_width_0_height_0__pin_36_upper , + top_width_0_height_0__pin_36_lower , top_width_0_height_0__pin_37_upper , + top_width_0_height_0__pin_37_lower , top_width_0_height_0__pin_38_upper , + top_width_0_height_0__pin_38_lower , top_width_0_height_0__pin_39_upper , + top_width_0_height_0__pin_39_lower , top_width_0_height_0__pin_40_upper , + top_width_0_height_0__pin_40_lower , top_width_0_height_0__pin_41_upper , + top_width_0_height_0__pin_41_lower , top_width_0_height_0__pin_42_upper , + top_width_0_height_0__pin_42_lower , top_width_0_height_0__pin_43_upper , + top_width_0_height_0__pin_43_lower , + right_width_0_height_0__pin_44_upper , + right_width_0_height_0__pin_44_lower , + right_width_0_height_0__pin_45_upper , + right_width_0_height_0__pin_45_lower , + right_width_0_height_0__pin_46_upper , + right_width_0_height_0__pin_46_lower , + right_width_0_height_0__pin_47_upper , + right_width_0_height_0__pin_47_lower , + right_width_0_height_0__pin_48_upper , + right_width_0_height_0__pin_48_lower , + right_width_0_height_0__pin_49_upper , + right_width_0_height_0__pin_49_lower , + right_width_0_height_0__pin_50_upper , + right_width_0_height_0__pin_50_lower , + right_width_0_height_0__pin_51_upper , + right_width_0_height_0__pin_51_lower , bottom_width_0_height_0__pin_52_ , + bottom_width_0_height_0__pin_53_ , bottom_width_0_height_0__pin_54_ , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + Test_en_E_in , Test_en_W_in , Test_en_W_out , Test_en_E_out , + pReset_N_in , Reset_E_in , Reset_W_in , Reset_W_out , Reset_E_out , + prog_clk_0_N_in , prog_clk_0_S_in , prog_clk_0_S_out , prog_clk_0_E_out , + prog_clk_0_W_out , prog_clk_0_N_out , clk_0_N_in , clk_0_S_in ) ; +input [0:0] pReset ; +input [0:0] top_width_0_height_0__pin_0_ ; +input [0:0] top_width_0_height_0__pin_1_ ; +input [0:0] top_width_0_height_0__pin_2_ ; +input [0:0] top_width_0_height_0__pin_3_ ; +input [0:0] top_width_0_height_0__pin_4_ ; +input [0:0] top_width_0_height_0__pin_5_ ; +input [0:0] top_width_0_height_0__pin_6_ ; +input [0:0] top_width_0_height_0__pin_7_ ; +input [0:0] top_width_0_height_0__pin_8_ ; +input [0:0] top_width_0_height_0__pin_9_ ; +input [0:0] top_width_0_height_0__pin_10_ ; +input [0:0] top_width_0_height_0__pin_11_ ; +input [0:0] top_width_0_height_0__pin_12_ ; +input [0:0] top_width_0_height_0__pin_13_ ; +input [0:0] top_width_0_height_0__pin_14_ ; +input [0:0] top_width_0_height_0__pin_15_ ; +input [0:0] top_width_0_height_0__pin_32_ ; +input [0:0] top_width_0_height_0__pin_33_ ; +input [0:0] top_width_0_height_0__pin_34_ ; +input [0:0] right_width_0_height_0__pin_16_ ; +input [0:0] right_width_0_height_0__pin_17_ ; +input [0:0] right_width_0_height_0__pin_18_ ; +input [0:0] right_width_0_height_0__pin_19_ ; +input [0:0] right_width_0_height_0__pin_20_ ; +input [0:0] right_width_0_height_0__pin_21_ ; +input [0:0] right_width_0_height_0__pin_22_ ; +input [0:0] right_width_0_height_0__pin_23_ ; +input [0:0] right_width_0_height_0__pin_24_ ; +input [0:0] right_width_0_height_0__pin_25_ ; +input [0:0] right_width_0_height_0__pin_26_ ; +input [0:0] right_width_0_height_0__pin_27_ ; +input [0:0] right_width_0_height_0__pin_28_ ; +input [0:0] right_width_0_height_0__pin_29_ ; +input [0:0] right_width_0_height_0__pin_30_ ; +input [0:0] right_width_0_height_0__pin_31_ ; +input [0:0] Reset ; +input [0:0] ccff_head ; +output [0:0] top_width_0_height_0__pin_36_upper ; +output [0:0] top_width_0_height_0__pin_36_lower ; +output [0:0] top_width_0_height_0__pin_37_upper ; +output [0:0] top_width_0_height_0__pin_37_lower ; +output [0:0] top_width_0_height_0__pin_38_upper ; +output [0:0] top_width_0_height_0__pin_38_lower ; +output [0:0] top_width_0_height_0__pin_39_upper ; +output [0:0] top_width_0_height_0__pin_39_lower ; +output [0:0] top_width_0_height_0__pin_40_upper ; +output [0:0] top_width_0_height_0__pin_40_lower ; +output [0:0] top_width_0_height_0__pin_41_upper ; +output [0:0] top_width_0_height_0__pin_41_lower ; +output [0:0] top_width_0_height_0__pin_42_upper ; +output [0:0] top_width_0_height_0__pin_42_lower ; +output [0:0] top_width_0_height_0__pin_43_upper ; +output [0:0] top_width_0_height_0__pin_43_lower ; +output [0:0] right_width_0_height_0__pin_44_upper ; +output [0:0] right_width_0_height_0__pin_44_lower ; +output [0:0] right_width_0_height_0__pin_45_upper ; +output [0:0] right_width_0_height_0__pin_45_lower ; +output [0:0] right_width_0_height_0__pin_46_upper ; +output [0:0] right_width_0_height_0__pin_46_lower ; +output [0:0] right_width_0_height_0__pin_47_upper ; +output [0:0] right_width_0_height_0__pin_47_lower ; +output [0:0] right_width_0_height_0__pin_48_upper ; +output [0:0] right_width_0_height_0__pin_48_lower ; +output [0:0] right_width_0_height_0__pin_49_upper ; +output [0:0] right_width_0_height_0__pin_49_lower ; +output [0:0] right_width_0_height_0__pin_50_upper ; +output [0:0] right_width_0_height_0__pin_50_lower ; +output [0:0] right_width_0_height_0__pin_51_upper ; +output [0:0] right_width_0_height_0__pin_51_lower ; +output [0:0] bottom_width_0_height_0__pin_52_ ; +output [0:0] bottom_width_0_height_0__pin_53_ ; +output [0:0] bottom_width_0_height_0__pin_54_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input Test_en_E_in ; +input Test_en_W_in ; +output Test_en_W_out ; +output Test_en_E_out ; +input pReset_N_in ; +input Reset_E_in ; +input Reset_W_in ; +output Reset_W_out ; +output Reset_E_out ; +input prog_clk_0_N_in ; +input prog_clk_0_S_in ; +output prog_clk_0_S_out ; +output prog_clk_0_E_out ; +output prog_clk_0_W_out ; +output prog_clk_0_N_out ; +input clk_0_N_in ; +input clk_0_S_in ; + +wire p_abuf12 ; +wire p_abuf11 ; +wire p_abuf16 ; +wire prog_clk_0 ; +wire [0:0] prog_clk ; +wire [0:0] clk ; +wire clk_0 ; +wire [0:0] Test_en ; + +assign SC_IN_BOT = SC_IN_TOP ; +assign Test_en_W_in = Test_en_E_in ; +assign Reset_W_in = Reset_E_in ; +assign prog_clk[0] = prog_clk_0 ; +assign prog_clk_0_S_in = prog_clk_0_N_in ; +assign clk_0 = clk[0] ; +assign clk_0_S_in = clk_0_N_in ; + +grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( + .pReset ( pReset ) , + .prog_clk ( { prog_clk_0 } ) , + .Test_en ( Test_en ) , + .clb_I0 ( { top_width_0_height_0__pin_0_[0] , + top_width_0_height_0__pin_1_[0] } ) , + .clb_I0i ( { top_width_0_height_0__pin_2_[0] , + top_width_0_height_0__pin_3_[0] } ) , + .clb_I1 ( { top_width_0_height_0__pin_4_[0] , + top_width_0_height_0__pin_5_[0] } ) , + .clb_I1i ( { top_width_0_height_0__pin_6_[0] , + top_width_0_height_0__pin_7_[0] } ) , + .clb_I2 ( { top_width_0_height_0__pin_8_[0] , + top_width_0_height_0__pin_9_[0] } ) , + .clb_I2i ( { top_width_0_height_0__pin_10_[0] , + top_width_0_height_0__pin_11_[0] } ) , + .clb_I3 ( { top_width_0_height_0__pin_12_[0] , + top_width_0_height_0__pin_13_[0] } ) , + .clb_I3i ( { top_width_0_height_0__pin_14_[0] , + top_width_0_height_0__pin_15_[0] } ) , + .clb_I4 ( { right_width_0_height_0__pin_16_[0] , + right_width_0_height_0__pin_17_[0] } ) , + .clb_I4i ( { right_width_0_height_0__pin_18_[0] , + right_width_0_height_0__pin_19_[0] } ) , + .clb_I5 ( { right_width_0_height_0__pin_20_[0] , + right_width_0_height_0__pin_21_[0] } ) , + .clb_I5i ( { right_width_0_height_0__pin_22_[0] , + right_width_0_height_0__pin_23_[0] } ) , + .clb_I6 ( { right_width_0_height_0__pin_24_[0] , + right_width_0_height_0__pin_25_[0] } ) , + .clb_I6i ( { right_width_0_height_0__pin_26_[0] , + right_width_0_height_0__pin_27_[0] } ) , + .clb_I7 ( { right_width_0_height_0__pin_28_[0] , + right_width_0_height_0__pin_29_[0] } ) , + .clb_I7i ( { right_width_0_height_0__pin_30_[0] , + right_width_0_height_0__pin_31_[0] } ) , + .clb_reg_in ( top_width_0_height_0__pin_32_ ) , + .clb_sc_in ( { SC_IN_BOT } ) , + .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_522_ , aps_rename_523_ , aps_rename_524_ , + aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , + aps_rename_528_ , aps_rename_529_ , aps_rename_530_ , + aps_rename_531_ , right_width_0_height_0__pin_46_lower[0] , + right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , + aps_rename_535_ , right_width_0_height_0__pin_50_lower[0] , + aps_rename_537_ } ) , + .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , + .clb_sc_out ( { aps_rename_538_ } ) , + .clb_cout ( bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) , + .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , + .p_abuf2 ( top_width_0_height_0__pin_36_lower[0] ) , + .p_abuf3 ( top_width_0_height_0__pin_39_lower[0] ) , + .p_abuf4 ( top_width_0_height_0__pin_38_lower[0] ) , + .p_abuf5 ( top_width_0_height_0__pin_41_lower[0] ) , + .p_abuf6 ( top_width_0_height_0__pin_40_lower[0] ) , + .p_abuf7 ( top_width_0_height_0__pin_43_lower[0] ) , + .p_abuf8 ( top_width_0_height_0__pin_42_lower[0] ) , + .p_abuf9 ( right_width_0_height_0__pin_45_lower[0] ) , + .p_abuf10 ( right_width_0_height_0__pin_44_lower[0] ) , + .p_abuf11 ( p_abuf11 ) , .p_abuf12 ( p_abuf12 ) , + .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , + .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , + .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_178 ) , .p1 ( optlc_net_179 ) , + .p2 ( optlc_net_180 ) , .p3 ( optlc_net_181 ) , .p4 ( optlc_net_182 ) , + .p5 ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , + .X ( Test_en[0] ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_539_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_540_ ) ) ; +sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; +sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ; +sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_541_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_542_ ) ) ; +sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , + .X ( prog_clk_0 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_1184 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2185 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3186 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_4187 ) ) ; +sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , + .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_523_ ) , + .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_524_ ) , + .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_525_ ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_526_ ) , + .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_527_ ) , + .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_528_ ) , + .X ( top_width_0_height_0__pin_42_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_529_ ) , + .X ( top_width_0_height_0__pin_43_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_530_ ) , + .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_531_ ) , + .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , + .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_534_ ) , + .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_535_ ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) , + .X ( right_width_0_height_0__pin_50_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , + .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , + .Y ( Test_en_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_539_ ) , + .Y ( BUF_net_133 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , + .Y ( Test_en_E_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_178 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_179 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_180 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_181 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_542_ ) , + .X ( Reset_E_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3981324 ( .A ( ctsbuf_net_1184 ) , + .X ( prog_clk_0_S_out ) ) ; +sky130_fd_sc_hd__clkbuf_8 cts_buf_4031329 ( .A ( ctsbuf_net_2185 ) , + .X ( prog_clk_0_E_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_4081334 ( .A ( ctsbuf_net_3186 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_4131339 ( .A ( ctsbuf_net_4187 ) , + .X ( prog_clk_0_N_out ) ) ; +endmodule + + +module fpga_core ( pReset , prog_clk , Test_en , IO_ISOL_N , clk , Reset , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , ccff_head , ccff_tail , sc_head , + sc_tail , h_incr0 ) ; +input [0:0] pReset ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] IO_ISOL_N ; +input [0:0] clk ; +input [0:0] Reset ; +input [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +output [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +input sc_head ; +output sc_tail ; +input h_incr0 ; + +wire [0:0] cbx_1__0__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__0_ccff_tail ; +wire [0:29] cbx_1__0__0_chanx_left_out ; +wire [0:29] cbx_1__0__0_chanx_right_out ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__10_ccff_tail ; +wire [0:29] cbx_1__0__10_chanx_left_out ; +wire [0:29] cbx_1__0__10_chanx_right_out ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__11_ccff_tail ; +wire [0:29] cbx_1__0__11_chanx_left_out ; +wire [0:29] cbx_1__0__11_chanx_right_out ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__1_ccff_tail ; +wire [0:29] cbx_1__0__1_chanx_left_out ; +wire [0:29] cbx_1__0__1_chanx_right_out ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__2_ccff_tail ; +wire [0:29] cbx_1__0__2_chanx_left_out ; +wire [0:29] cbx_1__0__2_chanx_right_out ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__3_ccff_tail ; +wire [0:29] cbx_1__0__3_chanx_left_out ; +wire [0:29] cbx_1__0__3_chanx_right_out ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__4_ccff_tail ; +wire [0:29] cbx_1__0__4_chanx_left_out ; +wire [0:29] cbx_1__0__4_chanx_right_out ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__5_ccff_tail ; +wire [0:29] cbx_1__0__5_chanx_left_out ; +wire [0:29] cbx_1__0__5_chanx_right_out ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__6_ccff_tail ; +wire [0:29] cbx_1__0__6_chanx_left_out ; +wire [0:29] cbx_1__0__6_chanx_right_out ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__7_ccff_tail ; +wire [0:29] cbx_1__0__7_chanx_left_out ; +wire [0:29] cbx_1__0__7_chanx_right_out ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__8_ccff_tail ; +wire [0:29] cbx_1__0__8_chanx_left_out ; +wire [0:29] cbx_1__0__8_chanx_right_out ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_16_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__0__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__0__9_ccff_tail ; +wire [0:29] cbx_1__0__9_chanx_left_out ; +wire [0:29] cbx_1__0__9_chanx_right_out ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__0_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__0_ccff_tail ; +wire [0:29] cbx_1__12__0_chanx_left_out ; +wire [0:29] cbx_1__12__0_chanx_right_out ; +wire [0:0] cbx_1__12__0_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__10_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__10_ccff_tail ; +wire [0:29] cbx_1__12__10_chanx_left_out ; +wire [0:29] cbx_1__12__10_chanx_right_out ; +wire [0:0] cbx_1__12__10_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__11_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__11_ccff_tail ; +wire [0:29] cbx_1__12__11_chanx_left_out ; +wire [0:29] cbx_1__12__11_chanx_right_out ; +wire [0:0] cbx_1__12__11_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__1_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__1_ccff_tail ; +wire [0:29] cbx_1__12__1_chanx_left_out ; +wire [0:29] cbx_1__12__1_chanx_right_out ; +wire [0:0] cbx_1__12__1_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__2_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__2_ccff_tail ; +wire [0:29] cbx_1__12__2_chanx_left_out ; +wire [0:29] cbx_1__12__2_chanx_right_out ; +wire [0:0] cbx_1__12__2_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__3_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__3_ccff_tail ; +wire [0:29] cbx_1__12__3_chanx_left_out ; +wire [0:29] cbx_1__12__3_chanx_right_out ; +wire [0:0] cbx_1__12__3_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__4_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__4_ccff_tail ; +wire [0:29] cbx_1__12__4_chanx_left_out ; +wire [0:29] cbx_1__12__4_chanx_right_out ; +wire [0:0] cbx_1__12__4_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__5_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__5_ccff_tail ; +wire [0:29] cbx_1__12__5_chanx_left_out ; +wire [0:29] cbx_1__12__5_chanx_right_out ; +wire [0:0] cbx_1__12__5_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__6_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__6_ccff_tail ; +wire [0:29] cbx_1__12__6_chanx_left_out ; +wire [0:29] cbx_1__12__6_chanx_right_out ; +wire [0:0] cbx_1__12__6_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__7_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__7_ccff_tail ; +wire [0:29] cbx_1__12__7_chanx_left_out ; +wire [0:29] cbx_1__12__7_chanx_right_out ; +wire [0:0] cbx_1__12__7_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__8_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__8_ccff_tail ; +wire [0:29] cbx_1__12__8_chanx_left_out ; +wire [0:29] cbx_1__12__8_chanx_right_out ; +wire [0:0] cbx_1__12__8_top_grid_pin_0_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__12__9_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__12__9_ccff_tail ; +wire [0:29] cbx_1__12__9_chanx_left_out ; +wire [0:29] cbx_1__12__9_chanx_right_out ; +wire [0:0] cbx_1__12__9_top_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__0_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__0_ccff_tail ; +wire [0:29] cbx_1__1__0_chanx_left_out ; +wire [0:29] cbx_1__1__0_chanx_right_out ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__100_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__100_ccff_tail ; +wire [0:29] cbx_1__1__100_chanx_left_out ; +wire [0:29] cbx_1__1__100_chanx_right_out ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__101_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__101_ccff_tail ; +wire [0:29] cbx_1__1__101_chanx_left_out ; +wire [0:29] cbx_1__1__101_chanx_right_out ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__102_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__102_ccff_tail ; +wire [0:29] cbx_1__1__102_chanx_left_out ; +wire [0:29] cbx_1__1__102_chanx_right_out ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__103_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__103_ccff_tail ; +wire [0:29] cbx_1__1__103_chanx_left_out ; +wire [0:29] cbx_1__1__103_chanx_right_out ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__104_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__104_ccff_tail ; +wire [0:29] cbx_1__1__104_chanx_left_out ; +wire [0:29] cbx_1__1__104_chanx_right_out ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__105_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__105_ccff_tail ; +wire [0:29] cbx_1__1__105_chanx_left_out ; +wire [0:29] cbx_1__1__105_chanx_right_out ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__106_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__106_ccff_tail ; +wire [0:29] cbx_1__1__106_chanx_left_out ; +wire [0:29] cbx_1__1__106_chanx_right_out ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__107_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__107_ccff_tail ; +wire [0:29] cbx_1__1__107_chanx_left_out ; +wire [0:29] cbx_1__1__107_chanx_right_out ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__108_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__108_ccff_tail ; +wire [0:29] cbx_1__1__108_chanx_left_out ; +wire [0:29] cbx_1__1__108_chanx_right_out ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__109_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__109_ccff_tail ; +wire [0:29] cbx_1__1__109_chanx_left_out ; +wire [0:29] cbx_1__1__109_chanx_right_out ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__10_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__10_ccff_tail ; +wire [0:29] cbx_1__1__10_chanx_left_out ; +wire [0:29] cbx_1__1__10_chanx_right_out ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__110_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__110_ccff_tail ; +wire [0:29] cbx_1__1__110_chanx_left_out ; +wire [0:29] cbx_1__1__110_chanx_right_out ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__111_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__111_ccff_tail ; +wire [0:29] cbx_1__1__111_chanx_left_out ; +wire [0:29] cbx_1__1__111_chanx_right_out ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__112_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__112_ccff_tail ; +wire [0:29] cbx_1__1__112_chanx_left_out ; +wire [0:29] cbx_1__1__112_chanx_right_out ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__113_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__113_ccff_tail ; +wire [0:29] cbx_1__1__113_chanx_left_out ; +wire [0:29] cbx_1__1__113_chanx_right_out ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__114_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__114_ccff_tail ; +wire [0:29] cbx_1__1__114_chanx_left_out ; +wire [0:29] cbx_1__1__114_chanx_right_out ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__115_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__115_ccff_tail ; +wire [0:29] cbx_1__1__115_chanx_left_out ; +wire [0:29] cbx_1__1__115_chanx_right_out ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__116_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__116_ccff_tail ; +wire [0:29] cbx_1__1__116_chanx_left_out ; +wire [0:29] cbx_1__1__116_chanx_right_out ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__117_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__117_ccff_tail ; +wire [0:29] cbx_1__1__117_chanx_left_out ; +wire [0:29] cbx_1__1__117_chanx_right_out ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__118_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__118_ccff_tail ; +wire [0:29] cbx_1__1__118_chanx_left_out ; +wire [0:29] cbx_1__1__118_chanx_right_out ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__119_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__119_ccff_tail ; +wire [0:29] cbx_1__1__119_chanx_left_out ; +wire [0:29] cbx_1__1__119_chanx_right_out ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__11_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__11_ccff_tail ; +wire [0:29] cbx_1__1__11_chanx_left_out ; +wire [0:29] cbx_1__1__11_chanx_right_out ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__120_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__120_ccff_tail ; +wire [0:29] cbx_1__1__120_chanx_left_out ; +wire [0:29] cbx_1__1__120_chanx_right_out ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__121_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__121_ccff_tail ; +wire [0:29] cbx_1__1__121_chanx_left_out ; +wire [0:29] cbx_1__1__121_chanx_right_out ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__122_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__122_ccff_tail ; +wire [0:29] cbx_1__1__122_chanx_left_out ; +wire [0:29] cbx_1__1__122_chanx_right_out ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__123_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__123_ccff_tail ; +wire [0:29] cbx_1__1__123_chanx_left_out ; +wire [0:29] cbx_1__1__123_chanx_right_out ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__124_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__124_ccff_tail ; +wire [0:29] cbx_1__1__124_chanx_left_out ; +wire [0:29] cbx_1__1__124_chanx_right_out ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__125_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__125_ccff_tail ; +wire [0:29] cbx_1__1__125_chanx_left_out ; +wire [0:29] cbx_1__1__125_chanx_right_out ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__126_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__126_ccff_tail ; +wire [0:29] cbx_1__1__126_chanx_left_out ; +wire [0:29] cbx_1__1__126_chanx_right_out ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__127_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__127_ccff_tail ; +wire [0:29] cbx_1__1__127_chanx_left_out ; +wire [0:29] cbx_1__1__127_chanx_right_out ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__128_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__128_ccff_tail ; +wire [0:29] cbx_1__1__128_chanx_left_out ; +wire [0:29] cbx_1__1__128_chanx_right_out ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__129_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__129_ccff_tail ; +wire [0:29] cbx_1__1__129_chanx_left_out ; +wire [0:29] cbx_1__1__129_chanx_right_out ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__12_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__12_ccff_tail ; +wire [0:29] cbx_1__1__12_chanx_left_out ; +wire [0:29] cbx_1__1__12_chanx_right_out ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__130_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__130_ccff_tail ; +wire [0:29] cbx_1__1__130_chanx_left_out ; +wire [0:29] cbx_1__1__130_chanx_right_out ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__131_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__131_ccff_tail ; +wire [0:29] cbx_1__1__131_chanx_left_out ; +wire [0:29] cbx_1__1__131_chanx_right_out ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__13_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__13_ccff_tail ; +wire [0:29] cbx_1__1__13_chanx_left_out ; +wire [0:29] cbx_1__1__13_chanx_right_out ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__14_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__14_ccff_tail ; +wire [0:29] cbx_1__1__14_chanx_left_out ; +wire [0:29] cbx_1__1__14_chanx_right_out ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__15_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__15_ccff_tail ; +wire [0:29] cbx_1__1__15_chanx_left_out ; +wire [0:29] cbx_1__1__15_chanx_right_out ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__16_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__16_ccff_tail ; +wire [0:29] cbx_1__1__16_chanx_left_out ; +wire [0:29] cbx_1__1__16_chanx_right_out ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__17_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__17_ccff_tail ; +wire [0:29] cbx_1__1__17_chanx_left_out ; +wire [0:29] cbx_1__1__17_chanx_right_out ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__18_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__18_ccff_tail ; +wire [0:29] cbx_1__1__18_chanx_left_out ; +wire [0:29] cbx_1__1__18_chanx_right_out ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__19_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__19_ccff_tail ; +wire [0:29] cbx_1__1__19_chanx_left_out ; +wire [0:29] cbx_1__1__19_chanx_right_out ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__1_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__1_ccff_tail ; +wire [0:29] cbx_1__1__1_chanx_left_out ; +wire [0:29] cbx_1__1__1_chanx_right_out ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__20_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__20_ccff_tail ; +wire [0:29] cbx_1__1__20_chanx_left_out ; +wire [0:29] cbx_1__1__20_chanx_right_out ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__21_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__21_ccff_tail ; +wire [0:29] cbx_1__1__21_chanx_left_out ; +wire [0:29] cbx_1__1__21_chanx_right_out ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__22_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__22_ccff_tail ; +wire [0:29] cbx_1__1__22_chanx_left_out ; +wire [0:29] cbx_1__1__22_chanx_right_out ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__23_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__23_ccff_tail ; +wire [0:29] cbx_1__1__23_chanx_left_out ; +wire [0:29] cbx_1__1__23_chanx_right_out ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__24_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__24_ccff_tail ; +wire [0:29] cbx_1__1__24_chanx_left_out ; +wire [0:29] cbx_1__1__24_chanx_right_out ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__25_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__25_ccff_tail ; +wire [0:29] cbx_1__1__25_chanx_left_out ; +wire [0:29] cbx_1__1__25_chanx_right_out ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__26_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__26_ccff_tail ; +wire [0:29] cbx_1__1__26_chanx_left_out ; +wire [0:29] cbx_1__1__26_chanx_right_out ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__27_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__27_ccff_tail ; +wire [0:29] cbx_1__1__27_chanx_left_out ; +wire [0:29] cbx_1__1__27_chanx_right_out ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__28_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__28_ccff_tail ; +wire [0:29] cbx_1__1__28_chanx_left_out ; +wire [0:29] cbx_1__1__28_chanx_right_out ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__29_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__29_ccff_tail ; +wire [0:29] cbx_1__1__29_chanx_left_out ; +wire [0:29] cbx_1__1__29_chanx_right_out ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__2_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__2_ccff_tail ; +wire [0:29] cbx_1__1__2_chanx_left_out ; +wire [0:29] cbx_1__1__2_chanx_right_out ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__30_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__30_ccff_tail ; +wire [0:29] cbx_1__1__30_chanx_left_out ; +wire [0:29] cbx_1__1__30_chanx_right_out ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__31_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__31_ccff_tail ; +wire [0:29] cbx_1__1__31_chanx_left_out ; +wire [0:29] cbx_1__1__31_chanx_right_out ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__32_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__32_ccff_tail ; +wire [0:29] cbx_1__1__32_chanx_left_out ; +wire [0:29] cbx_1__1__32_chanx_right_out ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__33_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__33_ccff_tail ; +wire [0:29] cbx_1__1__33_chanx_left_out ; +wire [0:29] cbx_1__1__33_chanx_right_out ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__34_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__34_ccff_tail ; +wire [0:29] cbx_1__1__34_chanx_left_out ; +wire [0:29] cbx_1__1__34_chanx_right_out ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__35_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__35_ccff_tail ; +wire [0:29] cbx_1__1__35_chanx_left_out ; +wire [0:29] cbx_1__1__35_chanx_right_out ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__36_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__36_ccff_tail ; +wire [0:29] cbx_1__1__36_chanx_left_out ; +wire [0:29] cbx_1__1__36_chanx_right_out ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__37_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__37_ccff_tail ; +wire [0:29] cbx_1__1__37_chanx_left_out ; +wire [0:29] cbx_1__1__37_chanx_right_out ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__38_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__38_ccff_tail ; +wire [0:29] cbx_1__1__38_chanx_left_out ; +wire [0:29] cbx_1__1__38_chanx_right_out ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__39_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__39_ccff_tail ; +wire [0:29] cbx_1__1__39_chanx_left_out ; +wire [0:29] cbx_1__1__39_chanx_right_out ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__3_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__3_ccff_tail ; +wire [0:29] cbx_1__1__3_chanx_left_out ; +wire [0:29] cbx_1__1__3_chanx_right_out ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__40_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__40_ccff_tail ; +wire [0:29] cbx_1__1__40_chanx_left_out ; +wire [0:29] cbx_1__1__40_chanx_right_out ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__41_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__41_ccff_tail ; +wire [0:29] cbx_1__1__41_chanx_left_out ; +wire [0:29] cbx_1__1__41_chanx_right_out ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__42_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__42_ccff_tail ; +wire [0:29] cbx_1__1__42_chanx_left_out ; +wire [0:29] cbx_1__1__42_chanx_right_out ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__43_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__43_ccff_tail ; +wire [0:29] cbx_1__1__43_chanx_left_out ; +wire [0:29] cbx_1__1__43_chanx_right_out ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__44_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__44_ccff_tail ; +wire [0:29] cbx_1__1__44_chanx_left_out ; +wire [0:29] cbx_1__1__44_chanx_right_out ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__45_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__45_ccff_tail ; +wire [0:29] cbx_1__1__45_chanx_left_out ; +wire [0:29] cbx_1__1__45_chanx_right_out ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__46_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__46_ccff_tail ; +wire [0:29] cbx_1__1__46_chanx_left_out ; +wire [0:29] cbx_1__1__46_chanx_right_out ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__47_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__47_ccff_tail ; +wire [0:29] cbx_1__1__47_chanx_left_out ; +wire [0:29] cbx_1__1__47_chanx_right_out ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__48_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__48_ccff_tail ; +wire [0:29] cbx_1__1__48_chanx_left_out ; +wire [0:29] cbx_1__1__48_chanx_right_out ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__49_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__49_ccff_tail ; +wire [0:29] cbx_1__1__49_chanx_left_out ; +wire [0:29] cbx_1__1__49_chanx_right_out ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__4_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__4_ccff_tail ; +wire [0:29] cbx_1__1__4_chanx_left_out ; +wire [0:29] cbx_1__1__4_chanx_right_out ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__50_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__50_ccff_tail ; +wire [0:29] cbx_1__1__50_chanx_left_out ; +wire [0:29] cbx_1__1__50_chanx_right_out ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__51_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__51_ccff_tail ; +wire [0:29] cbx_1__1__51_chanx_left_out ; +wire [0:29] cbx_1__1__51_chanx_right_out ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__52_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__52_ccff_tail ; +wire [0:29] cbx_1__1__52_chanx_left_out ; +wire [0:29] cbx_1__1__52_chanx_right_out ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__53_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__53_ccff_tail ; +wire [0:29] cbx_1__1__53_chanx_left_out ; +wire [0:29] cbx_1__1__53_chanx_right_out ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__54_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__54_ccff_tail ; +wire [0:29] cbx_1__1__54_chanx_left_out ; +wire [0:29] cbx_1__1__54_chanx_right_out ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__55_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__55_ccff_tail ; +wire [0:29] cbx_1__1__55_chanx_left_out ; +wire [0:29] cbx_1__1__55_chanx_right_out ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__56_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__56_ccff_tail ; +wire [0:29] cbx_1__1__56_chanx_left_out ; +wire [0:29] cbx_1__1__56_chanx_right_out ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__57_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__57_ccff_tail ; +wire [0:29] cbx_1__1__57_chanx_left_out ; +wire [0:29] cbx_1__1__57_chanx_right_out ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__58_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__58_ccff_tail ; +wire [0:29] cbx_1__1__58_chanx_left_out ; +wire [0:29] cbx_1__1__58_chanx_right_out ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__59_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__59_ccff_tail ; +wire [0:29] cbx_1__1__59_chanx_left_out ; +wire [0:29] cbx_1__1__59_chanx_right_out ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__5_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__5_ccff_tail ; +wire [0:29] cbx_1__1__5_chanx_left_out ; +wire [0:29] cbx_1__1__5_chanx_right_out ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__60_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__60_ccff_tail ; +wire [0:29] cbx_1__1__60_chanx_left_out ; +wire [0:29] cbx_1__1__60_chanx_right_out ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__61_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__61_ccff_tail ; +wire [0:29] cbx_1__1__61_chanx_left_out ; +wire [0:29] cbx_1__1__61_chanx_right_out ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__62_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__62_ccff_tail ; +wire [0:29] cbx_1__1__62_chanx_left_out ; +wire [0:29] cbx_1__1__62_chanx_right_out ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__63_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__63_ccff_tail ; +wire [0:29] cbx_1__1__63_chanx_left_out ; +wire [0:29] cbx_1__1__63_chanx_right_out ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__64_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__64_ccff_tail ; +wire [0:29] cbx_1__1__64_chanx_left_out ; +wire [0:29] cbx_1__1__64_chanx_right_out ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__65_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__65_ccff_tail ; +wire [0:29] cbx_1__1__65_chanx_left_out ; +wire [0:29] cbx_1__1__65_chanx_right_out ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__66_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__66_ccff_tail ; +wire [0:29] cbx_1__1__66_chanx_left_out ; +wire [0:29] cbx_1__1__66_chanx_right_out ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__67_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__67_ccff_tail ; +wire [0:29] cbx_1__1__67_chanx_left_out ; +wire [0:29] cbx_1__1__67_chanx_right_out ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__68_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__68_ccff_tail ; +wire [0:29] cbx_1__1__68_chanx_left_out ; +wire [0:29] cbx_1__1__68_chanx_right_out ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__69_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__69_ccff_tail ; +wire [0:29] cbx_1__1__69_chanx_left_out ; +wire [0:29] cbx_1__1__69_chanx_right_out ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__6_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__6_ccff_tail ; +wire [0:29] cbx_1__1__6_chanx_left_out ; +wire [0:29] cbx_1__1__6_chanx_right_out ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__70_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__70_ccff_tail ; +wire [0:29] cbx_1__1__70_chanx_left_out ; +wire [0:29] cbx_1__1__70_chanx_right_out ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__71_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__71_ccff_tail ; +wire [0:29] cbx_1__1__71_chanx_left_out ; +wire [0:29] cbx_1__1__71_chanx_right_out ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__72_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__72_ccff_tail ; +wire [0:29] cbx_1__1__72_chanx_left_out ; +wire [0:29] cbx_1__1__72_chanx_right_out ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__73_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__73_ccff_tail ; +wire [0:29] cbx_1__1__73_chanx_left_out ; +wire [0:29] cbx_1__1__73_chanx_right_out ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__74_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__74_ccff_tail ; +wire [0:29] cbx_1__1__74_chanx_left_out ; +wire [0:29] cbx_1__1__74_chanx_right_out ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__75_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__75_ccff_tail ; +wire [0:29] cbx_1__1__75_chanx_left_out ; +wire [0:29] cbx_1__1__75_chanx_right_out ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__76_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__76_ccff_tail ; +wire [0:29] cbx_1__1__76_chanx_left_out ; +wire [0:29] cbx_1__1__76_chanx_right_out ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__77_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__77_ccff_tail ; +wire [0:29] cbx_1__1__77_chanx_left_out ; +wire [0:29] cbx_1__1__77_chanx_right_out ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__78_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__78_ccff_tail ; +wire [0:29] cbx_1__1__78_chanx_left_out ; +wire [0:29] cbx_1__1__78_chanx_right_out ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__79_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__79_ccff_tail ; +wire [0:29] cbx_1__1__79_chanx_left_out ; +wire [0:29] cbx_1__1__79_chanx_right_out ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__7_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__7_ccff_tail ; +wire [0:29] cbx_1__1__7_chanx_left_out ; +wire [0:29] cbx_1__1__7_chanx_right_out ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__80_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__80_ccff_tail ; +wire [0:29] cbx_1__1__80_chanx_left_out ; +wire [0:29] cbx_1__1__80_chanx_right_out ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__81_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__81_ccff_tail ; +wire [0:29] cbx_1__1__81_chanx_left_out ; +wire [0:29] cbx_1__1__81_chanx_right_out ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__82_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__82_ccff_tail ; +wire [0:29] cbx_1__1__82_chanx_left_out ; +wire [0:29] cbx_1__1__82_chanx_right_out ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__83_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__83_ccff_tail ; +wire [0:29] cbx_1__1__83_chanx_left_out ; +wire [0:29] cbx_1__1__83_chanx_right_out ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__84_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__84_ccff_tail ; +wire [0:29] cbx_1__1__84_chanx_left_out ; +wire [0:29] cbx_1__1__84_chanx_right_out ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__85_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__85_ccff_tail ; +wire [0:29] cbx_1__1__85_chanx_left_out ; +wire [0:29] cbx_1__1__85_chanx_right_out ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__86_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__86_ccff_tail ; +wire [0:29] cbx_1__1__86_chanx_left_out ; +wire [0:29] cbx_1__1__86_chanx_right_out ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__87_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__87_ccff_tail ; +wire [0:29] cbx_1__1__87_chanx_left_out ; +wire [0:29] cbx_1__1__87_chanx_right_out ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__88_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__88_ccff_tail ; +wire [0:29] cbx_1__1__88_chanx_left_out ; +wire [0:29] cbx_1__1__88_chanx_right_out ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__89_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__89_ccff_tail ; +wire [0:29] cbx_1__1__89_chanx_left_out ; +wire [0:29] cbx_1__1__89_chanx_right_out ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__8_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__8_ccff_tail ; +wire [0:29] cbx_1__1__8_chanx_left_out ; +wire [0:29] cbx_1__1__8_chanx_right_out ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__90_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__90_ccff_tail ; +wire [0:29] cbx_1__1__90_chanx_left_out ; +wire [0:29] cbx_1__1__90_chanx_right_out ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__91_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__91_ccff_tail ; +wire [0:29] cbx_1__1__91_chanx_left_out ; +wire [0:29] cbx_1__1__91_chanx_right_out ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__92_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__92_ccff_tail ; +wire [0:29] cbx_1__1__92_chanx_left_out ; +wire [0:29] cbx_1__1__92_chanx_right_out ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__93_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__93_ccff_tail ; +wire [0:29] cbx_1__1__93_chanx_left_out ; +wire [0:29] cbx_1__1__93_chanx_right_out ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__94_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__94_ccff_tail ; +wire [0:29] cbx_1__1__94_chanx_left_out ; +wire [0:29] cbx_1__1__94_chanx_right_out ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__95_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__95_ccff_tail ; +wire [0:29] cbx_1__1__95_chanx_left_out ; +wire [0:29] cbx_1__1__95_chanx_right_out ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__96_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__96_ccff_tail ; +wire [0:29] cbx_1__1__96_chanx_left_out ; +wire [0:29] cbx_1__1__96_chanx_right_out ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__97_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__97_ccff_tail ; +wire [0:29] cbx_1__1__97_chanx_left_out ; +wire [0:29] cbx_1__1__97_chanx_right_out ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__98_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__98_ccff_tail ; +wire [0:29] cbx_1__1__98_chanx_left_out ; +wire [0:29] cbx_1__1__98_chanx_right_out ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__99_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__99_ccff_tail ; +wire [0:29] cbx_1__1__99_chanx_left_out ; +wire [0:29] cbx_1__1__99_chanx_right_out ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_0_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_10_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_11_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_12_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_13_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_14_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_15_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_1_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_2_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_3_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_4_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_5_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_6_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_7_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_8_ ; +wire [0:0] cbx_1__1__9_bottom_grid_pin_9_ ; +wire [0:0] cbx_1__1__9_ccff_tail ; +wire [0:29] cbx_1__1__9_chanx_left_out ; +wire [0:29] cbx_1__1__9_chanx_right_out ; +wire [0:0] cby_0__1__0_ccff_tail ; +wire [0:29] cby_0__1__0_chany_bottom_out ; +wire [0:29] cby_0__1__0_chany_top_out ; +wire [0:0] cby_0__1__0_left_grid_pin_0_ ; +wire [0:0] cby_0__1__10_ccff_tail ; +wire [0:29] cby_0__1__10_chany_bottom_out ; +wire [0:29] cby_0__1__10_chany_top_out ; +wire [0:0] cby_0__1__10_left_grid_pin_0_ ; +wire [0:0] cby_0__1__11_ccff_tail ; +wire [0:29] cby_0__1__11_chany_bottom_out ; +wire [0:29] cby_0__1__11_chany_top_out ; +wire [0:0] cby_0__1__11_left_grid_pin_0_ ; +wire [0:0] cby_0__1__1_ccff_tail ; +wire [0:29] cby_0__1__1_chany_bottom_out ; +wire [0:29] cby_0__1__1_chany_top_out ; +wire [0:0] cby_0__1__1_left_grid_pin_0_ ; +wire [0:0] cby_0__1__2_ccff_tail ; +wire [0:29] cby_0__1__2_chany_bottom_out ; +wire [0:29] cby_0__1__2_chany_top_out ; +wire [0:0] cby_0__1__2_left_grid_pin_0_ ; +wire [0:0] cby_0__1__3_ccff_tail ; +wire [0:29] cby_0__1__3_chany_bottom_out ; +wire [0:29] cby_0__1__3_chany_top_out ; +wire [0:0] cby_0__1__3_left_grid_pin_0_ ; +wire [0:0] cby_0__1__4_ccff_tail ; +wire [0:29] cby_0__1__4_chany_bottom_out ; +wire [0:29] cby_0__1__4_chany_top_out ; +wire [0:0] cby_0__1__4_left_grid_pin_0_ ; +wire [0:0] cby_0__1__5_ccff_tail ; +wire [0:29] cby_0__1__5_chany_bottom_out ; +wire [0:29] cby_0__1__5_chany_top_out ; +wire [0:0] cby_0__1__5_left_grid_pin_0_ ; +wire [0:0] cby_0__1__6_ccff_tail ; +wire [0:29] cby_0__1__6_chany_bottom_out ; +wire [0:29] cby_0__1__6_chany_top_out ; +wire [0:0] cby_0__1__6_left_grid_pin_0_ ; +wire [0:0] cby_0__1__7_ccff_tail ; +wire [0:29] cby_0__1__7_chany_bottom_out ; +wire [0:29] cby_0__1__7_chany_top_out ; +wire [0:0] cby_0__1__7_left_grid_pin_0_ ; +wire [0:0] cby_0__1__8_ccff_tail ; +wire [0:29] cby_0__1__8_chany_bottom_out ; +wire [0:29] cby_0__1__8_chany_top_out ; +wire [0:0] cby_0__1__8_left_grid_pin_0_ ; +wire [0:0] cby_0__1__9_ccff_tail ; +wire [0:29] cby_0__1__9_chany_bottom_out ; +wire [0:29] cby_0__1__9_chany_top_out ; +wire [0:0] cby_0__1__9_left_grid_pin_0_ ; +wire [0:0] cby_12__1__0_ccff_tail ; +wire [0:29] cby_12__1__0_chany_bottom_out ; +wire [0:29] cby_12__1__0_chany_top_out ; +wire [0:0] cby_12__1__0_left_grid_pin_16_ ; +wire [0:0] cby_12__1__0_left_grid_pin_17_ ; +wire [0:0] cby_12__1__0_left_grid_pin_18_ ; +wire [0:0] cby_12__1__0_left_grid_pin_19_ ; +wire [0:0] cby_12__1__0_left_grid_pin_20_ ; +wire [0:0] cby_12__1__0_left_grid_pin_21_ ; +wire [0:0] cby_12__1__0_left_grid_pin_22_ ; +wire [0:0] cby_12__1__0_left_grid_pin_23_ ; +wire [0:0] cby_12__1__0_left_grid_pin_24_ ; +wire [0:0] cby_12__1__0_left_grid_pin_25_ ; +wire [0:0] cby_12__1__0_left_grid_pin_26_ ; +wire [0:0] cby_12__1__0_left_grid_pin_27_ ; +wire [0:0] cby_12__1__0_left_grid_pin_28_ ; +wire [0:0] cby_12__1__0_left_grid_pin_29_ ; +wire [0:0] cby_12__1__0_left_grid_pin_30_ ; +wire [0:0] cby_12__1__0_left_grid_pin_31_ ; +wire [0:0] cby_12__1__0_right_grid_pin_0_ ; +wire [0:0] cby_12__1__10_ccff_tail ; +wire [0:29] cby_12__1__10_chany_bottom_out ; +wire [0:29] cby_12__1__10_chany_top_out ; +wire [0:0] cby_12__1__10_left_grid_pin_16_ ; +wire [0:0] cby_12__1__10_left_grid_pin_17_ ; +wire [0:0] cby_12__1__10_left_grid_pin_18_ ; +wire [0:0] cby_12__1__10_left_grid_pin_19_ ; +wire [0:0] cby_12__1__10_left_grid_pin_20_ ; +wire [0:0] cby_12__1__10_left_grid_pin_21_ ; +wire [0:0] cby_12__1__10_left_grid_pin_22_ ; +wire [0:0] cby_12__1__10_left_grid_pin_23_ ; +wire [0:0] cby_12__1__10_left_grid_pin_24_ ; +wire [0:0] cby_12__1__10_left_grid_pin_25_ ; +wire [0:0] cby_12__1__10_left_grid_pin_26_ ; +wire [0:0] cby_12__1__10_left_grid_pin_27_ ; +wire [0:0] cby_12__1__10_left_grid_pin_28_ ; +wire [0:0] cby_12__1__10_left_grid_pin_29_ ; +wire [0:0] cby_12__1__10_left_grid_pin_30_ ; +wire [0:0] cby_12__1__10_left_grid_pin_31_ ; +wire [0:0] cby_12__1__10_right_grid_pin_0_ ; +wire [0:0] cby_12__1__11_ccff_tail ; +wire [0:29] cby_12__1__11_chany_bottom_out ; +wire [0:29] cby_12__1__11_chany_top_out ; +wire [0:0] cby_12__1__11_left_grid_pin_16_ ; +wire [0:0] cby_12__1__11_left_grid_pin_17_ ; +wire [0:0] cby_12__1__11_left_grid_pin_18_ ; +wire [0:0] cby_12__1__11_left_grid_pin_19_ ; +wire [0:0] cby_12__1__11_left_grid_pin_20_ ; +wire [0:0] cby_12__1__11_left_grid_pin_21_ ; +wire [0:0] cby_12__1__11_left_grid_pin_22_ ; +wire [0:0] cby_12__1__11_left_grid_pin_23_ ; +wire [0:0] cby_12__1__11_left_grid_pin_24_ ; +wire [0:0] cby_12__1__11_left_grid_pin_25_ ; +wire [0:0] cby_12__1__11_left_grid_pin_26_ ; +wire [0:0] cby_12__1__11_left_grid_pin_27_ ; +wire [0:0] cby_12__1__11_left_grid_pin_28_ ; +wire [0:0] cby_12__1__11_left_grid_pin_29_ ; +wire [0:0] cby_12__1__11_left_grid_pin_30_ ; +wire [0:0] cby_12__1__11_left_grid_pin_31_ ; +wire [0:0] cby_12__1__11_right_grid_pin_0_ ; +wire [0:0] cby_12__1__1_ccff_tail ; +wire [0:29] cby_12__1__1_chany_bottom_out ; +wire [0:29] cby_12__1__1_chany_top_out ; +wire [0:0] cby_12__1__1_left_grid_pin_16_ ; +wire [0:0] cby_12__1__1_left_grid_pin_17_ ; +wire [0:0] cby_12__1__1_left_grid_pin_18_ ; +wire [0:0] cby_12__1__1_left_grid_pin_19_ ; +wire [0:0] cby_12__1__1_left_grid_pin_20_ ; +wire [0:0] cby_12__1__1_left_grid_pin_21_ ; +wire [0:0] cby_12__1__1_left_grid_pin_22_ ; +wire [0:0] cby_12__1__1_left_grid_pin_23_ ; +wire [0:0] cby_12__1__1_left_grid_pin_24_ ; +wire [0:0] cby_12__1__1_left_grid_pin_25_ ; +wire [0:0] cby_12__1__1_left_grid_pin_26_ ; +wire [0:0] cby_12__1__1_left_grid_pin_27_ ; +wire [0:0] cby_12__1__1_left_grid_pin_28_ ; +wire [0:0] cby_12__1__1_left_grid_pin_29_ ; +wire [0:0] cby_12__1__1_left_grid_pin_30_ ; +wire [0:0] cby_12__1__1_left_grid_pin_31_ ; +wire [0:0] cby_12__1__1_right_grid_pin_0_ ; +wire [0:0] cby_12__1__2_ccff_tail ; +wire [0:29] cby_12__1__2_chany_bottom_out ; +wire [0:29] cby_12__1__2_chany_top_out ; +wire [0:0] cby_12__1__2_left_grid_pin_16_ ; +wire [0:0] cby_12__1__2_left_grid_pin_17_ ; +wire [0:0] cby_12__1__2_left_grid_pin_18_ ; +wire [0:0] cby_12__1__2_left_grid_pin_19_ ; +wire [0:0] cby_12__1__2_left_grid_pin_20_ ; +wire [0:0] cby_12__1__2_left_grid_pin_21_ ; +wire [0:0] cby_12__1__2_left_grid_pin_22_ ; +wire [0:0] cby_12__1__2_left_grid_pin_23_ ; +wire [0:0] cby_12__1__2_left_grid_pin_24_ ; +wire [0:0] cby_12__1__2_left_grid_pin_25_ ; +wire [0:0] cby_12__1__2_left_grid_pin_26_ ; +wire [0:0] cby_12__1__2_left_grid_pin_27_ ; +wire [0:0] cby_12__1__2_left_grid_pin_28_ ; +wire [0:0] cby_12__1__2_left_grid_pin_29_ ; +wire [0:0] cby_12__1__2_left_grid_pin_30_ ; +wire [0:0] cby_12__1__2_left_grid_pin_31_ ; +wire [0:0] cby_12__1__2_right_grid_pin_0_ ; +wire [0:0] cby_12__1__3_ccff_tail ; +wire [0:29] cby_12__1__3_chany_bottom_out ; +wire [0:29] cby_12__1__3_chany_top_out ; +wire [0:0] cby_12__1__3_left_grid_pin_16_ ; +wire [0:0] cby_12__1__3_left_grid_pin_17_ ; +wire [0:0] cby_12__1__3_left_grid_pin_18_ ; +wire [0:0] cby_12__1__3_left_grid_pin_19_ ; +wire [0:0] cby_12__1__3_left_grid_pin_20_ ; +wire [0:0] cby_12__1__3_left_grid_pin_21_ ; +wire [0:0] cby_12__1__3_left_grid_pin_22_ ; +wire [0:0] cby_12__1__3_left_grid_pin_23_ ; +wire [0:0] cby_12__1__3_left_grid_pin_24_ ; +wire [0:0] cby_12__1__3_left_grid_pin_25_ ; +wire [0:0] cby_12__1__3_left_grid_pin_26_ ; +wire [0:0] cby_12__1__3_left_grid_pin_27_ ; +wire [0:0] cby_12__1__3_left_grid_pin_28_ ; +wire [0:0] cby_12__1__3_left_grid_pin_29_ ; +wire [0:0] cby_12__1__3_left_grid_pin_30_ ; +wire [0:0] cby_12__1__3_left_grid_pin_31_ ; +wire [0:0] cby_12__1__3_right_grid_pin_0_ ; +wire [0:0] cby_12__1__4_ccff_tail ; +wire [0:29] cby_12__1__4_chany_bottom_out ; +wire [0:29] cby_12__1__4_chany_top_out ; +wire [0:0] cby_12__1__4_left_grid_pin_16_ ; +wire [0:0] cby_12__1__4_left_grid_pin_17_ ; +wire [0:0] cby_12__1__4_left_grid_pin_18_ ; +wire [0:0] cby_12__1__4_left_grid_pin_19_ ; +wire [0:0] cby_12__1__4_left_grid_pin_20_ ; +wire [0:0] cby_12__1__4_left_grid_pin_21_ ; +wire [0:0] cby_12__1__4_left_grid_pin_22_ ; +wire [0:0] cby_12__1__4_left_grid_pin_23_ ; +wire [0:0] cby_12__1__4_left_grid_pin_24_ ; +wire [0:0] cby_12__1__4_left_grid_pin_25_ ; +wire [0:0] cby_12__1__4_left_grid_pin_26_ ; +wire [0:0] cby_12__1__4_left_grid_pin_27_ ; +wire [0:0] cby_12__1__4_left_grid_pin_28_ ; +wire [0:0] cby_12__1__4_left_grid_pin_29_ ; +wire [0:0] cby_12__1__4_left_grid_pin_30_ ; +wire [0:0] cby_12__1__4_left_grid_pin_31_ ; +wire [0:0] cby_12__1__4_right_grid_pin_0_ ; +wire [0:0] cby_12__1__5_ccff_tail ; +wire [0:29] cby_12__1__5_chany_bottom_out ; +wire [0:29] cby_12__1__5_chany_top_out ; +wire [0:0] cby_12__1__5_left_grid_pin_16_ ; +wire [0:0] cby_12__1__5_left_grid_pin_17_ ; +wire [0:0] cby_12__1__5_left_grid_pin_18_ ; +wire [0:0] cby_12__1__5_left_grid_pin_19_ ; +wire [0:0] cby_12__1__5_left_grid_pin_20_ ; +wire [0:0] cby_12__1__5_left_grid_pin_21_ ; +wire [0:0] cby_12__1__5_left_grid_pin_22_ ; +wire [0:0] cby_12__1__5_left_grid_pin_23_ ; +wire [0:0] cby_12__1__5_left_grid_pin_24_ ; +wire [0:0] cby_12__1__5_left_grid_pin_25_ ; +wire [0:0] cby_12__1__5_left_grid_pin_26_ ; +wire [0:0] cby_12__1__5_left_grid_pin_27_ ; +wire [0:0] cby_12__1__5_left_grid_pin_28_ ; +wire [0:0] cby_12__1__5_left_grid_pin_29_ ; +wire [0:0] cby_12__1__5_left_grid_pin_30_ ; +wire [0:0] cby_12__1__5_left_grid_pin_31_ ; +wire [0:0] cby_12__1__5_right_grid_pin_0_ ; +wire [0:0] cby_12__1__6_ccff_tail ; +wire [0:29] cby_12__1__6_chany_bottom_out ; +wire [0:29] cby_12__1__6_chany_top_out ; +wire [0:0] cby_12__1__6_left_grid_pin_16_ ; +wire [0:0] cby_12__1__6_left_grid_pin_17_ ; +wire [0:0] cby_12__1__6_left_grid_pin_18_ ; +wire [0:0] cby_12__1__6_left_grid_pin_19_ ; +wire [0:0] cby_12__1__6_left_grid_pin_20_ ; +wire [0:0] cby_12__1__6_left_grid_pin_21_ ; +wire [0:0] cby_12__1__6_left_grid_pin_22_ ; +wire [0:0] cby_12__1__6_left_grid_pin_23_ ; +wire [0:0] cby_12__1__6_left_grid_pin_24_ ; +wire [0:0] cby_12__1__6_left_grid_pin_25_ ; +wire [0:0] cby_12__1__6_left_grid_pin_26_ ; +wire [0:0] cby_12__1__6_left_grid_pin_27_ ; +wire [0:0] cby_12__1__6_left_grid_pin_28_ ; +wire [0:0] cby_12__1__6_left_grid_pin_29_ ; +wire [0:0] cby_12__1__6_left_grid_pin_30_ ; +wire [0:0] cby_12__1__6_left_grid_pin_31_ ; +wire [0:0] cby_12__1__6_right_grid_pin_0_ ; +wire [0:0] cby_12__1__7_ccff_tail ; +wire [0:29] cby_12__1__7_chany_bottom_out ; +wire [0:29] cby_12__1__7_chany_top_out ; +wire [0:0] cby_12__1__7_left_grid_pin_16_ ; +wire [0:0] cby_12__1__7_left_grid_pin_17_ ; +wire [0:0] cby_12__1__7_left_grid_pin_18_ ; +wire [0:0] cby_12__1__7_left_grid_pin_19_ ; +wire [0:0] cby_12__1__7_left_grid_pin_20_ ; +wire [0:0] cby_12__1__7_left_grid_pin_21_ ; +wire [0:0] cby_12__1__7_left_grid_pin_22_ ; +wire [0:0] cby_12__1__7_left_grid_pin_23_ ; +wire [0:0] cby_12__1__7_left_grid_pin_24_ ; +wire [0:0] cby_12__1__7_left_grid_pin_25_ ; +wire [0:0] cby_12__1__7_left_grid_pin_26_ ; +wire [0:0] cby_12__1__7_left_grid_pin_27_ ; +wire [0:0] cby_12__1__7_left_grid_pin_28_ ; +wire [0:0] cby_12__1__7_left_grid_pin_29_ ; +wire [0:0] cby_12__1__7_left_grid_pin_30_ ; +wire [0:0] cby_12__1__7_left_grid_pin_31_ ; +wire [0:0] cby_12__1__7_right_grid_pin_0_ ; +wire [0:0] cby_12__1__8_ccff_tail ; +wire [0:29] cby_12__1__8_chany_bottom_out ; +wire [0:29] cby_12__1__8_chany_top_out ; +wire [0:0] cby_12__1__8_left_grid_pin_16_ ; +wire [0:0] cby_12__1__8_left_grid_pin_17_ ; +wire [0:0] cby_12__1__8_left_grid_pin_18_ ; +wire [0:0] cby_12__1__8_left_grid_pin_19_ ; +wire [0:0] cby_12__1__8_left_grid_pin_20_ ; +wire [0:0] cby_12__1__8_left_grid_pin_21_ ; +wire [0:0] cby_12__1__8_left_grid_pin_22_ ; +wire [0:0] cby_12__1__8_left_grid_pin_23_ ; +wire [0:0] cby_12__1__8_left_grid_pin_24_ ; +wire [0:0] cby_12__1__8_left_grid_pin_25_ ; +wire [0:0] cby_12__1__8_left_grid_pin_26_ ; +wire [0:0] cby_12__1__8_left_grid_pin_27_ ; +wire [0:0] cby_12__1__8_left_grid_pin_28_ ; +wire [0:0] cby_12__1__8_left_grid_pin_29_ ; +wire [0:0] cby_12__1__8_left_grid_pin_30_ ; +wire [0:0] cby_12__1__8_left_grid_pin_31_ ; +wire [0:0] cby_12__1__8_right_grid_pin_0_ ; +wire [0:0] cby_12__1__9_ccff_tail ; +wire [0:29] cby_12__1__9_chany_bottom_out ; +wire [0:29] cby_12__1__9_chany_top_out ; +wire [0:0] cby_12__1__9_left_grid_pin_16_ ; +wire [0:0] cby_12__1__9_left_grid_pin_17_ ; +wire [0:0] cby_12__1__9_left_grid_pin_18_ ; +wire [0:0] cby_12__1__9_left_grid_pin_19_ ; +wire [0:0] cby_12__1__9_left_grid_pin_20_ ; +wire [0:0] cby_12__1__9_left_grid_pin_21_ ; +wire [0:0] cby_12__1__9_left_grid_pin_22_ ; +wire [0:0] cby_12__1__9_left_grid_pin_23_ ; +wire [0:0] cby_12__1__9_left_grid_pin_24_ ; +wire [0:0] cby_12__1__9_left_grid_pin_25_ ; +wire [0:0] cby_12__1__9_left_grid_pin_26_ ; +wire [0:0] cby_12__1__9_left_grid_pin_27_ ; +wire [0:0] cby_12__1__9_left_grid_pin_28_ ; +wire [0:0] cby_12__1__9_left_grid_pin_29_ ; +wire [0:0] cby_12__1__9_left_grid_pin_30_ ; +wire [0:0] cby_12__1__9_left_grid_pin_31_ ; +wire [0:0] cby_12__1__9_right_grid_pin_0_ ; +wire [0:0] cby_1__1__0_ccff_tail ; +wire [0:29] cby_1__1__0_chany_bottom_out ; +wire [0:29] cby_1__1__0_chany_top_out ; +wire [0:0] cby_1__1__0_left_grid_pin_16_ ; +wire [0:0] cby_1__1__0_left_grid_pin_17_ ; +wire [0:0] cby_1__1__0_left_grid_pin_18_ ; +wire [0:0] cby_1__1__0_left_grid_pin_19_ ; +wire [0:0] cby_1__1__0_left_grid_pin_20_ ; +wire [0:0] cby_1__1__0_left_grid_pin_21_ ; +wire [0:0] cby_1__1__0_left_grid_pin_22_ ; +wire [0:0] cby_1__1__0_left_grid_pin_23_ ; +wire [0:0] cby_1__1__0_left_grid_pin_24_ ; +wire [0:0] cby_1__1__0_left_grid_pin_25_ ; +wire [0:0] cby_1__1__0_left_grid_pin_26_ ; +wire [0:0] cby_1__1__0_left_grid_pin_27_ ; +wire [0:0] cby_1__1__0_left_grid_pin_28_ ; +wire [0:0] cby_1__1__0_left_grid_pin_29_ ; +wire [0:0] cby_1__1__0_left_grid_pin_30_ ; +wire [0:0] cby_1__1__0_left_grid_pin_31_ ; +wire [0:0] cby_1__1__100_ccff_tail ; +wire [0:29] cby_1__1__100_chany_bottom_out ; +wire [0:29] cby_1__1__100_chany_top_out ; +wire [0:0] cby_1__1__100_left_grid_pin_16_ ; +wire [0:0] cby_1__1__100_left_grid_pin_17_ ; +wire [0:0] cby_1__1__100_left_grid_pin_18_ ; +wire [0:0] cby_1__1__100_left_grid_pin_19_ ; +wire [0:0] cby_1__1__100_left_grid_pin_20_ ; +wire [0:0] cby_1__1__100_left_grid_pin_21_ ; +wire [0:0] cby_1__1__100_left_grid_pin_22_ ; +wire [0:0] cby_1__1__100_left_grid_pin_23_ ; +wire [0:0] cby_1__1__100_left_grid_pin_24_ ; +wire [0:0] cby_1__1__100_left_grid_pin_25_ ; +wire [0:0] cby_1__1__100_left_grid_pin_26_ ; +wire [0:0] cby_1__1__100_left_grid_pin_27_ ; +wire [0:0] cby_1__1__100_left_grid_pin_28_ ; +wire [0:0] cby_1__1__100_left_grid_pin_29_ ; +wire [0:0] cby_1__1__100_left_grid_pin_30_ ; +wire [0:0] cby_1__1__100_left_grid_pin_31_ ; +wire [0:0] cby_1__1__101_ccff_tail ; +wire [0:29] cby_1__1__101_chany_bottom_out ; +wire [0:29] cby_1__1__101_chany_top_out ; +wire [0:0] cby_1__1__101_left_grid_pin_16_ ; +wire [0:0] cby_1__1__101_left_grid_pin_17_ ; +wire [0:0] cby_1__1__101_left_grid_pin_18_ ; +wire [0:0] cby_1__1__101_left_grid_pin_19_ ; +wire [0:0] cby_1__1__101_left_grid_pin_20_ ; +wire [0:0] cby_1__1__101_left_grid_pin_21_ ; +wire [0:0] cby_1__1__101_left_grid_pin_22_ ; +wire [0:0] cby_1__1__101_left_grid_pin_23_ ; +wire [0:0] cby_1__1__101_left_grid_pin_24_ ; +wire [0:0] cby_1__1__101_left_grid_pin_25_ ; +wire [0:0] cby_1__1__101_left_grid_pin_26_ ; +wire [0:0] cby_1__1__101_left_grid_pin_27_ ; +wire [0:0] cby_1__1__101_left_grid_pin_28_ ; +wire [0:0] cby_1__1__101_left_grid_pin_29_ ; +wire [0:0] cby_1__1__101_left_grid_pin_30_ ; +wire [0:0] cby_1__1__101_left_grid_pin_31_ ; +wire [0:0] cby_1__1__102_ccff_tail ; +wire [0:29] cby_1__1__102_chany_bottom_out ; +wire [0:29] cby_1__1__102_chany_top_out ; +wire [0:0] cby_1__1__102_left_grid_pin_16_ ; +wire [0:0] cby_1__1__102_left_grid_pin_17_ ; +wire [0:0] cby_1__1__102_left_grid_pin_18_ ; +wire [0:0] cby_1__1__102_left_grid_pin_19_ ; +wire [0:0] cby_1__1__102_left_grid_pin_20_ ; +wire [0:0] cby_1__1__102_left_grid_pin_21_ ; +wire [0:0] cby_1__1__102_left_grid_pin_22_ ; +wire [0:0] cby_1__1__102_left_grid_pin_23_ ; +wire [0:0] cby_1__1__102_left_grid_pin_24_ ; +wire [0:0] cby_1__1__102_left_grid_pin_25_ ; +wire [0:0] cby_1__1__102_left_grid_pin_26_ ; +wire [0:0] cby_1__1__102_left_grid_pin_27_ ; +wire [0:0] cby_1__1__102_left_grid_pin_28_ ; +wire [0:0] cby_1__1__102_left_grid_pin_29_ ; +wire [0:0] cby_1__1__102_left_grid_pin_30_ ; +wire [0:0] cby_1__1__102_left_grid_pin_31_ ; +wire [0:0] cby_1__1__103_ccff_tail ; +wire [0:29] cby_1__1__103_chany_bottom_out ; +wire [0:29] cby_1__1__103_chany_top_out ; +wire [0:0] cby_1__1__103_left_grid_pin_16_ ; +wire [0:0] cby_1__1__103_left_grid_pin_17_ ; +wire [0:0] cby_1__1__103_left_grid_pin_18_ ; +wire [0:0] cby_1__1__103_left_grid_pin_19_ ; +wire [0:0] cby_1__1__103_left_grid_pin_20_ ; +wire [0:0] cby_1__1__103_left_grid_pin_21_ ; +wire [0:0] cby_1__1__103_left_grid_pin_22_ ; +wire [0:0] cby_1__1__103_left_grid_pin_23_ ; +wire [0:0] cby_1__1__103_left_grid_pin_24_ ; +wire [0:0] cby_1__1__103_left_grid_pin_25_ ; +wire [0:0] cby_1__1__103_left_grid_pin_26_ ; +wire [0:0] cby_1__1__103_left_grid_pin_27_ ; +wire [0:0] cby_1__1__103_left_grid_pin_28_ ; +wire [0:0] cby_1__1__103_left_grid_pin_29_ ; +wire [0:0] cby_1__1__103_left_grid_pin_30_ ; +wire [0:0] cby_1__1__103_left_grid_pin_31_ ; +wire [0:0] cby_1__1__104_ccff_tail ; +wire [0:29] cby_1__1__104_chany_bottom_out ; +wire [0:29] cby_1__1__104_chany_top_out ; +wire [0:0] cby_1__1__104_left_grid_pin_16_ ; +wire [0:0] cby_1__1__104_left_grid_pin_17_ ; +wire [0:0] cby_1__1__104_left_grid_pin_18_ ; +wire [0:0] cby_1__1__104_left_grid_pin_19_ ; +wire [0:0] cby_1__1__104_left_grid_pin_20_ ; +wire [0:0] cby_1__1__104_left_grid_pin_21_ ; +wire [0:0] cby_1__1__104_left_grid_pin_22_ ; +wire [0:0] cby_1__1__104_left_grid_pin_23_ ; +wire [0:0] cby_1__1__104_left_grid_pin_24_ ; +wire [0:0] cby_1__1__104_left_grid_pin_25_ ; +wire [0:0] cby_1__1__104_left_grid_pin_26_ ; +wire [0:0] cby_1__1__104_left_grid_pin_27_ ; +wire [0:0] cby_1__1__104_left_grid_pin_28_ ; +wire [0:0] cby_1__1__104_left_grid_pin_29_ ; +wire [0:0] cby_1__1__104_left_grid_pin_30_ ; +wire [0:0] cby_1__1__104_left_grid_pin_31_ ; +wire [0:0] cby_1__1__105_ccff_tail ; +wire [0:29] cby_1__1__105_chany_bottom_out ; +wire [0:29] cby_1__1__105_chany_top_out ; +wire [0:0] cby_1__1__105_left_grid_pin_16_ ; +wire [0:0] cby_1__1__105_left_grid_pin_17_ ; +wire [0:0] cby_1__1__105_left_grid_pin_18_ ; +wire [0:0] cby_1__1__105_left_grid_pin_19_ ; +wire [0:0] cby_1__1__105_left_grid_pin_20_ ; +wire [0:0] cby_1__1__105_left_grid_pin_21_ ; +wire [0:0] cby_1__1__105_left_grid_pin_22_ ; +wire [0:0] cby_1__1__105_left_grid_pin_23_ ; +wire [0:0] cby_1__1__105_left_grid_pin_24_ ; +wire [0:0] cby_1__1__105_left_grid_pin_25_ ; +wire [0:0] cby_1__1__105_left_grid_pin_26_ ; +wire [0:0] cby_1__1__105_left_grid_pin_27_ ; +wire [0:0] cby_1__1__105_left_grid_pin_28_ ; +wire [0:0] cby_1__1__105_left_grid_pin_29_ ; +wire [0:0] cby_1__1__105_left_grid_pin_30_ ; +wire [0:0] cby_1__1__105_left_grid_pin_31_ ; +wire [0:0] cby_1__1__106_ccff_tail ; +wire [0:29] cby_1__1__106_chany_bottom_out ; +wire [0:29] cby_1__1__106_chany_top_out ; +wire [0:0] cby_1__1__106_left_grid_pin_16_ ; +wire [0:0] cby_1__1__106_left_grid_pin_17_ ; +wire [0:0] cby_1__1__106_left_grid_pin_18_ ; +wire [0:0] cby_1__1__106_left_grid_pin_19_ ; +wire [0:0] cby_1__1__106_left_grid_pin_20_ ; +wire [0:0] cby_1__1__106_left_grid_pin_21_ ; +wire [0:0] cby_1__1__106_left_grid_pin_22_ ; +wire [0:0] cby_1__1__106_left_grid_pin_23_ ; +wire [0:0] cby_1__1__106_left_grid_pin_24_ ; +wire [0:0] cby_1__1__106_left_grid_pin_25_ ; +wire [0:0] cby_1__1__106_left_grid_pin_26_ ; +wire [0:0] cby_1__1__106_left_grid_pin_27_ ; +wire [0:0] cby_1__1__106_left_grid_pin_28_ ; +wire [0:0] cby_1__1__106_left_grid_pin_29_ ; +wire [0:0] cby_1__1__106_left_grid_pin_30_ ; +wire [0:0] cby_1__1__106_left_grid_pin_31_ ; +wire [0:0] cby_1__1__107_ccff_tail ; +wire [0:29] cby_1__1__107_chany_bottom_out ; +wire [0:29] cby_1__1__107_chany_top_out ; +wire [0:0] cby_1__1__107_left_grid_pin_16_ ; +wire [0:0] cby_1__1__107_left_grid_pin_17_ ; +wire [0:0] cby_1__1__107_left_grid_pin_18_ ; +wire [0:0] cby_1__1__107_left_grid_pin_19_ ; +wire [0:0] cby_1__1__107_left_grid_pin_20_ ; +wire [0:0] cby_1__1__107_left_grid_pin_21_ ; +wire [0:0] cby_1__1__107_left_grid_pin_22_ ; +wire [0:0] cby_1__1__107_left_grid_pin_23_ ; +wire [0:0] cby_1__1__107_left_grid_pin_24_ ; +wire [0:0] cby_1__1__107_left_grid_pin_25_ ; +wire [0:0] cby_1__1__107_left_grid_pin_26_ ; +wire [0:0] cby_1__1__107_left_grid_pin_27_ ; +wire [0:0] cby_1__1__107_left_grid_pin_28_ ; +wire [0:0] cby_1__1__107_left_grid_pin_29_ ; +wire [0:0] cby_1__1__107_left_grid_pin_30_ ; +wire [0:0] cby_1__1__107_left_grid_pin_31_ ; +wire [0:0] cby_1__1__108_ccff_tail ; +wire [0:29] cby_1__1__108_chany_bottom_out ; +wire [0:29] cby_1__1__108_chany_top_out ; +wire [0:0] cby_1__1__108_left_grid_pin_16_ ; +wire [0:0] cby_1__1__108_left_grid_pin_17_ ; +wire [0:0] cby_1__1__108_left_grid_pin_18_ ; +wire [0:0] cby_1__1__108_left_grid_pin_19_ ; +wire [0:0] cby_1__1__108_left_grid_pin_20_ ; +wire [0:0] cby_1__1__108_left_grid_pin_21_ ; +wire [0:0] cby_1__1__108_left_grid_pin_22_ ; +wire [0:0] cby_1__1__108_left_grid_pin_23_ ; +wire [0:0] cby_1__1__108_left_grid_pin_24_ ; +wire [0:0] cby_1__1__108_left_grid_pin_25_ ; +wire [0:0] cby_1__1__108_left_grid_pin_26_ ; +wire [0:0] cby_1__1__108_left_grid_pin_27_ ; +wire [0:0] cby_1__1__108_left_grid_pin_28_ ; +wire [0:0] cby_1__1__108_left_grid_pin_29_ ; +wire [0:0] cby_1__1__108_left_grid_pin_30_ ; +wire [0:0] cby_1__1__108_left_grid_pin_31_ ; +wire [0:0] cby_1__1__109_ccff_tail ; +wire [0:29] cby_1__1__109_chany_bottom_out ; +wire [0:29] cby_1__1__109_chany_top_out ; +wire [0:0] cby_1__1__109_left_grid_pin_16_ ; +wire [0:0] cby_1__1__109_left_grid_pin_17_ ; +wire [0:0] cby_1__1__109_left_grid_pin_18_ ; +wire [0:0] cby_1__1__109_left_grid_pin_19_ ; +wire [0:0] cby_1__1__109_left_grid_pin_20_ ; +wire [0:0] cby_1__1__109_left_grid_pin_21_ ; +wire [0:0] cby_1__1__109_left_grid_pin_22_ ; +wire [0:0] cby_1__1__109_left_grid_pin_23_ ; +wire [0:0] cby_1__1__109_left_grid_pin_24_ ; +wire [0:0] cby_1__1__109_left_grid_pin_25_ ; +wire [0:0] cby_1__1__109_left_grid_pin_26_ ; +wire [0:0] cby_1__1__109_left_grid_pin_27_ ; +wire [0:0] cby_1__1__109_left_grid_pin_28_ ; +wire [0:0] cby_1__1__109_left_grid_pin_29_ ; +wire [0:0] cby_1__1__109_left_grid_pin_30_ ; +wire [0:0] cby_1__1__109_left_grid_pin_31_ ; +wire [0:0] cby_1__1__10_ccff_tail ; +wire [0:29] cby_1__1__10_chany_bottom_out ; +wire [0:29] cby_1__1__10_chany_top_out ; +wire [0:0] cby_1__1__10_left_grid_pin_16_ ; +wire [0:0] cby_1__1__10_left_grid_pin_17_ ; +wire [0:0] cby_1__1__10_left_grid_pin_18_ ; +wire [0:0] cby_1__1__10_left_grid_pin_19_ ; +wire [0:0] cby_1__1__10_left_grid_pin_20_ ; +wire [0:0] cby_1__1__10_left_grid_pin_21_ ; +wire [0:0] cby_1__1__10_left_grid_pin_22_ ; +wire [0:0] cby_1__1__10_left_grid_pin_23_ ; +wire [0:0] cby_1__1__10_left_grid_pin_24_ ; +wire [0:0] cby_1__1__10_left_grid_pin_25_ ; +wire [0:0] cby_1__1__10_left_grid_pin_26_ ; +wire [0:0] cby_1__1__10_left_grid_pin_27_ ; +wire [0:0] cby_1__1__10_left_grid_pin_28_ ; +wire [0:0] cby_1__1__10_left_grid_pin_29_ ; +wire [0:0] cby_1__1__10_left_grid_pin_30_ ; +wire [0:0] cby_1__1__10_left_grid_pin_31_ ; +wire [0:0] cby_1__1__110_ccff_tail ; +wire [0:29] cby_1__1__110_chany_bottom_out ; +wire [0:29] cby_1__1__110_chany_top_out ; +wire [0:0] cby_1__1__110_left_grid_pin_16_ ; +wire [0:0] cby_1__1__110_left_grid_pin_17_ ; +wire [0:0] cby_1__1__110_left_grid_pin_18_ ; +wire [0:0] cby_1__1__110_left_grid_pin_19_ ; +wire [0:0] cby_1__1__110_left_grid_pin_20_ ; +wire [0:0] cby_1__1__110_left_grid_pin_21_ ; +wire [0:0] cby_1__1__110_left_grid_pin_22_ ; +wire [0:0] cby_1__1__110_left_grid_pin_23_ ; +wire [0:0] cby_1__1__110_left_grid_pin_24_ ; +wire [0:0] cby_1__1__110_left_grid_pin_25_ ; +wire [0:0] cby_1__1__110_left_grid_pin_26_ ; +wire [0:0] cby_1__1__110_left_grid_pin_27_ ; +wire [0:0] cby_1__1__110_left_grid_pin_28_ ; +wire [0:0] cby_1__1__110_left_grid_pin_29_ ; +wire [0:0] cby_1__1__110_left_grid_pin_30_ ; +wire [0:0] cby_1__1__110_left_grid_pin_31_ ; +wire [0:0] cby_1__1__111_ccff_tail ; +wire [0:29] cby_1__1__111_chany_bottom_out ; +wire [0:29] cby_1__1__111_chany_top_out ; +wire [0:0] cby_1__1__111_left_grid_pin_16_ ; +wire [0:0] cby_1__1__111_left_grid_pin_17_ ; +wire [0:0] cby_1__1__111_left_grid_pin_18_ ; +wire [0:0] cby_1__1__111_left_grid_pin_19_ ; +wire [0:0] cby_1__1__111_left_grid_pin_20_ ; +wire [0:0] cby_1__1__111_left_grid_pin_21_ ; +wire [0:0] cby_1__1__111_left_grid_pin_22_ ; +wire [0:0] cby_1__1__111_left_grid_pin_23_ ; +wire [0:0] cby_1__1__111_left_grid_pin_24_ ; +wire [0:0] cby_1__1__111_left_grid_pin_25_ ; +wire [0:0] cby_1__1__111_left_grid_pin_26_ ; +wire [0:0] cby_1__1__111_left_grid_pin_27_ ; +wire [0:0] cby_1__1__111_left_grid_pin_28_ ; +wire [0:0] cby_1__1__111_left_grid_pin_29_ ; +wire [0:0] cby_1__1__111_left_grid_pin_30_ ; +wire [0:0] cby_1__1__111_left_grid_pin_31_ ; +wire [0:0] cby_1__1__112_ccff_tail ; +wire [0:29] cby_1__1__112_chany_bottom_out ; +wire [0:29] cby_1__1__112_chany_top_out ; +wire [0:0] cby_1__1__112_left_grid_pin_16_ ; +wire [0:0] cby_1__1__112_left_grid_pin_17_ ; +wire [0:0] cby_1__1__112_left_grid_pin_18_ ; +wire [0:0] cby_1__1__112_left_grid_pin_19_ ; +wire [0:0] cby_1__1__112_left_grid_pin_20_ ; +wire [0:0] cby_1__1__112_left_grid_pin_21_ ; +wire [0:0] cby_1__1__112_left_grid_pin_22_ ; +wire [0:0] cby_1__1__112_left_grid_pin_23_ ; +wire [0:0] cby_1__1__112_left_grid_pin_24_ ; +wire [0:0] cby_1__1__112_left_grid_pin_25_ ; +wire [0:0] cby_1__1__112_left_grid_pin_26_ ; +wire [0:0] cby_1__1__112_left_grid_pin_27_ ; +wire [0:0] cby_1__1__112_left_grid_pin_28_ ; +wire [0:0] cby_1__1__112_left_grid_pin_29_ ; +wire [0:0] cby_1__1__112_left_grid_pin_30_ ; +wire [0:0] cby_1__1__112_left_grid_pin_31_ ; +wire [0:0] cby_1__1__113_ccff_tail ; +wire [0:29] cby_1__1__113_chany_bottom_out ; +wire [0:29] cby_1__1__113_chany_top_out ; +wire [0:0] cby_1__1__113_left_grid_pin_16_ ; +wire [0:0] cby_1__1__113_left_grid_pin_17_ ; +wire [0:0] cby_1__1__113_left_grid_pin_18_ ; +wire [0:0] cby_1__1__113_left_grid_pin_19_ ; +wire [0:0] cby_1__1__113_left_grid_pin_20_ ; +wire [0:0] cby_1__1__113_left_grid_pin_21_ ; +wire [0:0] cby_1__1__113_left_grid_pin_22_ ; +wire [0:0] cby_1__1__113_left_grid_pin_23_ ; +wire [0:0] cby_1__1__113_left_grid_pin_24_ ; +wire [0:0] cby_1__1__113_left_grid_pin_25_ ; +wire [0:0] cby_1__1__113_left_grid_pin_26_ ; +wire [0:0] cby_1__1__113_left_grid_pin_27_ ; +wire [0:0] cby_1__1__113_left_grid_pin_28_ ; +wire [0:0] cby_1__1__113_left_grid_pin_29_ ; +wire [0:0] cby_1__1__113_left_grid_pin_30_ ; +wire [0:0] cby_1__1__113_left_grid_pin_31_ ; +wire [0:0] cby_1__1__114_ccff_tail ; +wire [0:29] cby_1__1__114_chany_bottom_out ; +wire [0:29] cby_1__1__114_chany_top_out ; +wire [0:0] cby_1__1__114_left_grid_pin_16_ ; +wire [0:0] cby_1__1__114_left_grid_pin_17_ ; +wire [0:0] cby_1__1__114_left_grid_pin_18_ ; +wire [0:0] cby_1__1__114_left_grid_pin_19_ ; +wire [0:0] cby_1__1__114_left_grid_pin_20_ ; +wire [0:0] cby_1__1__114_left_grid_pin_21_ ; +wire [0:0] cby_1__1__114_left_grid_pin_22_ ; +wire [0:0] cby_1__1__114_left_grid_pin_23_ ; +wire [0:0] cby_1__1__114_left_grid_pin_24_ ; +wire [0:0] cby_1__1__114_left_grid_pin_25_ ; +wire [0:0] cby_1__1__114_left_grid_pin_26_ ; +wire [0:0] cby_1__1__114_left_grid_pin_27_ ; +wire [0:0] cby_1__1__114_left_grid_pin_28_ ; +wire [0:0] cby_1__1__114_left_grid_pin_29_ ; +wire [0:0] cby_1__1__114_left_grid_pin_30_ ; +wire [0:0] cby_1__1__114_left_grid_pin_31_ ; +wire [0:0] cby_1__1__115_ccff_tail ; +wire [0:29] cby_1__1__115_chany_bottom_out ; +wire [0:29] cby_1__1__115_chany_top_out ; +wire [0:0] cby_1__1__115_left_grid_pin_16_ ; +wire [0:0] cby_1__1__115_left_grid_pin_17_ ; +wire [0:0] cby_1__1__115_left_grid_pin_18_ ; +wire [0:0] cby_1__1__115_left_grid_pin_19_ ; +wire [0:0] cby_1__1__115_left_grid_pin_20_ ; +wire [0:0] cby_1__1__115_left_grid_pin_21_ ; +wire [0:0] cby_1__1__115_left_grid_pin_22_ ; +wire [0:0] cby_1__1__115_left_grid_pin_23_ ; +wire [0:0] cby_1__1__115_left_grid_pin_24_ ; +wire [0:0] cby_1__1__115_left_grid_pin_25_ ; +wire [0:0] cby_1__1__115_left_grid_pin_26_ ; +wire [0:0] cby_1__1__115_left_grid_pin_27_ ; +wire [0:0] cby_1__1__115_left_grid_pin_28_ ; +wire [0:0] cby_1__1__115_left_grid_pin_29_ ; +wire [0:0] cby_1__1__115_left_grid_pin_30_ ; +wire [0:0] cby_1__1__115_left_grid_pin_31_ ; +wire [0:0] cby_1__1__116_ccff_tail ; +wire [0:29] cby_1__1__116_chany_bottom_out ; +wire [0:29] cby_1__1__116_chany_top_out ; +wire [0:0] cby_1__1__116_left_grid_pin_16_ ; +wire [0:0] cby_1__1__116_left_grid_pin_17_ ; +wire [0:0] cby_1__1__116_left_grid_pin_18_ ; +wire [0:0] cby_1__1__116_left_grid_pin_19_ ; +wire [0:0] cby_1__1__116_left_grid_pin_20_ ; +wire [0:0] cby_1__1__116_left_grid_pin_21_ ; +wire [0:0] cby_1__1__116_left_grid_pin_22_ ; +wire [0:0] cby_1__1__116_left_grid_pin_23_ ; +wire [0:0] cby_1__1__116_left_grid_pin_24_ ; +wire [0:0] cby_1__1__116_left_grid_pin_25_ ; +wire [0:0] cby_1__1__116_left_grid_pin_26_ ; +wire [0:0] cby_1__1__116_left_grid_pin_27_ ; +wire [0:0] cby_1__1__116_left_grid_pin_28_ ; +wire [0:0] cby_1__1__116_left_grid_pin_29_ ; +wire [0:0] cby_1__1__116_left_grid_pin_30_ ; +wire [0:0] cby_1__1__116_left_grid_pin_31_ ; +wire [0:0] cby_1__1__117_ccff_tail ; +wire [0:29] cby_1__1__117_chany_bottom_out ; +wire [0:29] cby_1__1__117_chany_top_out ; +wire [0:0] cby_1__1__117_left_grid_pin_16_ ; +wire [0:0] cby_1__1__117_left_grid_pin_17_ ; +wire [0:0] cby_1__1__117_left_grid_pin_18_ ; +wire [0:0] cby_1__1__117_left_grid_pin_19_ ; +wire [0:0] cby_1__1__117_left_grid_pin_20_ ; +wire [0:0] cby_1__1__117_left_grid_pin_21_ ; +wire [0:0] cby_1__1__117_left_grid_pin_22_ ; +wire [0:0] cby_1__1__117_left_grid_pin_23_ ; +wire [0:0] cby_1__1__117_left_grid_pin_24_ ; +wire [0:0] cby_1__1__117_left_grid_pin_25_ ; +wire [0:0] cby_1__1__117_left_grid_pin_26_ ; +wire [0:0] cby_1__1__117_left_grid_pin_27_ ; +wire [0:0] cby_1__1__117_left_grid_pin_28_ ; +wire [0:0] cby_1__1__117_left_grid_pin_29_ ; +wire [0:0] cby_1__1__117_left_grid_pin_30_ ; +wire [0:0] cby_1__1__117_left_grid_pin_31_ ; +wire [0:0] cby_1__1__118_ccff_tail ; +wire [0:29] cby_1__1__118_chany_bottom_out ; +wire [0:29] cby_1__1__118_chany_top_out ; +wire [0:0] cby_1__1__118_left_grid_pin_16_ ; +wire [0:0] cby_1__1__118_left_grid_pin_17_ ; +wire [0:0] cby_1__1__118_left_grid_pin_18_ ; +wire [0:0] cby_1__1__118_left_grid_pin_19_ ; +wire [0:0] cby_1__1__118_left_grid_pin_20_ ; +wire [0:0] cby_1__1__118_left_grid_pin_21_ ; +wire [0:0] cby_1__1__118_left_grid_pin_22_ ; +wire [0:0] cby_1__1__118_left_grid_pin_23_ ; +wire [0:0] cby_1__1__118_left_grid_pin_24_ ; +wire [0:0] cby_1__1__118_left_grid_pin_25_ ; +wire [0:0] cby_1__1__118_left_grid_pin_26_ ; +wire [0:0] cby_1__1__118_left_grid_pin_27_ ; +wire [0:0] cby_1__1__118_left_grid_pin_28_ ; +wire [0:0] cby_1__1__118_left_grid_pin_29_ ; +wire [0:0] cby_1__1__118_left_grid_pin_30_ ; +wire [0:0] cby_1__1__118_left_grid_pin_31_ ; +wire [0:0] cby_1__1__119_ccff_tail ; +wire [0:29] cby_1__1__119_chany_bottom_out ; +wire [0:29] cby_1__1__119_chany_top_out ; +wire [0:0] cby_1__1__119_left_grid_pin_16_ ; +wire [0:0] cby_1__1__119_left_grid_pin_17_ ; +wire [0:0] cby_1__1__119_left_grid_pin_18_ ; +wire [0:0] cby_1__1__119_left_grid_pin_19_ ; +wire [0:0] cby_1__1__119_left_grid_pin_20_ ; +wire [0:0] cby_1__1__119_left_grid_pin_21_ ; +wire [0:0] cby_1__1__119_left_grid_pin_22_ ; +wire [0:0] cby_1__1__119_left_grid_pin_23_ ; +wire [0:0] cby_1__1__119_left_grid_pin_24_ ; +wire [0:0] cby_1__1__119_left_grid_pin_25_ ; +wire [0:0] cby_1__1__119_left_grid_pin_26_ ; +wire [0:0] cby_1__1__119_left_grid_pin_27_ ; +wire [0:0] cby_1__1__119_left_grid_pin_28_ ; +wire [0:0] cby_1__1__119_left_grid_pin_29_ ; +wire [0:0] cby_1__1__119_left_grid_pin_30_ ; +wire [0:0] cby_1__1__119_left_grid_pin_31_ ; +wire [0:0] cby_1__1__11_ccff_tail ; +wire [0:29] cby_1__1__11_chany_bottom_out ; +wire [0:29] cby_1__1__11_chany_top_out ; +wire [0:0] cby_1__1__11_left_grid_pin_16_ ; +wire [0:0] cby_1__1__11_left_grid_pin_17_ ; +wire [0:0] cby_1__1__11_left_grid_pin_18_ ; +wire [0:0] cby_1__1__11_left_grid_pin_19_ ; +wire [0:0] cby_1__1__11_left_grid_pin_20_ ; +wire [0:0] cby_1__1__11_left_grid_pin_21_ ; +wire [0:0] cby_1__1__11_left_grid_pin_22_ ; +wire [0:0] cby_1__1__11_left_grid_pin_23_ ; +wire [0:0] cby_1__1__11_left_grid_pin_24_ ; +wire [0:0] cby_1__1__11_left_grid_pin_25_ ; +wire [0:0] cby_1__1__11_left_grid_pin_26_ ; +wire [0:0] cby_1__1__11_left_grid_pin_27_ ; +wire [0:0] cby_1__1__11_left_grid_pin_28_ ; +wire [0:0] cby_1__1__11_left_grid_pin_29_ ; +wire [0:0] cby_1__1__11_left_grid_pin_30_ ; +wire [0:0] cby_1__1__11_left_grid_pin_31_ ; +wire [0:0] cby_1__1__120_ccff_tail ; +wire [0:29] cby_1__1__120_chany_bottom_out ; +wire [0:29] cby_1__1__120_chany_top_out ; +wire [0:0] cby_1__1__120_left_grid_pin_16_ ; +wire [0:0] cby_1__1__120_left_grid_pin_17_ ; +wire [0:0] cby_1__1__120_left_grid_pin_18_ ; +wire [0:0] cby_1__1__120_left_grid_pin_19_ ; +wire [0:0] cby_1__1__120_left_grid_pin_20_ ; +wire [0:0] cby_1__1__120_left_grid_pin_21_ ; +wire [0:0] cby_1__1__120_left_grid_pin_22_ ; +wire [0:0] cby_1__1__120_left_grid_pin_23_ ; +wire [0:0] cby_1__1__120_left_grid_pin_24_ ; +wire [0:0] cby_1__1__120_left_grid_pin_25_ ; +wire [0:0] cby_1__1__120_left_grid_pin_26_ ; +wire [0:0] cby_1__1__120_left_grid_pin_27_ ; +wire [0:0] cby_1__1__120_left_grid_pin_28_ ; +wire [0:0] cby_1__1__120_left_grid_pin_29_ ; +wire [0:0] cby_1__1__120_left_grid_pin_30_ ; +wire [0:0] cby_1__1__120_left_grid_pin_31_ ; +wire [0:0] cby_1__1__121_ccff_tail ; +wire [0:29] cby_1__1__121_chany_bottom_out ; +wire [0:29] cby_1__1__121_chany_top_out ; +wire [0:0] cby_1__1__121_left_grid_pin_16_ ; +wire [0:0] cby_1__1__121_left_grid_pin_17_ ; +wire [0:0] cby_1__1__121_left_grid_pin_18_ ; +wire [0:0] cby_1__1__121_left_grid_pin_19_ ; +wire [0:0] cby_1__1__121_left_grid_pin_20_ ; +wire [0:0] cby_1__1__121_left_grid_pin_21_ ; +wire [0:0] cby_1__1__121_left_grid_pin_22_ ; +wire [0:0] cby_1__1__121_left_grid_pin_23_ ; +wire [0:0] cby_1__1__121_left_grid_pin_24_ ; +wire [0:0] cby_1__1__121_left_grid_pin_25_ ; +wire [0:0] cby_1__1__121_left_grid_pin_26_ ; +wire [0:0] cby_1__1__121_left_grid_pin_27_ ; +wire [0:0] cby_1__1__121_left_grid_pin_28_ ; +wire [0:0] cby_1__1__121_left_grid_pin_29_ ; +wire [0:0] cby_1__1__121_left_grid_pin_30_ ; +wire [0:0] cby_1__1__121_left_grid_pin_31_ ; +wire [0:0] cby_1__1__122_ccff_tail ; +wire [0:29] cby_1__1__122_chany_bottom_out ; +wire [0:29] cby_1__1__122_chany_top_out ; +wire [0:0] cby_1__1__122_left_grid_pin_16_ ; +wire [0:0] cby_1__1__122_left_grid_pin_17_ ; +wire [0:0] cby_1__1__122_left_grid_pin_18_ ; +wire [0:0] cby_1__1__122_left_grid_pin_19_ ; +wire [0:0] cby_1__1__122_left_grid_pin_20_ ; +wire [0:0] cby_1__1__122_left_grid_pin_21_ ; +wire [0:0] cby_1__1__122_left_grid_pin_22_ ; +wire [0:0] cby_1__1__122_left_grid_pin_23_ ; +wire [0:0] cby_1__1__122_left_grid_pin_24_ ; +wire [0:0] cby_1__1__122_left_grid_pin_25_ ; +wire [0:0] cby_1__1__122_left_grid_pin_26_ ; +wire [0:0] cby_1__1__122_left_grid_pin_27_ ; +wire [0:0] cby_1__1__122_left_grid_pin_28_ ; +wire [0:0] cby_1__1__122_left_grid_pin_29_ ; +wire [0:0] cby_1__1__122_left_grid_pin_30_ ; +wire [0:0] cby_1__1__122_left_grid_pin_31_ ; +wire [0:0] cby_1__1__123_ccff_tail ; +wire [0:29] cby_1__1__123_chany_bottom_out ; +wire [0:29] cby_1__1__123_chany_top_out ; +wire [0:0] cby_1__1__123_left_grid_pin_16_ ; +wire [0:0] cby_1__1__123_left_grid_pin_17_ ; +wire [0:0] cby_1__1__123_left_grid_pin_18_ ; +wire [0:0] cby_1__1__123_left_grid_pin_19_ ; +wire [0:0] cby_1__1__123_left_grid_pin_20_ ; +wire [0:0] cby_1__1__123_left_grid_pin_21_ ; +wire [0:0] cby_1__1__123_left_grid_pin_22_ ; +wire [0:0] cby_1__1__123_left_grid_pin_23_ ; +wire [0:0] cby_1__1__123_left_grid_pin_24_ ; +wire [0:0] cby_1__1__123_left_grid_pin_25_ ; +wire [0:0] cby_1__1__123_left_grid_pin_26_ ; +wire [0:0] cby_1__1__123_left_grid_pin_27_ ; +wire [0:0] cby_1__1__123_left_grid_pin_28_ ; +wire [0:0] cby_1__1__123_left_grid_pin_29_ ; +wire [0:0] cby_1__1__123_left_grid_pin_30_ ; +wire [0:0] cby_1__1__123_left_grid_pin_31_ ; +wire [0:0] cby_1__1__124_ccff_tail ; +wire [0:29] cby_1__1__124_chany_bottom_out ; +wire [0:29] cby_1__1__124_chany_top_out ; +wire [0:0] cby_1__1__124_left_grid_pin_16_ ; +wire [0:0] cby_1__1__124_left_grid_pin_17_ ; +wire [0:0] cby_1__1__124_left_grid_pin_18_ ; +wire [0:0] cby_1__1__124_left_grid_pin_19_ ; +wire [0:0] cby_1__1__124_left_grid_pin_20_ ; +wire [0:0] cby_1__1__124_left_grid_pin_21_ ; +wire [0:0] cby_1__1__124_left_grid_pin_22_ ; +wire [0:0] cby_1__1__124_left_grid_pin_23_ ; +wire [0:0] cby_1__1__124_left_grid_pin_24_ ; +wire [0:0] cby_1__1__124_left_grid_pin_25_ ; +wire [0:0] cby_1__1__124_left_grid_pin_26_ ; +wire [0:0] cby_1__1__124_left_grid_pin_27_ ; +wire [0:0] cby_1__1__124_left_grid_pin_28_ ; +wire [0:0] cby_1__1__124_left_grid_pin_29_ ; +wire [0:0] cby_1__1__124_left_grid_pin_30_ ; +wire [0:0] cby_1__1__124_left_grid_pin_31_ ; +wire [0:0] cby_1__1__125_ccff_tail ; +wire [0:29] cby_1__1__125_chany_bottom_out ; +wire [0:29] cby_1__1__125_chany_top_out ; +wire [0:0] cby_1__1__125_left_grid_pin_16_ ; +wire [0:0] cby_1__1__125_left_grid_pin_17_ ; +wire [0:0] cby_1__1__125_left_grid_pin_18_ ; +wire [0:0] cby_1__1__125_left_grid_pin_19_ ; +wire [0:0] cby_1__1__125_left_grid_pin_20_ ; +wire [0:0] cby_1__1__125_left_grid_pin_21_ ; +wire [0:0] cby_1__1__125_left_grid_pin_22_ ; +wire [0:0] cby_1__1__125_left_grid_pin_23_ ; +wire [0:0] cby_1__1__125_left_grid_pin_24_ ; +wire [0:0] cby_1__1__125_left_grid_pin_25_ ; +wire [0:0] cby_1__1__125_left_grid_pin_26_ ; +wire [0:0] cby_1__1__125_left_grid_pin_27_ ; +wire [0:0] cby_1__1__125_left_grid_pin_28_ ; +wire [0:0] cby_1__1__125_left_grid_pin_29_ ; +wire [0:0] cby_1__1__125_left_grid_pin_30_ ; +wire [0:0] cby_1__1__125_left_grid_pin_31_ ; +wire [0:0] cby_1__1__126_ccff_tail ; +wire [0:29] cby_1__1__126_chany_bottom_out ; +wire [0:29] cby_1__1__126_chany_top_out ; +wire [0:0] cby_1__1__126_left_grid_pin_16_ ; +wire [0:0] cby_1__1__126_left_grid_pin_17_ ; +wire [0:0] cby_1__1__126_left_grid_pin_18_ ; +wire [0:0] cby_1__1__126_left_grid_pin_19_ ; +wire [0:0] cby_1__1__126_left_grid_pin_20_ ; +wire [0:0] cby_1__1__126_left_grid_pin_21_ ; +wire [0:0] cby_1__1__126_left_grid_pin_22_ ; +wire [0:0] cby_1__1__126_left_grid_pin_23_ ; +wire [0:0] cby_1__1__126_left_grid_pin_24_ ; +wire [0:0] cby_1__1__126_left_grid_pin_25_ ; +wire [0:0] cby_1__1__126_left_grid_pin_26_ ; +wire [0:0] cby_1__1__126_left_grid_pin_27_ ; +wire [0:0] cby_1__1__126_left_grid_pin_28_ ; +wire [0:0] cby_1__1__126_left_grid_pin_29_ ; +wire [0:0] cby_1__1__126_left_grid_pin_30_ ; +wire [0:0] cby_1__1__126_left_grid_pin_31_ ; +wire [0:0] cby_1__1__127_ccff_tail ; +wire [0:29] cby_1__1__127_chany_bottom_out ; +wire [0:29] cby_1__1__127_chany_top_out ; +wire [0:0] cby_1__1__127_left_grid_pin_16_ ; +wire [0:0] cby_1__1__127_left_grid_pin_17_ ; +wire [0:0] cby_1__1__127_left_grid_pin_18_ ; +wire [0:0] cby_1__1__127_left_grid_pin_19_ ; +wire [0:0] cby_1__1__127_left_grid_pin_20_ ; +wire [0:0] cby_1__1__127_left_grid_pin_21_ ; +wire [0:0] cby_1__1__127_left_grid_pin_22_ ; +wire [0:0] cby_1__1__127_left_grid_pin_23_ ; +wire [0:0] cby_1__1__127_left_grid_pin_24_ ; +wire [0:0] cby_1__1__127_left_grid_pin_25_ ; +wire [0:0] cby_1__1__127_left_grid_pin_26_ ; +wire [0:0] cby_1__1__127_left_grid_pin_27_ ; +wire [0:0] cby_1__1__127_left_grid_pin_28_ ; +wire [0:0] cby_1__1__127_left_grid_pin_29_ ; +wire [0:0] cby_1__1__127_left_grid_pin_30_ ; +wire [0:0] cby_1__1__127_left_grid_pin_31_ ; +wire [0:0] cby_1__1__128_ccff_tail ; +wire [0:29] cby_1__1__128_chany_bottom_out ; +wire [0:29] cby_1__1__128_chany_top_out ; +wire [0:0] cby_1__1__128_left_grid_pin_16_ ; +wire [0:0] cby_1__1__128_left_grid_pin_17_ ; +wire [0:0] cby_1__1__128_left_grid_pin_18_ ; +wire [0:0] cby_1__1__128_left_grid_pin_19_ ; +wire [0:0] cby_1__1__128_left_grid_pin_20_ ; +wire [0:0] cby_1__1__128_left_grid_pin_21_ ; +wire [0:0] cby_1__1__128_left_grid_pin_22_ ; +wire [0:0] cby_1__1__128_left_grid_pin_23_ ; +wire [0:0] cby_1__1__128_left_grid_pin_24_ ; +wire [0:0] cby_1__1__128_left_grid_pin_25_ ; +wire [0:0] cby_1__1__128_left_grid_pin_26_ ; +wire [0:0] cby_1__1__128_left_grid_pin_27_ ; +wire [0:0] cby_1__1__128_left_grid_pin_28_ ; +wire [0:0] cby_1__1__128_left_grid_pin_29_ ; +wire [0:0] cby_1__1__128_left_grid_pin_30_ ; +wire [0:0] cby_1__1__128_left_grid_pin_31_ ; +wire [0:0] cby_1__1__129_ccff_tail ; +wire [0:29] cby_1__1__129_chany_bottom_out ; +wire [0:29] cby_1__1__129_chany_top_out ; +wire [0:0] cby_1__1__129_left_grid_pin_16_ ; +wire [0:0] cby_1__1__129_left_grid_pin_17_ ; +wire [0:0] cby_1__1__129_left_grid_pin_18_ ; +wire [0:0] cby_1__1__129_left_grid_pin_19_ ; +wire [0:0] cby_1__1__129_left_grid_pin_20_ ; +wire [0:0] cby_1__1__129_left_grid_pin_21_ ; +wire [0:0] cby_1__1__129_left_grid_pin_22_ ; +wire [0:0] cby_1__1__129_left_grid_pin_23_ ; +wire [0:0] cby_1__1__129_left_grid_pin_24_ ; +wire [0:0] cby_1__1__129_left_grid_pin_25_ ; +wire [0:0] cby_1__1__129_left_grid_pin_26_ ; +wire [0:0] cby_1__1__129_left_grid_pin_27_ ; +wire [0:0] cby_1__1__129_left_grid_pin_28_ ; +wire [0:0] cby_1__1__129_left_grid_pin_29_ ; +wire [0:0] cby_1__1__129_left_grid_pin_30_ ; +wire [0:0] cby_1__1__129_left_grid_pin_31_ ; +wire [0:0] cby_1__1__12_ccff_tail ; +wire [0:29] cby_1__1__12_chany_bottom_out ; +wire [0:29] cby_1__1__12_chany_top_out ; +wire [0:0] cby_1__1__12_left_grid_pin_16_ ; +wire [0:0] cby_1__1__12_left_grid_pin_17_ ; +wire [0:0] cby_1__1__12_left_grid_pin_18_ ; +wire [0:0] cby_1__1__12_left_grid_pin_19_ ; +wire [0:0] cby_1__1__12_left_grid_pin_20_ ; +wire [0:0] cby_1__1__12_left_grid_pin_21_ ; +wire [0:0] cby_1__1__12_left_grid_pin_22_ ; +wire [0:0] cby_1__1__12_left_grid_pin_23_ ; +wire [0:0] cby_1__1__12_left_grid_pin_24_ ; +wire [0:0] cby_1__1__12_left_grid_pin_25_ ; +wire [0:0] cby_1__1__12_left_grid_pin_26_ ; +wire [0:0] cby_1__1__12_left_grid_pin_27_ ; +wire [0:0] cby_1__1__12_left_grid_pin_28_ ; +wire [0:0] cby_1__1__12_left_grid_pin_29_ ; +wire [0:0] cby_1__1__12_left_grid_pin_30_ ; +wire [0:0] cby_1__1__12_left_grid_pin_31_ ; +wire [0:0] cby_1__1__130_ccff_tail ; +wire [0:29] cby_1__1__130_chany_bottom_out ; +wire [0:29] cby_1__1__130_chany_top_out ; +wire [0:0] cby_1__1__130_left_grid_pin_16_ ; +wire [0:0] cby_1__1__130_left_grid_pin_17_ ; +wire [0:0] cby_1__1__130_left_grid_pin_18_ ; +wire [0:0] cby_1__1__130_left_grid_pin_19_ ; +wire [0:0] cby_1__1__130_left_grid_pin_20_ ; +wire [0:0] cby_1__1__130_left_grid_pin_21_ ; +wire [0:0] cby_1__1__130_left_grid_pin_22_ ; +wire [0:0] cby_1__1__130_left_grid_pin_23_ ; +wire [0:0] cby_1__1__130_left_grid_pin_24_ ; +wire [0:0] cby_1__1__130_left_grid_pin_25_ ; +wire [0:0] cby_1__1__130_left_grid_pin_26_ ; +wire [0:0] cby_1__1__130_left_grid_pin_27_ ; +wire [0:0] cby_1__1__130_left_grid_pin_28_ ; +wire [0:0] cby_1__1__130_left_grid_pin_29_ ; +wire [0:0] cby_1__1__130_left_grid_pin_30_ ; +wire [0:0] cby_1__1__130_left_grid_pin_31_ ; +wire [0:0] cby_1__1__131_ccff_tail ; +wire [0:29] cby_1__1__131_chany_bottom_out ; +wire [0:29] cby_1__1__131_chany_top_out ; +wire [0:0] cby_1__1__131_left_grid_pin_16_ ; +wire [0:0] cby_1__1__131_left_grid_pin_17_ ; +wire [0:0] cby_1__1__131_left_grid_pin_18_ ; +wire [0:0] cby_1__1__131_left_grid_pin_19_ ; +wire [0:0] cby_1__1__131_left_grid_pin_20_ ; +wire [0:0] cby_1__1__131_left_grid_pin_21_ ; +wire [0:0] cby_1__1__131_left_grid_pin_22_ ; +wire [0:0] cby_1__1__131_left_grid_pin_23_ ; +wire [0:0] cby_1__1__131_left_grid_pin_24_ ; +wire [0:0] cby_1__1__131_left_grid_pin_25_ ; +wire [0:0] cby_1__1__131_left_grid_pin_26_ ; +wire [0:0] cby_1__1__131_left_grid_pin_27_ ; +wire [0:0] cby_1__1__131_left_grid_pin_28_ ; +wire [0:0] cby_1__1__131_left_grid_pin_29_ ; +wire [0:0] cby_1__1__131_left_grid_pin_30_ ; +wire [0:0] cby_1__1__131_left_grid_pin_31_ ; +wire [0:0] cby_1__1__13_ccff_tail ; +wire [0:29] cby_1__1__13_chany_bottom_out ; +wire [0:29] cby_1__1__13_chany_top_out ; +wire [0:0] cby_1__1__13_left_grid_pin_16_ ; +wire [0:0] cby_1__1__13_left_grid_pin_17_ ; +wire [0:0] cby_1__1__13_left_grid_pin_18_ ; +wire [0:0] cby_1__1__13_left_grid_pin_19_ ; +wire [0:0] cby_1__1__13_left_grid_pin_20_ ; +wire [0:0] cby_1__1__13_left_grid_pin_21_ ; +wire [0:0] cby_1__1__13_left_grid_pin_22_ ; +wire [0:0] cby_1__1__13_left_grid_pin_23_ ; +wire [0:0] cby_1__1__13_left_grid_pin_24_ ; +wire [0:0] cby_1__1__13_left_grid_pin_25_ ; +wire [0:0] cby_1__1__13_left_grid_pin_26_ ; +wire [0:0] cby_1__1__13_left_grid_pin_27_ ; +wire [0:0] cby_1__1__13_left_grid_pin_28_ ; +wire [0:0] cby_1__1__13_left_grid_pin_29_ ; +wire [0:0] cby_1__1__13_left_grid_pin_30_ ; +wire [0:0] cby_1__1__13_left_grid_pin_31_ ; +wire [0:0] cby_1__1__14_ccff_tail ; +wire [0:29] cby_1__1__14_chany_bottom_out ; +wire [0:29] cby_1__1__14_chany_top_out ; +wire [0:0] cby_1__1__14_left_grid_pin_16_ ; +wire [0:0] cby_1__1__14_left_grid_pin_17_ ; +wire [0:0] cby_1__1__14_left_grid_pin_18_ ; +wire [0:0] cby_1__1__14_left_grid_pin_19_ ; +wire [0:0] cby_1__1__14_left_grid_pin_20_ ; +wire [0:0] cby_1__1__14_left_grid_pin_21_ ; +wire [0:0] cby_1__1__14_left_grid_pin_22_ ; +wire [0:0] cby_1__1__14_left_grid_pin_23_ ; +wire [0:0] cby_1__1__14_left_grid_pin_24_ ; +wire [0:0] cby_1__1__14_left_grid_pin_25_ ; +wire [0:0] cby_1__1__14_left_grid_pin_26_ ; +wire [0:0] cby_1__1__14_left_grid_pin_27_ ; +wire [0:0] cby_1__1__14_left_grid_pin_28_ ; +wire [0:0] cby_1__1__14_left_grid_pin_29_ ; +wire [0:0] cby_1__1__14_left_grid_pin_30_ ; +wire [0:0] cby_1__1__14_left_grid_pin_31_ ; +wire [0:0] cby_1__1__15_ccff_tail ; +wire [0:29] cby_1__1__15_chany_bottom_out ; +wire [0:29] cby_1__1__15_chany_top_out ; +wire [0:0] cby_1__1__15_left_grid_pin_16_ ; +wire [0:0] cby_1__1__15_left_grid_pin_17_ ; +wire [0:0] cby_1__1__15_left_grid_pin_18_ ; +wire [0:0] cby_1__1__15_left_grid_pin_19_ ; +wire [0:0] cby_1__1__15_left_grid_pin_20_ ; +wire [0:0] cby_1__1__15_left_grid_pin_21_ ; +wire [0:0] cby_1__1__15_left_grid_pin_22_ ; +wire [0:0] cby_1__1__15_left_grid_pin_23_ ; +wire [0:0] cby_1__1__15_left_grid_pin_24_ ; +wire [0:0] cby_1__1__15_left_grid_pin_25_ ; +wire [0:0] cby_1__1__15_left_grid_pin_26_ ; +wire [0:0] cby_1__1__15_left_grid_pin_27_ ; +wire [0:0] cby_1__1__15_left_grid_pin_28_ ; +wire [0:0] cby_1__1__15_left_grid_pin_29_ ; +wire [0:0] cby_1__1__15_left_grid_pin_30_ ; +wire [0:0] cby_1__1__15_left_grid_pin_31_ ; +wire [0:0] cby_1__1__16_ccff_tail ; +wire [0:29] cby_1__1__16_chany_bottom_out ; +wire [0:29] cby_1__1__16_chany_top_out ; +wire [0:0] cby_1__1__16_left_grid_pin_16_ ; +wire [0:0] cby_1__1__16_left_grid_pin_17_ ; +wire [0:0] cby_1__1__16_left_grid_pin_18_ ; +wire [0:0] cby_1__1__16_left_grid_pin_19_ ; +wire [0:0] cby_1__1__16_left_grid_pin_20_ ; +wire [0:0] cby_1__1__16_left_grid_pin_21_ ; +wire [0:0] cby_1__1__16_left_grid_pin_22_ ; +wire [0:0] cby_1__1__16_left_grid_pin_23_ ; +wire [0:0] cby_1__1__16_left_grid_pin_24_ ; +wire [0:0] cby_1__1__16_left_grid_pin_25_ ; +wire [0:0] cby_1__1__16_left_grid_pin_26_ ; +wire [0:0] cby_1__1__16_left_grid_pin_27_ ; +wire [0:0] cby_1__1__16_left_grid_pin_28_ ; +wire [0:0] cby_1__1__16_left_grid_pin_29_ ; +wire [0:0] cby_1__1__16_left_grid_pin_30_ ; +wire [0:0] cby_1__1__16_left_grid_pin_31_ ; +wire [0:0] cby_1__1__17_ccff_tail ; +wire [0:29] cby_1__1__17_chany_bottom_out ; +wire [0:29] cby_1__1__17_chany_top_out ; +wire [0:0] cby_1__1__17_left_grid_pin_16_ ; +wire [0:0] cby_1__1__17_left_grid_pin_17_ ; +wire [0:0] cby_1__1__17_left_grid_pin_18_ ; +wire [0:0] cby_1__1__17_left_grid_pin_19_ ; +wire [0:0] cby_1__1__17_left_grid_pin_20_ ; +wire [0:0] cby_1__1__17_left_grid_pin_21_ ; +wire [0:0] cby_1__1__17_left_grid_pin_22_ ; +wire [0:0] cby_1__1__17_left_grid_pin_23_ ; +wire [0:0] cby_1__1__17_left_grid_pin_24_ ; +wire [0:0] cby_1__1__17_left_grid_pin_25_ ; +wire [0:0] cby_1__1__17_left_grid_pin_26_ ; +wire [0:0] cby_1__1__17_left_grid_pin_27_ ; +wire [0:0] cby_1__1__17_left_grid_pin_28_ ; +wire [0:0] cby_1__1__17_left_grid_pin_29_ ; +wire [0:0] cby_1__1__17_left_grid_pin_30_ ; +wire [0:0] cby_1__1__17_left_grid_pin_31_ ; +wire [0:0] cby_1__1__18_ccff_tail ; +wire [0:29] cby_1__1__18_chany_bottom_out ; +wire [0:29] cby_1__1__18_chany_top_out ; +wire [0:0] cby_1__1__18_left_grid_pin_16_ ; +wire [0:0] cby_1__1__18_left_grid_pin_17_ ; +wire [0:0] cby_1__1__18_left_grid_pin_18_ ; +wire [0:0] cby_1__1__18_left_grid_pin_19_ ; +wire [0:0] cby_1__1__18_left_grid_pin_20_ ; +wire [0:0] cby_1__1__18_left_grid_pin_21_ ; +wire [0:0] cby_1__1__18_left_grid_pin_22_ ; +wire [0:0] cby_1__1__18_left_grid_pin_23_ ; +wire [0:0] cby_1__1__18_left_grid_pin_24_ ; +wire [0:0] cby_1__1__18_left_grid_pin_25_ ; +wire [0:0] cby_1__1__18_left_grid_pin_26_ ; +wire [0:0] cby_1__1__18_left_grid_pin_27_ ; +wire [0:0] cby_1__1__18_left_grid_pin_28_ ; +wire [0:0] cby_1__1__18_left_grid_pin_29_ ; +wire [0:0] cby_1__1__18_left_grid_pin_30_ ; +wire [0:0] cby_1__1__18_left_grid_pin_31_ ; +wire [0:0] cby_1__1__19_ccff_tail ; +wire [0:29] cby_1__1__19_chany_bottom_out ; +wire [0:29] cby_1__1__19_chany_top_out ; +wire [0:0] cby_1__1__19_left_grid_pin_16_ ; +wire [0:0] cby_1__1__19_left_grid_pin_17_ ; +wire [0:0] cby_1__1__19_left_grid_pin_18_ ; +wire [0:0] cby_1__1__19_left_grid_pin_19_ ; +wire [0:0] cby_1__1__19_left_grid_pin_20_ ; +wire [0:0] cby_1__1__19_left_grid_pin_21_ ; +wire [0:0] cby_1__1__19_left_grid_pin_22_ ; +wire [0:0] cby_1__1__19_left_grid_pin_23_ ; +wire [0:0] cby_1__1__19_left_grid_pin_24_ ; +wire [0:0] cby_1__1__19_left_grid_pin_25_ ; +wire [0:0] cby_1__1__19_left_grid_pin_26_ ; +wire [0:0] cby_1__1__19_left_grid_pin_27_ ; +wire [0:0] cby_1__1__19_left_grid_pin_28_ ; +wire [0:0] cby_1__1__19_left_grid_pin_29_ ; +wire [0:0] cby_1__1__19_left_grid_pin_30_ ; +wire [0:0] cby_1__1__19_left_grid_pin_31_ ; +wire [0:0] cby_1__1__1_ccff_tail ; +wire [0:29] cby_1__1__1_chany_bottom_out ; +wire [0:29] cby_1__1__1_chany_top_out ; +wire [0:0] cby_1__1__1_left_grid_pin_16_ ; +wire [0:0] cby_1__1__1_left_grid_pin_17_ ; +wire [0:0] cby_1__1__1_left_grid_pin_18_ ; +wire [0:0] cby_1__1__1_left_grid_pin_19_ ; +wire [0:0] cby_1__1__1_left_grid_pin_20_ ; +wire [0:0] cby_1__1__1_left_grid_pin_21_ ; +wire [0:0] cby_1__1__1_left_grid_pin_22_ ; +wire [0:0] cby_1__1__1_left_grid_pin_23_ ; +wire [0:0] cby_1__1__1_left_grid_pin_24_ ; +wire [0:0] cby_1__1__1_left_grid_pin_25_ ; +wire [0:0] cby_1__1__1_left_grid_pin_26_ ; +wire [0:0] cby_1__1__1_left_grid_pin_27_ ; +wire [0:0] cby_1__1__1_left_grid_pin_28_ ; +wire [0:0] cby_1__1__1_left_grid_pin_29_ ; +wire [0:0] cby_1__1__1_left_grid_pin_30_ ; +wire [0:0] cby_1__1__1_left_grid_pin_31_ ; +wire [0:0] cby_1__1__20_ccff_tail ; +wire [0:29] cby_1__1__20_chany_bottom_out ; +wire [0:29] cby_1__1__20_chany_top_out ; +wire [0:0] cby_1__1__20_left_grid_pin_16_ ; +wire [0:0] cby_1__1__20_left_grid_pin_17_ ; +wire [0:0] cby_1__1__20_left_grid_pin_18_ ; +wire [0:0] cby_1__1__20_left_grid_pin_19_ ; +wire [0:0] cby_1__1__20_left_grid_pin_20_ ; +wire [0:0] cby_1__1__20_left_grid_pin_21_ ; +wire [0:0] cby_1__1__20_left_grid_pin_22_ ; +wire [0:0] cby_1__1__20_left_grid_pin_23_ ; +wire [0:0] cby_1__1__20_left_grid_pin_24_ ; +wire [0:0] cby_1__1__20_left_grid_pin_25_ ; +wire [0:0] cby_1__1__20_left_grid_pin_26_ ; +wire [0:0] cby_1__1__20_left_grid_pin_27_ ; +wire [0:0] cby_1__1__20_left_grid_pin_28_ ; +wire [0:0] cby_1__1__20_left_grid_pin_29_ ; +wire [0:0] cby_1__1__20_left_grid_pin_30_ ; +wire [0:0] cby_1__1__20_left_grid_pin_31_ ; +wire [0:0] cby_1__1__21_ccff_tail ; +wire [0:29] cby_1__1__21_chany_bottom_out ; +wire [0:29] cby_1__1__21_chany_top_out ; +wire [0:0] cby_1__1__21_left_grid_pin_16_ ; +wire [0:0] cby_1__1__21_left_grid_pin_17_ ; +wire [0:0] cby_1__1__21_left_grid_pin_18_ ; +wire [0:0] cby_1__1__21_left_grid_pin_19_ ; +wire [0:0] cby_1__1__21_left_grid_pin_20_ ; +wire [0:0] cby_1__1__21_left_grid_pin_21_ ; +wire [0:0] cby_1__1__21_left_grid_pin_22_ ; +wire [0:0] cby_1__1__21_left_grid_pin_23_ ; +wire [0:0] cby_1__1__21_left_grid_pin_24_ ; +wire [0:0] cby_1__1__21_left_grid_pin_25_ ; +wire [0:0] cby_1__1__21_left_grid_pin_26_ ; +wire [0:0] cby_1__1__21_left_grid_pin_27_ ; +wire [0:0] cby_1__1__21_left_grid_pin_28_ ; +wire [0:0] cby_1__1__21_left_grid_pin_29_ ; +wire [0:0] cby_1__1__21_left_grid_pin_30_ ; +wire [0:0] cby_1__1__21_left_grid_pin_31_ ; +wire [0:0] cby_1__1__22_ccff_tail ; +wire [0:29] cby_1__1__22_chany_bottom_out ; +wire [0:29] cby_1__1__22_chany_top_out ; +wire [0:0] cby_1__1__22_left_grid_pin_16_ ; +wire [0:0] cby_1__1__22_left_grid_pin_17_ ; +wire [0:0] cby_1__1__22_left_grid_pin_18_ ; +wire [0:0] cby_1__1__22_left_grid_pin_19_ ; +wire [0:0] cby_1__1__22_left_grid_pin_20_ ; +wire [0:0] cby_1__1__22_left_grid_pin_21_ ; +wire [0:0] cby_1__1__22_left_grid_pin_22_ ; +wire [0:0] cby_1__1__22_left_grid_pin_23_ ; +wire [0:0] cby_1__1__22_left_grid_pin_24_ ; +wire [0:0] cby_1__1__22_left_grid_pin_25_ ; +wire [0:0] cby_1__1__22_left_grid_pin_26_ ; +wire [0:0] cby_1__1__22_left_grid_pin_27_ ; +wire [0:0] cby_1__1__22_left_grid_pin_28_ ; +wire [0:0] cby_1__1__22_left_grid_pin_29_ ; +wire [0:0] cby_1__1__22_left_grid_pin_30_ ; +wire [0:0] cby_1__1__22_left_grid_pin_31_ ; +wire [0:0] cby_1__1__23_ccff_tail ; +wire [0:29] cby_1__1__23_chany_bottom_out ; +wire [0:29] cby_1__1__23_chany_top_out ; +wire [0:0] cby_1__1__23_left_grid_pin_16_ ; +wire [0:0] cby_1__1__23_left_grid_pin_17_ ; +wire [0:0] cby_1__1__23_left_grid_pin_18_ ; +wire [0:0] cby_1__1__23_left_grid_pin_19_ ; +wire [0:0] cby_1__1__23_left_grid_pin_20_ ; +wire [0:0] cby_1__1__23_left_grid_pin_21_ ; +wire [0:0] cby_1__1__23_left_grid_pin_22_ ; +wire [0:0] cby_1__1__23_left_grid_pin_23_ ; +wire [0:0] cby_1__1__23_left_grid_pin_24_ ; +wire [0:0] cby_1__1__23_left_grid_pin_25_ ; +wire [0:0] cby_1__1__23_left_grid_pin_26_ ; +wire [0:0] cby_1__1__23_left_grid_pin_27_ ; +wire [0:0] cby_1__1__23_left_grid_pin_28_ ; +wire [0:0] cby_1__1__23_left_grid_pin_29_ ; +wire [0:0] cby_1__1__23_left_grid_pin_30_ ; +wire [0:0] cby_1__1__23_left_grid_pin_31_ ; +wire [0:0] cby_1__1__24_ccff_tail ; +wire [0:29] cby_1__1__24_chany_bottom_out ; +wire [0:29] cby_1__1__24_chany_top_out ; +wire [0:0] cby_1__1__24_left_grid_pin_16_ ; +wire [0:0] cby_1__1__24_left_grid_pin_17_ ; +wire [0:0] cby_1__1__24_left_grid_pin_18_ ; +wire [0:0] cby_1__1__24_left_grid_pin_19_ ; +wire [0:0] cby_1__1__24_left_grid_pin_20_ ; +wire [0:0] cby_1__1__24_left_grid_pin_21_ ; +wire [0:0] cby_1__1__24_left_grid_pin_22_ ; +wire [0:0] cby_1__1__24_left_grid_pin_23_ ; +wire [0:0] cby_1__1__24_left_grid_pin_24_ ; +wire [0:0] cby_1__1__24_left_grid_pin_25_ ; +wire [0:0] cby_1__1__24_left_grid_pin_26_ ; +wire [0:0] cby_1__1__24_left_grid_pin_27_ ; +wire [0:0] cby_1__1__24_left_grid_pin_28_ ; +wire [0:0] cby_1__1__24_left_grid_pin_29_ ; +wire [0:0] cby_1__1__24_left_grid_pin_30_ ; +wire [0:0] cby_1__1__24_left_grid_pin_31_ ; +wire [0:0] cby_1__1__25_ccff_tail ; +wire [0:29] cby_1__1__25_chany_bottom_out ; +wire [0:29] cby_1__1__25_chany_top_out ; +wire [0:0] cby_1__1__25_left_grid_pin_16_ ; +wire [0:0] cby_1__1__25_left_grid_pin_17_ ; +wire [0:0] cby_1__1__25_left_grid_pin_18_ ; +wire [0:0] cby_1__1__25_left_grid_pin_19_ ; +wire [0:0] cby_1__1__25_left_grid_pin_20_ ; +wire [0:0] cby_1__1__25_left_grid_pin_21_ ; +wire [0:0] cby_1__1__25_left_grid_pin_22_ ; +wire [0:0] cby_1__1__25_left_grid_pin_23_ ; +wire [0:0] cby_1__1__25_left_grid_pin_24_ ; +wire [0:0] cby_1__1__25_left_grid_pin_25_ ; +wire [0:0] cby_1__1__25_left_grid_pin_26_ ; +wire [0:0] cby_1__1__25_left_grid_pin_27_ ; +wire [0:0] cby_1__1__25_left_grid_pin_28_ ; +wire [0:0] cby_1__1__25_left_grid_pin_29_ ; +wire [0:0] cby_1__1__25_left_grid_pin_30_ ; +wire [0:0] cby_1__1__25_left_grid_pin_31_ ; +wire [0:0] cby_1__1__26_ccff_tail ; +wire [0:29] cby_1__1__26_chany_bottom_out ; +wire [0:29] cby_1__1__26_chany_top_out ; +wire [0:0] cby_1__1__26_left_grid_pin_16_ ; +wire [0:0] cby_1__1__26_left_grid_pin_17_ ; +wire [0:0] cby_1__1__26_left_grid_pin_18_ ; +wire [0:0] cby_1__1__26_left_grid_pin_19_ ; +wire [0:0] cby_1__1__26_left_grid_pin_20_ ; +wire [0:0] cby_1__1__26_left_grid_pin_21_ ; +wire [0:0] cby_1__1__26_left_grid_pin_22_ ; +wire [0:0] cby_1__1__26_left_grid_pin_23_ ; +wire [0:0] cby_1__1__26_left_grid_pin_24_ ; +wire [0:0] cby_1__1__26_left_grid_pin_25_ ; +wire [0:0] cby_1__1__26_left_grid_pin_26_ ; +wire [0:0] cby_1__1__26_left_grid_pin_27_ ; +wire [0:0] cby_1__1__26_left_grid_pin_28_ ; +wire [0:0] cby_1__1__26_left_grid_pin_29_ ; +wire [0:0] cby_1__1__26_left_grid_pin_30_ ; +wire [0:0] cby_1__1__26_left_grid_pin_31_ ; +wire [0:0] cby_1__1__27_ccff_tail ; +wire [0:29] cby_1__1__27_chany_bottom_out ; +wire [0:29] cby_1__1__27_chany_top_out ; +wire [0:0] cby_1__1__27_left_grid_pin_16_ ; +wire [0:0] cby_1__1__27_left_grid_pin_17_ ; +wire [0:0] cby_1__1__27_left_grid_pin_18_ ; +wire [0:0] cby_1__1__27_left_grid_pin_19_ ; +wire [0:0] cby_1__1__27_left_grid_pin_20_ ; +wire [0:0] cby_1__1__27_left_grid_pin_21_ ; +wire [0:0] cby_1__1__27_left_grid_pin_22_ ; +wire [0:0] cby_1__1__27_left_grid_pin_23_ ; +wire [0:0] cby_1__1__27_left_grid_pin_24_ ; +wire [0:0] cby_1__1__27_left_grid_pin_25_ ; +wire [0:0] cby_1__1__27_left_grid_pin_26_ ; +wire [0:0] cby_1__1__27_left_grid_pin_27_ ; +wire [0:0] cby_1__1__27_left_grid_pin_28_ ; +wire [0:0] cby_1__1__27_left_grid_pin_29_ ; +wire [0:0] cby_1__1__27_left_grid_pin_30_ ; +wire [0:0] cby_1__1__27_left_grid_pin_31_ ; +wire [0:0] cby_1__1__28_ccff_tail ; +wire [0:29] cby_1__1__28_chany_bottom_out ; +wire [0:29] cby_1__1__28_chany_top_out ; +wire [0:0] cby_1__1__28_left_grid_pin_16_ ; +wire [0:0] cby_1__1__28_left_grid_pin_17_ ; +wire [0:0] cby_1__1__28_left_grid_pin_18_ ; +wire [0:0] cby_1__1__28_left_grid_pin_19_ ; +wire [0:0] cby_1__1__28_left_grid_pin_20_ ; +wire [0:0] cby_1__1__28_left_grid_pin_21_ ; +wire [0:0] cby_1__1__28_left_grid_pin_22_ ; +wire [0:0] cby_1__1__28_left_grid_pin_23_ ; +wire [0:0] cby_1__1__28_left_grid_pin_24_ ; +wire [0:0] cby_1__1__28_left_grid_pin_25_ ; +wire [0:0] cby_1__1__28_left_grid_pin_26_ ; +wire [0:0] cby_1__1__28_left_grid_pin_27_ ; +wire [0:0] cby_1__1__28_left_grid_pin_28_ ; +wire [0:0] cby_1__1__28_left_grid_pin_29_ ; +wire [0:0] cby_1__1__28_left_grid_pin_30_ ; +wire [0:0] cby_1__1__28_left_grid_pin_31_ ; +wire [0:0] cby_1__1__29_ccff_tail ; +wire [0:29] cby_1__1__29_chany_bottom_out ; +wire [0:29] cby_1__1__29_chany_top_out ; +wire [0:0] cby_1__1__29_left_grid_pin_16_ ; +wire [0:0] cby_1__1__29_left_grid_pin_17_ ; +wire [0:0] cby_1__1__29_left_grid_pin_18_ ; +wire [0:0] cby_1__1__29_left_grid_pin_19_ ; +wire [0:0] cby_1__1__29_left_grid_pin_20_ ; +wire [0:0] cby_1__1__29_left_grid_pin_21_ ; +wire [0:0] cby_1__1__29_left_grid_pin_22_ ; +wire [0:0] cby_1__1__29_left_grid_pin_23_ ; +wire [0:0] cby_1__1__29_left_grid_pin_24_ ; +wire [0:0] cby_1__1__29_left_grid_pin_25_ ; +wire [0:0] cby_1__1__29_left_grid_pin_26_ ; +wire [0:0] cby_1__1__29_left_grid_pin_27_ ; +wire [0:0] cby_1__1__29_left_grid_pin_28_ ; +wire [0:0] cby_1__1__29_left_grid_pin_29_ ; +wire [0:0] cby_1__1__29_left_grid_pin_30_ ; +wire [0:0] cby_1__1__29_left_grid_pin_31_ ; +wire [0:0] cby_1__1__2_ccff_tail ; +wire [0:29] cby_1__1__2_chany_bottom_out ; +wire [0:29] cby_1__1__2_chany_top_out ; +wire [0:0] cby_1__1__2_left_grid_pin_16_ ; +wire [0:0] cby_1__1__2_left_grid_pin_17_ ; +wire [0:0] cby_1__1__2_left_grid_pin_18_ ; +wire [0:0] cby_1__1__2_left_grid_pin_19_ ; +wire [0:0] cby_1__1__2_left_grid_pin_20_ ; +wire [0:0] cby_1__1__2_left_grid_pin_21_ ; +wire [0:0] cby_1__1__2_left_grid_pin_22_ ; +wire [0:0] cby_1__1__2_left_grid_pin_23_ ; +wire [0:0] cby_1__1__2_left_grid_pin_24_ ; +wire [0:0] cby_1__1__2_left_grid_pin_25_ ; +wire [0:0] cby_1__1__2_left_grid_pin_26_ ; +wire [0:0] cby_1__1__2_left_grid_pin_27_ ; +wire [0:0] cby_1__1__2_left_grid_pin_28_ ; +wire [0:0] cby_1__1__2_left_grid_pin_29_ ; +wire [0:0] cby_1__1__2_left_grid_pin_30_ ; +wire [0:0] cby_1__1__2_left_grid_pin_31_ ; +wire [0:0] cby_1__1__30_ccff_tail ; +wire [0:29] cby_1__1__30_chany_bottom_out ; +wire [0:29] cby_1__1__30_chany_top_out ; +wire [0:0] cby_1__1__30_left_grid_pin_16_ ; +wire [0:0] cby_1__1__30_left_grid_pin_17_ ; +wire [0:0] cby_1__1__30_left_grid_pin_18_ ; +wire [0:0] cby_1__1__30_left_grid_pin_19_ ; +wire [0:0] cby_1__1__30_left_grid_pin_20_ ; +wire [0:0] cby_1__1__30_left_grid_pin_21_ ; +wire [0:0] cby_1__1__30_left_grid_pin_22_ ; +wire [0:0] cby_1__1__30_left_grid_pin_23_ ; +wire [0:0] cby_1__1__30_left_grid_pin_24_ ; +wire [0:0] cby_1__1__30_left_grid_pin_25_ ; +wire [0:0] cby_1__1__30_left_grid_pin_26_ ; +wire [0:0] cby_1__1__30_left_grid_pin_27_ ; +wire [0:0] cby_1__1__30_left_grid_pin_28_ ; +wire [0:0] cby_1__1__30_left_grid_pin_29_ ; +wire [0:0] cby_1__1__30_left_grid_pin_30_ ; +wire [0:0] cby_1__1__30_left_grid_pin_31_ ; +wire [0:0] cby_1__1__31_ccff_tail ; +wire [0:29] cby_1__1__31_chany_bottom_out ; +wire [0:29] cby_1__1__31_chany_top_out ; +wire [0:0] cby_1__1__31_left_grid_pin_16_ ; +wire [0:0] cby_1__1__31_left_grid_pin_17_ ; +wire [0:0] cby_1__1__31_left_grid_pin_18_ ; +wire [0:0] cby_1__1__31_left_grid_pin_19_ ; +wire [0:0] cby_1__1__31_left_grid_pin_20_ ; +wire [0:0] cby_1__1__31_left_grid_pin_21_ ; +wire [0:0] cby_1__1__31_left_grid_pin_22_ ; +wire [0:0] cby_1__1__31_left_grid_pin_23_ ; +wire [0:0] cby_1__1__31_left_grid_pin_24_ ; +wire [0:0] cby_1__1__31_left_grid_pin_25_ ; +wire [0:0] cby_1__1__31_left_grid_pin_26_ ; +wire [0:0] cby_1__1__31_left_grid_pin_27_ ; +wire [0:0] cby_1__1__31_left_grid_pin_28_ ; +wire [0:0] cby_1__1__31_left_grid_pin_29_ ; +wire [0:0] cby_1__1__31_left_grid_pin_30_ ; +wire [0:0] cby_1__1__31_left_grid_pin_31_ ; +wire [0:0] cby_1__1__32_ccff_tail ; +wire [0:29] cby_1__1__32_chany_bottom_out ; +wire [0:29] cby_1__1__32_chany_top_out ; +wire [0:0] cby_1__1__32_left_grid_pin_16_ ; +wire [0:0] cby_1__1__32_left_grid_pin_17_ ; +wire [0:0] cby_1__1__32_left_grid_pin_18_ ; +wire [0:0] cby_1__1__32_left_grid_pin_19_ ; +wire [0:0] cby_1__1__32_left_grid_pin_20_ ; +wire [0:0] cby_1__1__32_left_grid_pin_21_ ; +wire [0:0] cby_1__1__32_left_grid_pin_22_ ; +wire [0:0] cby_1__1__32_left_grid_pin_23_ ; +wire [0:0] cby_1__1__32_left_grid_pin_24_ ; +wire [0:0] cby_1__1__32_left_grid_pin_25_ ; +wire [0:0] cby_1__1__32_left_grid_pin_26_ ; +wire [0:0] cby_1__1__32_left_grid_pin_27_ ; +wire [0:0] cby_1__1__32_left_grid_pin_28_ ; +wire [0:0] cby_1__1__32_left_grid_pin_29_ ; +wire [0:0] cby_1__1__32_left_grid_pin_30_ ; +wire [0:0] cby_1__1__32_left_grid_pin_31_ ; +wire [0:0] cby_1__1__33_ccff_tail ; +wire [0:29] cby_1__1__33_chany_bottom_out ; +wire [0:29] cby_1__1__33_chany_top_out ; +wire [0:0] cby_1__1__33_left_grid_pin_16_ ; +wire [0:0] cby_1__1__33_left_grid_pin_17_ ; +wire [0:0] cby_1__1__33_left_grid_pin_18_ ; +wire [0:0] cby_1__1__33_left_grid_pin_19_ ; +wire [0:0] cby_1__1__33_left_grid_pin_20_ ; +wire [0:0] cby_1__1__33_left_grid_pin_21_ ; +wire [0:0] cby_1__1__33_left_grid_pin_22_ ; +wire [0:0] cby_1__1__33_left_grid_pin_23_ ; +wire [0:0] cby_1__1__33_left_grid_pin_24_ ; +wire [0:0] cby_1__1__33_left_grid_pin_25_ ; +wire [0:0] cby_1__1__33_left_grid_pin_26_ ; +wire [0:0] cby_1__1__33_left_grid_pin_27_ ; +wire [0:0] cby_1__1__33_left_grid_pin_28_ ; +wire [0:0] cby_1__1__33_left_grid_pin_29_ ; +wire [0:0] cby_1__1__33_left_grid_pin_30_ ; +wire [0:0] cby_1__1__33_left_grid_pin_31_ ; +wire [0:0] cby_1__1__34_ccff_tail ; +wire [0:29] cby_1__1__34_chany_bottom_out ; +wire [0:29] cby_1__1__34_chany_top_out ; +wire [0:0] cby_1__1__34_left_grid_pin_16_ ; +wire [0:0] cby_1__1__34_left_grid_pin_17_ ; +wire [0:0] cby_1__1__34_left_grid_pin_18_ ; +wire [0:0] cby_1__1__34_left_grid_pin_19_ ; +wire [0:0] cby_1__1__34_left_grid_pin_20_ ; +wire [0:0] cby_1__1__34_left_grid_pin_21_ ; +wire [0:0] cby_1__1__34_left_grid_pin_22_ ; +wire [0:0] cby_1__1__34_left_grid_pin_23_ ; +wire [0:0] cby_1__1__34_left_grid_pin_24_ ; +wire [0:0] cby_1__1__34_left_grid_pin_25_ ; +wire [0:0] cby_1__1__34_left_grid_pin_26_ ; +wire [0:0] cby_1__1__34_left_grid_pin_27_ ; +wire [0:0] cby_1__1__34_left_grid_pin_28_ ; +wire [0:0] cby_1__1__34_left_grid_pin_29_ ; +wire [0:0] cby_1__1__34_left_grid_pin_30_ ; +wire [0:0] cby_1__1__34_left_grid_pin_31_ ; +wire [0:0] cby_1__1__35_ccff_tail ; +wire [0:29] cby_1__1__35_chany_bottom_out ; +wire [0:29] cby_1__1__35_chany_top_out ; +wire [0:0] cby_1__1__35_left_grid_pin_16_ ; +wire [0:0] cby_1__1__35_left_grid_pin_17_ ; +wire [0:0] cby_1__1__35_left_grid_pin_18_ ; +wire [0:0] cby_1__1__35_left_grid_pin_19_ ; +wire [0:0] cby_1__1__35_left_grid_pin_20_ ; +wire [0:0] cby_1__1__35_left_grid_pin_21_ ; +wire [0:0] cby_1__1__35_left_grid_pin_22_ ; +wire [0:0] cby_1__1__35_left_grid_pin_23_ ; +wire [0:0] cby_1__1__35_left_grid_pin_24_ ; +wire [0:0] cby_1__1__35_left_grid_pin_25_ ; +wire [0:0] cby_1__1__35_left_grid_pin_26_ ; +wire [0:0] cby_1__1__35_left_grid_pin_27_ ; +wire [0:0] cby_1__1__35_left_grid_pin_28_ ; +wire [0:0] cby_1__1__35_left_grid_pin_29_ ; +wire [0:0] cby_1__1__35_left_grid_pin_30_ ; +wire [0:0] cby_1__1__35_left_grid_pin_31_ ; +wire [0:0] cby_1__1__36_ccff_tail ; +wire [0:29] cby_1__1__36_chany_bottom_out ; +wire [0:29] cby_1__1__36_chany_top_out ; +wire [0:0] cby_1__1__36_left_grid_pin_16_ ; +wire [0:0] cby_1__1__36_left_grid_pin_17_ ; +wire [0:0] cby_1__1__36_left_grid_pin_18_ ; +wire [0:0] cby_1__1__36_left_grid_pin_19_ ; +wire [0:0] cby_1__1__36_left_grid_pin_20_ ; +wire [0:0] cby_1__1__36_left_grid_pin_21_ ; +wire [0:0] cby_1__1__36_left_grid_pin_22_ ; +wire [0:0] cby_1__1__36_left_grid_pin_23_ ; +wire [0:0] cby_1__1__36_left_grid_pin_24_ ; +wire [0:0] cby_1__1__36_left_grid_pin_25_ ; +wire [0:0] cby_1__1__36_left_grid_pin_26_ ; +wire [0:0] cby_1__1__36_left_grid_pin_27_ ; +wire [0:0] cby_1__1__36_left_grid_pin_28_ ; +wire [0:0] cby_1__1__36_left_grid_pin_29_ ; +wire [0:0] cby_1__1__36_left_grid_pin_30_ ; +wire [0:0] cby_1__1__36_left_grid_pin_31_ ; +wire [0:0] cby_1__1__37_ccff_tail ; +wire [0:29] cby_1__1__37_chany_bottom_out ; +wire [0:29] cby_1__1__37_chany_top_out ; +wire [0:0] cby_1__1__37_left_grid_pin_16_ ; +wire [0:0] cby_1__1__37_left_grid_pin_17_ ; +wire [0:0] cby_1__1__37_left_grid_pin_18_ ; +wire [0:0] cby_1__1__37_left_grid_pin_19_ ; +wire [0:0] cby_1__1__37_left_grid_pin_20_ ; +wire [0:0] cby_1__1__37_left_grid_pin_21_ ; +wire [0:0] cby_1__1__37_left_grid_pin_22_ ; +wire [0:0] cby_1__1__37_left_grid_pin_23_ ; +wire [0:0] cby_1__1__37_left_grid_pin_24_ ; +wire [0:0] cby_1__1__37_left_grid_pin_25_ ; +wire [0:0] cby_1__1__37_left_grid_pin_26_ ; +wire [0:0] cby_1__1__37_left_grid_pin_27_ ; +wire [0:0] cby_1__1__37_left_grid_pin_28_ ; +wire [0:0] cby_1__1__37_left_grid_pin_29_ ; +wire [0:0] cby_1__1__37_left_grid_pin_30_ ; +wire [0:0] cby_1__1__37_left_grid_pin_31_ ; +wire [0:0] cby_1__1__38_ccff_tail ; +wire [0:29] cby_1__1__38_chany_bottom_out ; +wire [0:29] cby_1__1__38_chany_top_out ; +wire [0:0] cby_1__1__38_left_grid_pin_16_ ; +wire [0:0] cby_1__1__38_left_grid_pin_17_ ; +wire [0:0] cby_1__1__38_left_grid_pin_18_ ; +wire [0:0] cby_1__1__38_left_grid_pin_19_ ; +wire [0:0] cby_1__1__38_left_grid_pin_20_ ; +wire [0:0] cby_1__1__38_left_grid_pin_21_ ; +wire [0:0] cby_1__1__38_left_grid_pin_22_ ; +wire [0:0] cby_1__1__38_left_grid_pin_23_ ; +wire [0:0] cby_1__1__38_left_grid_pin_24_ ; +wire [0:0] cby_1__1__38_left_grid_pin_25_ ; +wire [0:0] cby_1__1__38_left_grid_pin_26_ ; +wire [0:0] cby_1__1__38_left_grid_pin_27_ ; +wire [0:0] cby_1__1__38_left_grid_pin_28_ ; +wire [0:0] cby_1__1__38_left_grid_pin_29_ ; +wire [0:0] cby_1__1__38_left_grid_pin_30_ ; +wire [0:0] cby_1__1__38_left_grid_pin_31_ ; +wire [0:0] cby_1__1__39_ccff_tail ; +wire [0:29] cby_1__1__39_chany_bottom_out ; +wire [0:29] cby_1__1__39_chany_top_out ; +wire [0:0] cby_1__1__39_left_grid_pin_16_ ; +wire [0:0] cby_1__1__39_left_grid_pin_17_ ; +wire [0:0] cby_1__1__39_left_grid_pin_18_ ; +wire [0:0] cby_1__1__39_left_grid_pin_19_ ; +wire [0:0] cby_1__1__39_left_grid_pin_20_ ; +wire [0:0] cby_1__1__39_left_grid_pin_21_ ; +wire [0:0] cby_1__1__39_left_grid_pin_22_ ; +wire [0:0] cby_1__1__39_left_grid_pin_23_ ; +wire [0:0] cby_1__1__39_left_grid_pin_24_ ; +wire [0:0] cby_1__1__39_left_grid_pin_25_ ; +wire [0:0] cby_1__1__39_left_grid_pin_26_ ; +wire [0:0] cby_1__1__39_left_grid_pin_27_ ; +wire [0:0] cby_1__1__39_left_grid_pin_28_ ; +wire [0:0] cby_1__1__39_left_grid_pin_29_ ; +wire [0:0] cby_1__1__39_left_grid_pin_30_ ; +wire [0:0] cby_1__1__39_left_grid_pin_31_ ; +wire [0:0] cby_1__1__3_ccff_tail ; +wire [0:29] cby_1__1__3_chany_bottom_out ; +wire [0:29] cby_1__1__3_chany_top_out ; +wire [0:0] cby_1__1__3_left_grid_pin_16_ ; +wire [0:0] cby_1__1__3_left_grid_pin_17_ ; +wire [0:0] cby_1__1__3_left_grid_pin_18_ ; +wire [0:0] cby_1__1__3_left_grid_pin_19_ ; +wire [0:0] cby_1__1__3_left_grid_pin_20_ ; +wire [0:0] cby_1__1__3_left_grid_pin_21_ ; +wire [0:0] cby_1__1__3_left_grid_pin_22_ ; +wire [0:0] cby_1__1__3_left_grid_pin_23_ ; +wire [0:0] cby_1__1__3_left_grid_pin_24_ ; +wire [0:0] cby_1__1__3_left_grid_pin_25_ ; +wire [0:0] cby_1__1__3_left_grid_pin_26_ ; +wire [0:0] cby_1__1__3_left_grid_pin_27_ ; +wire [0:0] cby_1__1__3_left_grid_pin_28_ ; +wire [0:0] cby_1__1__3_left_grid_pin_29_ ; +wire [0:0] cby_1__1__3_left_grid_pin_30_ ; +wire [0:0] cby_1__1__3_left_grid_pin_31_ ; +wire [0:0] cby_1__1__40_ccff_tail ; +wire [0:29] cby_1__1__40_chany_bottom_out ; +wire [0:29] cby_1__1__40_chany_top_out ; +wire [0:0] cby_1__1__40_left_grid_pin_16_ ; +wire [0:0] cby_1__1__40_left_grid_pin_17_ ; +wire [0:0] cby_1__1__40_left_grid_pin_18_ ; +wire [0:0] cby_1__1__40_left_grid_pin_19_ ; +wire [0:0] cby_1__1__40_left_grid_pin_20_ ; +wire [0:0] cby_1__1__40_left_grid_pin_21_ ; +wire [0:0] cby_1__1__40_left_grid_pin_22_ ; +wire [0:0] cby_1__1__40_left_grid_pin_23_ ; +wire [0:0] cby_1__1__40_left_grid_pin_24_ ; +wire [0:0] cby_1__1__40_left_grid_pin_25_ ; +wire [0:0] cby_1__1__40_left_grid_pin_26_ ; +wire [0:0] cby_1__1__40_left_grid_pin_27_ ; +wire [0:0] cby_1__1__40_left_grid_pin_28_ ; +wire [0:0] cby_1__1__40_left_grid_pin_29_ ; +wire [0:0] cby_1__1__40_left_grid_pin_30_ ; +wire [0:0] cby_1__1__40_left_grid_pin_31_ ; +wire [0:0] cby_1__1__41_ccff_tail ; +wire [0:29] cby_1__1__41_chany_bottom_out ; +wire [0:29] cby_1__1__41_chany_top_out ; +wire [0:0] cby_1__1__41_left_grid_pin_16_ ; +wire [0:0] cby_1__1__41_left_grid_pin_17_ ; +wire [0:0] cby_1__1__41_left_grid_pin_18_ ; +wire [0:0] cby_1__1__41_left_grid_pin_19_ ; +wire [0:0] cby_1__1__41_left_grid_pin_20_ ; +wire [0:0] cby_1__1__41_left_grid_pin_21_ ; +wire [0:0] cby_1__1__41_left_grid_pin_22_ ; +wire [0:0] cby_1__1__41_left_grid_pin_23_ ; +wire [0:0] cby_1__1__41_left_grid_pin_24_ ; +wire [0:0] cby_1__1__41_left_grid_pin_25_ ; +wire [0:0] cby_1__1__41_left_grid_pin_26_ ; +wire [0:0] cby_1__1__41_left_grid_pin_27_ ; +wire [0:0] cby_1__1__41_left_grid_pin_28_ ; +wire [0:0] cby_1__1__41_left_grid_pin_29_ ; +wire [0:0] cby_1__1__41_left_grid_pin_30_ ; +wire [0:0] cby_1__1__41_left_grid_pin_31_ ; +wire [0:0] cby_1__1__42_ccff_tail ; +wire [0:29] cby_1__1__42_chany_bottom_out ; +wire [0:29] cby_1__1__42_chany_top_out ; +wire [0:0] cby_1__1__42_left_grid_pin_16_ ; +wire [0:0] cby_1__1__42_left_grid_pin_17_ ; +wire [0:0] cby_1__1__42_left_grid_pin_18_ ; +wire [0:0] cby_1__1__42_left_grid_pin_19_ ; +wire [0:0] cby_1__1__42_left_grid_pin_20_ ; +wire [0:0] cby_1__1__42_left_grid_pin_21_ ; +wire [0:0] cby_1__1__42_left_grid_pin_22_ ; +wire [0:0] cby_1__1__42_left_grid_pin_23_ ; +wire [0:0] cby_1__1__42_left_grid_pin_24_ ; +wire [0:0] cby_1__1__42_left_grid_pin_25_ ; +wire [0:0] cby_1__1__42_left_grid_pin_26_ ; +wire [0:0] cby_1__1__42_left_grid_pin_27_ ; +wire [0:0] cby_1__1__42_left_grid_pin_28_ ; +wire [0:0] cby_1__1__42_left_grid_pin_29_ ; +wire [0:0] cby_1__1__42_left_grid_pin_30_ ; +wire [0:0] cby_1__1__42_left_grid_pin_31_ ; +wire [0:0] cby_1__1__43_ccff_tail ; +wire [0:29] cby_1__1__43_chany_bottom_out ; +wire [0:29] cby_1__1__43_chany_top_out ; +wire [0:0] cby_1__1__43_left_grid_pin_16_ ; +wire [0:0] cby_1__1__43_left_grid_pin_17_ ; +wire [0:0] cby_1__1__43_left_grid_pin_18_ ; +wire [0:0] cby_1__1__43_left_grid_pin_19_ ; +wire [0:0] cby_1__1__43_left_grid_pin_20_ ; +wire [0:0] cby_1__1__43_left_grid_pin_21_ ; +wire [0:0] cby_1__1__43_left_grid_pin_22_ ; +wire [0:0] cby_1__1__43_left_grid_pin_23_ ; +wire [0:0] cby_1__1__43_left_grid_pin_24_ ; +wire [0:0] cby_1__1__43_left_grid_pin_25_ ; +wire [0:0] cby_1__1__43_left_grid_pin_26_ ; +wire [0:0] cby_1__1__43_left_grid_pin_27_ ; +wire [0:0] cby_1__1__43_left_grid_pin_28_ ; +wire [0:0] cby_1__1__43_left_grid_pin_29_ ; +wire [0:0] cby_1__1__43_left_grid_pin_30_ ; +wire [0:0] cby_1__1__43_left_grid_pin_31_ ; +wire [0:0] cby_1__1__44_ccff_tail ; +wire [0:29] cby_1__1__44_chany_bottom_out ; +wire [0:29] cby_1__1__44_chany_top_out ; +wire [0:0] cby_1__1__44_left_grid_pin_16_ ; +wire [0:0] cby_1__1__44_left_grid_pin_17_ ; +wire [0:0] cby_1__1__44_left_grid_pin_18_ ; +wire [0:0] cby_1__1__44_left_grid_pin_19_ ; +wire [0:0] cby_1__1__44_left_grid_pin_20_ ; +wire [0:0] cby_1__1__44_left_grid_pin_21_ ; +wire [0:0] cby_1__1__44_left_grid_pin_22_ ; +wire [0:0] cby_1__1__44_left_grid_pin_23_ ; +wire [0:0] cby_1__1__44_left_grid_pin_24_ ; +wire [0:0] cby_1__1__44_left_grid_pin_25_ ; +wire [0:0] cby_1__1__44_left_grid_pin_26_ ; +wire [0:0] cby_1__1__44_left_grid_pin_27_ ; +wire [0:0] cby_1__1__44_left_grid_pin_28_ ; +wire [0:0] cby_1__1__44_left_grid_pin_29_ ; +wire [0:0] cby_1__1__44_left_grid_pin_30_ ; +wire [0:0] cby_1__1__44_left_grid_pin_31_ ; +wire [0:0] cby_1__1__45_ccff_tail ; +wire [0:29] cby_1__1__45_chany_bottom_out ; +wire [0:29] cby_1__1__45_chany_top_out ; +wire [0:0] cby_1__1__45_left_grid_pin_16_ ; +wire [0:0] cby_1__1__45_left_grid_pin_17_ ; +wire [0:0] cby_1__1__45_left_grid_pin_18_ ; +wire [0:0] cby_1__1__45_left_grid_pin_19_ ; +wire [0:0] cby_1__1__45_left_grid_pin_20_ ; +wire [0:0] cby_1__1__45_left_grid_pin_21_ ; +wire [0:0] cby_1__1__45_left_grid_pin_22_ ; +wire [0:0] cby_1__1__45_left_grid_pin_23_ ; +wire [0:0] cby_1__1__45_left_grid_pin_24_ ; +wire [0:0] cby_1__1__45_left_grid_pin_25_ ; +wire [0:0] cby_1__1__45_left_grid_pin_26_ ; +wire [0:0] cby_1__1__45_left_grid_pin_27_ ; +wire [0:0] cby_1__1__45_left_grid_pin_28_ ; +wire [0:0] cby_1__1__45_left_grid_pin_29_ ; +wire [0:0] cby_1__1__45_left_grid_pin_30_ ; +wire [0:0] cby_1__1__45_left_grid_pin_31_ ; +wire [0:0] cby_1__1__46_ccff_tail ; +wire [0:29] cby_1__1__46_chany_bottom_out ; +wire [0:29] cby_1__1__46_chany_top_out ; +wire [0:0] cby_1__1__46_left_grid_pin_16_ ; +wire [0:0] cby_1__1__46_left_grid_pin_17_ ; +wire [0:0] cby_1__1__46_left_grid_pin_18_ ; +wire [0:0] cby_1__1__46_left_grid_pin_19_ ; +wire [0:0] cby_1__1__46_left_grid_pin_20_ ; +wire [0:0] cby_1__1__46_left_grid_pin_21_ ; +wire [0:0] cby_1__1__46_left_grid_pin_22_ ; +wire [0:0] cby_1__1__46_left_grid_pin_23_ ; +wire [0:0] cby_1__1__46_left_grid_pin_24_ ; +wire [0:0] cby_1__1__46_left_grid_pin_25_ ; +wire [0:0] cby_1__1__46_left_grid_pin_26_ ; +wire [0:0] cby_1__1__46_left_grid_pin_27_ ; +wire [0:0] cby_1__1__46_left_grid_pin_28_ ; +wire [0:0] cby_1__1__46_left_grid_pin_29_ ; +wire [0:0] cby_1__1__46_left_grid_pin_30_ ; +wire [0:0] cby_1__1__46_left_grid_pin_31_ ; +wire [0:0] cby_1__1__47_ccff_tail ; +wire [0:29] cby_1__1__47_chany_bottom_out ; +wire [0:29] cby_1__1__47_chany_top_out ; +wire [0:0] cby_1__1__47_left_grid_pin_16_ ; +wire [0:0] cby_1__1__47_left_grid_pin_17_ ; +wire [0:0] cby_1__1__47_left_grid_pin_18_ ; +wire [0:0] cby_1__1__47_left_grid_pin_19_ ; +wire [0:0] cby_1__1__47_left_grid_pin_20_ ; +wire [0:0] cby_1__1__47_left_grid_pin_21_ ; +wire [0:0] cby_1__1__47_left_grid_pin_22_ ; +wire [0:0] cby_1__1__47_left_grid_pin_23_ ; +wire [0:0] cby_1__1__47_left_grid_pin_24_ ; +wire [0:0] cby_1__1__47_left_grid_pin_25_ ; +wire [0:0] cby_1__1__47_left_grid_pin_26_ ; +wire [0:0] cby_1__1__47_left_grid_pin_27_ ; +wire [0:0] cby_1__1__47_left_grid_pin_28_ ; +wire [0:0] cby_1__1__47_left_grid_pin_29_ ; +wire [0:0] cby_1__1__47_left_grid_pin_30_ ; +wire [0:0] cby_1__1__47_left_grid_pin_31_ ; +wire [0:0] cby_1__1__48_ccff_tail ; +wire [0:29] cby_1__1__48_chany_bottom_out ; +wire [0:29] cby_1__1__48_chany_top_out ; +wire [0:0] cby_1__1__48_left_grid_pin_16_ ; +wire [0:0] cby_1__1__48_left_grid_pin_17_ ; +wire [0:0] cby_1__1__48_left_grid_pin_18_ ; +wire [0:0] cby_1__1__48_left_grid_pin_19_ ; +wire [0:0] cby_1__1__48_left_grid_pin_20_ ; +wire [0:0] cby_1__1__48_left_grid_pin_21_ ; +wire [0:0] cby_1__1__48_left_grid_pin_22_ ; +wire [0:0] cby_1__1__48_left_grid_pin_23_ ; +wire [0:0] cby_1__1__48_left_grid_pin_24_ ; +wire [0:0] cby_1__1__48_left_grid_pin_25_ ; +wire [0:0] cby_1__1__48_left_grid_pin_26_ ; +wire [0:0] cby_1__1__48_left_grid_pin_27_ ; +wire [0:0] cby_1__1__48_left_grid_pin_28_ ; +wire [0:0] cby_1__1__48_left_grid_pin_29_ ; +wire [0:0] cby_1__1__48_left_grid_pin_30_ ; +wire [0:0] cby_1__1__48_left_grid_pin_31_ ; +wire [0:0] cby_1__1__49_ccff_tail ; +wire [0:29] cby_1__1__49_chany_bottom_out ; +wire [0:29] cby_1__1__49_chany_top_out ; +wire [0:0] cby_1__1__49_left_grid_pin_16_ ; +wire [0:0] cby_1__1__49_left_grid_pin_17_ ; +wire [0:0] cby_1__1__49_left_grid_pin_18_ ; +wire [0:0] cby_1__1__49_left_grid_pin_19_ ; +wire [0:0] cby_1__1__49_left_grid_pin_20_ ; +wire [0:0] cby_1__1__49_left_grid_pin_21_ ; +wire [0:0] cby_1__1__49_left_grid_pin_22_ ; +wire [0:0] cby_1__1__49_left_grid_pin_23_ ; +wire [0:0] cby_1__1__49_left_grid_pin_24_ ; +wire [0:0] cby_1__1__49_left_grid_pin_25_ ; +wire [0:0] cby_1__1__49_left_grid_pin_26_ ; +wire [0:0] cby_1__1__49_left_grid_pin_27_ ; +wire [0:0] cby_1__1__49_left_grid_pin_28_ ; +wire [0:0] cby_1__1__49_left_grid_pin_29_ ; +wire [0:0] cby_1__1__49_left_grid_pin_30_ ; +wire [0:0] cby_1__1__49_left_grid_pin_31_ ; +wire [0:0] cby_1__1__4_ccff_tail ; +wire [0:29] cby_1__1__4_chany_bottom_out ; +wire [0:29] cby_1__1__4_chany_top_out ; +wire [0:0] cby_1__1__4_left_grid_pin_16_ ; +wire [0:0] cby_1__1__4_left_grid_pin_17_ ; +wire [0:0] cby_1__1__4_left_grid_pin_18_ ; +wire [0:0] cby_1__1__4_left_grid_pin_19_ ; +wire [0:0] cby_1__1__4_left_grid_pin_20_ ; +wire [0:0] cby_1__1__4_left_grid_pin_21_ ; +wire [0:0] cby_1__1__4_left_grid_pin_22_ ; +wire [0:0] cby_1__1__4_left_grid_pin_23_ ; +wire [0:0] cby_1__1__4_left_grid_pin_24_ ; +wire [0:0] cby_1__1__4_left_grid_pin_25_ ; +wire [0:0] cby_1__1__4_left_grid_pin_26_ ; +wire [0:0] cby_1__1__4_left_grid_pin_27_ ; +wire [0:0] cby_1__1__4_left_grid_pin_28_ ; +wire [0:0] cby_1__1__4_left_grid_pin_29_ ; +wire [0:0] cby_1__1__4_left_grid_pin_30_ ; +wire [0:0] cby_1__1__4_left_grid_pin_31_ ; +wire [0:0] cby_1__1__50_ccff_tail ; +wire [0:29] cby_1__1__50_chany_bottom_out ; +wire [0:29] cby_1__1__50_chany_top_out ; +wire [0:0] cby_1__1__50_left_grid_pin_16_ ; +wire [0:0] cby_1__1__50_left_grid_pin_17_ ; +wire [0:0] cby_1__1__50_left_grid_pin_18_ ; +wire [0:0] cby_1__1__50_left_grid_pin_19_ ; +wire [0:0] cby_1__1__50_left_grid_pin_20_ ; +wire [0:0] cby_1__1__50_left_grid_pin_21_ ; +wire [0:0] cby_1__1__50_left_grid_pin_22_ ; +wire [0:0] cby_1__1__50_left_grid_pin_23_ ; +wire [0:0] cby_1__1__50_left_grid_pin_24_ ; +wire [0:0] cby_1__1__50_left_grid_pin_25_ ; +wire [0:0] cby_1__1__50_left_grid_pin_26_ ; +wire [0:0] cby_1__1__50_left_grid_pin_27_ ; +wire [0:0] cby_1__1__50_left_grid_pin_28_ ; +wire [0:0] cby_1__1__50_left_grid_pin_29_ ; +wire [0:0] cby_1__1__50_left_grid_pin_30_ ; +wire [0:0] cby_1__1__50_left_grid_pin_31_ ; +wire [0:0] cby_1__1__51_ccff_tail ; +wire [0:29] cby_1__1__51_chany_bottom_out ; +wire [0:29] cby_1__1__51_chany_top_out ; +wire [0:0] cby_1__1__51_left_grid_pin_16_ ; +wire [0:0] cby_1__1__51_left_grid_pin_17_ ; +wire [0:0] cby_1__1__51_left_grid_pin_18_ ; +wire [0:0] cby_1__1__51_left_grid_pin_19_ ; +wire [0:0] cby_1__1__51_left_grid_pin_20_ ; +wire [0:0] cby_1__1__51_left_grid_pin_21_ ; +wire [0:0] cby_1__1__51_left_grid_pin_22_ ; +wire [0:0] cby_1__1__51_left_grid_pin_23_ ; +wire [0:0] cby_1__1__51_left_grid_pin_24_ ; +wire [0:0] cby_1__1__51_left_grid_pin_25_ ; +wire [0:0] cby_1__1__51_left_grid_pin_26_ ; +wire [0:0] cby_1__1__51_left_grid_pin_27_ ; +wire [0:0] cby_1__1__51_left_grid_pin_28_ ; +wire [0:0] cby_1__1__51_left_grid_pin_29_ ; +wire [0:0] cby_1__1__51_left_grid_pin_30_ ; +wire [0:0] cby_1__1__51_left_grid_pin_31_ ; +wire [0:0] cby_1__1__52_ccff_tail ; +wire [0:29] cby_1__1__52_chany_bottom_out ; +wire [0:29] cby_1__1__52_chany_top_out ; +wire [0:0] cby_1__1__52_left_grid_pin_16_ ; +wire [0:0] cby_1__1__52_left_grid_pin_17_ ; +wire [0:0] cby_1__1__52_left_grid_pin_18_ ; +wire [0:0] cby_1__1__52_left_grid_pin_19_ ; +wire [0:0] cby_1__1__52_left_grid_pin_20_ ; +wire [0:0] cby_1__1__52_left_grid_pin_21_ ; +wire [0:0] cby_1__1__52_left_grid_pin_22_ ; +wire [0:0] cby_1__1__52_left_grid_pin_23_ ; +wire [0:0] cby_1__1__52_left_grid_pin_24_ ; +wire [0:0] cby_1__1__52_left_grid_pin_25_ ; +wire [0:0] cby_1__1__52_left_grid_pin_26_ ; +wire [0:0] cby_1__1__52_left_grid_pin_27_ ; +wire [0:0] cby_1__1__52_left_grid_pin_28_ ; +wire [0:0] cby_1__1__52_left_grid_pin_29_ ; +wire [0:0] cby_1__1__52_left_grid_pin_30_ ; +wire [0:0] cby_1__1__52_left_grid_pin_31_ ; +wire [0:0] cby_1__1__53_ccff_tail ; +wire [0:29] cby_1__1__53_chany_bottom_out ; +wire [0:29] cby_1__1__53_chany_top_out ; +wire [0:0] cby_1__1__53_left_grid_pin_16_ ; +wire [0:0] cby_1__1__53_left_grid_pin_17_ ; +wire [0:0] cby_1__1__53_left_grid_pin_18_ ; +wire [0:0] cby_1__1__53_left_grid_pin_19_ ; +wire [0:0] cby_1__1__53_left_grid_pin_20_ ; +wire [0:0] cby_1__1__53_left_grid_pin_21_ ; +wire [0:0] cby_1__1__53_left_grid_pin_22_ ; +wire [0:0] cby_1__1__53_left_grid_pin_23_ ; +wire [0:0] cby_1__1__53_left_grid_pin_24_ ; +wire [0:0] cby_1__1__53_left_grid_pin_25_ ; +wire [0:0] cby_1__1__53_left_grid_pin_26_ ; +wire [0:0] cby_1__1__53_left_grid_pin_27_ ; +wire [0:0] cby_1__1__53_left_grid_pin_28_ ; +wire [0:0] cby_1__1__53_left_grid_pin_29_ ; +wire [0:0] cby_1__1__53_left_grid_pin_30_ ; +wire [0:0] cby_1__1__53_left_grid_pin_31_ ; +wire [0:0] cby_1__1__54_ccff_tail ; +wire [0:29] cby_1__1__54_chany_bottom_out ; +wire [0:29] cby_1__1__54_chany_top_out ; +wire [0:0] cby_1__1__54_left_grid_pin_16_ ; +wire [0:0] cby_1__1__54_left_grid_pin_17_ ; +wire [0:0] cby_1__1__54_left_grid_pin_18_ ; +wire [0:0] cby_1__1__54_left_grid_pin_19_ ; +wire [0:0] cby_1__1__54_left_grid_pin_20_ ; +wire [0:0] cby_1__1__54_left_grid_pin_21_ ; +wire [0:0] cby_1__1__54_left_grid_pin_22_ ; +wire [0:0] cby_1__1__54_left_grid_pin_23_ ; +wire [0:0] cby_1__1__54_left_grid_pin_24_ ; +wire [0:0] cby_1__1__54_left_grid_pin_25_ ; +wire [0:0] cby_1__1__54_left_grid_pin_26_ ; +wire [0:0] cby_1__1__54_left_grid_pin_27_ ; +wire [0:0] cby_1__1__54_left_grid_pin_28_ ; +wire [0:0] cby_1__1__54_left_grid_pin_29_ ; +wire [0:0] cby_1__1__54_left_grid_pin_30_ ; +wire [0:0] cby_1__1__54_left_grid_pin_31_ ; +wire [0:0] cby_1__1__55_ccff_tail ; +wire [0:29] cby_1__1__55_chany_bottom_out ; +wire [0:29] cby_1__1__55_chany_top_out ; +wire [0:0] cby_1__1__55_left_grid_pin_16_ ; +wire [0:0] cby_1__1__55_left_grid_pin_17_ ; +wire [0:0] cby_1__1__55_left_grid_pin_18_ ; +wire [0:0] cby_1__1__55_left_grid_pin_19_ ; +wire [0:0] cby_1__1__55_left_grid_pin_20_ ; +wire [0:0] cby_1__1__55_left_grid_pin_21_ ; +wire [0:0] cby_1__1__55_left_grid_pin_22_ ; +wire [0:0] cby_1__1__55_left_grid_pin_23_ ; +wire [0:0] cby_1__1__55_left_grid_pin_24_ ; +wire [0:0] cby_1__1__55_left_grid_pin_25_ ; +wire [0:0] cby_1__1__55_left_grid_pin_26_ ; +wire [0:0] cby_1__1__55_left_grid_pin_27_ ; +wire [0:0] cby_1__1__55_left_grid_pin_28_ ; +wire [0:0] cby_1__1__55_left_grid_pin_29_ ; +wire [0:0] cby_1__1__55_left_grid_pin_30_ ; +wire [0:0] cby_1__1__55_left_grid_pin_31_ ; +wire [0:0] cby_1__1__56_ccff_tail ; +wire [0:29] cby_1__1__56_chany_bottom_out ; +wire [0:29] cby_1__1__56_chany_top_out ; +wire [0:0] cby_1__1__56_left_grid_pin_16_ ; +wire [0:0] cby_1__1__56_left_grid_pin_17_ ; +wire [0:0] cby_1__1__56_left_grid_pin_18_ ; +wire [0:0] cby_1__1__56_left_grid_pin_19_ ; +wire [0:0] cby_1__1__56_left_grid_pin_20_ ; +wire [0:0] cby_1__1__56_left_grid_pin_21_ ; +wire [0:0] cby_1__1__56_left_grid_pin_22_ ; +wire [0:0] cby_1__1__56_left_grid_pin_23_ ; +wire [0:0] cby_1__1__56_left_grid_pin_24_ ; +wire [0:0] cby_1__1__56_left_grid_pin_25_ ; +wire [0:0] cby_1__1__56_left_grid_pin_26_ ; +wire [0:0] cby_1__1__56_left_grid_pin_27_ ; +wire [0:0] cby_1__1__56_left_grid_pin_28_ ; +wire [0:0] cby_1__1__56_left_grid_pin_29_ ; +wire [0:0] cby_1__1__56_left_grid_pin_30_ ; +wire [0:0] cby_1__1__56_left_grid_pin_31_ ; +wire [0:0] cby_1__1__57_ccff_tail ; +wire [0:29] cby_1__1__57_chany_bottom_out ; +wire [0:29] cby_1__1__57_chany_top_out ; +wire [0:0] cby_1__1__57_left_grid_pin_16_ ; +wire [0:0] cby_1__1__57_left_grid_pin_17_ ; +wire [0:0] cby_1__1__57_left_grid_pin_18_ ; +wire [0:0] cby_1__1__57_left_grid_pin_19_ ; +wire [0:0] cby_1__1__57_left_grid_pin_20_ ; +wire [0:0] cby_1__1__57_left_grid_pin_21_ ; +wire [0:0] cby_1__1__57_left_grid_pin_22_ ; +wire [0:0] cby_1__1__57_left_grid_pin_23_ ; +wire [0:0] cby_1__1__57_left_grid_pin_24_ ; +wire [0:0] cby_1__1__57_left_grid_pin_25_ ; +wire [0:0] cby_1__1__57_left_grid_pin_26_ ; +wire [0:0] cby_1__1__57_left_grid_pin_27_ ; +wire [0:0] cby_1__1__57_left_grid_pin_28_ ; +wire [0:0] cby_1__1__57_left_grid_pin_29_ ; +wire [0:0] cby_1__1__57_left_grid_pin_30_ ; +wire [0:0] cby_1__1__57_left_grid_pin_31_ ; +wire [0:0] cby_1__1__58_ccff_tail ; +wire [0:29] cby_1__1__58_chany_bottom_out ; +wire [0:29] cby_1__1__58_chany_top_out ; +wire [0:0] cby_1__1__58_left_grid_pin_16_ ; +wire [0:0] cby_1__1__58_left_grid_pin_17_ ; +wire [0:0] cby_1__1__58_left_grid_pin_18_ ; +wire [0:0] cby_1__1__58_left_grid_pin_19_ ; +wire [0:0] cby_1__1__58_left_grid_pin_20_ ; +wire [0:0] cby_1__1__58_left_grid_pin_21_ ; +wire [0:0] cby_1__1__58_left_grid_pin_22_ ; +wire [0:0] cby_1__1__58_left_grid_pin_23_ ; +wire [0:0] cby_1__1__58_left_grid_pin_24_ ; +wire [0:0] cby_1__1__58_left_grid_pin_25_ ; +wire [0:0] cby_1__1__58_left_grid_pin_26_ ; +wire [0:0] cby_1__1__58_left_grid_pin_27_ ; +wire [0:0] cby_1__1__58_left_grid_pin_28_ ; +wire [0:0] cby_1__1__58_left_grid_pin_29_ ; +wire [0:0] cby_1__1__58_left_grid_pin_30_ ; +wire [0:0] cby_1__1__58_left_grid_pin_31_ ; +wire [0:0] cby_1__1__59_ccff_tail ; +wire [0:29] cby_1__1__59_chany_bottom_out ; +wire [0:29] cby_1__1__59_chany_top_out ; +wire [0:0] cby_1__1__59_left_grid_pin_16_ ; +wire [0:0] cby_1__1__59_left_grid_pin_17_ ; +wire [0:0] cby_1__1__59_left_grid_pin_18_ ; +wire [0:0] cby_1__1__59_left_grid_pin_19_ ; +wire [0:0] cby_1__1__59_left_grid_pin_20_ ; +wire [0:0] cby_1__1__59_left_grid_pin_21_ ; +wire [0:0] cby_1__1__59_left_grid_pin_22_ ; +wire [0:0] cby_1__1__59_left_grid_pin_23_ ; +wire [0:0] cby_1__1__59_left_grid_pin_24_ ; +wire [0:0] cby_1__1__59_left_grid_pin_25_ ; +wire [0:0] cby_1__1__59_left_grid_pin_26_ ; +wire [0:0] cby_1__1__59_left_grid_pin_27_ ; +wire [0:0] cby_1__1__59_left_grid_pin_28_ ; +wire [0:0] cby_1__1__59_left_grid_pin_29_ ; +wire [0:0] cby_1__1__59_left_grid_pin_30_ ; +wire [0:0] cby_1__1__59_left_grid_pin_31_ ; +wire [0:0] cby_1__1__5_ccff_tail ; +wire [0:29] cby_1__1__5_chany_bottom_out ; +wire [0:29] cby_1__1__5_chany_top_out ; +wire [0:0] cby_1__1__5_left_grid_pin_16_ ; +wire [0:0] cby_1__1__5_left_grid_pin_17_ ; +wire [0:0] cby_1__1__5_left_grid_pin_18_ ; +wire [0:0] cby_1__1__5_left_grid_pin_19_ ; +wire [0:0] cby_1__1__5_left_grid_pin_20_ ; +wire [0:0] cby_1__1__5_left_grid_pin_21_ ; +wire [0:0] cby_1__1__5_left_grid_pin_22_ ; +wire [0:0] cby_1__1__5_left_grid_pin_23_ ; +wire [0:0] cby_1__1__5_left_grid_pin_24_ ; +wire [0:0] cby_1__1__5_left_grid_pin_25_ ; +wire [0:0] cby_1__1__5_left_grid_pin_26_ ; +wire [0:0] cby_1__1__5_left_grid_pin_27_ ; +wire [0:0] cby_1__1__5_left_grid_pin_28_ ; +wire [0:0] cby_1__1__5_left_grid_pin_29_ ; +wire [0:0] cby_1__1__5_left_grid_pin_30_ ; +wire [0:0] cby_1__1__5_left_grid_pin_31_ ; +wire [0:0] cby_1__1__60_ccff_tail ; +wire [0:29] cby_1__1__60_chany_bottom_out ; +wire [0:29] cby_1__1__60_chany_top_out ; +wire [0:0] cby_1__1__60_left_grid_pin_16_ ; +wire [0:0] cby_1__1__60_left_grid_pin_17_ ; +wire [0:0] cby_1__1__60_left_grid_pin_18_ ; +wire [0:0] cby_1__1__60_left_grid_pin_19_ ; +wire [0:0] cby_1__1__60_left_grid_pin_20_ ; +wire [0:0] cby_1__1__60_left_grid_pin_21_ ; +wire [0:0] cby_1__1__60_left_grid_pin_22_ ; +wire [0:0] cby_1__1__60_left_grid_pin_23_ ; +wire [0:0] cby_1__1__60_left_grid_pin_24_ ; +wire [0:0] cby_1__1__60_left_grid_pin_25_ ; +wire [0:0] cby_1__1__60_left_grid_pin_26_ ; +wire [0:0] cby_1__1__60_left_grid_pin_27_ ; +wire [0:0] cby_1__1__60_left_grid_pin_28_ ; +wire [0:0] cby_1__1__60_left_grid_pin_29_ ; +wire [0:0] cby_1__1__60_left_grid_pin_30_ ; +wire [0:0] cby_1__1__60_left_grid_pin_31_ ; +wire [0:0] cby_1__1__61_ccff_tail ; +wire [0:29] cby_1__1__61_chany_bottom_out ; +wire [0:29] cby_1__1__61_chany_top_out ; +wire [0:0] cby_1__1__61_left_grid_pin_16_ ; +wire [0:0] cby_1__1__61_left_grid_pin_17_ ; +wire [0:0] cby_1__1__61_left_grid_pin_18_ ; +wire [0:0] cby_1__1__61_left_grid_pin_19_ ; +wire [0:0] cby_1__1__61_left_grid_pin_20_ ; +wire [0:0] cby_1__1__61_left_grid_pin_21_ ; +wire [0:0] cby_1__1__61_left_grid_pin_22_ ; +wire [0:0] cby_1__1__61_left_grid_pin_23_ ; +wire [0:0] cby_1__1__61_left_grid_pin_24_ ; +wire [0:0] cby_1__1__61_left_grid_pin_25_ ; +wire [0:0] cby_1__1__61_left_grid_pin_26_ ; +wire [0:0] cby_1__1__61_left_grid_pin_27_ ; +wire [0:0] cby_1__1__61_left_grid_pin_28_ ; +wire [0:0] cby_1__1__61_left_grid_pin_29_ ; +wire [0:0] cby_1__1__61_left_grid_pin_30_ ; +wire [0:0] cby_1__1__61_left_grid_pin_31_ ; +wire [0:0] cby_1__1__62_ccff_tail ; +wire [0:29] cby_1__1__62_chany_bottom_out ; +wire [0:29] cby_1__1__62_chany_top_out ; +wire [0:0] cby_1__1__62_left_grid_pin_16_ ; +wire [0:0] cby_1__1__62_left_grid_pin_17_ ; +wire [0:0] cby_1__1__62_left_grid_pin_18_ ; +wire [0:0] cby_1__1__62_left_grid_pin_19_ ; +wire [0:0] cby_1__1__62_left_grid_pin_20_ ; +wire [0:0] cby_1__1__62_left_grid_pin_21_ ; +wire [0:0] cby_1__1__62_left_grid_pin_22_ ; +wire [0:0] cby_1__1__62_left_grid_pin_23_ ; +wire [0:0] cby_1__1__62_left_grid_pin_24_ ; +wire [0:0] cby_1__1__62_left_grid_pin_25_ ; +wire [0:0] cby_1__1__62_left_grid_pin_26_ ; +wire [0:0] cby_1__1__62_left_grid_pin_27_ ; +wire [0:0] cby_1__1__62_left_grid_pin_28_ ; +wire [0:0] cby_1__1__62_left_grid_pin_29_ ; +wire [0:0] cby_1__1__62_left_grid_pin_30_ ; +wire [0:0] cby_1__1__62_left_grid_pin_31_ ; +wire [0:0] cby_1__1__63_ccff_tail ; +wire [0:29] cby_1__1__63_chany_bottom_out ; +wire [0:29] cby_1__1__63_chany_top_out ; +wire [0:0] cby_1__1__63_left_grid_pin_16_ ; +wire [0:0] cby_1__1__63_left_grid_pin_17_ ; +wire [0:0] cby_1__1__63_left_grid_pin_18_ ; +wire [0:0] cby_1__1__63_left_grid_pin_19_ ; +wire [0:0] cby_1__1__63_left_grid_pin_20_ ; +wire [0:0] cby_1__1__63_left_grid_pin_21_ ; +wire [0:0] cby_1__1__63_left_grid_pin_22_ ; +wire [0:0] cby_1__1__63_left_grid_pin_23_ ; +wire [0:0] cby_1__1__63_left_grid_pin_24_ ; +wire [0:0] cby_1__1__63_left_grid_pin_25_ ; +wire [0:0] cby_1__1__63_left_grid_pin_26_ ; +wire [0:0] cby_1__1__63_left_grid_pin_27_ ; +wire [0:0] cby_1__1__63_left_grid_pin_28_ ; +wire [0:0] cby_1__1__63_left_grid_pin_29_ ; +wire [0:0] cby_1__1__63_left_grid_pin_30_ ; +wire [0:0] cby_1__1__63_left_grid_pin_31_ ; +wire [0:0] cby_1__1__64_ccff_tail ; +wire [0:29] cby_1__1__64_chany_bottom_out ; +wire [0:29] cby_1__1__64_chany_top_out ; +wire [0:0] cby_1__1__64_left_grid_pin_16_ ; +wire [0:0] cby_1__1__64_left_grid_pin_17_ ; +wire [0:0] cby_1__1__64_left_grid_pin_18_ ; +wire [0:0] cby_1__1__64_left_grid_pin_19_ ; +wire [0:0] cby_1__1__64_left_grid_pin_20_ ; +wire [0:0] cby_1__1__64_left_grid_pin_21_ ; +wire [0:0] cby_1__1__64_left_grid_pin_22_ ; +wire [0:0] cby_1__1__64_left_grid_pin_23_ ; +wire [0:0] cby_1__1__64_left_grid_pin_24_ ; +wire [0:0] cby_1__1__64_left_grid_pin_25_ ; +wire [0:0] cby_1__1__64_left_grid_pin_26_ ; +wire [0:0] cby_1__1__64_left_grid_pin_27_ ; +wire [0:0] cby_1__1__64_left_grid_pin_28_ ; +wire [0:0] cby_1__1__64_left_grid_pin_29_ ; +wire [0:0] cby_1__1__64_left_grid_pin_30_ ; +wire [0:0] cby_1__1__64_left_grid_pin_31_ ; +wire [0:0] cby_1__1__65_ccff_tail ; +wire [0:29] cby_1__1__65_chany_bottom_out ; +wire [0:29] cby_1__1__65_chany_top_out ; +wire [0:0] cby_1__1__65_left_grid_pin_16_ ; +wire [0:0] cby_1__1__65_left_grid_pin_17_ ; +wire [0:0] cby_1__1__65_left_grid_pin_18_ ; +wire [0:0] cby_1__1__65_left_grid_pin_19_ ; +wire [0:0] cby_1__1__65_left_grid_pin_20_ ; +wire [0:0] cby_1__1__65_left_grid_pin_21_ ; +wire [0:0] cby_1__1__65_left_grid_pin_22_ ; +wire [0:0] cby_1__1__65_left_grid_pin_23_ ; +wire [0:0] cby_1__1__65_left_grid_pin_24_ ; +wire [0:0] cby_1__1__65_left_grid_pin_25_ ; +wire [0:0] cby_1__1__65_left_grid_pin_26_ ; +wire [0:0] cby_1__1__65_left_grid_pin_27_ ; +wire [0:0] cby_1__1__65_left_grid_pin_28_ ; +wire [0:0] cby_1__1__65_left_grid_pin_29_ ; +wire [0:0] cby_1__1__65_left_grid_pin_30_ ; +wire [0:0] cby_1__1__65_left_grid_pin_31_ ; +wire [0:0] cby_1__1__66_ccff_tail ; +wire [0:29] cby_1__1__66_chany_bottom_out ; +wire [0:29] cby_1__1__66_chany_top_out ; +wire [0:0] cby_1__1__66_left_grid_pin_16_ ; +wire [0:0] cby_1__1__66_left_grid_pin_17_ ; +wire [0:0] cby_1__1__66_left_grid_pin_18_ ; +wire [0:0] cby_1__1__66_left_grid_pin_19_ ; +wire [0:0] cby_1__1__66_left_grid_pin_20_ ; +wire [0:0] cby_1__1__66_left_grid_pin_21_ ; +wire [0:0] cby_1__1__66_left_grid_pin_22_ ; +wire [0:0] cby_1__1__66_left_grid_pin_23_ ; +wire [0:0] cby_1__1__66_left_grid_pin_24_ ; +wire [0:0] cby_1__1__66_left_grid_pin_25_ ; +wire [0:0] cby_1__1__66_left_grid_pin_26_ ; +wire [0:0] cby_1__1__66_left_grid_pin_27_ ; +wire [0:0] cby_1__1__66_left_grid_pin_28_ ; +wire [0:0] cby_1__1__66_left_grid_pin_29_ ; +wire [0:0] cby_1__1__66_left_grid_pin_30_ ; +wire [0:0] cby_1__1__66_left_grid_pin_31_ ; +wire [0:0] cby_1__1__67_ccff_tail ; +wire [0:29] cby_1__1__67_chany_bottom_out ; +wire [0:29] cby_1__1__67_chany_top_out ; +wire [0:0] cby_1__1__67_left_grid_pin_16_ ; +wire [0:0] cby_1__1__67_left_grid_pin_17_ ; +wire [0:0] cby_1__1__67_left_grid_pin_18_ ; +wire [0:0] cby_1__1__67_left_grid_pin_19_ ; +wire [0:0] cby_1__1__67_left_grid_pin_20_ ; +wire [0:0] cby_1__1__67_left_grid_pin_21_ ; +wire [0:0] cby_1__1__67_left_grid_pin_22_ ; +wire [0:0] cby_1__1__67_left_grid_pin_23_ ; +wire [0:0] cby_1__1__67_left_grid_pin_24_ ; +wire [0:0] cby_1__1__67_left_grid_pin_25_ ; +wire [0:0] cby_1__1__67_left_grid_pin_26_ ; +wire [0:0] cby_1__1__67_left_grid_pin_27_ ; +wire [0:0] cby_1__1__67_left_grid_pin_28_ ; +wire [0:0] cby_1__1__67_left_grid_pin_29_ ; +wire [0:0] cby_1__1__67_left_grid_pin_30_ ; +wire [0:0] cby_1__1__67_left_grid_pin_31_ ; +wire [0:0] cby_1__1__68_ccff_tail ; +wire [0:29] cby_1__1__68_chany_bottom_out ; +wire [0:29] cby_1__1__68_chany_top_out ; +wire [0:0] cby_1__1__68_left_grid_pin_16_ ; +wire [0:0] cby_1__1__68_left_grid_pin_17_ ; +wire [0:0] cby_1__1__68_left_grid_pin_18_ ; +wire [0:0] cby_1__1__68_left_grid_pin_19_ ; +wire [0:0] cby_1__1__68_left_grid_pin_20_ ; +wire [0:0] cby_1__1__68_left_grid_pin_21_ ; +wire [0:0] cby_1__1__68_left_grid_pin_22_ ; +wire [0:0] cby_1__1__68_left_grid_pin_23_ ; +wire [0:0] cby_1__1__68_left_grid_pin_24_ ; +wire [0:0] cby_1__1__68_left_grid_pin_25_ ; +wire [0:0] cby_1__1__68_left_grid_pin_26_ ; +wire [0:0] cby_1__1__68_left_grid_pin_27_ ; +wire [0:0] cby_1__1__68_left_grid_pin_28_ ; +wire [0:0] cby_1__1__68_left_grid_pin_29_ ; +wire [0:0] cby_1__1__68_left_grid_pin_30_ ; +wire [0:0] cby_1__1__68_left_grid_pin_31_ ; +wire [0:0] cby_1__1__69_ccff_tail ; +wire [0:29] cby_1__1__69_chany_bottom_out ; +wire [0:29] cby_1__1__69_chany_top_out ; +wire [0:0] cby_1__1__69_left_grid_pin_16_ ; +wire [0:0] cby_1__1__69_left_grid_pin_17_ ; +wire [0:0] cby_1__1__69_left_grid_pin_18_ ; +wire [0:0] cby_1__1__69_left_grid_pin_19_ ; +wire [0:0] cby_1__1__69_left_grid_pin_20_ ; +wire [0:0] cby_1__1__69_left_grid_pin_21_ ; +wire [0:0] cby_1__1__69_left_grid_pin_22_ ; +wire [0:0] cby_1__1__69_left_grid_pin_23_ ; +wire [0:0] cby_1__1__69_left_grid_pin_24_ ; +wire [0:0] cby_1__1__69_left_grid_pin_25_ ; +wire [0:0] cby_1__1__69_left_grid_pin_26_ ; +wire [0:0] cby_1__1__69_left_grid_pin_27_ ; +wire [0:0] cby_1__1__69_left_grid_pin_28_ ; +wire [0:0] cby_1__1__69_left_grid_pin_29_ ; +wire [0:0] cby_1__1__69_left_grid_pin_30_ ; +wire [0:0] cby_1__1__69_left_grid_pin_31_ ; +wire [0:0] cby_1__1__6_ccff_tail ; +wire [0:29] cby_1__1__6_chany_bottom_out ; +wire [0:29] cby_1__1__6_chany_top_out ; +wire [0:0] cby_1__1__6_left_grid_pin_16_ ; +wire [0:0] cby_1__1__6_left_grid_pin_17_ ; +wire [0:0] cby_1__1__6_left_grid_pin_18_ ; +wire [0:0] cby_1__1__6_left_grid_pin_19_ ; +wire [0:0] cby_1__1__6_left_grid_pin_20_ ; +wire [0:0] cby_1__1__6_left_grid_pin_21_ ; +wire [0:0] cby_1__1__6_left_grid_pin_22_ ; +wire [0:0] cby_1__1__6_left_grid_pin_23_ ; +wire [0:0] cby_1__1__6_left_grid_pin_24_ ; +wire [0:0] cby_1__1__6_left_grid_pin_25_ ; +wire [0:0] cby_1__1__6_left_grid_pin_26_ ; +wire [0:0] cby_1__1__6_left_grid_pin_27_ ; +wire [0:0] cby_1__1__6_left_grid_pin_28_ ; +wire [0:0] cby_1__1__6_left_grid_pin_29_ ; +wire [0:0] cby_1__1__6_left_grid_pin_30_ ; +wire [0:0] cby_1__1__6_left_grid_pin_31_ ; +wire [0:0] cby_1__1__70_ccff_tail ; +wire [0:29] cby_1__1__70_chany_bottom_out ; +wire [0:29] cby_1__1__70_chany_top_out ; +wire [0:0] cby_1__1__70_left_grid_pin_16_ ; +wire [0:0] cby_1__1__70_left_grid_pin_17_ ; +wire [0:0] cby_1__1__70_left_grid_pin_18_ ; +wire [0:0] cby_1__1__70_left_grid_pin_19_ ; +wire [0:0] cby_1__1__70_left_grid_pin_20_ ; +wire [0:0] cby_1__1__70_left_grid_pin_21_ ; +wire [0:0] cby_1__1__70_left_grid_pin_22_ ; +wire [0:0] cby_1__1__70_left_grid_pin_23_ ; +wire [0:0] cby_1__1__70_left_grid_pin_24_ ; +wire [0:0] cby_1__1__70_left_grid_pin_25_ ; +wire [0:0] cby_1__1__70_left_grid_pin_26_ ; +wire [0:0] cby_1__1__70_left_grid_pin_27_ ; +wire [0:0] cby_1__1__70_left_grid_pin_28_ ; +wire [0:0] cby_1__1__70_left_grid_pin_29_ ; +wire [0:0] cby_1__1__70_left_grid_pin_30_ ; +wire [0:0] cby_1__1__70_left_grid_pin_31_ ; +wire [0:0] cby_1__1__71_ccff_tail ; +wire [0:29] cby_1__1__71_chany_bottom_out ; +wire [0:29] cby_1__1__71_chany_top_out ; +wire [0:0] cby_1__1__71_left_grid_pin_16_ ; +wire [0:0] cby_1__1__71_left_grid_pin_17_ ; +wire [0:0] cby_1__1__71_left_grid_pin_18_ ; +wire [0:0] cby_1__1__71_left_grid_pin_19_ ; +wire [0:0] cby_1__1__71_left_grid_pin_20_ ; +wire [0:0] cby_1__1__71_left_grid_pin_21_ ; +wire [0:0] cby_1__1__71_left_grid_pin_22_ ; +wire [0:0] cby_1__1__71_left_grid_pin_23_ ; +wire [0:0] cby_1__1__71_left_grid_pin_24_ ; +wire [0:0] cby_1__1__71_left_grid_pin_25_ ; +wire [0:0] cby_1__1__71_left_grid_pin_26_ ; +wire [0:0] cby_1__1__71_left_grid_pin_27_ ; +wire [0:0] cby_1__1__71_left_grid_pin_28_ ; +wire [0:0] cby_1__1__71_left_grid_pin_29_ ; +wire [0:0] cby_1__1__71_left_grid_pin_30_ ; +wire [0:0] cby_1__1__71_left_grid_pin_31_ ; +wire [0:0] cby_1__1__72_ccff_tail ; +wire [0:29] cby_1__1__72_chany_bottom_out ; +wire [0:29] cby_1__1__72_chany_top_out ; +wire [0:0] cby_1__1__72_left_grid_pin_16_ ; +wire [0:0] cby_1__1__72_left_grid_pin_17_ ; +wire [0:0] cby_1__1__72_left_grid_pin_18_ ; +wire [0:0] cby_1__1__72_left_grid_pin_19_ ; +wire [0:0] cby_1__1__72_left_grid_pin_20_ ; +wire [0:0] cby_1__1__72_left_grid_pin_21_ ; +wire [0:0] cby_1__1__72_left_grid_pin_22_ ; +wire [0:0] cby_1__1__72_left_grid_pin_23_ ; +wire [0:0] cby_1__1__72_left_grid_pin_24_ ; +wire [0:0] cby_1__1__72_left_grid_pin_25_ ; +wire [0:0] cby_1__1__72_left_grid_pin_26_ ; +wire [0:0] cby_1__1__72_left_grid_pin_27_ ; +wire [0:0] cby_1__1__72_left_grid_pin_28_ ; +wire [0:0] cby_1__1__72_left_grid_pin_29_ ; +wire [0:0] cby_1__1__72_left_grid_pin_30_ ; +wire [0:0] cby_1__1__72_left_grid_pin_31_ ; +wire [0:0] cby_1__1__73_ccff_tail ; +wire [0:29] cby_1__1__73_chany_bottom_out ; +wire [0:29] cby_1__1__73_chany_top_out ; +wire [0:0] cby_1__1__73_left_grid_pin_16_ ; +wire [0:0] cby_1__1__73_left_grid_pin_17_ ; +wire [0:0] cby_1__1__73_left_grid_pin_18_ ; +wire [0:0] cby_1__1__73_left_grid_pin_19_ ; +wire [0:0] cby_1__1__73_left_grid_pin_20_ ; +wire [0:0] cby_1__1__73_left_grid_pin_21_ ; +wire [0:0] cby_1__1__73_left_grid_pin_22_ ; +wire [0:0] cby_1__1__73_left_grid_pin_23_ ; +wire [0:0] cby_1__1__73_left_grid_pin_24_ ; +wire [0:0] cby_1__1__73_left_grid_pin_25_ ; +wire [0:0] cby_1__1__73_left_grid_pin_26_ ; +wire [0:0] cby_1__1__73_left_grid_pin_27_ ; +wire [0:0] cby_1__1__73_left_grid_pin_28_ ; +wire [0:0] cby_1__1__73_left_grid_pin_29_ ; +wire [0:0] cby_1__1__73_left_grid_pin_30_ ; +wire [0:0] cby_1__1__73_left_grid_pin_31_ ; +wire [0:0] cby_1__1__74_ccff_tail ; +wire [0:29] cby_1__1__74_chany_bottom_out ; +wire [0:29] cby_1__1__74_chany_top_out ; +wire [0:0] cby_1__1__74_left_grid_pin_16_ ; +wire [0:0] cby_1__1__74_left_grid_pin_17_ ; +wire [0:0] cby_1__1__74_left_grid_pin_18_ ; +wire [0:0] cby_1__1__74_left_grid_pin_19_ ; +wire [0:0] cby_1__1__74_left_grid_pin_20_ ; +wire [0:0] cby_1__1__74_left_grid_pin_21_ ; +wire [0:0] cby_1__1__74_left_grid_pin_22_ ; +wire [0:0] cby_1__1__74_left_grid_pin_23_ ; +wire [0:0] cby_1__1__74_left_grid_pin_24_ ; +wire [0:0] cby_1__1__74_left_grid_pin_25_ ; +wire [0:0] cby_1__1__74_left_grid_pin_26_ ; +wire [0:0] cby_1__1__74_left_grid_pin_27_ ; +wire [0:0] cby_1__1__74_left_grid_pin_28_ ; +wire [0:0] cby_1__1__74_left_grid_pin_29_ ; +wire [0:0] cby_1__1__74_left_grid_pin_30_ ; +wire [0:0] cby_1__1__74_left_grid_pin_31_ ; +wire [0:0] cby_1__1__75_ccff_tail ; +wire [0:29] cby_1__1__75_chany_bottom_out ; +wire [0:29] cby_1__1__75_chany_top_out ; +wire [0:0] cby_1__1__75_left_grid_pin_16_ ; +wire [0:0] cby_1__1__75_left_grid_pin_17_ ; +wire [0:0] cby_1__1__75_left_grid_pin_18_ ; +wire [0:0] cby_1__1__75_left_grid_pin_19_ ; +wire [0:0] cby_1__1__75_left_grid_pin_20_ ; +wire [0:0] cby_1__1__75_left_grid_pin_21_ ; +wire [0:0] cby_1__1__75_left_grid_pin_22_ ; +wire [0:0] cby_1__1__75_left_grid_pin_23_ ; +wire [0:0] cby_1__1__75_left_grid_pin_24_ ; +wire [0:0] cby_1__1__75_left_grid_pin_25_ ; +wire [0:0] cby_1__1__75_left_grid_pin_26_ ; +wire [0:0] cby_1__1__75_left_grid_pin_27_ ; +wire [0:0] cby_1__1__75_left_grid_pin_28_ ; +wire [0:0] cby_1__1__75_left_grid_pin_29_ ; +wire [0:0] cby_1__1__75_left_grid_pin_30_ ; +wire [0:0] cby_1__1__75_left_grid_pin_31_ ; +wire [0:0] cby_1__1__76_ccff_tail ; +wire [0:29] cby_1__1__76_chany_bottom_out ; +wire [0:29] cby_1__1__76_chany_top_out ; +wire [0:0] cby_1__1__76_left_grid_pin_16_ ; +wire [0:0] cby_1__1__76_left_grid_pin_17_ ; +wire [0:0] cby_1__1__76_left_grid_pin_18_ ; +wire [0:0] cby_1__1__76_left_grid_pin_19_ ; +wire [0:0] cby_1__1__76_left_grid_pin_20_ ; +wire [0:0] cby_1__1__76_left_grid_pin_21_ ; +wire [0:0] cby_1__1__76_left_grid_pin_22_ ; +wire [0:0] cby_1__1__76_left_grid_pin_23_ ; +wire [0:0] cby_1__1__76_left_grid_pin_24_ ; +wire [0:0] cby_1__1__76_left_grid_pin_25_ ; +wire [0:0] cby_1__1__76_left_grid_pin_26_ ; +wire [0:0] cby_1__1__76_left_grid_pin_27_ ; +wire [0:0] cby_1__1__76_left_grid_pin_28_ ; +wire [0:0] cby_1__1__76_left_grid_pin_29_ ; +wire [0:0] cby_1__1__76_left_grid_pin_30_ ; +wire [0:0] cby_1__1__76_left_grid_pin_31_ ; +wire [0:0] cby_1__1__77_ccff_tail ; +wire [0:29] cby_1__1__77_chany_bottom_out ; +wire [0:29] cby_1__1__77_chany_top_out ; +wire [0:0] cby_1__1__77_left_grid_pin_16_ ; +wire [0:0] cby_1__1__77_left_grid_pin_17_ ; +wire [0:0] cby_1__1__77_left_grid_pin_18_ ; +wire [0:0] cby_1__1__77_left_grid_pin_19_ ; +wire [0:0] cby_1__1__77_left_grid_pin_20_ ; +wire [0:0] cby_1__1__77_left_grid_pin_21_ ; +wire [0:0] cby_1__1__77_left_grid_pin_22_ ; +wire [0:0] cby_1__1__77_left_grid_pin_23_ ; +wire [0:0] cby_1__1__77_left_grid_pin_24_ ; +wire [0:0] cby_1__1__77_left_grid_pin_25_ ; +wire [0:0] cby_1__1__77_left_grid_pin_26_ ; +wire [0:0] cby_1__1__77_left_grid_pin_27_ ; +wire [0:0] cby_1__1__77_left_grid_pin_28_ ; +wire [0:0] cby_1__1__77_left_grid_pin_29_ ; +wire [0:0] cby_1__1__77_left_grid_pin_30_ ; +wire [0:0] cby_1__1__77_left_grid_pin_31_ ; +wire [0:0] cby_1__1__78_ccff_tail ; +wire [0:29] cby_1__1__78_chany_bottom_out ; +wire [0:29] cby_1__1__78_chany_top_out ; +wire [0:0] cby_1__1__78_left_grid_pin_16_ ; +wire [0:0] cby_1__1__78_left_grid_pin_17_ ; +wire [0:0] cby_1__1__78_left_grid_pin_18_ ; +wire [0:0] cby_1__1__78_left_grid_pin_19_ ; +wire [0:0] cby_1__1__78_left_grid_pin_20_ ; +wire [0:0] cby_1__1__78_left_grid_pin_21_ ; +wire [0:0] cby_1__1__78_left_grid_pin_22_ ; +wire [0:0] cby_1__1__78_left_grid_pin_23_ ; +wire [0:0] cby_1__1__78_left_grid_pin_24_ ; +wire [0:0] cby_1__1__78_left_grid_pin_25_ ; +wire [0:0] cby_1__1__78_left_grid_pin_26_ ; +wire [0:0] cby_1__1__78_left_grid_pin_27_ ; +wire [0:0] cby_1__1__78_left_grid_pin_28_ ; +wire [0:0] cby_1__1__78_left_grid_pin_29_ ; +wire [0:0] cby_1__1__78_left_grid_pin_30_ ; +wire [0:0] cby_1__1__78_left_grid_pin_31_ ; +wire [0:0] cby_1__1__79_ccff_tail ; +wire [0:29] cby_1__1__79_chany_bottom_out ; +wire [0:29] cby_1__1__79_chany_top_out ; +wire [0:0] cby_1__1__79_left_grid_pin_16_ ; +wire [0:0] cby_1__1__79_left_grid_pin_17_ ; +wire [0:0] cby_1__1__79_left_grid_pin_18_ ; +wire [0:0] cby_1__1__79_left_grid_pin_19_ ; +wire [0:0] cby_1__1__79_left_grid_pin_20_ ; +wire [0:0] cby_1__1__79_left_grid_pin_21_ ; +wire [0:0] cby_1__1__79_left_grid_pin_22_ ; +wire [0:0] cby_1__1__79_left_grid_pin_23_ ; +wire [0:0] cby_1__1__79_left_grid_pin_24_ ; +wire [0:0] cby_1__1__79_left_grid_pin_25_ ; +wire [0:0] cby_1__1__79_left_grid_pin_26_ ; +wire [0:0] cby_1__1__79_left_grid_pin_27_ ; +wire [0:0] cby_1__1__79_left_grid_pin_28_ ; +wire [0:0] cby_1__1__79_left_grid_pin_29_ ; +wire [0:0] cby_1__1__79_left_grid_pin_30_ ; +wire [0:0] cby_1__1__79_left_grid_pin_31_ ; +wire [0:0] cby_1__1__7_ccff_tail ; +wire [0:29] cby_1__1__7_chany_bottom_out ; +wire [0:29] cby_1__1__7_chany_top_out ; +wire [0:0] cby_1__1__7_left_grid_pin_16_ ; +wire [0:0] cby_1__1__7_left_grid_pin_17_ ; +wire [0:0] cby_1__1__7_left_grid_pin_18_ ; +wire [0:0] cby_1__1__7_left_grid_pin_19_ ; +wire [0:0] cby_1__1__7_left_grid_pin_20_ ; +wire [0:0] cby_1__1__7_left_grid_pin_21_ ; +wire [0:0] cby_1__1__7_left_grid_pin_22_ ; +wire [0:0] cby_1__1__7_left_grid_pin_23_ ; +wire [0:0] cby_1__1__7_left_grid_pin_24_ ; +wire [0:0] cby_1__1__7_left_grid_pin_25_ ; +wire [0:0] cby_1__1__7_left_grid_pin_26_ ; +wire [0:0] cby_1__1__7_left_grid_pin_27_ ; +wire [0:0] cby_1__1__7_left_grid_pin_28_ ; +wire [0:0] cby_1__1__7_left_grid_pin_29_ ; +wire [0:0] cby_1__1__7_left_grid_pin_30_ ; +wire [0:0] cby_1__1__7_left_grid_pin_31_ ; +wire [0:0] cby_1__1__80_ccff_tail ; +wire [0:29] cby_1__1__80_chany_bottom_out ; +wire [0:29] cby_1__1__80_chany_top_out ; +wire [0:0] cby_1__1__80_left_grid_pin_16_ ; +wire [0:0] cby_1__1__80_left_grid_pin_17_ ; +wire [0:0] cby_1__1__80_left_grid_pin_18_ ; +wire [0:0] cby_1__1__80_left_grid_pin_19_ ; +wire [0:0] cby_1__1__80_left_grid_pin_20_ ; +wire [0:0] cby_1__1__80_left_grid_pin_21_ ; +wire [0:0] cby_1__1__80_left_grid_pin_22_ ; +wire [0:0] cby_1__1__80_left_grid_pin_23_ ; +wire [0:0] cby_1__1__80_left_grid_pin_24_ ; +wire [0:0] cby_1__1__80_left_grid_pin_25_ ; +wire [0:0] cby_1__1__80_left_grid_pin_26_ ; +wire [0:0] cby_1__1__80_left_grid_pin_27_ ; +wire [0:0] cby_1__1__80_left_grid_pin_28_ ; +wire [0:0] cby_1__1__80_left_grid_pin_29_ ; +wire [0:0] cby_1__1__80_left_grid_pin_30_ ; +wire [0:0] cby_1__1__80_left_grid_pin_31_ ; +wire [0:0] cby_1__1__81_ccff_tail ; +wire [0:29] cby_1__1__81_chany_bottom_out ; +wire [0:29] cby_1__1__81_chany_top_out ; +wire [0:0] cby_1__1__81_left_grid_pin_16_ ; +wire [0:0] cby_1__1__81_left_grid_pin_17_ ; +wire [0:0] cby_1__1__81_left_grid_pin_18_ ; +wire [0:0] cby_1__1__81_left_grid_pin_19_ ; +wire [0:0] cby_1__1__81_left_grid_pin_20_ ; +wire [0:0] cby_1__1__81_left_grid_pin_21_ ; +wire [0:0] cby_1__1__81_left_grid_pin_22_ ; +wire [0:0] cby_1__1__81_left_grid_pin_23_ ; +wire [0:0] cby_1__1__81_left_grid_pin_24_ ; +wire [0:0] cby_1__1__81_left_grid_pin_25_ ; +wire [0:0] cby_1__1__81_left_grid_pin_26_ ; +wire [0:0] cby_1__1__81_left_grid_pin_27_ ; +wire [0:0] cby_1__1__81_left_grid_pin_28_ ; +wire [0:0] cby_1__1__81_left_grid_pin_29_ ; +wire [0:0] cby_1__1__81_left_grid_pin_30_ ; +wire [0:0] cby_1__1__81_left_grid_pin_31_ ; +wire [0:0] cby_1__1__82_ccff_tail ; +wire [0:29] cby_1__1__82_chany_bottom_out ; +wire [0:29] cby_1__1__82_chany_top_out ; +wire [0:0] cby_1__1__82_left_grid_pin_16_ ; +wire [0:0] cby_1__1__82_left_grid_pin_17_ ; +wire [0:0] cby_1__1__82_left_grid_pin_18_ ; +wire [0:0] cby_1__1__82_left_grid_pin_19_ ; +wire [0:0] cby_1__1__82_left_grid_pin_20_ ; +wire [0:0] cby_1__1__82_left_grid_pin_21_ ; +wire [0:0] cby_1__1__82_left_grid_pin_22_ ; +wire [0:0] cby_1__1__82_left_grid_pin_23_ ; +wire [0:0] cby_1__1__82_left_grid_pin_24_ ; +wire [0:0] cby_1__1__82_left_grid_pin_25_ ; +wire [0:0] cby_1__1__82_left_grid_pin_26_ ; +wire [0:0] cby_1__1__82_left_grid_pin_27_ ; +wire [0:0] cby_1__1__82_left_grid_pin_28_ ; +wire [0:0] cby_1__1__82_left_grid_pin_29_ ; +wire [0:0] cby_1__1__82_left_grid_pin_30_ ; +wire [0:0] cby_1__1__82_left_grid_pin_31_ ; +wire [0:0] cby_1__1__83_ccff_tail ; +wire [0:29] cby_1__1__83_chany_bottom_out ; +wire [0:29] cby_1__1__83_chany_top_out ; +wire [0:0] cby_1__1__83_left_grid_pin_16_ ; +wire [0:0] cby_1__1__83_left_grid_pin_17_ ; +wire [0:0] cby_1__1__83_left_grid_pin_18_ ; +wire [0:0] cby_1__1__83_left_grid_pin_19_ ; +wire [0:0] cby_1__1__83_left_grid_pin_20_ ; +wire [0:0] cby_1__1__83_left_grid_pin_21_ ; +wire [0:0] cby_1__1__83_left_grid_pin_22_ ; +wire [0:0] cby_1__1__83_left_grid_pin_23_ ; +wire [0:0] cby_1__1__83_left_grid_pin_24_ ; +wire [0:0] cby_1__1__83_left_grid_pin_25_ ; +wire [0:0] cby_1__1__83_left_grid_pin_26_ ; +wire [0:0] cby_1__1__83_left_grid_pin_27_ ; +wire [0:0] cby_1__1__83_left_grid_pin_28_ ; +wire [0:0] cby_1__1__83_left_grid_pin_29_ ; +wire [0:0] cby_1__1__83_left_grid_pin_30_ ; +wire [0:0] cby_1__1__83_left_grid_pin_31_ ; +wire [0:0] cby_1__1__84_ccff_tail ; +wire [0:29] cby_1__1__84_chany_bottom_out ; +wire [0:29] cby_1__1__84_chany_top_out ; +wire [0:0] cby_1__1__84_left_grid_pin_16_ ; +wire [0:0] cby_1__1__84_left_grid_pin_17_ ; +wire [0:0] cby_1__1__84_left_grid_pin_18_ ; +wire [0:0] cby_1__1__84_left_grid_pin_19_ ; +wire [0:0] cby_1__1__84_left_grid_pin_20_ ; +wire [0:0] cby_1__1__84_left_grid_pin_21_ ; +wire [0:0] cby_1__1__84_left_grid_pin_22_ ; +wire [0:0] cby_1__1__84_left_grid_pin_23_ ; +wire [0:0] cby_1__1__84_left_grid_pin_24_ ; +wire [0:0] cby_1__1__84_left_grid_pin_25_ ; +wire [0:0] cby_1__1__84_left_grid_pin_26_ ; +wire [0:0] cby_1__1__84_left_grid_pin_27_ ; +wire [0:0] cby_1__1__84_left_grid_pin_28_ ; +wire [0:0] cby_1__1__84_left_grid_pin_29_ ; +wire [0:0] cby_1__1__84_left_grid_pin_30_ ; +wire [0:0] cby_1__1__84_left_grid_pin_31_ ; +wire [0:0] cby_1__1__85_ccff_tail ; +wire [0:29] cby_1__1__85_chany_bottom_out ; +wire [0:29] cby_1__1__85_chany_top_out ; +wire [0:0] cby_1__1__85_left_grid_pin_16_ ; +wire [0:0] cby_1__1__85_left_grid_pin_17_ ; +wire [0:0] cby_1__1__85_left_grid_pin_18_ ; +wire [0:0] cby_1__1__85_left_grid_pin_19_ ; +wire [0:0] cby_1__1__85_left_grid_pin_20_ ; +wire [0:0] cby_1__1__85_left_grid_pin_21_ ; +wire [0:0] cby_1__1__85_left_grid_pin_22_ ; +wire [0:0] cby_1__1__85_left_grid_pin_23_ ; +wire [0:0] cby_1__1__85_left_grid_pin_24_ ; +wire [0:0] cby_1__1__85_left_grid_pin_25_ ; +wire [0:0] cby_1__1__85_left_grid_pin_26_ ; +wire [0:0] cby_1__1__85_left_grid_pin_27_ ; +wire [0:0] cby_1__1__85_left_grid_pin_28_ ; +wire [0:0] cby_1__1__85_left_grid_pin_29_ ; +wire [0:0] cby_1__1__85_left_grid_pin_30_ ; +wire [0:0] cby_1__1__85_left_grid_pin_31_ ; +wire [0:0] cby_1__1__86_ccff_tail ; +wire [0:29] cby_1__1__86_chany_bottom_out ; +wire [0:29] cby_1__1__86_chany_top_out ; +wire [0:0] cby_1__1__86_left_grid_pin_16_ ; +wire [0:0] cby_1__1__86_left_grid_pin_17_ ; +wire [0:0] cby_1__1__86_left_grid_pin_18_ ; +wire [0:0] cby_1__1__86_left_grid_pin_19_ ; +wire [0:0] cby_1__1__86_left_grid_pin_20_ ; +wire [0:0] cby_1__1__86_left_grid_pin_21_ ; +wire [0:0] cby_1__1__86_left_grid_pin_22_ ; +wire [0:0] cby_1__1__86_left_grid_pin_23_ ; +wire [0:0] cby_1__1__86_left_grid_pin_24_ ; +wire [0:0] cby_1__1__86_left_grid_pin_25_ ; +wire [0:0] cby_1__1__86_left_grid_pin_26_ ; +wire [0:0] cby_1__1__86_left_grid_pin_27_ ; +wire [0:0] cby_1__1__86_left_grid_pin_28_ ; +wire [0:0] cby_1__1__86_left_grid_pin_29_ ; +wire [0:0] cby_1__1__86_left_grid_pin_30_ ; +wire [0:0] cby_1__1__86_left_grid_pin_31_ ; +wire [0:0] cby_1__1__87_ccff_tail ; +wire [0:29] cby_1__1__87_chany_bottom_out ; +wire [0:29] cby_1__1__87_chany_top_out ; +wire [0:0] cby_1__1__87_left_grid_pin_16_ ; +wire [0:0] cby_1__1__87_left_grid_pin_17_ ; +wire [0:0] cby_1__1__87_left_grid_pin_18_ ; +wire [0:0] cby_1__1__87_left_grid_pin_19_ ; +wire [0:0] cby_1__1__87_left_grid_pin_20_ ; +wire [0:0] cby_1__1__87_left_grid_pin_21_ ; +wire [0:0] cby_1__1__87_left_grid_pin_22_ ; +wire [0:0] cby_1__1__87_left_grid_pin_23_ ; +wire [0:0] cby_1__1__87_left_grid_pin_24_ ; +wire [0:0] cby_1__1__87_left_grid_pin_25_ ; +wire [0:0] cby_1__1__87_left_grid_pin_26_ ; +wire [0:0] cby_1__1__87_left_grid_pin_27_ ; +wire [0:0] cby_1__1__87_left_grid_pin_28_ ; +wire [0:0] cby_1__1__87_left_grid_pin_29_ ; +wire [0:0] cby_1__1__87_left_grid_pin_30_ ; +wire [0:0] cby_1__1__87_left_grid_pin_31_ ; +wire [0:0] cby_1__1__88_ccff_tail ; +wire [0:29] cby_1__1__88_chany_bottom_out ; +wire [0:29] cby_1__1__88_chany_top_out ; +wire [0:0] cby_1__1__88_left_grid_pin_16_ ; +wire [0:0] cby_1__1__88_left_grid_pin_17_ ; +wire [0:0] cby_1__1__88_left_grid_pin_18_ ; +wire [0:0] cby_1__1__88_left_grid_pin_19_ ; +wire [0:0] cby_1__1__88_left_grid_pin_20_ ; +wire [0:0] cby_1__1__88_left_grid_pin_21_ ; +wire [0:0] cby_1__1__88_left_grid_pin_22_ ; +wire [0:0] cby_1__1__88_left_grid_pin_23_ ; +wire [0:0] cby_1__1__88_left_grid_pin_24_ ; +wire [0:0] cby_1__1__88_left_grid_pin_25_ ; +wire [0:0] cby_1__1__88_left_grid_pin_26_ ; +wire [0:0] cby_1__1__88_left_grid_pin_27_ ; +wire [0:0] cby_1__1__88_left_grid_pin_28_ ; +wire [0:0] cby_1__1__88_left_grid_pin_29_ ; +wire [0:0] cby_1__1__88_left_grid_pin_30_ ; +wire [0:0] cby_1__1__88_left_grid_pin_31_ ; +wire [0:0] cby_1__1__89_ccff_tail ; +wire [0:29] cby_1__1__89_chany_bottom_out ; +wire [0:29] cby_1__1__89_chany_top_out ; +wire [0:0] cby_1__1__89_left_grid_pin_16_ ; +wire [0:0] cby_1__1__89_left_grid_pin_17_ ; +wire [0:0] cby_1__1__89_left_grid_pin_18_ ; +wire [0:0] cby_1__1__89_left_grid_pin_19_ ; +wire [0:0] cby_1__1__89_left_grid_pin_20_ ; +wire [0:0] cby_1__1__89_left_grid_pin_21_ ; +wire [0:0] cby_1__1__89_left_grid_pin_22_ ; +wire [0:0] cby_1__1__89_left_grid_pin_23_ ; +wire [0:0] cby_1__1__89_left_grid_pin_24_ ; +wire [0:0] cby_1__1__89_left_grid_pin_25_ ; +wire [0:0] cby_1__1__89_left_grid_pin_26_ ; +wire [0:0] cby_1__1__89_left_grid_pin_27_ ; +wire [0:0] cby_1__1__89_left_grid_pin_28_ ; +wire [0:0] cby_1__1__89_left_grid_pin_29_ ; +wire [0:0] cby_1__1__89_left_grid_pin_30_ ; +wire [0:0] cby_1__1__89_left_grid_pin_31_ ; +wire [0:0] cby_1__1__8_ccff_tail ; +wire [0:29] cby_1__1__8_chany_bottom_out ; +wire [0:29] cby_1__1__8_chany_top_out ; +wire [0:0] cby_1__1__8_left_grid_pin_16_ ; +wire [0:0] cby_1__1__8_left_grid_pin_17_ ; +wire [0:0] cby_1__1__8_left_grid_pin_18_ ; +wire [0:0] cby_1__1__8_left_grid_pin_19_ ; +wire [0:0] cby_1__1__8_left_grid_pin_20_ ; +wire [0:0] cby_1__1__8_left_grid_pin_21_ ; +wire [0:0] cby_1__1__8_left_grid_pin_22_ ; +wire [0:0] cby_1__1__8_left_grid_pin_23_ ; +wire [0:0] cby_1__1__8_left_grid_pin_24_ ; +wire [0:0] cby_1__1__8_left_grid_pin_25_ ; +wire [0:0] cby_1__1__8_left_grid_pin_26_ ; +wire [0:0] cby_1__1__8_left_grid_pin_27_ ; +wire [0:0] cby_1__1__8_left_grid_pin_28_ ; +wire [0:0] cby_1__1__8_left_grid_pin_29_ ; +wire [0:0] cby_1__1__8_left_grid_pin_30_ ; +wire [0:0] cby_1__1__8_left_grid_pin_31_ ; +wire [0:0] cby_1__1__90_ccff_tail ; +wire [0:29] cby_1__1__90_chany_bottom_out ; +wire [0:29] cby_1__1__90_chany_top_out ; +wire [0:0] cby_1__1__90_left_grid_pin_16_ ; +wire [0:0] cby_1__1__90_left_grid_pin_17_ ; +wire [0:0] cby_1__1__90_left_grid_pin_18_ ; +wire [0:0] cby_1__1__90_left_grid_pin_19_ ; +wire [0:0] cby_1__1__90_left_grid_pin_20_ ; +wire [0:0] cby_1__1__90_left_grid_pin_21_ ; +wire [0:0] cby_1__1__90_left_grid_pin_22_ ; +wire [0:0] cby_1__1__90_left_grid_pin_23_ ; +wire [0:0] cby_1__1__90_left_grid_pin_24_ ; +wire [0:0] cby_1__1__90_left_grid_pin_25_ ; +wire [0:0] cby_1__1__90_left_grid_pin_26_ ; +wire [0:0] cby_1__1__90_left_grid_pin_27_ ; +wire [0:0] cby_1__1__90_left_grid_pin_28_ ; +wire [0:0] cby_1__1__90_left_grid_pin_29_ ; +wire [0:0] cby_1__1__90_left_grid_pin_30_ ; +wire [0:0] cby_1__1__90_left_grid_pin_31_ ; +wire [0:0] cby_1__1__91_ccff_tail ; +wire [0:29] cby_1__1__91_chany_bottom_out ; +wire [0:29] cby_1__1__91_chany_top_out ; +wire [0:0] cby_1__1__91_left_grid_pin_16_ ; +wire [0:0] cby_1__1__91_left_grid_pin_17_ ; +wire [0:0] cby_1__1__91_left_grid_pin_18_ ; +wire [0:0] cby_1__1__91_left_grid_pin_19_ ; +wire [0:0] cby_1__1__91_left_grid_pin_20_ ; +wire [0:0] cby_1__1__91_left_grid_pin_21_ ; +wire [0:0] cby_1__1__91_left_grid_pin_22_ ; +wire [0:0] cby_1__1__91_left_grid_pin_23_ ; +wire [0:0] cby_1__1__91_left_grid_pin_24_ ; +wire [0:0] cby_1__1__91_left_grid_pin_25_ ; +wire [0:0] cby_1__1__91_left_grid_pin_26_ ; +wire [0:0] cby_1__1__91_left_grid_pin_27_ ; +wire [0:0] cby_1__1__91_left_grid_pin_28_ ; +wire [0:0] cby_1__1__91_left_grid_pin_29_ ; +wire [0:0] cby_1__1__91_left_grid_pin_30_ ; +wire [0:0] cby_1__1__91_left_grid_pin_31_ ; +wire [0:0] cby_1__1__92_ccff_tail ; +wire [0:29] cby_1__1__92_chany_bottom_out ; +wire [0:29] cby_1__1__92_chany_top_out ; +wire [0:0] cby_1__1__92_left_grid_pin_16_ ; +wire [0:0] cby_1__1__92_left_grid_pin_17_ ; +wire [0:0] cby_1__1__92_left_grid_pin_18_ ; +wire [0:0] cby_1__1__92_left_grid_pin_19_ ; +wire [0:0] cby_1__1__92_left_grid_pin_20_ ; +wire [0:0] cby_1__1__92_left_grid_pin_21_ ; +wire [0:0] cby_1__1__92_left_grid_pin_22_ ; +wire [0:0] cby_1__1__92_left_grid_pin_23_ ; +wire [0:0] cby_1__1__92_left_grid_pin_24_ ; +wire [0:0] cby_1__1__92_left_grid_pin_25_ ; +wire [0:0] cby_1__1__92_left_grid_pin_26_ ; +wire [0:0] cby_1__1__92_left_grid_pin_27_ ; +wire [0:0] cby_1__1__92_left_grid_pin_28_ ; +wire [0:0] cby_1__1__92_left_grid_pin_29_ ; +wire [0:0] cby_1__1__92_left_grid_pin_30_ ; +wire [0:0] cby_1__1__92_left_grid_pin_31_ ; +wire [0:0] cby_1__1__93_ccff_tail ; +wire [0:29] cby_1__1__93_chany_bottom_out ; +wire [0:29] cby_1__1__93_chany_top_out ; +wire [0:0] cby_1__1__93_left_grid_pin_16_ ; +wire [0:0] cby_1__1__93_left_grid_pin_17_ ; +wire [0:0] cby_1__1__93_left_grid_pin_18_ ; +wire [0:0] cby_1__1__93_left_grid_pin_19_ ; +wire [0:0] cby_1__1__93_left_grid_pin_20_ ; +wire [0:0] cby_1__1__93_left_grid_pin_21_ ; +wire [0:0] cby_1__1__93_left_grid_pin_22_ ; +wire [0:0] cby_1__1__93_left_grid_pin_23_ ; +wire [0:0] cby_1__1__93_left_grid_pin_24_ ; +wire [0:0] cby_1__1__93_left_grid_pin_25_ ; +wire [0:0] cby_1__1__93_left_grid_pin_26_ ; +wire [0:0] cby_1__1__93_left_grid_pin_27_ ; +wire [0:0] cby_1__1__93_left_grid_pin_28_ ; +wire [0:0] cby_1__1__93_left_grid_pin_29_ ; +wire [0:0] cby_1__1__93_left_grid_pin_30_ ; +wire [0:0] cby_1__1__93_left_grid_pin_31_ ; +wire [0:0] cby_1__1__94_ccff_tail ; +wire [0:29] cby_1__1__94_chany_bottom_out ; +wire [0:29] cby_1__1__94_chany_top_out ; +wire [0:0] cby_1__1__94_left_grid_pin_16_ ; +wire [0:0] cby_1__1__94_left_grid_pin_17_ ; +wire [0:0] cby_1__1__94_left_grid_pin_18_ ; +wire [0:0] cby_1__1__94_left_grid_pin_19_ ; +wire [0:0] cby_1__1__94_left_grid_pin_20_ ; +wire [0:0] cby_1__1__94_left_grid_pin_21_ ; +wire [0:0] cby_1__1__94_left_grid_pin_22_ ; +wire [0:0] cby_1__1__94_left_grid_pin_23_ ; +wire [0:0] cby_1__1__94_left_grid_pin_24_ ; +wire [0:0] cby_1__1__94_left_grid_pin_25_ ; +wire [0:0] cby_1__1__94_left_grid_pin_26_ ; +wire [0:0] cby_1__1__94_left_grid_pin_27_ ; +wire [0:0] cby_1__1__94_left_grid_pin_28_ ; +wire [0:0] cby_1__1__94_left_grid_pin_29_ ; +wire [0:0] cby_1__1__94_left_grid_pin_30_ ; +wire [0:0] cby_1__1__94_left_grid_pin_31_ ; +wire [0:0] cby_1__1__95_ccff_tail ; +wire [0:29] cby_1__1__95_chany_bottom_out ; +wire [0:29] cby_1__1__95_chany_top_out ; +wire [0:0] cby_1__1__95_left_grid_pin_16_ ; +wire [0:0] cby_1__1__95_left_grid_pin_17_ ; +wire [0:0] cby_1__1__95_left_grid_pin_18_ ; +wire [0:0] cby_1__1__95_left_grid_pin_19_ ; +wire [0:0] cby_1__1__95_left_grid_pin_20_ ; +wire [0:0] cby_1__1__95_left_grid_pin_21_ ; +wire [0:0] cby_1__1__95_left_grid_pin_22_ ; +wire [0:0] cby_1__1__95_left_grid_pin_23_ ; +wire [0:0] cby_1__1__95_left_grid_pin_24_ ; +wire [0:0] cby_1__1__95_left_grid_pin_25_ ; +wire [0:0] cby_1__1__95_left_grid_pin_26_ ; +wire [0:0] cby_1__1__95_left_grid_pin_27_ ; +wire [0:0] cby_1__1__95_left_grid_pin_28_ ; +wire [0:0] cby_1__1__95_left_grid_pin_29_ ; +wire [0:0] cby_1__1__95_left_grid_pin_30_ ; +wire [0:0] cby_1__1__95_left_grid_pin_31_ ; +wire [0:0] cby_1__1__96_ccff_tail ; +wire [0:29] cby_1__1__96_chany_bottom_out ; +wire [0:29] cby_1__1__96_chany_top_out ; +wire [0:0] cby_1__1__96_left_grid_pin_16_ ; +wire [0:0] cby_1__1__96_left_grid_pin_17_ ; +wire [0:0] cby_1__1__96_left_grid_pin_18_ ; +wire [0:0] cby_1__1__96_left_grid_pin_19_ ; +wire [0:0] cby_1__1__96_left_grid_pin_20_ ; +wire [0:0] cby_1__1__96_left_grid_pin_21_ ; +wire [0:0] cby_1__1__96_left_grid_pin_22_ ; +wire [0:0] cby_1__1__96_left_grid_pin_23_ ; +wire [0:0] cby_1__1__96_left_grid_pin_24_ ; +wire [0:0] cby_1__1__96_left_grid_pin_25_ ; +wire [0:0] cby_1__1__96_left_grid_pin_26_ ; +wire [0:0] cby_1__1__96_left_grid_pin_27_ ; +wire [0:0] cby_1__1__96_left_grid_pin_28_ ; +wire [0:0] cby_1__1__96_left_grid_pin_29_ ; +wire [0:0] cby_1__1__96_left_grid_pin_30_ ; +wire [0:0] cby_1__1__96_left_grid_pin_31_ ; +wire [0:0] cby_1__1__97_ccff_tail ; +wire [0:29] cby_1__1__97_chany_bottom_out ; +wire [0:29] cby_1__1__97_chany_top_out ; +wire [0:0] cby_1__1__97_left_grid_pin_16_ ; +wire [0:0] cby_1__1__97_left_grid_pin_17_ ; +wire [0:0] cby_1__1__97_left_grid_pin_18_ ; +wire [0:0] cby_1__1__97_left_grid_pin_19_ ; +wire [0:0] cby_1__1__97_left_grid_pin_20_ ; +wire [0:0] cby_1__1__97_left_grid_pin_21_ ; +wire [0:0] cby_1__1__97_left_grid_pin_22_ ; +wire [0:0] cby_1__1__97_left_grid_pin_23_ ; +wire [0:0] cby_1__1__97_left_grid_pin_24_ ; +wire [0:0] cby_1__1__97_left_grid_pin_25_ ; +wire [0:0] cby_1__1__97_left_grid_pin_26_ ; +wire [0:0] cby_1__1__97_left_grid_pin_27_ ; +wire [0:0] cby_1__1__97_left_grid_pin_28_ ; +wire [0:0] cby_1__1__97_left_grid_pin_29_ ; +wire [0:0] cby_1__1__97_left_grid_pin_30_ ; +wire [0:0] cby_1__1__97_left_grid_pin_31_ ; +wire [0:0] cby_1__1__98_ccff_tail ; +wire [0:29] cby_1__1__98_chany_bottom_out ; +wire [0:29] cby_1__1__98_chany_top_out ; +wire [0:0] cby_1__1__98_left_grid_pin_16_ ; +wire [0:0] cby_1__1__98_left_grid_pin_17_ ; +wire [0:0] cby_1__1__98_left_grid_pin_18_ ; +wire [0:0] cby_1__1__98_left_grid_pin_19_ ; +wire [0:0] cby_1__1__98_left_grid_pin_20_ ; +wire [0:0] cby_1__1__98_left_grid_pin_21_ ; +wire [0:0] cby_1__1__98_left_grid_pin_22_ ; +wire [0:0] cby_1__1__98_left_grid_pin_23_ ; +wire [0:0] cby_1__1__98_left_grid_pin_24_ ; +wire [0:0] cby_1__1__98_left_grid_pin_25_ ; +wire [0:0] cby_1__1__98_left_grid_pin_26_ ; +wire [0:0] cby_1__1__98_left_grid_pin_27_ ; +wire [0:0] cby_1__1__98_left_grid_pin_28_ ; +wire [0:0] cby_1__1__98_left_grid_pin_29_ ; +wire [0:0] cby_1__1__98_left_grid_pin_30_ ; +wire [0:0] cby_1__1__98_left_grid_pin_31_ ; +wire [0:0] cby_1__1__99_ccff_tail ; +wire [0:29] cby_1__1__99_chany_bottom_out ; +wire [0:29] cby_1__1__99_chany_top_out ; +wire [0:0] cby_1__1__99_left_grid_pin_16_ ; +wire [0:0] cby_1__1__99_left_grid_pin_17_ ; +wire [0:0] cby_1__1__99_left_grid_pin_18_ ; +wire [0:0] cby_1__1__99_left_grid_pin_19_ ; +wire [0:0] cby_1__1__99_left_grid_pin_20_ ; +wire [0:0] cby_1__1__99_left_grid_pin_21_ ; +wire [0:0] cby_1__1__99_left_grid_pin_22_ ; +wire [0:0] cby_1__1__99_left_grid_pin_23_ ; +wire [0:0] cby_1__1__99_left_grid_pin_24_ ; +wire [0:0] cby_1__1__99_left_grid_pin_25_ ; +wire [0:0] cby_1__1__99_left_grid_pin_26_ ; +wire [0:0] cby_1__1__99_left_grid_pin_27_ ; +wire [0:0] cby_1__1__99_left_grid_pin_28_ ; +wire [0:0] cby_1__1__99_left_grid_pin_29_ ; +wire [0:0] cby_1__1__99_left_grid_pin_30_ ; +wire [0:0] cby_1__1__99_left_grid_pin_31_ ; +wire [0:0] cby_1__1__9_ccff_tail ; +wire [0:29] cby_1__1__9_chany_bottom_out ; +wire [0:29] cby_1__1__9_chany_top_out ; +wire [0:0] cby_1__1__9_left_grid_pin_16_ ; +wire [0:0] cby_1__1__9_left_grid_pin_17_ ; +wire [0:0] cby_1__1__9_left_grid_pin_18_ ; +wire [0:0] cby_1__1__9_left_grid_pin_19_ ; +wire [0:0] cby_1__1__9_left_grid_pin_20_ ; +wire [0:0] cby_1__1__9_left_grid_pin_21_ ; +wire [0:0] cby_1__1__9_left_grid_pin_22_ ; +wire [0:0] cby_1__1__9_left_grid_pin_23_ ; +wire [0:0] cby_1__1__9_left_grid_pin_24_ ; +wire [0:0] cby_1__1__9_left_grid_pin_25_ ; +wire [0:0] cby_1__1__9_left_grid_pin_26_ ; +wire [0:0] cby_1__1__9_left_grid_pin_27_ ; +wire [0:0] cby_1__1__9_left_grid_pin_28_ ; +wire [0:0] cby_1__1__9_left_grid_pin_29_ ; +wire [0:0] cby_1__1__9_left_grid_pin_30_ ; +wire [0:0] cby_1__1__9_left_grid_pin_31_ ; +wire [0:0] direct_interc_0_out ; +wire [0:0] direct_interc_100_out ; +wire [0:0] direct_interc_101_out ; +wire [0:0] direct_interc_102_out ; +wire [0:0] direct_interc_103_out ; +wire [0:0] direct_interc_104_out ; +wire [0:0] direct_interc_105_out ; +wire [0:0] direct_interc_106_out ; +wire [0:0] direct_interc_107_out ; +wire [0:0] direct_interc_108_out ; +wire [0:0] direct_interc_109_out ; +wire [0:0] direct_interc_10_out ; +wire [0:0] direct_interc_110_out ; +wire [0:0] direct_interc_111_out ; +wire [0:0] direct_interc_112_out ; +wire [0:0] direct_interc_113_out ; +wire [0:0] direct_interc_114_out ; +wire [0:0] direct_interc_115_out ; +wire [0:0] direct_interc_116_out ; +wire [0:0] direct_interc_117_out ; +wire [0:0] direct_interc_118_out ; +wire [0:0] direct_interc_119_out ; +wire [0:0] direct_interc_11_out ; +wire [0:0] direct_interc_120_out ; +wire [0:0] direct_interc_121_out ; +wire [0:0] direct_interc_122_out ; +wire [0:0] direct_interc_123_out ; +wire [0:0] direct_interc_124_out ; +wire [0:0] direct_interc_125_out ; +wire [0:0] direct_interc_126_out ; +wire [0:0] direct_interc_127_out ; +wire [0:0] direct_interc_128_out ; +wire [0:0] direct_interc_129_out ; +wire [0:0] direct_interc_12_out ; +wire [0:0] direct_interc_130_out ; +wire [0:0] direct_interc_131_out ; +wire [0:0] direct_interc_132_out ; +wire [0:0] direct_interc_133_out ; +wire [0:0] direct_interc_134_out ; +wire [0:0] direct_interc_135_out ; +wire [0:0] direct_interc_136_out ; +wire [0:0] direct_interc_137_out ; +wire [0:0] direct_interc_138_out ; +wire [0:0] direct_interc_139_out ; +wire [0:0] direct_interc_13_out ; +wire [0:0] direct_interc_140_out ; +wire [0:0] direct_interc_141_out ; +wire [0:0] direct_interc_142_out ; +wire [0:0] direct_interc_143_out ; +wire [0:0] direct_interc_144_out ; +wire [0:0] direct_interc_145_out ; +wire [0:0] direct_interc_146_out ; +wire [0:0] direct_interc_147_out ; +wire [0:0] direct_interc_148_out ; +wire [0:0] direct_interc_149_out ; +wire [0:0] direct_interc_14_out ; +wire [0:0] direct_interc_150_out ; +wire [0:0] direct_interc_151_out ; +wire [0:0] direct_interc_152_out ; +wire [0:0] direct_interc_153_out ; +wire [0:0] direct_interc_154_out ; +wire [0:0] direct_interc_155_out ; +wire [0:0] direct_interc_156_out ; +wire [0:0] direct_interc_157_out ; +wire [0:0] direct_interc_158_out ; +wire [0:0] direct_interc_159_out ; +wire [0:0] direct_interc_15_out ; +wire [0:0] direct_interc_160_out ; +wire [0:0] direct_interc_161_out ; +wire [0:0] direct_interc_162_out ; +wire [0:0] direct_interc_163_out ; +wire [0:0] direct_interc_164_out ; +wire [0:0] direct_interc_165_out ; +wire [0:0] direct_interc_166_out ; +wire [0:0] direct_interc_167_out ; +wire [0:0] direct_interc_168_out ; +wire [0:0] direct_interc_169_out ; +wire [0:0] direct_interc_16_out ; +wire [0:0] direct_interc_170_out ; +wire [0:0] direct_interc_171_out ; +wire [0:0] direct_interc_172_out ; +wire [0:0] direct_interc_173_out ; +wire [0:0] direct_interc_174_out ; +wire [0:0] direct_interc_175_out ; +wire [0:0] direct_interc_176_out ; +wire [0:0] direct_interc_177_out ; +wire [0:0] direct_interc_178_out ; +wire [0:0] direct_interc_179_out ; +wire [0:0] direct_interc_17_out ; +wire [0:0] direct_interc_180_out ; +wire [0:0] direct_interc_181_out ; +wire [0:0] direct_interc_182_out ; +wire [0:0] direct_interc_183_out ; +wire [0:0] direct_interc_184_out ; +wire [0:0] direct_interc_185_out ; +wire [0:0] direct_interc_186_out ; +wire [0:0] direct_interc_187_out ; +wire [0:0] direct_interc_188_out ; +wire [0:0] direct_interc_189_out ; +wire [0:0] direct_interc_18_out ; +wire [0:0] direct_interc_190_out ; +wire [0:0] direct_interc_191_out ; +wire [0:0] direct_interc_192_out ; +wire [0:0] direct_interc_193_out ; +wire [0:0] direct_interc_194_out ; +wire [0:0] direct_interc_195_out ; +wire [0:0] direct_interc_196_out ; +wire [0:0] direct_interc_197_out ; +wire [0:0] direct_interc_198_out ; +wire [0:0] direct_interc_199_out ; +wire [0:0] direct_interc_19_out ; +wire [0:0] direct_interc_1_out ; +wire [0:0] direct_interc_200_out ; +wire [0:0] direct_interc_201_out ; +wire [0:0] direct_interc_202_out ; +wire [0:0] direct_interc_203_out ; +wire [0:0] direct_interc_204_out ; +wire [0:0] direct_interc_205_out ; +wire [0:0] direct_interc_206_out ; +wire [0:0] direct_interc_207_out ; +wire [0:0] direct_interc_208_out ; +wire [0:0] direct_interc_209_out ; +wire [0:0] direct_interc_20_out ; +wire [0:0] direct_interc_210_out ; +wire [0:0] direct_interc_211_out ; +wire [0:0] direct_interc_212_out ; +wire [0:0] direct_interc_213_out ; +wire [0:0] direct_interc_214_out ; +wire [0:0] direct_interc_215_out ; +wire [0:0] direct_interc_216_out ; +wire [0:0] direct_interc_217_out ; +wire [0:0] direct_interc_218_out ; +wire [0:0] direct_interc_219_out ; +wire [0:0] direct_interc_21_out ; +wire [0:0] direct_interc_220_out ; +wire [0:0] direct_interc_221_out ; +wire [0:0] direct_interc_222_out ; +wire [0:0] direct_interc_223_out ; +wire [0:0] direct_interc_224_out ; +wire [0:0] direct_interc_225_out ; +wire [0:0] direct_interc_226_out ; +wire [0:0] direct_interc_227_out ; +wire [0:0] direct_interc_228_out ; +wire [0:0] direct_interc_229_out ; +wire [0:0] direct_interc_22_out ; +wire [0:0] direct_interc_230_out ; +wire [0:0] direct_interc_231_out ; +wire [0:0] direct_interc_232_out ; +wire [0:0] direct_interc_233_out ; +wire [0:0] direct_interc_234_out ; +wire [0:0] direct_interc_235_out ; +wire [0:0] direct_interc_236_out ; +wire [0:0] direct_interc_237_out ; +wire [0:0] direct_interc_238_out ; +wire [0:0] direct_interc_239_out ; +wire [0:0] direct_interc_23_out ; +wire [0:0] direct_interc_240_out ; +wire [0:0] direct_interc_241_out ; +wire [0:0] direct_interc_242_out ; +wire [0:0] direct_interc_243_out ; +wire [0:0] direct_interc_244_out ; +wire [0:0] direct_interc_245_out ; +wire [0:0] direct_interc_246_out ; +wire [0:0] direct_interc_247_out ; +wire [0:0] direct_interc_248_out ; +wire [0:0] direct_interc_249_out ; +wire [0:0] direct_interc_24_out ; +wire [0:0] direct_interc_250_out ; +wire [0:0] direct_interc_251_out ; +wire [0:0] direct_interc_252_out ; +wire [0:0] direct_interc_253_out ; +wire [0:0] direct_interc_254_out ; +wire [0:0] direct_interc_255_out ; +wire [0:0] direct_interc_256_out ; +wire [0:0] direct_interc_257_out ; +wire [0:0] direct_interc_258_out ; +wire [0:0] direct_interc_259_out ; +wire [0:0] direct_interc_25_out ; +wire [0:0] direct_interc_260_out ; +wire [0:0] direct_interc_261_out ; +wire [0:0] direct_interc_262_out ; +wire [0:0] direct_interc_263_out ; +wire [0:0] direct_interc_264_out ; +wire [0:0] direct_interc_265_out ; +wire [0:0] direct_interc_266_out ; +wire [0:0] direct_interc_267_out ; +wire [0:0] direct_interc_268_out ; +wire [0:0] direct_interc_269_out ; +wire [0:0] direct_interc_26_out ; +wire [0:0] direct_interc_270_out ; +wire [0:0] direct_interc_271_out ; +wire [0:0] direct_interc_272_out ; +wire [0:0] direct_interc_273_out ; +wire [0:0] direct_interc_274_out ; +wire [0:0] direct_interc_275_out ; +wire [0:0] direct_interc_276_out ; +wire [0:0] direct_interc_277_out ; +wire [0:0] direct_interc_278_out ; +wire [0:0] direct_interc_279_out ; +wire [0:0] direct_interc_27_out ; +wire [0:0] direct_interc_280_out ; +wire [0:0] direct_interc_281_out ; +wire [0:0] direct_interc_282_out ; +wire [0:0] direct_interc_283_out ; +wire [0:0] direct_interc_284_out ; +wire [0:0] direct_interc_285_out ; +wire [0:0] direct_interc_286_out ; +wire [0:0] direct_interc_287_out ; +wire [0:0] direct_interc_288_out ; +wire [0:0] direct_interc_289_out ; +wire [0:0] direct_interc_28_out ; +wire [0:0] direct_interc_290_out ; +wire [0:0] direct_interc_291_out ; +wire [0:0] direct_interc_292_out ; +wire [0:0] direct_interc_293_out ; +wire [0:0] direct_interc_294_out ; +wire [0:0] direct_interc_295_out ; +wire [0:0] direct_interc_296_out ; +wire [0:0] direct_interc_297_out ; +wire [0:0] direct_interc_298_out ; +wire [0:0] direct_interc_299_out ; +wire [0:0] direct_interc_29_out ; +wire [0:0] direct_interc_2_out ; +wire [0:0] direct_interc_300_out ; +wire [0:0] direct_interc_301_out ; +wire [0:0] direct_interc_302_out ; +wire [0:0] direct_interc_303_out ; +wire [0:0] direct_interc_304_out ; +wire [0:0] direct_interc_305_out ; +wire [0:0] direct_interc_306_out ; +wire [0:0] direct_interc_307_out ; +wire [0:0] direct_interc_308_out ; +wire [0:0] direct_interc_309_out ; +wire [0:0] direct_interc_30_out ; +wire [0:0] direct_interc_310_out ; +wire [0:0] direct_interc_311_out ; +wire [0:0] direct_interc_312_out ; +wire [0:0] direct_interc_313_out ; +wire [0:0] direct_interc_314_out ; +wire [0:0] direct_interc_315_out ; +wire [0:0] direct_interc_316_out ; +wire [0:0] direct_interc_317_out ; +wire [0:0] direct_interc_318_out ; +wire [0:0] direct_interc_319_out ; +wire [0:0] direct_interc_31_out ; +wire [0:0] direct_interc_320_out ; +wire [0:0] direct_interc_321_out ; +wire [0:0] direct_interc_322_out ; +wire [0:0] direct_interc_323_out ; +wire [0:0] direct_interc_324_out ; +wire [0:0] direct_interc_325_out ; +wire [0:0] direct_interc_326_out ; +wire [0:0] direct_interc_327_out ; +wire [0:0] direct_interc_328_out ; +wire [0:0] direct_interc_329_out ; +wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_330_out ; +wire [0:0] direct_interc_331_out ; +wire [0:0] direct_interc_332_out ; +wire [0:0] direct_interc_333_out ; +wire [0:0] direct_interc_334_out ; +wire [0:0] direct_interc_335_out ; +wire [0:0] direct_interc_336_out ; +wire [0:0] direct_interc_337_out ; +wire [0:0] direct_interc_338_out ; +wire [0:0] direct_interc_339_out ; +wire [0:0] direct_interc_33_out ; +wire [0:0] direct_interc_340_out ; +wire [0:0] direct_interc_341_out ; +wire [0:0] direct_interc_342_out ; +wire [0:0] direct_interc_343_out ; +wire [0:0] direct_interc_344_out ; +wire [0:0] direct_interc_345_out ; +wire [0:0] direct_interc_346_out ; +wire [0:0] direct_interc_347_out ; +wire [0:0] direct_interc_348_out ; +wire [0:0] direct_interc_349_out ; +wire [0:0] direct_interc_34_out ; +wire [0:0] direct_interc_350_out ; +wire [0:0] direct_interc_351_out ; +wire [0:0] direct_interc_352_out ; +wire [0:0] direct_interc_353_out ; +wire [0:0] direct_interc_354_out ; +wire [0:0] direct_interc_355_out ; +wire [0:0] direct_interc_356_out ; +wire [0:0] direct_interc_357_out ; +wire [0:0] direct_interc_358_out ; +wire [0:0] direct_interc_359_out ; +wire [0:0] direct_interc_35_out ; +wire [0:0] direct_interc_360_out ; +wire [0:0] direct_interc_361_out ; +wire [0:0] direct_interc_362_out ; +wire [0:0] direct_interc_363_out ; +wire [0:0] direct_interc_364_out ; +wire [0:0] direct_interc_365_out ; +wire [0:0] direct_interc_366_out ; +wire [0:0] direct_interc_367_out ; +wire [0:0] direct_interc_368_out ; +wire [0:0] direct_interc_369_out ; +wire [0:0] direct_interc_36_out ; +wire [0:0] direct_interc_370_out ; +wire [0:0] direct_interc_371_out ; +wire [0:0] direct_interc_372_out ; +wire [0:0] direct_interc_373_out ; +wire [0:0] direct_interc_374_out ; +wire [0:0] direct_interc_375_out ; +wire [0:0] direct_interc_376_out ; +wire [0:0] direct_interc_377_out ; +wire [0:0] direct_interc_378_out ; +wire [0:0] direct_interc_379_out ; +wire [0:0] direct_interc_37_out ; +wire [0:0] direct_interc_380_out ; +wire [0:0] direct_interc_381_out ; +wire [0:0] direct_interc_382_out ; +wire [0:0] direct_interc_383_out ; +wire [0:0] direct_interc_384_out ; +wire [0:0] direct_interc_385_out ; +wire [0:0] direct_interc_386_out ; +wire [0:0] direct_interc_387_out ; +wire [0:0] direct_interc_388_out ; +wire [0:0] direct_interc_389_out ; +wire [0:0] direct_interc_38_out ; +wire [0:0] direct_interc_390_out ; +wire [0:0] direct_interc_391_out ; +wire [0:0] direct_interc_392_out ; +wire [0:0] direct_interc_393_out ; +wire [0:0] direct_interc_394_out ; +wire [0:0] direct_interc_395_out ; +wire [0:0] direct_interc_396_out ; +wire [0:0] direct_interc_397_out ; +wire [0:0] direct_interc_398_out ; +wire [0:0] direct_interc_399_out ; +wire [0:0] direct_interc_39_out ; +wire [0:0] direct_interc_3_out ; +wire [0:0] direct_interc_400_out ; +wire [0:0] direct_interc_401_out ; +wire [0:0] direct_interc_402_out ; +wire [0:0] direct_interc_403_out ; +wire [0:0] direct_interc_404_out ; +wire [0:0] direct_interc_405_out ; +wire [0:0] direct_interc_406_out ; +wire [0:0] direct_interc_40_out ; +wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_42_out ; +wire [0:0] direct_interc_43_out ; +wire [0:0] direct_interc_44_out ; +wire [0:0] direct_interc_45_out ; +wire [0:0] direct_interc_46_out ; +wire [0:0] direct_interc_47_out ; +wire [0:0] direct_interc_48_out ; +wire [0:0] direct_interc_49_out ; +wire [0:0] direct_interc_4_out ; +wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_51_out ; +wire [0:0] direct_interc_52_out ; +wire [0:0] direct_interc_53_out ; +wire [0:0] direct_interc_54_out ; +wire [0:0] direct_interc_55_out ; +wire [0:0] direct_interc_56_out ; +wire [0:0] direct_interc_57_out ; +wire [0:0] direct_interc_58_out ; +wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_5_out ; +wire [0:0] direct_interc_60_out ; +wire [0:0] direct_interc_61_out ; +wire [0:0] direct_interc_62_out ; +wire [0:0] direct_interc_63_out ; +wire [0:0] direct_interc_64_out ; +wire [0:0] direct_interc_65_out ; +wire [0:0] direct_interc_66_out ; +wire [0:0] direct_interc_67_out ; +wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_69_out ; +wire [0:0] direct_interc_6_out ; +wire [0:0] direct_interc_70_out ; +wire [0:0] direct_interc_71_out ; +wire [0:0] direct_interc_72_out ; +wire [0:0] direct_interc_73_out ; +wire [0:0] direct_interc_74_out ; +wire [0:0] direct_interc_75_out ; +wire [0:0] direct_interc_76_out ; +wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_78_out ; +wire [0:0] direct_interc_79_out ; +wire [0:0] direct_interc_7_out ; +wire [0:0] direct_interc_80_out ; +wire [0:0] direct_interc_81_out ; +wire [0:0] direct_interc_82_out ; +wire [0:0] direct_interc_83_out ; +wire [0:0] direct_interc_84_out ; +wire [0:0] direct_interc_85_out ; +wire [0:0] direct_interc_86_out ; +wire [0:0] direct_interc_87_out ; +wire [0:0] direct_interc_88_out ; +wire [0:0] direct_interc_89_out ; +wire [0:0] direct_interc_8_out ; +wire [0:0] direct_interc_90_out ; +wire [0:0] direct_interc_91_out ; +wire [0:0] direct_interc_92_out ; +wire [0:0] direct_interc_93_out ; +wire [0:0] direct_interc_94_out ; +wire [0:0] direct_interc_95_out ; +wire [0:0] direct_interc_96_out ; +wire [0:0] direct_interc_97_out ; +wire [0:0] direct_interc_98_out ; +wire [0:0] direct_interc_99_out ; +wire [0:0] direct_interc_9_out ; +wire [0:0] grid_clb_0_ccff_tail ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_0_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_0_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_100_ccff_tail ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_100_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_100_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_101_ccff_tail ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_101_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_101_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_102_ccff_tail ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_102_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_102_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_103_ccff_tail ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_103_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_103_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_104_ccff_tail ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_104_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_104_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_105_ccff_tail ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_105_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_105_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_106_ccff_tail ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_106_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_106_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_107_ccff_tail ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_107_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_107_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_108_ccff_tail ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_108_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_108_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_109_ccff_tail ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_109_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_109_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_10_ccff_tail ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_10_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_10_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_110_ccff_tail ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_110_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_110_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_111_ccff_tail ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_111_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_111_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_112_ccff_tail ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_112_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_112_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_113_ccff_tail ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_113_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_113_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_114_ccff_tail ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_114_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_114_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_115_ccff_tail ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_115_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_115_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_116_ccff_tail ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_116_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_116_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_117_ccff_tail ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_117_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_117_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_118_ccff_tail ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_118_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_118_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_119_ccff_tail ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_119_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_119_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_11_ccff_tail ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_11_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_11_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_120_ccff_tail ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_120_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_120_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_121_ccff_tail ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_121_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_121_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_122_ccff_tail ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_122_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_122_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_123_ccff_tail ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_123_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_123_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_124_ccff_tail ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_124_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_124_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_125_ccff_tail ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_125_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_125_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_126_ccff_tail ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_126_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_126_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_127_ccff_tail ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_127_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_127_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_128_ccff_tail ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_128_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_128_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_129_ccff_tail ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_129_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_129_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_53_ ; +wire [0:0] grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_12_ccff_tail ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_12_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_12_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_130_ccff_tail ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_130_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_130_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_131_ccff_tail ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_131_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_131_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_132_ccff_tail ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_132_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_132_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_133_ccff_tail ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_133_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_133_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_134_ccff_tail ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_134_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_134_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_135_ccff_tail ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_135_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_135_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_136_ccff_tail ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_136_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_136_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_137_ccff_tail ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_137_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_137_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_138_ccff_tail ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_138_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_138_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_139_ccff_tail ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_139_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_139_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_13_ccff_tail ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_13_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_13_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_140_ccff_tail ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_140_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_140_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_141_ccff_tail ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_141_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_141_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_142_ccff_tail ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_142_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_142_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_143_ccff_tail ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_143_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_143_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_14_ccff_tail ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_14_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_14_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_15_ccff_tail ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_15_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_15_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_16_ccff_tail ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_16_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_16_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_17_ccff_tail ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_17_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_17_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_18_ccff_tail ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_18_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_18_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_19_ccff_tail ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_19_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_19_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_33_ ; +wire [0:0] grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_1_ccff_tail ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_1_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_1_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_20_ccff_tail ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_20_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_20_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_21_ccff_tail ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_21_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_21_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_22_ccff_tail ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_22_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_22_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_23_ccff_tail ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_23_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_23_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_24_ccff_tail ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_24_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_24_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_25_ccff_tail ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_25_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_25_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_26_ccff_tail ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_26_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_26_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_27_ccff_tail ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_27_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_27_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_28_ccff_tail ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_28_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_28_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_29_ccff_tail ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_29_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_29_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_2_ccff_tail ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_2_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_2_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_30_ccff_tail ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_30_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_30_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_31_ccff_tail ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_31_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_31_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_32_ccff_tail ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_32_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_32_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_33_ccff_tail ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_33_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_33_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_34_ccff_tail ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_34_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_34_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_35_ccff_tail ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_35_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_35_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_36_ccff_tail ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_36_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_36_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_37_ccff_tail ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_37_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_37_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_38_ccff_tail ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_38_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_38_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_39_ccff_tail ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_39_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_39_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_3_ccff_tail ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_3_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_3_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_40_ccff_tail ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_40_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_40_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_41_ccff_tail ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_41_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_41_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_42_ccff_tail ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_42_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_42_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_43_ccff_tail ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_43_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_43_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_44_ccff_tail ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_44_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_44_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_45_ccff_tail ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_45_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_45_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_46_ccff_tail ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_46_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_46_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_47_ccff_tail ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_47_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_47_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_48_ccff_tail ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_48_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_48_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_49_ccff_tail ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_49_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_49_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_4_ccff_tail ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_4_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_4_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_50_ccff_tail ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_50_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_50_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_51_ccff_tail ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_51_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_51_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_52_ccff_tail ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_52_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_52_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_53_ccff_tail ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_53_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_53_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_54_ccff_tail ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_54_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_54_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_55_ccff_tail ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_55_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_55_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_56_ccff_tail ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_56_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_56_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_57_ccff_tail ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_57_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_57_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_58_ccff_tail ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_58_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_58_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_59_ccff_tail ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_59_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_59_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_5_ccff_tail ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_5_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_5_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_60_ccff_tail ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_60_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_60_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_61_ccff_tail ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_61_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_61_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_62_ccff_tail ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_62_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_62_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_63_ccff_tail ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_63_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_63_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_64_ccff_tail ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_64_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_64_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_65_ccff_tail ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_65_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_65_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_66_ccff_tail ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_66_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_66_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_67_ccff_tail ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_67_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_67_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_68_ccff_tail ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_68_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_68_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_69_ccff_tail ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_69_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_69_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_6_ccff_tail ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_6_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_6_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_70_ccff_tail ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_70_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_70_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_71_ccff_tail ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_71_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_71_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_72_ccff_tail ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_72_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_72_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_73_ccff_tail ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_73_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_73_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_74_ccff_tail ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_74_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_74_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_75_ccff_tail ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_75_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_75_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_76_ccff_tail ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_76_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_76_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_77_ccff_tail ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_77_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_77_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_78_ccff_tail ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_78_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_78_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_79_ccff_tail ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_79_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_79_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_7_ccff_tail ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_7_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_7_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_80_ccff_tail ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_80_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_80_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_81_ccff_tail ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_81_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_81_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_82_ccff_tail ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_82_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_82_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_83_ccff_tail ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_83_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_83_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_84_ccff_tail ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_84_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_84_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_85_ccff_tail ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_85_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_85_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_86_ccff_tail ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_86_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_86_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_87_ccff_tail ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_87_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_87_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_88_ccff_tail ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_88_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_88_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_89_ccff_tail ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_89_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_89_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_8_ccff_tail ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_8_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_8_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_90_ccff_tail ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_90_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_90_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_91_ccff_tail ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_91_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_91_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_92_ccff_tail ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_92_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_92_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_93_ccff_tail ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_93_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_93_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_94_ccff_tail ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_94_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_94_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_95_ccff_tail ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_95_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_95_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_96_ccff_tail ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_96_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_96_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_97_ccff_tail ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_97_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_97_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_98_ccff_tail ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_98_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_98_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_99_ccff_tail ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_99_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_99_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ; +wire [0:0] grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ; +wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ; +wire [0:0] grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ; +wire [0:0] grid_clb_9_ccff_tail ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_44_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_45_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_46_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_47_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_48_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_49_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_50_upper ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_lower ; +wire [0:0] grid_clb_9_right_width_0_height_0__pin_51_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_36_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_37_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_38_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_39_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_40_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_41_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_42_upper ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_lower ; +wire [0:0] grid_clb_9_top_width_0_height_0__pin_43_upper ; +wire [0:0] grid_io_bottom_0_ccff_tail ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_0_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_10_ccff_tail ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_10_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_11_ccff_tail ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_11_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_1_ccff_tail ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_1_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_2_ccff_tail ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_2_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_3_ccff_tail ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_3_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_4_ccff_tail ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_4_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_5_ccff_tail ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_5_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_6_ccff_tail ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_6_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_7_ccff_tail ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_7_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_8_ccff_tail ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_8_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_bottom_9_ccff_tail ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_11_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_13_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_15_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_17_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_3_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_5_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_7_upper ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_lower ; +wire [0:0] grid_io_bottom_9_top_width_0_height_0__pin_9_upper ; +wire [0:0] grid_io_left_0_ccff_tail ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_0_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_10_ccff_tail ; +wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_10_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_11_ccff_tail ; +wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_11_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_1_ccff_tail ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_1_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_2_ccff_tail ; +wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_2_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_3_ccff_tail ; +wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_3_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_4_ccff_tail ; +wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_4_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_5_ccff_tail ; +wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_5_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_6_ccff_tail ; +wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_6_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_7_ccff_tail ; +wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_7_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_8_ccff_tail ; +wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_8_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_left_9_ccff_tail ; +wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_left_9_right_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_0_ccff_tail ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_0_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_10_ccff_tail ; +wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_10_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_11_ccff_tail ; +wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_11_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_1_ccff_tail ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_1_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_2_ccff_tail ; +wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_2_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_3_ccff_tail ; +wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_3_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_4_ccff_tail ; +wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_4_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_5_ccff_tail ; +wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_5_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_6_ccff_tail ; +wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_6_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_7_ccff_tail ; +wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_7_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_8_ccff_tail ; +wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_8_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_right_9_ccff_tail ; +wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_right_9_left_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_0_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_0_ccff_tail ; +wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_10_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_10_ccff_tail ; +wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_11_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_11_ccff_tail ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_1_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_1_ccff_tail ; +wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_2_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_2_ccff_tail ; +wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_3_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_3_ccff_tail ; +wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_4_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_4_ccff_tail ; +wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_5_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_5_ccff_tail ; +wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_6_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_6_ccff_tail ; +wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_7_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_7_ccff_tail ; +wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_8_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_8_ccff_tail ; +wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_lower ; +wire [0:0] grid_io_top_9_bottom_width_0_height_0__pin_1_upper ; +wire [0:0] grid_io_top_9_ccff_tail ; +wire [0:29] sb_0__0__0_chanx_right_out ; +wire [0:29] sb_0__0__0_chany_top_out ; +wire [0:0] sb_0__12__0_ccff_tail ; +wire [0:29] sb_0__12__0_chanx_right_out ; +wire [0:29] sb_0__12__0_chany_bottom_out ; +wire [0:0] sb_0__1__0_ccff_tail ; +wire [0:29] sb_0__1__0_chanx_right_out ; +wire [0:29] sb_0__1__0_chany_bottom_out ; +wire [0:29] sb_0__1__0_chany_top_out ; +wire [0:0] sb_0__1__10_ccff_tail ; +wire [0:29] sb_0__1__10_chanx_right_out ; +wire [0:29] sb_0__1__10_chany_bottom_out ; +wire [0:29] sb_0__1__10_chany_top_out ; +wire [0:0] sb_0__1__1_ccff_tail ; +wire [0:29] sb_0__1__1_chanx_right_out ; +wire [0:29] sb_0__1__1_chany_bottom_out ; +wire [0:29] sb_0__1__1_chany_top_out ; +wire [0:0] sb_0__1__2_ccff_tail ; +wire [0:29] sb_0__1__2_chanx_right_out ; +wire [0:29] sb_0__1__2_chany_bottom_out ; +wire [0:29] sb_0__1__2_chany_top_out ; +wire [0:0] sb_0__1__3_ccff_tail ; +wire [0:29] sb_0__1__3_chanx_right_out ; +wire [0:29] sb_0__1__3_chany_bottom_out ; +wire [0:29] sb_0__1__3_chany_top_out ; +wire [0:0] sb_0__1__4_ccff_tail ; +wire [0:29] sb_0__1__4_chanx_right_out ; +wire [0:29] sb_0__1__4_chany_bottom_out ; +wire [0:29] sb_0__1__4_chany_top_out ; +wire [0:0] sb_0__1__5_ccff_tail ; +wire [0:29] sb_0__1__5_chanx_right_out ; +wire [0:29] sb_0__1__5_chany_bottom_out ; +wire [0:29] sb_0__1__5_chany_top_out ; +wire [0:0] sb_0__1__6_ccff_tail ; +wire [0:29] sb_0__1__6_chanx_right_out ; +wire [0:29] sb_0__1__6_chany_bottom_out ; +wire [0:29] sb_0__1__6_chany_top_out ; +wire [0:0] sb_0__1__7_ccff_tail ; +wire [0:29] sb_0__1__7_chanx_right_out ; +wire [0:29] sb_0__1__7_chany_bottom_out ; +wire [0:29] sb_0__1__7_chany_top_out ; +wire [0:0] sb_0__1__8_ccff_tail ; +wire [0:29] sb_0__1__8_chanx_right_out ; +wire [0:29] sb_0__1__8_chany_bottom_out ; +wire [0:29] sb_0__1__8_chany_top_out ; +wire [0:0] sb_0__1__9_ccff_tail ; +wire [0:29] sb_0__1__9_chanx_right_out ; +wire [0:29] sb_0__1__9_chany_bottom_out ; +wire [0:29] sb_0__1__9_chany_top_out ; +wire [0:0] sb_12__0__0_ccff_tail ; +wire [0:29] sb_12__0__0_chanx_left_out ; +wire [0:29] sb_12__0__0_chany_top_out ; +wire [0:0] sb_12__12__0_ccff_tail ; +wire [0:29] sb_12__12__0_chanx_left_out ; +wire [0:29] sb_12__12__0_chany_bottom_out ; +wire [0:0] sb_12__1__0_ccff_tail ; +wire [0:29] sb_12__1__0_chanx_left_out ; +wire [0:29] sb_12__1__0_chany_bottom_out ; +wire [0:29] sb_12__1__0_chany_top_out ; +wire [0:0] sb_12__1__10_ccff_tail ; +wire [0:29] sb_12__1__10_chanx_left_out ; +wire [0:29] sb_12__1__10_chany_bottom_out ; +wire [0:29] sb_12__1__10_chany_top_out ; +wire [0:0] sb_12__1__1_ccff_tail ; +wire [0:29] sb_12__1__1_chanx_left_out ; +wire [0:29] sb_12__1__1_chany_bottom_out ; +wire [0:29] sb_12__1__1_chany_top_out ; +wire [0:0] sb_12__1__2_ccff_tail ; +wire [0:29] sb_12__1__2_chanx_left_out ; +wire [0:29] sb_12__1__2_chany_bottom_out ; +wire [0:29] sb_12__1__2_chany_top_out ; +wire [0:0] sb_12__1__3_ccff_tail ; +wire [0:29] sb_12__1__3_chanx_left_out ; +wire [0:29] sb_12__1__3_chany_bottom_out ; +wire [0:29] sb_12__1__3_chany_top_out ; +wire [0:0] sb_12__1__4_ccff_tail ; +wire [0:29] sb_12__1__4_chanx_left_out ; +wire [0:29] sb_12__1__4_chany_bottom_out ; +wire [0:29] sb_12__1__4_chany_top_out ; +wire [0:0] sb_12__1__5_ccff_tail ; +wire [0:29] sb_12__1__5_chanx_left_out ; +wire [0:29] sb_12__1__5_chany_bottom_out ; +wire [0:29] sb_12__1__5_chany_top_out ; +wire [0:0] sb_12__1__6_ccff_tail ; +wire [0:29] sb_12__1__6_chanx_left_out ; +wire [0:29] sb_12__1__6_chany_bottom_out ; +wire [0:29] sb_12__1__6_chany_top_out ; +wire [0:0] sb_12__1__7_ccff_tail ; +wire [0:29] sb_12__1__7_chanx_left_out ; +wire [0:29] sb_12__1__7_chany_bottom_out ; +wire [0:29] sb_12__1__7_chany_top_out ; +wire [0:0] sb_12__1__8_ccff_tail ; +wire [0:29] sb_12__1__8_chanx_left_out ; +wire [0:29] sb_12__1__8_chany_bottom_out ; +wire [0:29] sb_12__1__8_chany_top_out ; +wire [0:0] sb_12__1__9_ccff_tail ; +wire [0:29] sb_12__1__9_chanx_left_out ; +wire [0:29] sb_12__1__9_chany_bottom_out ; +wire [0:29] sb_12__1__9_chany_top_out ; +wire [0:0] sb_1__0__0_ccff_tail ; +wire [0:29] sb_1__0__0_chanx_left_out ; +wire [0:29] sb_1__0__0_chanx_right_out ; +wire [0:29] sb_1__0__0_chany_top_out ; +wire [0:0] sb_1__0__10_ccff_tail ; +wire [0:29] sb_1__0__10_chanx_left_out ; +wire [0:29] sb_1__0__10_chanx_right_out ; +wire [0:29] sb_1__0__10_chany_top_out ; +wire [0:0] sb_1__0__1_ccff_tail ; +wire [0:29] sb_1__0__1_chanx_left_out ; +wire [0:29] sb_1__0__1_chanx_right_out ; +wire [0:29] sb_1__0__1_chany_top_out ; +wire [0:0] sb_1__0__2_ccff_tail ; +wire [0:29] sb_1__0__2_chanx_left_out ; +wire [0:29] sb_1__0__2_chanx_right_out ; +wire [0:29] sb_1__0__2_chany_top_out ; +wire [0:0] sb_1__0__3_ccff_tail ; +wire [0:29] sb_1__0__3_chanx_left_out ; +wire [0:29] sb_1__0__3_chanx_right_out ; +wire [0:29] sb_1__0__3_chany_top_out ; +wire [0:0] sb_1__0__4_ccff_tail ; +wire [0:29] sb_1__0__4_chanx_left_out ; +wire [0:29] sb_1__0__4_chanx_right_out ; +wire [0:29] sb_1__0__4_chany_top_out ; +wire [0:0] sb_1__0__5_ccff_tail ; +wire [0:29] sb_1__0__5_chanx_left_out ; +wire [0:29] sb_1__0__5_chanx_right_out ; +wire [0:29] sb_1__0__5_chany_top_out ; +wire [0:0] sb_1__0__6_ccff_tail ; +wire [0:29] sb_1__0__6_chanx_left_out ; +wire [0:29] sb_1__0__6_chanx_right_out ; +wire [0:29] sb_1__0__6_chany_top_out ; +wire [0:0] sb_1__0__7_ccff_tail ; +wire [0:29] sb_1__0__7_chanx_left_out ; +wire [0:29] sb_1__0__7_chanx_right_out ; +wire [0:29] sb_1__0__7_chany_top_out ; +wire [0:0] sb_1__0__8_ccff_tail ; +wire [0:29] sb_1__0__8_chanx_left_out ; +wire [0:29] sb_1__0__8_chanx_right_out ; +wire [0:29] sb_1__0__8_chany_top_out ; +wire [0:0] sb_1__0__9_ccff_tail ; +wire [0:29] sb_1__0__9_chanx_left_out ; +wire [0:29] sb_1__0__9_chanx_right_out ; +wire [0:29] sb_1__0__9_chany_top_out ; +wire [0:0] sb_1__12__0_ccff_tail ; +wire [0:29] sb_1__12__0_chanx_left_out ; +wire [0:29] sb_1__12__0_chanx_right_out ; +wire [0:29] sb_1__12__0_chany_bottom_out ; +wire [0:0] sb_1__12__10_ccff_tail ; +wire [0:29] sb_1__12__10_chanx_left_out ; +wire [0:29] sb_1__12__10_chanx_right_out ; +wire [0:29] sb_1__12__10_chany_bottom_out ; +wire [0:0] sb_1__12__1_ccff_tail ; +wire [0:29] sb_1__12__1_chanx_left_out ; +wire [0:29] sb_1__12__1_chanx_right_out ; +wire [0:29] sb_1__12__1_chany_bottom_out ; +wire [0:0] sb_1__12__2_ccff_tail ; +wire [0:29] sb_1__12__2_chanx_left_out ; +wire [0:29] sb_1__12__2_chanx_right_out ; +wire [0:29] sb_1__12__2_chany_bottom_out ; +wire [0:0] sb_1__12__3_ccff_tail ; +wire [0:29] sb_1__12__3_chanx_left_out ; +wire [0:29] sb_1__12__3_chanx_right_out ; +wire [0:29] sb_1__12__3_chany_bottom_out ; +wire [0:0] sb_1__12__4_ccff_tail ; +wire [0:29] sb_1__12__4_chanx_left_out ; +wire [0:29] sb_1__12__4_chanx_right_out ; +wire [0:29] sb_1__12__4_chany_bottom_out ; +wire [0:0] sb_1__12__5_ccff_tail ; +wire [0:29] sb_1__12__5_chanx_left_out ; +wire [0:29] sb_1__12__5_chanx_right_out ; +wire [0:29] sb_1__12__5_chany_bottom_out ; +wire [0:0] sb_1__12__6_ccff_tail ; +wire [0:29] sb_1__12__6_chanx_left_out ; +wire [0:29] sb_1__12__6_chanx_right_out ; +wire [0:29] sb_1__12__6_chany_bottom_out ; +wire [0:0] sb_1__12__7_ccff_tail ; +wire [0:29] sb_1__12__7_chanx_left_out ; +wire [0:29] sb_1__12__7_chanx_right_out ; +wire [0:29] sb_1__12__7_chany_bottom_out ; +wire [0:0] sb_1__12__8_ccff_tail ; +wire [0:29] sb_1__12__8_chanx_left_out ; +wire [0:29] sb_1__12__8_chanx_right_out ; +wire [0:29] sb_1__12__8_chany_bottom_out ; +wire [0:0] sb_1__12__9_ccff_tail ; +wire [0:29] sb_1__12__9_chanx_left_out ; +wire [0:29] sb_1__12__9_chanx_right_out ; +wire [0:29] sb_1__12__9_chany_bottom_out ; +wire [0:0] sb_1__1__0_ccff_tail ; +wire [0:29] sb_1__1__0_chanx_left_out ; +wire [0:29] sb_1__1__0_chanx_right_out ; +wire [0:29] sb_1__1__0_chany_bottom_out ; +wire [0:29] sb_1__1__0_chany_top_out ; +wire [0:0] sb_1__1__100_ccff_tail ; +wire [0:29] sb_1__1__100_chanx_left_out ; +wire [0:29] sb_1__1__100_chanx_right_out ; +wire [0:29] sb_1__1__100_chany_bottom_out ; +wire [0:29] sb_1__1__100_chany_top_out ; +wire [0:0] sb_1__1__101_ccff_tail ; +wire [0:29] sb_1__1__101_chanx_left_out ; +wire [0:29] sb_1__1__101_chanx_right_out ; +wire [0:29] sb_1__1__101_chany_bottom_out ; +wire [0:29] sb_1__1__101_chany_top_out ; +wire [0:0] sb_1__1__102_ccff_tail ; +wire [0:29] sb_1__1__102_chanx_left_out ; +wire [0:29] sb_1__1__102_chanx_right_out ; +wire [0:29] sb_1__1__102_chany_bottom_out ; +wire [0:29] sb_1__1__102_chany_top_out ; +wire [0:0] sb_1__1__103_ccff_tail ; +wire [0:29] sb_1__1__103_chanx_left_out ; +wire [0:29] sb_1__1__103_chanx_right_out ; +wire [0:29] sb_1__1__103_chany_bottom_out ; +wire [0:29] sb_1__1__103_chany_top_out ; +wire [0:0] sb_1__1__104_ccff_tail ; +wire [0:29] sb_1__1__104_chanx_left_out ; +wire [0:29] sb_1__1__104_chanx_right_out ; +wire [0:29] sb_1__1__104_chany_bottom_out ; +wire [0:29] sb_1__1__104_chany_top_out ; +wire [0:0] sb_1__1__105_ccff_tail ; +wire [0:29] sb_1__1__105_chanx_left_out ; +wire [0:29] sb_1__1__105_chanx_right_out ; +wire [0:29] sb_1__1__105_chany_bottom_out ; +wire [0:29] sb_1__1__105_chany_top_out ; +wire [0:0] sb_1__1__106_ccff_tail ; +wire [0:29] sb_1__1__106_chanx_left_out ; +wire [0:29] sb_1__1__106_chanx_right_out ; +wire [0:29] sb_1__1__106_chany_bottom_out ; +wire [0:29] sb_1__1__106_chany_top_out ; +wire [0:0] sb_1__1__107_ccff_tail ; +wire [0:29] sb_1__1__107_chanx_left_out ; +wire [0:29] sb_1__1__107_chanx_right_out ; +wire [0:29] sb_1__1__107_chany_bottom_out ; +wire [0:29] sb_1__1__107_chany_top_out ; +wire [0:0] sb_1__1__108_ccff_tail ; +wire [0:29] sb_1__1__108_chanx_left_out ; +wire [0:29] sb_1__1__108_chanx_right_out ; +wire [0:29] sb_1__1__108_chany_bottom_out ; +wire [0:29] sb_1__1__108_chany_top_out ; +wire [0:0] sb_1__1__109_ccff_tail ; +wire [0:29] sb_1__1__109_chanx_left_out ; +wire [0:29] sb_1__1__109_chanx_right_out ; +wire [0:29] sb_1__1__109_chany_bottom_out ; +wire [0:29] sb_1__1__109_chany_top_out ; +wire [0:0] sb_1__1__10_ccff_tail ; +wire [0:29] sb_1__1__10_chanx_left_out ; +wire [0:29] sb_1__1__10_chanx_right_out ; +wire [0:29] sb_1__1__10_chany_bottom_out ; +wire [0:29] sb_1__1__10_chany_top_out ; +wire [0:0] sb_1__1__110_ccff_tail ; +wire [0:29] sb_1__1__110_chanx_left_out ; +wire [0:29] sb_1__1__110_chanx_right_out ; +wire [0:29] sb_1__1__110_chany_bottom_out ; +wire [0:29] sb_1__1__110_chany_top_out ; +wire [0:0] sb_1__1__111_ccff_tail ; +wire [0:29] sb_1__1__111_chanx_left_out ; +wire [0:29] sb_1__1__111_chanx_right_out ; +wire [0:29] sb_1__1__111_chany_bottom_out ; +wire [0:29] sb_1__1__111_chany_top_out ; +wire [0:0] sb_1__1__112_ccff_tail ; +wire [0:29] sb_1__1__112_chanx_left_out ; +wire [0:29] sb_1__1__112_chanx_right_out ; +wire [0:29] sb_1__1__112_chany_bottom_out ; +wire [0:29] sb_1__1__112_chany_top_out ; +wire [0:0] sb_1__1__113_ccff_tail ; +wire [0:29] sb_1__1__113_chanx_left_out ; +wire [0:29] sb_1__1__113_chanx_right_out ; +wire [0:29] sb_1__1__113_chany_bottom_out ; +wire [0:29] sb_1__1__113_chany_top_out ; +wire [0:0] sb_1__1__114_ccff_tail ; +wire [0:29] sb_1__1__114_chanx_left_out ; +wire [0:29] sb_1__1__114_chanx_right_out ; +wire [0:29] sb_1__1__114_chany_bottom_out ; +wire [0:29] sb_1__1__114_chany_top_out ; +wire [0:0] sb_1__1__115_ccff_tail ; +wire [0:29] sb_1__1__115_chanx_left_out ; +wire [0:29] sb_1__1__115_chanx_right_out ; +wire [0:29] sb_1__1__115_chany_bottom_out ; +wire [0:29] sb_1__1__115_chany_top_out ; +wire [0:0] sb_1__1__116_ccff_tail ; +wire [0:29] sb_1__1__116_chanx_left_out ; +wire [0:29] sb_1__1__116_chanx_right_out ; +wire [0:29] sb_1__1__116_chany_bottom_out ; +wire [0:29] sb_1__1__116_chany_top_out ; +wire [0:0] sb_1__1__117_ccff_tail ; +wire [0:29] sb_1__1__117_chanx_left_out ; +wire [0:29] sb_1__1__117_chanx_right_out ; +wire [0:29] sb_1__1__117_chany_bottom_out ; +wire [0:29] sb_1__1__117_chany_top_out ; +wire [0:0] sb_1__1__118_ccff_tail ; +wire [0:29] sb_1__1__118_chanx_left_out ; +wire [0:29] sb_1__1__118_chanx_right_out ; +wire [0:29] sb_1__1__118_chany_bottom_out ; +wire [0:29] sb_1__1__118_chany_top_out ; +wire [0:0] sb_1__1__119_ccff_tail ; +wire [0:29] sb_1__1__119_chanx_left_out ; +wire [0:29] sb_1__1__119_chanx_right_out ; +wire [0:29] sb_1__1__119_chany_bottom_out ; +wire [0:29] sb_1__1__119_chany_top_out ; +wire [0:0] sb_1__1__11_ccff_tail ; +wire [0:29] sb_1__1__11_chanx_left_out ; +wire [0:29] sb_1__1__11_chanx_right_out ; +wire [0:29] sb_1__1__11_chany_bottom_out ; +wire [0:29] sb_1__1__11_chany_top_out ; +wire [0:0] sb_1__1__120_ccff_tail ; +wire [0:29] sb_1__1__120_chanx_left_out ; +wire [0:29] sb_1__1__120_chanx_right_out ; +wire [0:29] sb_1__1__120_chany_bottom_out ; +wire [0:29] sb_1__1__120_chany_top_out ; +wire [0:0] sb_1__1__12_ccff_tail ; +wire [0:29] sb_1__1__12_chanx_left_out ; +wire [0:29] sb_1__1__12_chanx_right_out ; +wire [0:29] sb_1__1__12_chany_bottom_out ; +wire [0:29] sb_1__1__12_chany_top_out ; +wire [0:0] sb_1__1__13_ccff_tail ; +wire [0:29] sb_1__1__13_chanx_left_out ; +wire [0:29] sb_1__1__13_chanx_right_out ; +wire [0:29] sb_1__1__13_chany_bottom_out ; +wire [0:29] sb_1__1__13_chany_top_out ; +wire [0:0] sb_1__1__14_ccff_tail ; +wire [0:29] sb_1__1__14_chanx_left_out ; +wire [0:29] sb_1__1__14_chanx_right_out ; +wire [0:29] sb_1__1__14_chany_bottom_out ; +wire [0:29] sb_1__1__14_chany_top_out ; +wire [0:0] sb_1__1__15_ccff_tail ; +wire [0:29] sb_1__1__15_chanx_left_out ; +wire [0:29] sb_1__1__15_chanx_right_out ; +wire [0:29] sb_1__1__15_chany_bottom_out ; +wire [0:29] sb_1__1__15_chany_top_out ; +wire [0:0] sb_1__1__16_ccff_tail ; +wire [0:29] sb_1__1__16_chanx_left_out ; +wire [0:29] sb_1__1__16_chanx_right_out ; +wire [0:29] sb_1__1__16_chany_bottom_out ; +wire [0:29] sb_1__1__16_chany_top_out ; +wire [0:0] sb_1__1__17_ccff_tail ; +wire [0:29] sb_1__1__17_chanx_left_out ; +wire [0:29] sb_1__1__17_chanx_right_out ; +wire [0:29] sb_1__1__17_chany_bottom_out ; +wire [0:29] sb_1__1__17_chany_top_out ; +wire [0:0] sb_1__1__18_ccff_tail ; +wire [0:29] sb_1__1__18_chanx_left_out ; +wire [0:29] sb_1__1__18_chanx_right_out ; +wire [0:29] sb_1__1__18_chany_bottom_out ; +wire [0:29] sb_1__1__18_chany_top_out ; +wire [0:0] sb_1__1__19_ccff_tail ; +wire [0:29] sb_1__1__19_chanx_left_out ; +wire [0:29] sb_1__1__19_chanx_right_out ; +wire [0:29] sb_1__1__19_chany_bottom_out ; +wire [0:29] sb_1__1__19_chany_top_out ; +wire [0:0] sb_1__1__1_ccff_tail ; +wire [0:29] sb_1__1__1_chanx_left_out ; +wire [0:29] sb_1__1__1_chanx_right_out ; +wire [0:29] sb_1__1__1_chany_bottom_out ; +wire [0:29] sb_1__1__1_chany_top_out ; +wire [0:0] sb_1__1__20_ccff_tail ; +wire [0:29] sb_1__1__20_chanx_left_out ; +wire [0:29] sb_1__1__20_chanx_right_out ; +wire [0:29] sb_1__1__20_chany_bottom_out ; +wire [0:29] sb_1__1__20_chany_top_out ; +wire [0:0] sb_1__1__21_ccff_tail ; +wire [0:29] sb_1__1__21_chanx_left_out ; +wire [0:29] sb_1__1__21_chanx_right_out ; +wire [0:29] sb_1__1__21_chany_bottom_out ; +wire [0:29] sb_1__1__21_chany_top_out ; +wire [0:0] sb_1__1__22_ccff_tail ; +wire [0:29] sb_1__1__22_chanx_left_out ; +wire [0:29] sb_1__1__22_chanx_right_out ; +wire [0:29] sb_1__1__22_chany_bottom_out ; +wire [0:29] sb_1__1__22_chany_top_out ; +wire [0:0] sb_1__1__23_ccff_tail ; +wire [0:29] sb_1__1__23_chanx_left_out ; +wire [0:29] sb_1__1__23_chanx_right_out ; +wire [0:29] sb_1__1__23_chany_bottom_out ; +wire [0:29] sb_1__1__23_chany_top_out ; +wire [0:0] sb_1__1__24_ccff_tail ; +wire [0:29] sb_1__1__24_chanx_left_out ; +wire [0:29] sb_1__1__24_chanx_right_out ; +wire [0:29] sb_1__1__24_chany_bottom_out ; +wire [0:29] sb_1__1__24_chany_top_out ; +wire [0:0] sb_1__1__25_ccff_tail ; +wire [0:29] sb_1__1__25_chanx_left_out ; +wire [0:29] sb_1__1__25_chanx_right_out ; +wire [0:29] sb_1__1__25_chany_bottom_out ; +wire [0:29] sb_1__1__25_chany_top_out ; +wire [0:0] sb_1__1__26_ccff_tail ; +wire [0:29] sb_1__1__26_chanx_left_out ; +wire [0:29] sb_1__1__26_chanx_right_out ; +wire [0:29] sb_1__1__26_chany_bottom_out ; +wire [0:29] sb_1__1__26_chany_top_out ; +wire [0:0] sb_1__1__27_ccff_tail ; +wire [0:29] sb_1__1__27_chanx_left_out ; +wire [0:29] sb_1__1__27_chanx_right_out ; +wire [0:29] sb_1__1__27_chany_bottom_out ; +wire [0:29] sb_1__1__27_chany_top_out ; +wire [0:0] sb_1__1__28_ccff_tail ; +wire [0:29] sb_1__1__28_chanx_left_out ; +wire [0:29] sb_1__1__28_chanx_right_out ; +wire [0:29] sb_1__1__28_chany_bottom_out ; +wire [0:29] sb_1__1__28_chany_top_out ; +wire [0:0] sb_1__1__29_ccff_tail ; +wire [0:29] sb_1__1__29_chanx_left_out ; +wire [0:29] sb_1__1__29_chanx_right_out ; +wire [0:29] sb_1__1__29_chany_bottom_out ; +wire [0:29] sb_1__1__29_chany_top_out ; +wire [0:0] sb_1__1__2_ccff_tail ; +wire [0:29] sb_1__1__2_chanx_left_out ; +wire [0:29] sb_1__1__2_chanx_right_out ; +wire [0:29] sb_1__1__2_chany_bottom_out ; +wire [0:29] sb_1__1__2_chany_top_out ; +wire [0:0] sb_1__1__30_ccff_tail ; +wire [0:29] sb_1__1__30_chanx_left_out ; +wire [0:29] sb_1__1__30_chanx_right_out ; +wire [0:29] sb_1__1__30_chany_bottom_out ; +wire [0:29] sb_1__1__30_chany_top_out ; +wire [0:0] sb_1__1__31_ccff_tail ; +wire [0:29] sb_1__1__31_chanx_left_out ; +wire [0:29] sb_1__1__31_chanx_right_out ; +wire [0:29] sb_1__1__31_chany_bottom_out ; +wire [0:29] sb_1__1__31_chany_top_out ; +wire [0:0] sb_1__1__32_ccff_tail ; +wire [0:29] sb_1__1__32_chanx_left_out ; +wire [0:29] sb_1__1__32_chanx_right_out ; +wire [0:29] sb_1__1__32_chany_bottom_out ; +wire [0:29] sb_1__1__32_chany_top_out ; +wire [0:0] sb_1__1__33_ccff_tail ; +wire [0:29] sb_1__1__33_chanx_left_out ; +wire [0:29] sb_1__1__33_chanx_right_out ; +wire [0:29] sb_1__1__33_chany_bottom_out ; +wire [0:29] sb_1__1__33_chany_top_out ; +wire [0:0] sb_1__1__34_ccff_tail ; +wire [0:29] sb_1__1__34_chanx_left_out ; +wire [0:29] sb_1__1__34_chanx_right_out ; +wire [0:29] sb_1__1__34_chany_bottom_out ; +wire [0:29] sb_1__1__34_chany_top_out ; +wire [0:0] sb_1__1__35_ccff_tail ; +wire [0:29] sb_1__1__35_chanx_left_out ; +wire [0:29] sb_1__1__35_chanx_right_out ; +wire [0:29] sb_1__1__35_chany_bottom_out ; +wire [0:29] sb_1__1__35_chany_top_out ; +wire [0:0] sb_1__1__36_ccff_tail ; +wire [0:29] sb_1__1__36_chanx_left_out ; +wire [0:29] sb_1__1__36_chanx_right_out ; +wire [0:29] sb_1__1__36_chany_bottom_out ; +wire [0:29] sb_1__1__36_chany_top_out ; +wire [0:0] sb_1__1__37_ccff_tail ; +wire [0:29] sb_1__1__37_chanx_left_out ; +wire [0:29] sb_1__1__37_chanx_right_out ; +wire [0:29] sb_1__1__37_chany_bottom_out ; +wire [0:29] sb_1__1__37_chany_top_out ; +wire [0:0] sb_1__1__38_ccff_tail ; +wire [0:29] sb_1__1__38_chanx_left_out ; +wire [0:29] sb_1__1__38_chanx_right_out ; +wire [0:29] sb_1__1__38_chany_bottom_out ; +wire [0:29] sb_1__1__38_chany_top_out ; +wire [0:0] sb_1__1__39_ccff_tail ; +wire [0:29] sb_1__1__39_chanx_left_out ; +wire [0:29] sb_1__1__39_chanx_right_out ; +wire [0:29] sb_1__1__39_chany_bottom_out ; +wire [0:29] sb_1__1__39_chany_top_out ; +wire [0:0] sb_1__1__3_ccff_tail ; +wire [0:29] sb_1__1__3_chanx_left_out ; +wire [0:29] sb_1__1__3_chanx_right_out ; +wire [0:29] sb_1__1__3_chany_bottom_out ; +wire [0:29] sb_1__1__3_chany_top_out ; +wire [0:0] sb_1__1__40_ccff_tail ; +wire [0:29] sb_1__1__40_chanx_left_out ; +wire [0:29] sb_1__1__40_chanx_right_out ; +wire [0:29] sb_1__1__40_chany_bottom_out ; +wire [0:29] sb_1__1__40_chany_top_out ; +wire [0:0] sb_1__1__41_ccff_tail ; +wire [0:29] sb_1__1__41_chanx_left_out ; +wire [0:29] sb_1__1__41_chanx_right_out ; +wire [0:29] sb_1__1__41_chany_bottom_out ; +wire [0:29] sb_1__1__41_chany_top_out ; +wire [0:0] sb_1__1__42_ccff_tail ; +wire [0:29] sb_1__1__42_chanx_left_out ; +wire [0:29] sb_1__1__42_chanx_right_out ; +wire [0:29] sb_1__1__42_chany_bottom_out ; +wire [0:29] sb_1__1__42_chany_top_out ; +wire [0:0] sb_1__1__43_ccff_tail ; +wire [0:29] sb_1__1__43_chanx_left_out ; +wire [0:29] sb_1__1__43_chanx_right_out ; +wire [0:29] sb_1__1__43_chany_bottom_out ; +wire [0:29] sb_1__1__43_chany_top_out ; +wire [0:0] sb_1__1__44_ccff_tail ; +wire [0:29] sb_1__1__44_chanx_left_out ; +wire [0:29] sb_1__1__44_chanx_right_out ; +wire [0:29] sb_1__1__44_chany_bottom_out ; +wire [0:29] sb_1__1__44_chany_top_out ; +wire [0:0] sb_1__1__45_ccff_tail ; +wire [0:29] sb_1__1__45_chanx_left_out ; +wire [0:29] sb_1__1__45_chanx_right_out ; +wire [0:29] sb_1__1__45_chany_bottom_out ; +wire [0:29] sb_1__1__45_chany_top_out ; +wire [0:0] sb_1__1__46_ccff_tail ; +wire [0:29] sb_1__1__46_chanx_left_out ; +wire [0:29] sb_1__1__46_chanx_right_out ; +wire [0:29] sb_1__1__46_chany_bottom_out ; +wire [0:29] sb_1__1__46_chany_top_out ; +wire [0:0] sb_1__1__47_ccff_tail ; +wire [0:29] sb_1__1__47_chanx_left_out ; +wire [0:29] sb_1__1__47_chanx_right_out ; +wire [0:29] sb_1__1__47_chany_bottom_out ; +wire [0:29] sb_1__1__47_chany_top_out ; +wire [0:0] sb_1__1__48_ccff_tail ; +wire [0:29] sb_1__1__48_chanx_left_out ; +wire [0:29] sb_1__1__48_chanx_right_out ; +wire [0:29] sb_1__1__48_chany_bottom_out ; +wire [0:29] sb_1__1__48_chany_top_out ; +wire [0:0] sb_1__1__49_ccff_tail ; +wire [0:29] sb_1__1__49_chanx_left_out ; +wire [0:29] sb_1__1__49_chanx_right_out ; +wire [0:29] sb_1__1__49_chany_bottom_out ; +wire [0:29] sb_1__1__49_chany_top_out ; +wire [0:0] sb_1__1__4_ccff_tail ; +wire [0:29] sb_1__1__4_chanx_left_out ; +wire [0:29] sb_1__1__4_chanx_right_out ; +wire [0:29] sb_1__1__4_chany_bottom_out ; +wire [0:29] sb_1__1__4_chany_top_out ; +wire [0:0] sb_1__1__50_ccff_tail ; +wire [0:29] sb_1__1__50_chanx_left_out ; +wire [0:29] sb_1__1__50_chanx_right_out ; +wire [0:29] sb_1__1__50_chany_bottom_out ; +wire [0:29] sb_1__1__50_chany_top_out ; +wire [0:0] sb_1__1__51_ccff_tail ; +wire [0:29] sb_1__1__51_chanx_left_out ; +wire [0:29] sb_1__1__51_chanx_right_out ; +wire [0:29] sb_1__1__51_chany_bottom_out ; +wire [0:29] sb_1__1__51_chany_top_out ; +wire [0:0] sb_1__1__52_ccff_tail ; +wire [0:29] sb_1__1__52_chanx_left_out ; +wire [0:29] sb_1__1__52_chanx_right_out ; +wire [0:29] sb_1__1__52_chany_bottom_out ; +wire [0:29] sb_1__1__52_chany_top_out ; +wire [0:0] sb_1__1__53_ccff_tail ; +wire [0:29] sb_1__1__53_chanx_left_out ; +wire [0:29] sb_1__1__53_chanx_right_out ; +wire [0:29] sb_1__1__53_chany_bottom_out ; +wire [0:29] sb_1__1__53_chany_top_out ; +wire [0:0] sb_1__1__54_ccff_tail ; +wire [0:29] sb_1__1__54_chanx_left_out ; +wire [0:29] sb_1__1__54_chanx_right_out ; +wire [0:29] sb_1__1__54_chany_bottom_out ; +wire [0:29] sb_1__1__54_chany_top_out ; +wire [0:0] sb_1__1__55_ccff_tail ; +wire [0:29] sb_1__1__55_chanx_left_out ; +wire [0:29] sb_1__1__55_chanx_right_out ; +wire [0:29] sb_1__1__55_chany_bottom_out ; +wire [0:29] sb_1__1__55_chany_top_out ; +wire [0:0] sb_1__1__56_ccff_tail ; +wire [0:29] sb_1__1__56_chanx_left_out ; +wire [0:29] sb_1__1__56_chanx_right_out ; +wire [0:29] sb_1__1__56_chany_bottom_out ; +wire [0:29] sb_1__1__56_chany_top_out ; +wire [0:0] sb_1__1__57_ccff_tail ; +wire [0:29] sb_1__1__57_chanx_left_out ; +wire [0:29] sb_1__1__57_chanx_right_out ; +wire [0:29] sb_1__1__57_chany_bottom_out ; +wire [0:29] sb_1__1__57_chany_top_out ; +wire [0:0] sb_1__1__58_ccff_tail ; +wire [0:29] sb_1__1__58_chanx_left_out ; +wire [0:29] sb_1__1__58_chanx_right_out ; +wire [0:29] sb_1__1__58_chany_bottom_out ; +wire [0:29] sb_1__1__58_chany_top_out ; +wire [0:0] sb_1__1__59_ccff_tail ; +wire [0:29] sb_1__1__59_chanx_left_out ; +wire [0:29] sb_1__1__59_chanx_right_out ; +wire [0:29] sb_1__1__59_chany_bottom_out ; +wire [0:29] sb_1__1__59_chany_top_out ; +wire [0:0] sb_1__1__5_ccff_tail ; +wire [0:29] sb_1__1__5_chanx_left_out ; +wire [0:29] sb_1__1__5_chanx_right_out ; +wire [0:29] sb_1__1__5_chany_bottom_out ; +wire [0:29] sb_1__1__5_chany_top_out ; +wire [0:0] sb_1__1__60_ccff_tail ; +wire [0:29] sb_1__1__60_chanx_left_out ; +wire [0:29] sb_1__1__60_chanx_right_out ; +wire [0:29] sb_1__1__60_chany_bottom_out ; +wire [0:29] sb_1__1__60_chany_top_out ; +wire [0:0] sb_1__1__61_ccff_tail ; +wire [0:29] sb_1__1__61_chanx_left_out ; +wire [0:29] sb_1__1__61_chanx_right_out ; +wire [0:29] sb_1__1__61_chany_bottom_out ; +wire [0:29] sb_1__1__61_chany_top_out ; +wire [0:0] sb_1__1__62_ccff_tail ; +wire [0:29] sb_1__1__62_chanx_left_out ; +wire [0:29] sb_1__1__62_chanx_right_out ; +wire [0:29] sb_1__1__62_chany_bottom_out ; +wire [0:29] sb_1__1__62_chany_top_out ; +wire [0:0] sb_1__1__63_ccff_tail ; +wire [0:29] sb_1__1__63_chanx_left_out ; +wire [0:29] sb_1__1__63_chanx_right_out ; +wire [0:29] sb_1__1__63_chany_bottom_out ; +wire [0:29] sb_1__1__63_chany_top_out ; +wire [0:0] sb_1__1__64_ccff_tail ; +wire [0:29] sb_1__1__64_chanx_left_out ; +wire [0:29] sb_1__1__64_chanx_right_out ; +wire [0:29] sb_1__1__64_chany_bottom_out ; +wire [0:29] sb_1__1__64_chany_top_out ; +wire [0:0] sb_1__1__65_ccff_tail ; +wire [0:29] sb_1__1__65_chanx_left_out ; +wire [0:29] sb_1__1__65_chanx_right_out ; +wire [0:29] sb_1__1__65_chany_bottom_out ; +wire [0:29] sb_1__1__65_chany_top_out ; +wire [0:0] sb_1__1__66_ccff_tail ; +wire [0:29] sb_1__1__66_chanx_left_out ; +wire [0:29] sb_1__1__66_chanx_right_out ; +wire [0:29] sb_1__1__66_chany_bottom_out ; +wire [0:29] sb_1__1__66_chany_top_out ; +wire [0:0] sb_1__1__67_ccff_tail ; +wire [0:29] sb_1__1__67_chanx_left_out ; +wire [0:29] sb_1__1__67_chanx_right_out ; +wire [0:29] sb_1__1__67_chany_bottom_out ; +wire [0:29] sb_1__1__67_chany_top_out ; +wire [0:0] sb_1__1__68_ccff_tail ; +wire [0:29] sb_1__1__68_chanx_left_out ; +wire [0:29] sb_1__1__68_chanx_right_out ; +wire [0:29] sb_1__1__68_chany_bottom_out ; +wire [0:29] sb_1__1__68_chany_top_out ; +wire [0:0] sb_1__1__69_ccff_tail ; +wire [0:29] sb_1__1__69_chanx_left_out ; +wire [0:29] sb_1__1__69_chanx_right_out ; +wire [0:29] sb_1__1__69_chany_bottom_out ; +wire [0:29] sb_1__1__69_chany_top_out ; +wire [0:0] sb_1__1__6_ccff_tail ; +wire [0:29] sb_1__1__6_chanx_left_out ; +wire [0:29] sb_1__1__6_chanx_right_out ; +wire [0:29] sb_1__1__6_chany_bottom_out ; +wire [0:29] sb_1__1__6_chany_top_out ; +wire [0:0] sb_1__1__70_ccff_tail ; +wire [0:29] sb_1__1__70_chanx_left_out ; +wire [0:29] sb_1__1__70_chanx_right_out ; +wire [0:29] sb_1__1__70_chany_bottom_out ; +wire [0:29] sb_1__1__70_chany_top_out ; +wire [0:0] sb_1__1__71_ccff_tail ; +wire [0:29] sb_1__1__71_chanx_left_out ; +wire [0:29] sb_1__1__71_chanx_right_out ; +wire [0:29] sb_1__1__71_chany_bottom_out ; +wire [0:29] sb_1__1__71_chany_top_out ; +wire [0:0] sb_1__1__72_ccff_tail ; +wire [0:29] sb_1__1__72_chanx_left_out ; +wire [0:29] sb_1__1__72_chanx_right_out ; +wire [0:29] sb_1__1__72_chany_bottom_out ; +wire [0:29] sb_1__1__72_chany_top_out ; +wire [0:0] sb_1__1__73_ccff_tail ; +wire [0:29] sb_1__1__73_chanx_left_out ; +wire [0:29] sb_1__1__73_chanx_right_out ; +wire [0:29] sb_1__1__73_chany_bottom_out ; +wire [0:29] sb_1__1__73_chany_top_out ; +wire [0:0] sb_1__1__74_ccff_tail ; +wire [0:29] sb_1__1__74_chanx_left_out ; +wire [0:29] sb_1__1__74_chanx_right_out ; +wire [0:29] sb_1__1__74_chany_bottom_out ; +wire [0:29] sb_1__1__74_chany_top_out ; +wire [0:0] sb_1__1__75_ccff_tail ; +wire [0:29] sb_1__1__75_chanx_left_out ; +wire [0:29] sb_1__1__75_chanx_right_out ; +wire [0:29] sb_1__1__75_chany_bottom_out ; +wire [0:29] sb_1__1__75_chany_top_out ; +wire [0:0] sb_1__1__76_ccff_tail ; +wire [0:29] sb_1__1__76_chanx_left_out ; +wire [0:29] sb_1__1__76_chanx_right_out ; +wire [0:29] sb_1__1__76_chany_bottom_out ; +wire [0:29] sb_1__1__76_chany_top_out ; +wire [0:0] sb_1__1__77_ccff_tail ; +wire [0:29] sb_1__1__77_chanx_left_out ; +wire [0:29] sb_1__1__77_chanx_right_out ; +wire [0:29] sb_1__1__77_chany_bottom_out ; +wire [0:29] sb_1__1__77_chany_top_out ; +wire [0:0] sb_1__1__78_ccff_tail ; +wire [0:29] sb_1__1__78_chanx_left_out ; +wire [0:29] sb_1__1__78_chanx_right_out ; +wire [0:29] sb_1__1__78_chany_bottom_out ; +wire [0:29] sb_1__1__78_chany_top_out ; +wire [0:0] sb_1__1__79_ccff_tail ; +wire [0:29] sb_1__1__79_chanx_left_out ; +wire [0:29] sb_1__1__79_chanx_right_out ; +wire [0:29] sb_1__1__79_chany_bottom_out ; +wire [0:29] sb_1__1__79_chany_top_out ; +wire [0:0] sb_1__1__7_ccff_tail ; +wire [0:29] sb_1__1__7_chanx_left_out ; +wire [0:29] sb_1__1__7_chanx_right_out ; +wire [0:29] sb_1__1__7_chany_bottom_out ; +wire [0:29] sb_1__1__7_chany_top_out ; +wire [0:0] sb_1__1__80_ccff_tail ; +wire [0:29] sb_1__1__80_chanx_left_out ; +wire [0:29] sb_1__1__80_chanx_right_out ; +wire [0:29] sb_1__1__80_chany_bottom_out ; +wire [0:29] sb_1__1__80_chany_top_out ; +wire [0:0] sb_1__1__81_ccff_tail ; +wire [0:29] sb_1__1__81_chanx_left_out ; +wire [0:29] sb_1__1__81_chanx_right_out ; +wire [0:29] sb_1__1__81_chany_bottom_out ; +wire [0:29] sb_1__1__81_chany_top_out ; +wire [0:0] sb_1__1__82_ccff_tail ; +wire [0:29] sb_1__1__82_chanx_left_out ; +wire [0:29] sb_1__1__82_chanx_right_out ; +wire [0:29] sb_1__1__82_chany_bottom_out ; +wire [0:29] sb_1__1__82_chany_top_out ; +wire [0:0] sb_1__1__83_ccff_tail ; +wire [0:29] sb_1__1__83_chanx_left_out ; +wire [0:29] sb_1__1__83_chanx_right_out ; +wire [0:29] sb_1__1__83_chany_bottom_out ; +wire [0:29] sb_1__1__83_chany_top_out ; +wire [0:0] sb_1__1__84_ccff_tail ; +wire [0:29] sb_1__1__84_chanx_left_out ; +wire [0:29] sb_1__1__84_chanx_right_out ; +wire [0:29] sb_1__1__84_chany_bottom_out ; +wire [0:29] sb_1__1__84_chany_top_out ; +wire [0:0] sb_1__1__85_ccff_tail ; +wire [0:29] sb_1__1__85_chanx_left_out ; +wire [0:29] sb_1__1__85_chanx_right_out ; +wire [0:29] sb_1__1__85_chany_bottom_out ; +wire [0:29] sb_1__1__85_chany_top_out ; +wire [0:0] sb_1__1__86_ccff_tail ; +wire [0:29] sb_1__1__86_chanx_left_out ; +wire [0:29] sb_1__1__86_chanx_right_out ; +wire [0:29] sb_1__1__86_chany_bottom_out ; +wire [0:29] sb_1__1__86_chany_top_out ; +wire [0:0] sb_1__1__87_ccff_tail ; +wire [0:29] sb_1__1__87_chanx_left_out ; +wire [0:29] sb_1__1__87_chanx_right_out ; +wire [0:29] sb_1__1__87_chany_bottom_out ; +wire [0:29] sb_1__1__87_chany_top_out ; +wire [0:0] sb_1__1__88_ccff_tail ; +wire [0:29] sb_1__1__88_chanx_left_out ; +wire [0:29] sb_1__1__88_chanx_right_out ; +wire [0:29] sb_1__1__88_chany_bottom_out ; +wire [0:29] sb_1__1__88_chany_top_out ; +wire [0:0] sb_1__1__89_ccff_tail ; +wire [0:29] sb_1__1__89_chanx_left_out ; +wire [0:29] sb_1__1__89_chanx_right_out ; +wire [0:29] sb_1__1__89_chany_bottom_out ; +wire [0:29] sb_1__1__89_chany_top_out ; +wire [0:0] sb_1__1__8_ccff_tail ; +wire [0:29] sb_1__1__8_chanx_left_out ; +wire [0:29] sb_1__1__8_chanx_right_out ; +wire [0:29] sb_1__1__8_chany_bottom_out ; +wire [0:29] sb_1__1__8_chany_top_out ; +wire [0:0] sb_1__1__90_ccff_tail ; +wire [0:29] sb_1__1__90_chanx_left_out ; +wire [0:29] sb_1__1__90_chanx_right_out ; +wire [0:29] sb_1__1__90_chany_bottom_out ; +wire [0:29] sb_1__1__90_chany_top_out ; +wire [0:0] sb_1__1__91_ccff_tail ; +wire [0:29] sb_1__1__91_chanx_left_out ; +wire [0:29] sb_1__1__91_chanx_right_out ; +wire [0:29] sb_1__1__91_chany_bottom_out ; +wire [0:29] sb_1__1__91_chany_top_out ; +wire [0:0] sb_1__1__92_ccff_tail ; +wire [0:29] sb_1__1__92_chanx_left_out ; +wire [0:29] sb_1__1__92_chanx_right_out ; +wire [0:29] sb_1__1__92_chany_bottom_out ; +wire [0:29] sb_1__1__92_chany_top_out ; +wire [0:0] sb_1__1__93_ccff_tail ; +wire [0:29] sb_1__1__93_chanx_left_out ; +wire [0:29] sb_1__1__93_chanx_right_out ; +wire [0:29] sb_1__1__93_chany_bottom_out ; +wire [0:29] sb_1__1__93_chany_top_out ; +wire [0:0] sb_1__1__94_ccff_tail ; +wire [0:29] sb_1__1__94_chanx_left_out ; +wire [0:29] sb_1__1__94_chanx_right_out ; +wire [0:29] sb_1__1__94_chany_bottom_out ; +wire [0:29] sb_1__1__94_chany_top_out ; +wire [0:0] sb_1__1__95_ccff_tail ; +wire [0:29] sb_1__1__95_chanx_left_out ; +wire [0:29] sb_1__1__95_chanx_right_out ; +wire [0:29] sb_1__1__95_chany_bottom_out ; +wire [0:29] sb_1__1__95_chany_top_out ; +wire [0:0] sb_1__1__96_ccff_tail ; +wire [0:29] sb_1__1__96_chanx_left_out ; +wire [0:29] sb_1__1__96_chanx_right_out ; +wire [0:29] sb_1__1__96_chany_bottom_out ; +wire [0:29] sb_1__1__96_chany_top_out ; +wire [0:0] sb_1__1__97_ccff_tail ; +wire [0:29] sb_1__1__97_chanx_left_out ; +wire [0:29] sb_1__1__97_chanx_right_out ; +wire [0:29] sb_1__1__97_chany_bottom_out ; +wire [0:29] sb_1__1__97_chany_top_out ; +wire [0:0] sb_1__1__98_ccff_tail ; +wire [0:29] sb_1__1__98_chanx_left_out ; +wire [0:29] sb_1__1__98_chanx_right_out ; +wire [0:29] sb_1__1__98_chany_bottom_out ; +wire [0:29] sb_1__1__98_chany_top_out ; +wire [0:0] sb_1__1__99_ccff_tail ; +wire [0:29] sb_1__1__99_chanx_left_out ; +wire [0:29] sb_1__1__99_chanx_right_out ; +wire [0:29] sb_1__1__99_chany_bottom_out ; +wire [0:29] sb_1__1__99_chany_top_out ; +wire [0:0] sb_1__1__9_ccff_tail ; +wire [0:29] sb_1__1__9_chanx_left_out ; +wire [0:29] sb_1__1__9_chanx_right_out ; +wire [0:29] sb_1__1__9_chany_bottom_out ; +wire [0:29] sb_1__1__9_chany_top_out ; +wire [1:0] UNCONN ; +wire [317:0] scff_Wires ; +wire [132:0] regin_feedthrough_wires ; +wire [132:0] regout_feedthrough_wires ; +wire [132:0] cin_feedthrough_wires ; +wire [132:0] cout_feedthrough_wires ; +wire [287:0] Test_enWires ; +wire [636:0] pResetWires ; +wire [287:0] ResetWires ; +wire [624:0] prog_clk_0_wires ; +wire [251:0] prog_clk_1_wires ; +wire [135:0] prog_clk_2_wires ; +wire [100:0] prog_clk_3_wires ; +wire [251:0] clk_1_wires ; +wire [135:0] clk_2_wires ; +wire [100:0] clk_3_wires ; + +grid_clb grid_clb_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[0] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[0] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_3 } ) , + .ccff_head ( grid_io_left_0_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_0_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_0_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_0_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_0_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_0_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_0_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_0_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_0_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_4 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_1__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[23] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_5 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6 ) , .SC_OUT_BOT ( scff_Wires[25] ) , + .Test_en_E_in ( Test_enWires[24] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_8 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_9 ) , + .pReset_N_in ( pResetWires[63] ) , .Reset_E_in ( ResetWires[24] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_10 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_11 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_12 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[4] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_13 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[0] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[1] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[3] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_14 ) , + .clk_0_N_in ( clk_1_wires[4] ) , .clk_0_S_in ( SYNOPSYS_UNCONNECTED_15 ) ) ; +grid_clb grid_clb_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_16 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[1] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_17 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[1] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_18 } ) , + .ccff_head ( grid_io_left_1_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_1_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_1_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_1_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_1_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_1_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_1_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_1_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_1_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[0] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_19 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[0] ) , + .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[21] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_20 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_OUT_BOT ( scff_Wires[22] ) , + .Test_en_E_in ( Test_enWires[46] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_22 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_23 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_24 ) , + .pReset_N_in ( pResetWires[112] ) , .Reset_E_in ( ResetWires[46] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_25 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_26 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_27 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_28 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[3] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[6] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[7] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[9] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_29 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_30 ) , .clk_0_S_in ( clk_1_wires[3] ) ) ; +grid_clb grid_clb_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_31 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[2] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_32 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[2] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_33 } ) , + .ccff_head ( grid_io_left_2_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_2_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_2_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_2_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_2_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_2_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_2_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_2_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_2_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[1] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_34 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[1] ) , + .ccff_tail ( grid_clb_2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[19] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_35 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_36 ) , .SC_OUT_BOT ( scff_Wires[20] ) , + .Test_en_E_in ( Test_enWires[68] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_37 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_38 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_39 ) , + .pReset_N_in ( pResetWires[161] ) , .Reset_E_in ( ResetWires[68] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_40 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_41 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_42 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[11] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_43 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[11] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[12] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[14] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_44 ) , + .clk_0_N_in ( clk_1_wires[11] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_45 ) ) ; +grid_clb grid_clb_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_46 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[3] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_47 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[3] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_48 } ) , + .ccff_head ( grid_io_left_3_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_3_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_3_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_3_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_3_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_3_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_3_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_3_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_3_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[2] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_49 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[2] ) , + .ccff_tail ( grid_clb_3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[17] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_50 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_51 ) , .SC_OUT_BOT ( scff_Wires[18] ) , + .Test_en_E_in ( Test_enWires[90] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_52 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_53 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_54 ) , + .pReset_N_in ( pResetWires[210] ) , .Reset_E_in ( ResetWires[90] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_55 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_56 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_57 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_58 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[10] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[16] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[17] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[19] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_59 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_60 ) , + .clk_0_S_in ( clk_1_wires[10] ) ) ; +grid_clb grid_clb_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_61 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[4] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_62 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[4] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_63 } ) , + .ccff_head ( grid_io_left_4_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_4_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_4_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_4_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_4_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_4_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_4_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_4_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_4_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[3] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_64 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[3] ) , + .ccff_tail ( grid_clb_4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[15] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_65 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_66 ) , .SC_OUT_BOT ( scff_Wires[16] ) , + .Test_en_E_in ( Test_enWires[112] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_67 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_68 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_69 ) , + .pReset_N_in ( pResetWires[259] ) , .Reset_E_in ( ResetWires[112] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_70 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_71 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_72 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[18] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_73 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[21] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[22] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[24] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_74 ) , + .clk_0_N_in ( clk_1_wires[18] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_75 ) ) ; +grid_clb grid_clb_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_76 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[5] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_77 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[5] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_78 } ) , + .ccff_head ( grid_io_left_5_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_5_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_5_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_5_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_5_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_5_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_5_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_5_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_5_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[4] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_79 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[4] ) , + .ccff_tail ( grid_clb_5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[13] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_80 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_81 ) , .SC_OUT_BOT ( scff_Wires[14] ) , + .Test_en_E_in ( Test_enWires[134] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_82 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_83 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_84 ) , + .pReset_N_in ( pResetWires[308] ) , .Reset_E_in ( ResetWires[134] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_85 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_86 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_87 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_88 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[17] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[26] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[27] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[29] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_89 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_90 ) , + .clk_0_S_in ( clk_1_wires[17] ) ) ; +grid_clb grid_clb_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_91 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[6] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_92 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[6] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_93 } ) , + .ccff_head ( grid_io_left_6_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_6_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_6_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_6_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_6_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_6_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_6_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_6_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_6_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[5] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_94 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[5] ) , + .ccff_tail ( grid_clb_6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[11] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_95 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_96 ) , .SC_OUT_BOT ( scff_Wires[12] ) , + .Test_en_E_in ( Test_enWires[156] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_97 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_98 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_99 ) , + .pReset_N_in ( pResetWires[357] ) , .Reset_E_in ( ResetWires[156] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_100 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_101 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_102 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[25] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_103 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[31] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[32] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[34] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_104 ) , + .clk_0_N_in ( clk_1_wires[25] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_105 ) ) ; +grid_clb grid_clb_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_106 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[7] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_107 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[7] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_108 } ) , + .ccff_head ( grid_io_left_7_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_7_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_7_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_7_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_7_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_7_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_7_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_7_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_7_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[6] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_109 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[6] ) , + .ccff_tail ( grid_clb_7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[9] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_110 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_111 ) , + .SC_OUT_BOT ( scff_Wires[10] ) , .Test_en_E_in ( Test_enWires[178] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_112 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_113 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_114 ) , + .pReset_N_in ( pResetWires[406] ) , .Reset_E_in ( ResetWires[178] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_115 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_116 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_117 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_118 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[24] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[36] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[37] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[39] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_119 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_120 ) , + .clk_0_S_in ( clk_1_wires[24] ) ) ; +grid_clb grid_clb_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_121 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[8] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_122 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[8] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_123 } ) , + .ccff_head ( grid_io_left_8_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_8_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_8_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_8_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_8_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_8_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_8_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_8_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_8_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[7] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_124 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[7] ) , + .ccff_tail ( grid_clb_8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[7] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_125 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_126 ) , .SC_OUT_BOT ( scff_Wires[8] ) , + .Test_en_E_in ( Test_enWires[200] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_127 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_128 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_129 ) , + .pReset_N_in ( pResetWires[455] ) , .Reset_E_in ( ResetWires[200] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_130 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_131 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_132 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[32] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_133 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[41] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[42] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[44] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_134 ) , + .clk_0_N_in ( clk_1_wires[32] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_135 ) ) ; +grid_clb grid_clb_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_136 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[9] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_137 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[9] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_138 } ) , + .ccff_head ( grid_io_left_9_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_9_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_9_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_9_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_9_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_9_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_9_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_9_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_9_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[8] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_139 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[8] ) , + .ccff_tail ( grid_clb_9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[5] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_140 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_141 ) , .SC_OUT_BOT ( scff_Wires[6] ) , + .Test_en_E_in ( Test_enWires[222] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_142 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_143 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_144 ) , + .pReset_N_in ( pResetWires[504] ) , .Reset_E_in ( ResetWires[222] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_145 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_146 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_147 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_148 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[31] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[46] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[47] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[49] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_149 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_150 ) , + .clk_0_S_in ( clk_1_wires[31] ) ) ; +grid_clb grid_clb_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_151 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[10] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_152 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[10] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_153 } ) , + .ccff_head ( grid_io_left_10_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_10_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_10_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_10_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_10_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_10_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_10_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_10_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_10_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[9] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_154 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[9] ) , + .ccff_tail ( grid_clb_10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[3] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_155 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_156 ) , .SC_OUT_BOT ( scff_Wires[4] ) , + .Test_en_E_in ( Test_enWires[244] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_157 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_158 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_159 ) , + .pReset_N_in ( pResetWires[553] ) , .Reset_E_in ( ResetWires[244] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_160 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_161 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_162 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[39] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_163 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[51] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[52] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[54] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_164 ) , + .clk_0_N_in ( clk_1_wires[39] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_165 ) ) ; +grid_clb grid_clb_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_166 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_167 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_1__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_168 } ) , + .ccff_head ( grid_io_left_11_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_11_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_11_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_11_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_11_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_11_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_11_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_11_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_11_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[10] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_169 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[10] ) , + .ccff_tail ( grid_clb_11_ccff_tail ) , .SC_IN_TOP ( scff_Wires[1] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_170 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_171 ) , .SC_OUT_BOT ( scff_Wires[2] ) , + .Test_en_E_in ( Test_enWires[266] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_172 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_173 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_174 ) , + .pReset_N_in ( pResetWires[602] ) , .Reset_E_in ( ResetWires[266] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_175 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_176 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_177 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_178 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[38] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[56] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[57] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[61] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[59] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_179 ) , + .clk_0_S_in ( clk_1_wires[38] ) ) ; +grid_clb grid_clb_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_180 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[11] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_181 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[11] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_182 } ) , + .ccff_head ( cby_1__1__0_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_12_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_12_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_12_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_12_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_12_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_12_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_12_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_12_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_183 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_12_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_184 ) , .SC_IN_BOT ( scff_Wires[28] ) , + .SC_OUT_TOP ( scff_Wires[29] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_185 ) , + .Test_en_E_in ( Test_enWires[25] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_186 ) , + .Test_en_W_out ( Test_enWires[26] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_187 ) , + .pReset_N_in ( pResetWires[68] ) , .Reset_E_in ( ResetWires[25] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_188 ) , + .Reset_W_out ( ResetWires[26] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_189 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[6] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_190 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[63] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[64] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_191 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_192 ) , + .clk_0_N_in ( clk_1_wires[6] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_193 ) ) ; +grid_clb grid_clb_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_194 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[12] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_195 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[12] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_196 } ) , + .ccff_head ( cby_1__1__1_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_13_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_13_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_13_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_13_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_13_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_13_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_13_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_13_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[11] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_197 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[11] ) , + .ccff_tail ( grid_clb_13_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_198 ) , .SC_IN_BOT ( scff_Wires[30] ) , + .SC_OUT_TOP ( scff_Wires[31] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_199 ) , + .Test_en_E_in ( Test_enWires[47] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_200 ) , + .Test_en_W_out ( Test_enWires[48] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_201 ) , + .pReset_N_in ( pResetWires[117] ) , .Reset_E_in ( ResetWires[47] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_202 ) , + .Reset_W_out ( ResetWires[48] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_203 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_204 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[5] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[66] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[67] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_205 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_206 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_207 ) , + .clk_0_S_in ( clk_1_wires[5] ) ) ; +grid_clb grid_clb_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_208 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[13] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_209 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[13] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_210 } ) , + .ccff_head ( cby_1__1__2_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_14_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_14_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_14_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_14_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_14_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_14_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_14_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_14_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[12] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_211 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[12] ) , + .ccff_tail ( grid_clb_14_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_212 ) , .SC_IN_BOT ( scff_Wires[32] ) , + .SC_OUT_TOP ( scff_Wires[33] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_213 ) , + .Test_en_E_in ( Test_enWires[69] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_214 ) , + .Test_en_W_out ( Test_enWires[70] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_215 ) , + .pReset_N_in ( pResetWires[166] ) , .Reset_E_in ( ResetWires[69] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_216 ) , + .Reset_W_out ( ResetWires[70] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_217 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[13] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_218 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[69] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[70] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_219 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_220 ) , + .clk_0_N_in ( clk_1_wires[13] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_221 ) ) ; +grid_clb grid_clb_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_222 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[14] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_223 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[14] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_224 } ) , + .ccff_head ( cby_1__1__3_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_15_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_15_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_15_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_15_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_15_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_15_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_15_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_15_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[13] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_225 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[13] ) , + .ccff_tail ( grid_clb_15_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_226 ) , .SC_IN_BOT ( scff_Wires[34] ) , + .SC_OUT_TOP ( scff_Wires[35] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_227 ) , + .Test_en_E_in ( Test_enWires[91] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_228 ) , + .Test_en_W_out ( Test_enWires[92] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_229 ) , + .pReset_N_in ( pResetWires[215] ) , .Reset_E_in ( ResetWires[91] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_230 ) , + .Reset_W_out ( ResetWires[92] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_231 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_232 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[12] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[72] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[73] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_233 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_234 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_235 ) , + .clk_0_S_in ( clk_1_wires[12] ) ) ; +grid_clb grid_clb_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_236 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[15] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_237 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[15] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_238 } ) , + .ccff_head ( cby_1__1__4_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_16_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_16_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_16_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_16_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_16_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_16_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_16_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_16_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[14] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_239 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[14] ) , + .ccff_tail ( grid_clb_16_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_240 ) , .SC_IN_BOT ( scff_Wires[36] ) , + .SC_OUT_TOP ( scff_Wires[37] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_241 ) , + .Test_en_E_in ( Test_enWires[113] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_242 ) , + .Test_en_W_out ( Test_enWires[114] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_243 ) , + .pReset_N_in ( pResetWires[264] ) , .Reset_E_in ( ResetWires[113] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_244 ) , + .Reset_W_out ( ResetWires[114] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_245 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[20] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_246 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[75] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[76] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_247 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_248 ) , + .clk_0_N_in ( clk_1_wires[20] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_249 ) ) ; +grid_clb grid_clb_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_250 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[16] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_251 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[16] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_252 } ) , + .ccff_head ( cby_1__1__5_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_17_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_17_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_17_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_17_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_17_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_17_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_17_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_17_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[15] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_253 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[15] ) , + .ccff_tail ( grid_clb_17_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_254 ) , .SC_IN_BOT ( scff_Wires[38] ) , + .SC_OUT_TOP ( scff_Wires[39] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_255 ) , + .Test_en_E_in ( Test_enWires[135] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_256 ) , + .Test_en_W_out ( Test_enWires[136] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_257 ) , + .pReset_N_in ( pResetWires[313] ) , .Reset_E_in ( ResetWires[135] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_258 ) , + .Reset_W_out ( ResetWires[136] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_259 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_260 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[19] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[78] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[79] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_261 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_262 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_263 ) , + .clk_0_S_in ( clk_1_wires[19] ) ) ; +grid_clb grid_clb_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_264 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[17] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_265 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[17] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_266 } ) , + .ccff_head ( cby_1__1__6_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_18_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_18_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_18_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_18_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_18_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_18_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_18_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_18_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[16] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_267 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[16] ) , + .ccff_tail ( grid_clb_18_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_268 ) , .SC_IN_BOT ( scff_Wires[40] ) , + .SC_OUT_TOP ( scff_Wires[41] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_269 ) , + .Test_en_E_in ( Test_enWires[157] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_270 ) , + .Test_en_W_out ( Test_enWires[158] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_271 ) , + .pReset_N_in ( pResetWires[362] ) , .Reset_E_in ( ResetWires[157] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_272 ) , + .Reset_W_out ( ResetWires[158] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_273 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[27] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_274 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[81] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[82] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_275 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_276 ) , + .clk_0_N_in ( clk_1_wires[27] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_277 ) ) ; +grid_clb grid_clb_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_278 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[18] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_279 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[18] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_280 } ) , + .ccff_head ( cby_1__1__7_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_19_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_19_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_19_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_19_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_19_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_19_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_19_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_19_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[17] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_281 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[17] ) , + .ccff_tail ( grid_clb_19_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_282 ) , .SC_IN_BOT ( scff_Wires[42] ) , + .SC_OUT_TOP ( scff_Wires[43] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_283 ) , + .Test_en_E_in ( Test_enWires[179] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_284 ) , + .Test_en_W_out ( Test_enWires[180] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_285 ) , + .pReset_N_in ( pResetWires[411] ) , .Reset_E_in ( ResetWires[179] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_286 ) , + .Reset_W_out ( ResetWires[180] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_287 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_288 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[26] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[84] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[85] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_289 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_290 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_291 ) , + .clk_0_S_in ( clk_1_wires[26] ) ) ; +grid_clb grid_clb_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_292 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[19] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_293 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[19] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_294 } ) , + .ccff_head ( cby_1__1__8_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_20_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_20_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_20_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_20_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_20_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_20_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_20_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_20_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[18] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_295 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[18] ) , + .ccff_tail ( grid_clb_20_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_296 ) , .SC_IN_BOT ( scff_Wires[44] ) , + .SC_OUT_TOP ( scff_Wires[45] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_297 ) , + .Test_en_E_in ( Test_enWires[201] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_298 ) , + .Test_en_W_out ( Test_enWires[202] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_299 ) , + .pReset_N_in ( pResetWires[460] ) , .Reset_E_in ( ResetWires[201] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_300 ) , + .Reset_W_out ( ResetWires[202] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_301 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[34] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_302 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[87] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[88] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_303 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_304 ) , + .clk_0_N_in ( clk_1_wires[34] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_305 ) ) ; +grid_clb grid_clb_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_306 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[20] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_307 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[20] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_308 } ) , + .ccff_head ( cby_1__1__9_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_21_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_21_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_21_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_21_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_21_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_21_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_21_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_21_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[19] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_309 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[19] ) , + .ccff_tail ( grid_clb_21_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_310 ) , .SC_IN_BOT ( scff_Wires[46] ) , + .SC_OUT_TOP ( scff_Wires[47] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_311 ) , + .Test_en_E_in ( Test_enWires[223] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_312 ) , + .Test_en_W_out ( Test_enWires[224] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_313 ) , + .pReset_N_in ( pResetWires[509] ) , .Reset_E_in ( ResetWires[223] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_314 ) , + .Reset_W_out ( ResetWires[224] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_315 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_316 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[33] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[90] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[91] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_317 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_318 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_319 ) , + .clk_0_S_in ( clk_1_wires[33] ) ) ; +grid_clb grid_clb_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_320 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[21] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_321 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[21] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_322 } ) , + .ccff_head ( cby_1__1__10_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_22_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_22_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_22_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_22_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_22_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_22_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_22_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_22_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[20] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_323 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[20] ) , + .ccff_tail ( grid_clb_22_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_324 ) , .SC_IN_BOT ( scff_Wires[48] ) , + .SC_OUT_TOP ( scff_Wires[49] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_325 ) , + .Test_en_E_in ( Test_enWires[245] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_326 ) , + .Test_en_W_out ( Test_enWires[246] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_327 ) , + .pReset_N_in ( pResetWires[558] ) , .Reset_E_in ( ResetWires[245] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_328 ) , + .Reset_W_out ( ResetWires[246] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_329 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[41] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_330 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[93] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[94] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_331 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_332 ) , + .clk_0_N_in ( clk_1_wires[41] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_333 ) ) ; +grid_clb grid_clb_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_334 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_335 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_2__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_336 } ) , + .ccff_head ( cby_1__1__11_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_23_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_23_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_23_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_23_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_23_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_23_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_23_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_23_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[21] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_337 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[21] ) , + .ccff_tail ( grid_clb_23_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_338 ) , .SC_IN_BOT ( scff_Wires[50] ) , + .SC_OUT_TOP ( scff_Wires[51] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_339 ) , + .Test_en_E_in ( Test_enWires[267] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_340 ) , + .Test_en_W_out ( Test_enWires[268] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_341 ) , + .pReset_N_in ( pResetWires[606] ) , .Reset_E_in ( ResetWires[267] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_342 ) , + .Reset_W_out ( ResetWires[268] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_343 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_344 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[40] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[96] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[97] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_345 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[99] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_346 ) , + .clk_0_S_in ( clk_1_wires[40] ) ) ; +grid_clb grid_clb_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_347 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[22] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_348 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[22] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_349 } ) , + .ccff_head ( cby_1__1__12_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_24_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_24_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_24_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_24_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_24_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_24_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_24_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_24_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_350 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_3__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[76] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_351 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_352 ) , + .SC_OUT_BOT ( scff_Wires[78] ) , .Test_en_E_in ( Test_enWires[27] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_353 ) , + .Test_en_W_out ( Test_enWires[28] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_354 ) , + .pReset_N_in ( pResetWires[72] ) , .Reset_E_in ( ResetWires[27] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_355 ) , + .Reset_W_out ( ResetWires[28] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_356 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[46] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_357 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[101] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[102] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_358 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_359 ) , + .clk_0_N_in ( clk_1_wires[46] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_360 ) ) ; +grid_clb grid_clb_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_361 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[23] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_362 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[23] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_363 } ) , + .ccff_head ( cby_1__1__13_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_25_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_25_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_25_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_25_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_25_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_25_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_25_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_25_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[22] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_364 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[22] ) , + .ccff_tail ( grid_clb_25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[74] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_365 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_366 ) , + .SC_OUT_BOT ( scff_Wires[75] ) , .Test_en_E_in ( Test_enWires[49] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_367 ) , + .Test_en_W_out ( Test_enWires[50] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_368 ) , + .pReset_N_in ( pResetWires[121] ) , .Reset_E_in ( ResetWires[49] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_369 ) , + .Reset_W_out ( ResetWires[50] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_370 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_371 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[45] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[104] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[105] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_372 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_373 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_374 ) , + .clk_0_S_in ( clk_1_wires[45] ) ) ; +grid_clb grid_clb_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_375 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[24] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_376 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[24] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_377 } ) , + .ccff_head ( cby_1__1__14_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_26_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_26_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_26_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_26_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_26_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_26_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_26_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_26_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[23] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_378 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[23] ) , + .ccff_tail ( grid_clb_26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[72] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_379 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_380 ) , + .SC_OUT_BOT ( scff_Wires[73] ) , .Test_en_E_in ( Test_enWires[71] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_381 ) , + .Test_en_W_out ( Test_enWires[72] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_382 ) , + .pReset_N_in ( pResetWires[170] ) , .Reset_E_in ( ResetWires[71] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_383 ) , + .Reset_W_out ( ResetWires[72] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_384 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[53] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_385 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[107] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[108] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_386 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_387 ) , + .clk_0_N_in ( clk_1_wires[53] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_388 ) ) ; +grid_clb grid_clb_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_389 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[25] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_390 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[25] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_391 } ) , + .ccff_head ( cby_1__1__15_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_27_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_27_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_27_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_27_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_27_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_27_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_27_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_27_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[24] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_392 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[24] ) , + .ccff_tail ( grid_clb_27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[70] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_393 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_394 ) , + .SC_OUT_BOT ( scff_Wires[71] ) , .Test_en_E_in ( Test_enWires[93] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_395 ) , + .Test_en_W_out ( Test_enWires[94] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_396 ) , + .pReset_N_in ( pResetWires[219] ) , .Reset_E_in ( ResetWires[93] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_397 ) , + .Reset_W_out ( ResetWires[94] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_398 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_399 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[52] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[110] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[111] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_400 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_401 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_402 ) , + .clk_0_S_in ( clk_1_wires[52] ) ) ; +grid_clb grid_clb_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_403 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[26] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_404 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[26] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_405 } ) , + .ccff_head ( cby_1__1__16_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_28_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_28_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_28_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_28_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_28_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_28_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_28_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_28_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[25] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_406 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[25] ) , + .ccff_tail ( grid_clb_28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[68] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_407 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_408 ) , + .SC_OUT_BOT ( scff_Wires[69] ) , .Test_en_E_in ( Test_enWires[115] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_409 ) , + .Test_en_W_out ( Test_enWires[116] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_410 ) , + .pReset_N_in ( pResetWires[268] ) , .Reset_E_in ( ResetWires[115] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_411 ) , + .Reset_W_out ( ResetWires[116] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_412 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[60] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_413 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[113] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[114] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_414 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_415 ) , + .clk_0_N_in ( clk_1_wires[60] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_416 ) ) ; +grid_clb grid_clb_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_417 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[27] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_418 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[27] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_419 } ) , + .ccff_head ( cby_1__1__17_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_29_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_29_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_29_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_29_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_29_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_29_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_29_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_29_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[26] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_420 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[26] ) , + .ccff_tail ( grid_clb_29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[66] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_421 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_422 ) , + .SC_OUT_BOT ( scff_Wires[67] ) , .Test_en_E_in ( Test_enWires[137] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_423 ) , + .Test_en_W_out ( Test_enWires[138] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_424 ) , + .pReset_N_in ( pResetWires[317] ) , .Reset_E_in ( ResetWires[137] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_425 ) , + .Reset_W_out ( ResetWires[138] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_426 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_427 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[59] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[116] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[117] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_428 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_429 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_430 ) , + .clk_0_S_in ( clk_1_wires[59] ) ) ; +grid_clb grid_clb_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_431 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[28] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_432 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[28] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_433 } ) , + .ccff_head ( cby_1__1__18_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_30_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_30_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_30_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_30_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_30_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_30_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_30_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_30_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[27] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_434 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[27] ) , + .ccff_tail ( grid_clb_30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[64] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_435 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_436 ) , + .SC_OUT_BOT ( scff_Wires[65] ) , .Test_en_E_in ( Test_enWires[159] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_437 ) , + .Test_en_W_out ( Test_enWires[160] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_438 ) , + .pReset_N_in ( pResetWires[366] ) , .Reset_E_in ( ResetWires[159] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_439 ) , + .Reset_W_out ( ResetWires[160] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_440 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[67] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_441 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[119] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[120] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_442 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_443 ) , + .clk_0_N_in ( clk_1_wires[67] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_444 ) ) ; +grid_clb grid_clb_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_445 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[29] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_446 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[29] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_447 } ) , + .ccff_head ( cby_1__1__19_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_31_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_31_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_31_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_31_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_31_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_31_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_31_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_31_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[28] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_448 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[28] ) , + .ccff_tail ( grid_clb_31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[62] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_449 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_450 ) , + .SC_OUT_BOT ( scff_Wires[63] ) , .Test_en_E_in ( Test_enWires[181] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_451 ) , + .Test_en_W_out ( Test_enWires[182] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_452 ) , + .pReset_N_in ( pResetWires[415] ) , .Reset_E_in ( ResetWires[181] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_453 ) , + .Reset_W_out ( ResetWires[182] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_454 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_455 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[66] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[122] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[123] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_456 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_457 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_458 ) , + .clk_0_S_in ( clk_1_wires[66] ) ) ; +grid_clb grid_clb_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_459 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[30] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_460 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[30] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_461 } ) , + .ccff_head ( cby_1__1__20_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_32_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_32_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_32_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_32_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_32_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_32_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_32_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_32_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[29] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_462 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[29] ) , + .ccff_tail ( grid_clb_32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[60] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_463 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_464 ) , + .SC_OUT_BOT ( scff_Wires[61] ) , .Test_en_E_in ( Test_enWires[203] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_465 ) , + .Test_en_W_out ( Test_enWires[204] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_466 ) , + .pReset_N_in ( pResetWires[464] ) , .Reset_E_in ( ResetWires[203] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_467 ) , + .Reset_W_out ( ResetWires[204] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_468 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[74] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_469 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[125] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[126] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_470 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_471 ) , + .clk_0_N_in ( clk_1_wires[74] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_472 ) ) ; +grid_clb grid_clb_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_473 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[31] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_474 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[31] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_475 } ) , + .ccff_head ( cby_1__1__21_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_33_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_33_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_33_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_33_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_33_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_33_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_33_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_33_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[30] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_476 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[30] ) , + .ccff_tail ( grid_clb_33_ccff_tail ) , .SC_IN_TOP ( scff_Wires[58] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_477 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_478 ) , + .SC_OUT_BOT ( scff_Wires[59] ) , .Test_en_E_in ( Test_enWires[225] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_479 ) , + .Test_en_W_out ( Test_enWires[226] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_480 ) , + .pReset_N_in ( pResetWires[513] ) , .Reset_E_in ( ResetWires[225] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_481 ) , + .Reset_W_out ( ResetWires[226] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_482 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_483 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[73] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[128] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[129] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_484 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_485 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_486 ) , + .clk_0_S_in ( clk_1_wires[73] ) ) ; +grid_clb grid_clb_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_487 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[32] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_488 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[32] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_489 } ) , + .ccff_head ( cby_1__1__22_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_34_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_34_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_34_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_34_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_34_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_34_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_34_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_34_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[31] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_490 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[31] ) , + .ccff_tail ( grid_clb_34_ccff_tail ) , .SC_IN_TOP ( scff_Wires[56] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_491 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_492 ) , + .SC_OUT_BOT ( scff_Wires[57] ) , .Test_en_E_in ( Test_enWires[247] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_493 ) , + .Test_en_W_out ( Test_enWires[248] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_494 ) , + .pReset_N_in ( pResetWires[562] ) , .Reset_E_in ( ResetWires[247] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_495 ) , + .Reset_W_out ( ResetWires[248] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_496 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[81] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_497 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[131] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[132] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_498 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_499 ) , + .clk_0_N_in ( clk_1_wires[81] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_500 ) ) ; +grid_clb grid_clb_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_501 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_502 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_3__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_503 } ) , + .ccff_head ( cby_1__1__23_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_35_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_35_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_35_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_35_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_35_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_35_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_35_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_35_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[32] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_504 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[32] ) , + .ccff_tail ( grid_clb_35_ccff_tail ) , .SC_IN_TOP ( scff_Wires[54] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_505 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_506 ) , + .SC_OUT_BOT ( scff_Wires[55] ) , .Test_en_E_in ( Test_enWires[269] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_507 ) , + .Test_en_W_out ( Test_enWires[270] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_508 ) , + .pReset_N_in ( pResetWires[609] ) , .Reset_E_in ( ResetWires[269] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_509 ) , + .Reset_W_out ( ResetWires[270] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_510 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_511 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[80] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[134] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[135] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_512 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[137] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_513 ) , + .clk_0_S_in ( clk_1_wires[80] ) ) ; +grid_clb grid_clb_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_514 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[33] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_515 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[33] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_516 } ) , + .ccff_head ( cby_1__1__24_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_36_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_36_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_36_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_36_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_36_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_36_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_36_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_36_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_517 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_4__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_36_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_518 ) , .SC_IN_BOT ( scff_Wires[81] ) , + .SC_OUT_TOP ( scff_Wires[82] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_519 ) , + .Test_en_E_in ( Test_enWires[29] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_520 ) , + .Test_en_W_out ( Test_enWires[30] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_521 ) , + .pReset_N_in ( pResetWires[76] ) , .Reset_E_in ( ResetWires[29] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_522 ) , + .Reset_W_out ( ResetWires[30] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_523 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[48] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_524 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[139] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[140] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_525 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_526 ) , + .clk_0_N_in ( clk_1_wires[48] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_527 ) ) ; +grid_clb grid_clb_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_528 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[34] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_529 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[34] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_530 } ) , + .ccff_head ( cby_1__1__25_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_37_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_37_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_37_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_37_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_37_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_37_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_37_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_37_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[33] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_531 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[33] ) , + .ccff_tail ( grid_clb_37_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_532 ) , .SC_IN_BOT ( scff_Wires[83] ) , + .SC_OUT_TOP ( scff_Wires[84] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_533 ) , + .Test_en_E_in ( Test_enWires[51] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_534 ) , + .Test_en_W_out ( Test_enWires[52] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_535 ) , + .pReset_N_in ( pResetWires[125] ) , .Reset_E_in ( ResetWires[51] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_536 ) , + .Reset_W_out ( ResetWires[52] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_537 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_538 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[47] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[142] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[143] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_539 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_540 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_541 ) , + .clk_0_S_in ( clk_1_wires[47] ) ) ; +grid_clb grid_clb_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_542 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[35] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_543 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[35] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_544 } ) , + .ccff_head ( cby_1__1__26_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_38_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_38_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_38_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_38_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_38_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_38_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_38_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_38_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[34] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_545 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[34] ) , + .ccff_tail ( grid_clb_38_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_546 ) , .SC_IN_BOT ( scff_Wires[85] ) , + .SC_OUT_TOP ( scff_Wires[86] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_547 ) , + .Test_en_E_in ( Test_enWires[73] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_548 ) , + .Test_en_W_out ( Test_enWires[74] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_549 ) , + .pReset_N_in ( pResetWires[174] ) , .Reset_E_in ( ResetWires[73] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_550 ) , + .Reset_W_out ( ResetWires[74] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_551 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[55] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_552 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[145] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[146] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_553 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_554 ) , + .clk_0_N_in ( clk_1_wires[55] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_555 ) ) ; +grid_clb grid_clb_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_556 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[36] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_557 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[36] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_558 } ) , + .ccff_head ( cby_1__1__27_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_39_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_39_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_39_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_39_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_39_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_39_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_39_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_39_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[35] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_559 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[35] ) , + .ccff_tail ( grid_clb_39_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_560 ) , .SC_IN_BOT ( scff_Wires[87] ) , + .SC_OUT_TOP ( scff_Wires[88] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_561 ) , + .Test_en_E_in ( Test_enWires[95] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_562 ) , + .Test_en_W_out ( Test_enWires[96] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_563 ) , + .pReset_N_in ( pResetWires[223] ) , .Reset_E_in ( ResetWires[95] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_564 ) , + .Reset_W_out ( ResetWires[96] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_565 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_566 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[54] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[148] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[149] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_567 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_568 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_569 ) , + .clk_0_S_in ( clk_1_wires[54] ) ) ; +grid_clb grid_clb_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_570 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[37] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_571 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[37] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_572 } ) , + .ccff_head ( cby_1__1__28_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_40_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_40_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_40_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_40_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_40_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_40_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_40_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_40_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[36] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_573 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[36] ) , + .ccff_tail ( grid_clb_40_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_574 ) , .SC_IN_BOT ( scff_Wires[89] ) , + .SC_OUT_TOP ( scff_Wires[90] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_575 ) , + .Test_en_E_in ( Test_enWires[117] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_576 ) , + .Test_en_W_out ( Test_enWires[118] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_577 ) , + .pReset_N_in ( pResetWires[272] ) , .Reset_E_in ( ResetWires[117] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_578 ) , + .Reset_W_out ( ResetWires[118] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_579 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[62] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_580 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[151] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[152] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_581 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_582 ) , + .clk_0_N_in ( clk_1_wires[62] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_583 ) ) ; +grid_clb grid_clb_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_584 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[38] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_585 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[38] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_586 } ) , + .ccff_head ( cby_1__1__29_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_41_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_41_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_41_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_41_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_41_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_41_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_41_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_41_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[37] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_587 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[37] ) , + .ccff_tail ( grid_clb_41_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_588 ) , .SC_IN_BOT ( scff_Wires[91] ) , + .SC_OUT_TOP ( scff_Wires[92] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_589 ) , + .Test_en_E_in ( Test_enWires[139] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_590 ) , + .Test_en_W_out ( Test_enWires[140] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_591 ) , + .pReset_N_in ( pResetWires[321] ) , .Reset_E_in ( ResetWires[139] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_592 ) , + .Reset_W_out ( ResetWires[140] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_593 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_594 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[61] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[154] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[155] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_595 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_596 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_597 ) , + .clk_0_S_in ( clk_1_wires[61] ) ) ; +grid_clb grid_clb_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_598 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[39] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_599 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[39] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_600 } ) , + .ccff_head ( cby_1__1__30_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_42_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_42_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_42_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_42_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_42_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_42_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_42_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_42_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[38] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_601 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[38] ) , + .ccff_tail ( grid_clb_42_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_602 ) , .SC_IN_BOT ( scff_Wires[93] ) , + .SC_OUT_TOP ( scff_Wires[94] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_603 ) , + .Test_en_E_in ( Test_enWires[161] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_604 ) , + .Test_en_W_out ( Test_enWires[162] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_605 ) , + .pReset_N_in ( pResetWires[370] ) , .Reset_E_in ( ResetWires[161] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_606 ) , + .Reset_W_out ( ResetWires[162] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_607 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[69] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_608 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[157] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[158] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_609 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_610 ) , + .clk_0_N_in ( clk_1_wires[69] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_611 ) ) ; +grid_clb grid_clb_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_612 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[40] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_613 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[40] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_614 } ) , + .ccff_head ( cby_1__1__31_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_43_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_43_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_43_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_43_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_43_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_43_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_43_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_43_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[39] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_615 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[39] ) , + .ccff_tail ( grid_clb_43_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_616 ) , .SC_IN_BOT ( scff_Wires[95] ) , + .SC_OUT_TOP ( scff_Wires[96] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_617 ) , + .Test_en_E_in ( Test_enWires[183] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_618 ) , + .Test_en_W_out ( Test_enWires[184] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_619 ) , + .pReset_N_in ( pResetWires[419] ) , .Reset_E_in ( ResetWires[183] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_620 ) , + .Reset_W_out ( ResetWires[184] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_621 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_622 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[68] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[160] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[161] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_623 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_624 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_625 ) , + .clk_0_S_in ( clk_1_wires[68] ) ) ; +grid_clb grid_clb_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_626 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[41] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_627 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[41] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_628 } ) , + .ccff_head ( cby_1__1__32_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_44_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_44_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_44_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_44_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_44_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_44_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_44_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_44_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[40] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_629 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[40] ) , + .ccff_tail ( grid_clb_44_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_630 ) , .SC_IN_BOT ( scff_Wires[97] ) , + .SC_OUT_TOP ( scff_Wires[98] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_631 ) , + .Test_en_E_in ( Test_enWires[205] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_632 ) , + .Test_en_W_out ( Test_enWires[206] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_633 ) , + .pReset_N_in ( pResetWires[468] ) , .Reset_E_in ( ResetWires[205] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_634 ) , + .Reset_W_out ( ResetWires[206] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_635 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[76] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_636 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[163] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[164] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_637 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_638 ) , + .clk_0_N_in ( clk_1_wires[76] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_639 ) ) ; +grid_clb grid_clb_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_640 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[42] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_641 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[42] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_642 } ) , + .ccff_head ( cby_1__1__33_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_45_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_45_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_45_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_45_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_45_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_45_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_45_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_45_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[41] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_643 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[41] ) , + .ccff_tail ( grid_clb_45_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_644 ) , .SC_IN_BOT ( scff_Wires[99] ) , + .SC_OUT_TOP ( scff_Wires[100] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_645 ) , + .Test_en_E_in ( Test_enWires[227] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_646 ) , + .Test_en_W_out ( Test_enWires[228] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_647 ) , + .pReset_N_in ( pResetWires[517] ) , .Reset_E_in ( ResetWires[227] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_648 ) , + .Reset_W_out ( ResetWires[228] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_649 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_650 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[75] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[166] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[167] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_651 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_652 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_653 ) , + .clk_0_S_in ( clk_1_wires[75] ) ) ; +grid_clb grid_clb_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_654 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[43] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_655 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[43] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_656 } ) , + .ccff_head ( cby_1__1__34_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_46_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_46_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_46_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_46_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_46_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_46_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_46_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_46_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[42] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_657 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[42] ) , + .ccff_tail ( grid_clb_46_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_658 ) , .SC_IN_BOT ( scff_Wires[101] ) , + .SC_OUT_TOP ( scff_Wires[102] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_659 ) , + .Test_en_E_in ( Test_enWires[249] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_660 ) , + .Test_en_W_out ( Test_enWires[250] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_661 ) , + .pReset_N_in ( pResetWires[566] ) , .Reset_E_in ( ResetWires[249] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_662 ) , + .Reset_W_out ( ResetWires[250] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_663 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[83] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_664 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[169] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[170] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_665 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_666 ) , + .clk_0_N_in ( clk_1_wires[83] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_667 ) ) ; +grid_clb grid_clb_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_668 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_669 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_4__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_670 } ) , + .ccff_head ( cby_1__1__35_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_47_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_47_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_47_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_47_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_47_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_47_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_47_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_47_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[43] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_671 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[43] ) , + .ccff_tail ( grid_clb_47_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_672 ) , .SC_IN_BOT ( scff_Wires[103] ) , + .SC_OUT_TOP ( scff_Wires[104] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_673 ) , + .Test_en_E_in ( Test_enWires[271] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_674 ) , + .Test_en_W_out ( Test_enWires[272] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_675 ) , + .pReset_N_in ( pResetWires[612] ) , .Reset_E_in ( ResetWires[271] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_676 ) , + .Reset_W_out ( ResetWires[272] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_677 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_678 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[82] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[172] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[173] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_679 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[175] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_680 ) , + .clk_0_S_in ( clk_1_wires[82] ) ) ; +grid_clb grid_clb_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_681 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[44] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_682 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[44] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_683 } ) , + .ccff_head ( cby_1__1__36_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_48_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_48_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_48_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_48_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_48_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_48_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_48_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_48_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_684 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_5__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[129] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_685 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_686 ) , + .SC_OUT_BOT ( scff_Wires[131] ) , .Test_en_E_in ( Test_enWires[31] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_687 ) , + .Test_en_W_out ( Test_enWires[32] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_688 ) , + .pReset_N_in ( pResetWires[80] ) , .Reset_E_in ( ResetWires[31] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_689 ) , + .Reset_W_out ( ResetWires[32] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_690 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[88] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_691 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[177] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[178] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_692 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_693 ) , + .clk_0_N_in ( clk_1_wires[88] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_694 ) ) ; +grid_clb grid_clb_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_695 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[45] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_696 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[45] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_697 } ) , + .ccff_head ( cby_1__1__37_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_49_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_49_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_49_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_49_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_49_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_49_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_49_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_49_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[44] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_698 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[44] ) , + .ccff_tail ( grid_clb_49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[127] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_699 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_700 ) , + .SC_OUT_BOT ( scff_Wires[128] ) , .Test_en_E_in ( Test_enWires[53] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_701 ) , + .Test_en_W_out ( Test_enWires[54] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_702 ) , + .pReset_N_in ( pResetWires[129] ) , .Reset_E_in ( ResetWires[53] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_703 ) , + .Reset_W_out ( ResetWires[54] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_704 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_705 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[87] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[180] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[181] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_706 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_707 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_708 ) , + .clk_0_S_in ( clk_1_wires[87] ) ) ; +grid_clb grid_clb_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_709 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[46] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_710 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[46] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_711 } ) , + .ccff_head ( cby_1__1__38_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_50_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_50_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_50_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_50_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_50_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_50_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_50_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_50_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[45] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_712 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[45] ) , + .ccff_tail ( grid_clb_50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[125] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_713 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_714 ) , + .SC_OUT_BOT ( scff_Wires[126] ) , .Test_en_E_in ( Test_enWires[75] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_715 ) , + .Test_en_W_out ( Test_enWires[76] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_716 ) , + .pReset_N_in ( pResetWires[178] ) , .Reset_E_in ( ResetWires[75] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_717 ) , + .Reset_W_out ( ResetWires[76] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_718 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[95] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_719 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[183] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[184] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_720 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_721 ) , + .clk_0_N_in ( clk_1_wires[95] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_722 ) ) ; +grid_clb grid_clb_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_723 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[47] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_724 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[47] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_725 } ) , + .ccff_head ( cby_1__1__39_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_51_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_51_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_51_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_51_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_51_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_51_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_51_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_51_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[46] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_726 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[46] ) , + .ccff_tail ( grid_clb_51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[123] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_727 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_728 ) , + .SC_OUT_BOT ( scff_Wires[124] ) , .Test_en_E_in ( Test_enWires[97] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_729 ) , + .Test_en_W_out ( Test_enWires[98] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_730 ) , + .pReset_N_in ( pResetWires[227] ) , .Reset_E_in ( ResetWires[97] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_731 ) , + .Reset_W_out ( ResetWires[98] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_732 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_733 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[94] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[186] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[187] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_734 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_735 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_736 ) , + .clk_0_S_in ( clk_1_wires[94] ) ) ; +grid_clb grid_clb_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_737 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[48] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_738 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[48] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_739 } ) , + .ccff_head ( cby_1__1__40_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_52_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_52_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_52_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_52_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_52_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_52_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_52_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_52_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[47] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_740 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[47] ) , + .ccff_tail ( grid_clb_52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[121] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_741 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_742 ) , + .SC_OUT_BOT ( scff_Wires[122] ) , .Test_en_E_in ( Test_enWires[119] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_743 ) , + .Test_en_W_out ( Test_enWires[120] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_744 ) , + .pReset_N_in ( pResetWires[276] ) , .Reset_E_in ( ResetWires[119] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_745 ) , + .Reset_W_out ( ResetWires[120] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_746 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[102] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_747 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[189] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[190] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_748 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_749 ) , + .clk_0_N_in ( clk_1_wires[102] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_750 ) ) ; +grid_clb grid_clb_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_751 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[49] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_752 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[49] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_753 } ) , + .ccff_head ( cby_1__1__41_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_53_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_53_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_53_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_53_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_53_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_53_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_53_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_53_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[48] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_754 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[48] ) , + .ccff_tail ( grid_clb_53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[119] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_755 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_756 ) , + .SC_OUT_BOT ( scff_Wires[120] ) , .Test_en_E_in ( Test_enWires[141] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_757 ) , + .Test_en_W_out ( Test_enWires[142] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_758 ) , + .pReset_N_in ( pResetWires[325] ) , .Reset_E_in ( ResetWires[141] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_759 ) , + .Reset_W_out ( ResetWires[142] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_760 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_761 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[101] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[192] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[193] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_762 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_763 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_764 ) , + .clk_0_S_in ( clk_1_wires[101] ) ) ; +grid_clb grid_clb_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_765 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[50] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_766 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[50] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_767 } ) , + .ccff_head ( cby_1__1__42_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_54_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_54_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_54_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_54_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_54_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_54_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_54_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_54_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[49] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_768 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[49] ) , + .ccff_tail ( grid_clb_54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[117] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_769 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_770 ) , + .SC_OUT_BOT ( scff_Wires[118] ) , .Test_en_E_in ( Test_enWires[163] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_771 ) , + .Test_en_W_out ( Test_enWires[164] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_772 ) , + .pReset_N_in ( pResetWires[374] ) , .Reset_E_in ( ResetWires[163] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_773 ) , + .Reset_W_out ( ResetWires[164] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_774 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[109] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_775 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[195] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[196] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_776 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_777 ) , + .clk_0_N_in ( clk_1_wires[109] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_778 ) ) ; +grid_clb grid_clb_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_779 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[51] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_780 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[51] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_781 } ) , + .ccff_head ( cby_1__1__43_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_55_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_55_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_55_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_55_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_55_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_55_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_55_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_55_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[50] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_782 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[50] ) , + .ccff_tail ( grid_clb_55_ccff_tail ) , .SC_IN_TOP ( scff_Wires[115] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_783 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_784 ) , + .SC_OUT_BOT ( scff_Wires[116] ) , .Test_en_E_in ( Test_enWires[185] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_785 ) , + .Test_en_W_out ( Test_enWires[186] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_786 ) , + .pReset_N_in ( pResetWires[423] ) , .Reset_E_in ( ResetWires[185] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_787 ) , + .Reset_W_out ( ResetWires[186] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_788 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_789 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[108] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[198] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[199] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_790 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_791 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_792 ) , + .clk_0_S_in ( clk_1_wires[108] ) ) ; +grid_clb grid_clb_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_793 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[52] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_794 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[52] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_795 } ) , + .ccff_head ( cby_1__1__44_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_56_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_56_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_56_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_56_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_56_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_56_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_56_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_56_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[51] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_796 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[51] ) , + .ccff_tail ( grid_clb_56_ccff_tail ) , .SC_IN_TOP ( scff_Wires[113] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_797 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_798 ) , + .SC_OUT_BOT ( scff_Wires[114] ) , .Test_en_E_in ( Test_enWires[207] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_799 ) , + .Test_en_W_out ( Test_enWires[208] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_800 ) , + .pReset_N_in ( pResetWires[472] ) , .Reset_E_in ( ResetWires[207] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_801 ) , + .Reset_W_out ( ResetWires[208] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_802 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[116] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_803 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[201] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[202] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_804 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_805 ) , + .clk_0_N_in ( clk_1_wires[116] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_806 ) ) ; +grid_clb grid_clb_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_807 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[53] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_808 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[53] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_809 } ) , + .ccff_head ( cby_1__1__45_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_57_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_57_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_57_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_57_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_57_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_57_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_57_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_57_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[52] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_810 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[52] ) , + .ccff_tail ( grid_clb_57_ccff_tail ) , .SC_IN_TOP ( scff_Wires[111] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_811 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_812 ) , + .SC_OUT_BOT ( scff_Wires[112] ) , .Test_en_E_in ( Test_enWires[229] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_813 ) , + .Test_en_W_out ( Test_enWires[230] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_814 ) , + .pReset_N_in ( pResetWires[521] ) , .Reset_E_in ( ResetWires[229] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_815 ) , + .Reset_W_out ( ResetWires[230] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_816 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_817 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[115] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[204] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[205] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_818 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_819 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_820 ) , + .clk_0_S_in ( clk_1_wires[115] ) ) ; +grid_clb grid_clb_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_821 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[54] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_822 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[54] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_823 } ) , + .ccff_head ( cby_1__1__46_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_58_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_58_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_58_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_58_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_58_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_58_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_58_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_58_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[53] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_824 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[53] ) , + .ccff_tail ( grid_clb_58_ccff_tail ) , .SC_IN_TOP ( scff_Wires[109] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_825 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_826 ) , + .SC_OUT_BOT ( scff_Wires[110] ) , .Test_en_E_in ( Test_enWires[251] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_827 ) , + .Test_en_W_out ( Test_enWires[252] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_828 ) , + .pReset_N_in ( pResetWires[570] ) , .Reset_E_in ( ResetWires[251] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_829 ) , + .Reset_W_out ( ResetWires[252] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_830 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[123] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_831 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[207] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[208] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_832 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_833 ) , + .clk_0_N_in ( clk_1_wires[123] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_834 ) ) ; +grid_clb grid_clb_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_835 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_836 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_5__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_837 } ) , + .ccff_head ( cby_1__1__47_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_59_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_59_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_59_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_59_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_59_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_59_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_59_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_59_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[54] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_838 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[54] ) , + .ccff_tail ( grid_clb_59_ccff_tail ) , .SC_IN_TOP ( scff_Wires[107] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_839 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_840 ) , + .SC_OUT_BOT ( scff_Wires[108] ) , .Test_en_E_in ( Test_enWires[273] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_841 ) , + .Test_en_W_out ( Test_enWires[274] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_842 ) , + .pReset_N_in ( pResetWires[615] ) , .Reset_E_in ( ResetWires[273] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_843 ) , + .Reset_W_out ( ResetWires[274] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_844 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_845 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[122] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[210] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[211] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_846 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[213] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_847 ) , + .clk_0_S_in ( clk_1_wires[122] ) ) ; +grid_clb grid_clb_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_848 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[55] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_849 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[55] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_850 } ) , + .ccff_head ( cby_1__1__48_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_60_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_60_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_60_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_60_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_60_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_60_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_60_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_60_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_851 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_6__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_60_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_852 ) , .SC_IN_BOT ( scff_Wires[134] ) , + .SC_OUT_TOP ( scff_Wires[135] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_853 ) , + .Test_en_E_in ( Test_enWires[33] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_854 ) , + .Test_en_W_out ( Test_enWires[34] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_855 ) , + .pReset_N_in ( pResetWires[84] ) , .Reset_E_in ( ResetWires[33] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_856 ) , + .Reset_W_out ( ResetWires[34] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_857 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[90] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_858 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[215] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[216] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_859 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_860 ) , + .clk_0_N_in ( clk_1_wires[90] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_861 ) ) ; +grid_clb grid_clb_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_862 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[56] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_863 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[56] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_864 } ) , + .ccff_head ( cby_1__1__49_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_61_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_61_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_61_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_61_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_61_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_61_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_61_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_61_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[55] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_865 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[55] ) , + .ccff_tail ( grid_clb_61_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_866 ) , .SC_IN_BOT ( scff_Wires[136] ) , + .SC_OUT_TOP ( scff_Wires[137] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_867 ) , + .Test_en_E_in ( Test_enWires[55] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_868 ) , + .Test_en_W_out ( Test_enWires[56] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_869 ) , + .pReset_N_in ( pResetWires[133] ) , .Reset_E_in ( ResetWires[55] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_870 ) , + .Reset_W_out ( ResetWires[56] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_871 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_872 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[89] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[218] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[219] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_873 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_874 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_875 ) , + .clk_0_S_in ( clk_1_wires[89] ) ) ; +grid_clb grid_clb_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_876 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[57] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_877 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[57] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_878 } ) , + .ccff_head ( cby_1__1__50_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_62_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_62_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_62_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_62_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_62_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_62_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_62_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_62_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[56] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_879 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[56] ) , + .ccff_tail ( grid_clb_62_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_880 ) , .SC_IN_BOT ( scff_Wires[138] ) , + .SC_OUT_TOP ( scff_Wires[139] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_881 ) , + .Test_en_E_in ( Test_enWires[77] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_882 ) , + .Test_en_W_out ( Test_enWires[78] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_883 ) , + .pReset_N_in ( pResetWires[182] ) , .Reset_E_in ( ResetWires[77] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_884 ) , + .Reset_W_out ( ResetWires[78] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_885 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[97] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_886 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[221] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[222] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_887 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_888 ) , + .clk_0_N_in ( clk_1_wires[97] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_889 ) ) ; +grid_clb grid_clb_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_890 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[58] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_891 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[58] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_892 } ) , + .ccff_head ( cby_1__1__51_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_63_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_63_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_63_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_63_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_63_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_63_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_63_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_63_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[57] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_893 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[57] ) , + .ccff_tail ( grid_clb_63_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_894 ) , .SC_IN_BOT ( scff_Wires[140] ) , + .SC_OUT_TOP ( scff_Wires[141] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_895 ) , + .Test_en_E_in ( Test_enWires[99] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_896 ) , + .Test_en_W_out ( Test_enWires[100] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_897 ) , + .pReset_N_in ( pResetWires[231] ) , .Reset_E_in ( ResetWires[99] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_898 ) , + .Reset_W_out ( ResetWires[100] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_899 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_900 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[96] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[224] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[225] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_901 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_902 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_903 ) , + .clk_0_S_in ( clk_1_wires[96] ) ) ; +grid_clb grid_clb_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_904 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[59] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_905 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[59] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_906 } ) , + .ccff_head ( cby_1__1__52_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_64_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_64_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_64_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_64_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_64_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_64_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_64_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_64_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[58] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_907 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[58] ) , + .ccff_tail ( grid_clb_64_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_908 ) , .SC_IN_BOT ( scff_Wires[142] ) , + .SC_OUT_TOP ( scff_Wires[143] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_909 ) , + .Test_en_E_in ( Test_enWires[121] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_910 ) , + .Test_en_W_out ( Test_enWires[122] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_911 ) , + .pReset_N_in ( pResetWires[280] ) , .Reset_E_in ( ResetWires[121] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_912 ) , + .Reset_W_out ( ResetWires[122] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_913 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[104] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_914 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[227] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[228] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_915 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_916 ) , + .clk_0_N_in ( clk_1_wires[104] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_917 ) ) ; +grid_clb grid_clb_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_918 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[60] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_919 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[60] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_920 } ) , + .ccff_head ( cby_1__1__53_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_65_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_65_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_65_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_65_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_65_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_65_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_65_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_65_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[59] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_921 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[59] ) , + .ccff_tail ( grid_clb_65_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_922 ) , .SC_IN_BOT ( scff_Wires[144] ) , + .SC_OUT_TOP ( scff_Wires[145] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_923 ) , + .Test_en_E_in ( Test_enWires[143] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_924 ) , + .Test_en_W_out ( Test_enWires[144] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_925 ) , + .pReset_N_in ( pResetWires[329] ) , .Reset_E_in ( ResetWires[143] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_926 ) , + .Reset_W_out ( ResetWires[144] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_927 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_928 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[103] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[230] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[231] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_929 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_930 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_931 ) , + .clk_0_S_in ( clk_1_wires[103] ) ) ; +grid_clb grid_clb_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_932 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[61] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_933 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[61] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_934 } ) , + .ccff_head ( cby_1__1__54_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_66_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_66_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_66_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_66_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_66_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_66_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_66_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_66_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[60] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_935 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[60] ) , + .ccff_tail ( grid_clb_66_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_936 ) , .SC_IN_BOT ( scff_Wires[146] ) , + .SC_OUT_TOP ( scff_Wires[147] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_937 ) , + .Test_en_E_in ( Test_enWires[165] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_938 ) , + .Test_en_W_out ( Test_enWires[166] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_939 ) , + .pReset_N_in ( pResetWires[378] ) , .Reset_E_in ( ResetWires[165] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_940 ) , + .Reset_W_out ( ResetWires[166] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_941 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[111] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_942 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[233] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[234] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_943 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_944 ) , + .clk_0_N_in ( clk_1_wires[111] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_945 ) ) ; +grid_clb grid_clb_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_946 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[62] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_947 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[62] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_948 } ) , + .ccff_head ( cby_1__1__55_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_67_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_67_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_67_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_67_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_67_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_67_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_67_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_67_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[61] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_949 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[61] ) , + .ccff_tail ( grid_clb_67_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_950 ) , .SC_IN_BOT ( scff_Wires[148] ) , + .SC_OUT_TOP ( scff_Wires[149] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_951 ) , + .Test_en_E_in ( Test_enWires[187] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_952 ) , + .Test_en_W_out ( Test_enWires[188] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_953 ) , + .pReset_N_in ( pResetWires[427] ) , .Reset_E_in ( ResetWires[187] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_954 ) , + .Reset_W_out ( ResetWires[188] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_955 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_956 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[110] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[236] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[237] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_957 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_958 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_959 ) , + .clk_0_S_in ( clk_1_wires[110] ) ) ; +grid_clb grid_clb_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_960 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[63] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_961 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[63] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_962 } ) , + .ccff_head ( cby_1__1__56_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_68_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_68_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_68_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_68_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_68_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_68_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_68_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_68_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[62] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_963 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[62] ) , + .ccff_tail ( grid_clb_68_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_964 ) , .SC_IN_BOT ( scff_Wires[150] ) , + .SC_OUT_TOP ( scff_Wires[151] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_965 ) , + .Test_en_E_in ( Test_enWires[209] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_966 ) , + .Test_en_W_out ( Test_enWires[210] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_967 ) , + .pReset_N_in ( pResetWires[476] ) , .Reset_E_in ( ResetWires[209] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_968 ) , + .Reset_W_out ( ResetWires[210] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_969 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[118] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_970 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[239] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[240] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_971 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_972 ) , + .clk_0_N_in ( clk_1_wires[118] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_973 ) ) ; +grid_clb grid_clb_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_974 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[64] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_975 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[64] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_976 } ) , + .ccff_head ( cby_1__1__57_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_69_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_69_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_69_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_69_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_69_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_69_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_69_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_69_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[63] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_977 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[63] ) , + .ccff_tail ( grid_clb_69_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_978 ) , .SC_IN_BOT ( scff_Wires[152] ) , + .SC_OUT_TOP ( scff_Wires[153] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_979 ) , + .Test_en_E_in ( Test_enWires[231] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_980 ) , + .Test_en_W_out ( Test_enWires[232] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_981 ) , + .pReset_N_in ( pResetWires[525] ) , .Reset_E_in ( ResetWires[231] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_982 ) , + .Reset_W_out ( ResetWires[232] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_983 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_984 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[117] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[242] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[243] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_985 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_986 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_987 ) , + .clk_0_S_in ( clk_1_wires[117] ) ) ; +grid_clb grid_clb_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_988 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[65] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_989 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[65] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_990 } ) , + .ccff_head ( cby_1__1__58_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_70_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_70_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_70_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_70_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_70_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_70_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_70_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_70_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[64] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_991 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[64] ) , + .ccff_tail ( grid_clb_70_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_992 ) , .SC_IN_BOT ( scff_Wires[154] ) , + .SC_OUT_TOP ( scff_Wires[155] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_993 ) , + .Test_en_E_in ( Test_enWires[253] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_994 ) , + .Test_en_W_out ( Test_enWires[254] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_995 ) , + .pReset_N_in ( pResetWires[574] ) , .Reset_E_in ( ResetWires[253] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_996 ) , + .Reset_W_out ( ResetWires[254] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_997 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[125] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_998 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[245] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[246] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_999 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1000 ) , + .clk_0_N_in ( clk_1_wires[125] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1001 ) ) ; +grid_clb grid_clb_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1002 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1003 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_6__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1004 } ) , + .ccff_head ( cby_1__1__59_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_71_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_71_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_71_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_71_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_71_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_71_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_71_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_71_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[65] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1005 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[65] ) , + .ccff_tail ( grid_clb_71_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1006 ) , + .SC_IN_BOT ( scff_Wires[156] ) , .SC_OUT_TOP ( scff_Wires[157] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1007 ) , + .Test_en_E_in ( Test_enWires[275] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_1008 ) , + .Test_en_W_out ( Test_enWires[276] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1009 ) , + .pReset_N_in ( pResetWires[618] ) , .Reset_E_in ( ResetWires[275] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_1010 ) , + .Reset_W_out ( ResetWires[276] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1011 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1012 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[124] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[248] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[249] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1013 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[251] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1014 ) , + .clk_0_S_in ( clk_1_wires[124] ) ) ; +grid_clb grid_clb_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1015 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[66] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1016 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[66] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1017 } ) , + .ccff_head ( cby_1__1__60_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_72_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_72_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_72_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_72_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_72_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_72_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_72_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_72_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1018 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_7__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[182] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1019 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1020 ) , + .SC_OUT_BOT ( scff_Wires[184] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1021 ) , + .Test_en_W_in ( Test_enWires[35] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1022 ) , + .Test_en_E_out ( Test_enWires[36] ) , .pReset_N_in ( pResetWires[88] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1023 ) , + .Reset_W_in ( ResetWires[35] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1024 ) , + .Reset_E_out ( ResetWires[36] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[130] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1025 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[253] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[254] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1026 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1027 ) , + .clk_0_N_in ( clk_1_wires[130] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1028 ) ) ; +grid_clb grid_clb_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1029 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[67] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1030 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[67] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1031 } ) , + .ccff_head ( cby_1__1__61_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_73_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_73_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_73_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_73_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_73_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_73_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_73_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_73_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[66] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1032 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[66] ) , + .ccff_tail ( grid_clb_73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[180] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1033 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1034 ) , + .SC_OUT_BOT ( scff_Wires[181] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1035 ) , + .Test_en_W_in ( Test_enWires[57] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1036 ) , + .Test_en_E_out ( Test_enWires[58] ) , .pReset_N_in ( pResetWires[137] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1037 ) , + .Reset_W_in ( ResetWires[57] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1038 ) , + .Reset_E_out ( ResetWires[58] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1039 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[129] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[256] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[257] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1040 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1041 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1042 ) , + .clk_0_S_in ( clk_1_wires[129] ) ) ; +grid_clb grid_clb_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1043 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[68] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1044 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[68] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1045 } ) , + .ccff_head ( cby_1__1__62_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_74_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_74_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_74_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_74_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_74_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_74_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_74_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_74_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[67] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1046 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[67] ) , + .ccff_tail ( grid_clb_74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[178] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1047 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1048 ) , + .SC_OUT_BOT ( scff_Wires[179] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1049 ) , + .Test_en_W_in ( Test_enWires[79] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1050 ) , + .Test_en_E_out ( Test_enWires[80] ) , .pReset_N_in ( pResetWires[186] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1051 ) , + .Reset_W_in ( ResetWires[79] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1052 ) , + .Reset_E_out ( ResetWires[80] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[137] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1053 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[259] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[260] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1054 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1055 ) , + .clk_0_N_in ( clk_1_wires[137] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1056 ) ) ; +grid_clb grid_clb_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1057 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[69] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1058 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[69] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1059 } ) , + .ccff_head ( cby_1__1__63_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_75_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_75_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_75_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_75_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_75_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_75_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_75_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_75_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[68] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1060 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[68] ) , + .ccff_tail ( grid_clb_75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[176] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1061 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1062 ) , + .SC_OUT_BOT ( scff_Wires[177] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1063 ) , + .Test_en_W_in ( Test_enWires[101] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1064 ) , + .Test_en_E_out ( Test_enWires[102] ) , .pReset_N_in ( pResetWires[235] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1065 ) , + .Reset_W_in ( ResetWires[101] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1066 ) , + .Reset_E_out ( ResetWires[102] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1067 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[136] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[262] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[263] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1068 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1069 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1070 ) , + .clk_0_S_in ( clk_1_wires[136] ) ) ; +grid_clb grid_clb_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1071 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[70] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1072 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[70] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1073 } ) , + .ccff_head ( cby_1__1__64_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_76_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_76_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_76_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_76_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_76_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_76_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_76_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_76_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[69] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1074 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[69] ) , + .ccff_tail ( grid_clb_76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[174] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1075 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1076 ) , + .SC_OUT_BOT ( scff_Wires[175] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1077 ) , + .Test_en_W_in ( Test_enWires[123] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1078 ) , + .Test_en_E_out ( Test_enWires[124] ) , .pReset_N_in ( pResetWires[284] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1079 ) , + .Reset_W_in ( ResetWires[123] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1080 ) , + .Reset_E_out ( ResetWires[124] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[144] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1081 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[265] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[266] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1082 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1083 ) , + .clk_0_N_in ( clk_1_wires[144] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1084 ) ) ; +grid_clb grid_clb_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1085 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[71] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1086 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[71] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1087 } ) , + .ccff_head ( cby_1__1__65_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_77_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_77_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_77_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_77_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_77_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_77_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_77_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_77_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[70] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1088 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[70] ) , + .ccff_tail ( grid_clb_77_ccff_tail ) , .SC_IN_TOP ( scff_Wires[172] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1089 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1090 ) , + .SC_OUT_BOT ( scff_Wires[173] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1091 ) , + .Test_en_W_in ( Test_enWires[145] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1092 ) , + .Test_en_E_out ( Test_enWires[146] ) , .pReset_N_in ( pResetWires[333] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1093 ) , + .Reset_W_in ( ResetWires[145] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1094 ) , + .Reset_E_out ( ResetWires[146] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1095 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[143] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[268] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[269] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1096 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1097 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1098 ) , + .clk_0_S_in ( clk_1_wires[143] ) ) ; +grid_clb grid_clb_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1099 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[72] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1100 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[72] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1101 } ) , + .ccff_head ( cby_1__1__66_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_78_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_78_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_78_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_78_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_78_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_78_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_78_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_78_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[71] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1102 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[71] ) , + .ccff_tail ( grid_clb_78_ccff_tail ) , .SC_IN_TOP ( scff_Wires[170] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1103 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1104 ) , + .SC_OUT_BOT ( scff_Wires[171] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1105 ) , + .Test_en_W_in ( Test_enWires[167] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1106 ) , + .Test_en_E_out ( Test_enWires[168] ) , .pReset_N_in ( pResetWires[382] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1107 ) , + .Reset_W_in ( ResetWires[167] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1108 ) , + .Reset_E_out ( ResetWires[168] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[151] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1109 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[271] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[272] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1110 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1111 ) , + .clk_0_N_in ( clk_1_wires[151] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1112 ) ) ; +grid_clb grid_clb_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1113 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[73] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1114 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[73] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1115 } ) , + .ccff_head ( cby_1__1__67_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_79_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_79_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_79_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_79_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_79_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_79_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_79_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_79_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[72] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1116 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[72] ) , + .ccff_tail ( grid_clb_79_ccff_tail ) , .SC_IN_TOP ( scff_Wires[168] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1117 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1118 ) , + .SC_OUT_BOT ( scff_Wires[169] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1119 ) , + .Test_en_W_in ( Test_enWires[189] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1120 ) , + .Test_en_E_out ( Test_enWires[190] ) , .pReset_N_in ( pResetWires[431] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1121 ) , + .Reset_W_in ( ResetWires[189] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1122 ) , + .Reset_E_out ( ResetWires[190] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1123 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[150] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[274] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[275] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1124 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1125 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1126 ) , + .clk_0_S_in ( clk_1_wires[150] ) ) ; +grid_clb grid_clb_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1127 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[74] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1128 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[74] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1129 } ) , + .ccff_head ( cby_1__1__68_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_80_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_80_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_80_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_80_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_80_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_80_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_80_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_80_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[73] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1130 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[73] ) , + .ccff_tail ( grid_clb_80_ccff_tail ) , .SC_IN_TOP ( scff_Wires[166] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1131 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1132 ) , + .SC_OUT_BOT ( scff_Wires[167] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1133 ) , + .Test_en_W_in ( Test_enWires[211] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1134 ) , + .Test_en_E_out ( Test_enWires[212] ) , .pReset_N_in ( pResetWires[480] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1135 ) , + .Reset_W_in ( ResetWires[211] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1136 ) , + .Reset_E_out ( ResetWires[212] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[158] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1137 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[277] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[278] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1138 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1139 ) , + .clk_0_N_in ( clk_1_wires[158] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1140 ) ) ; +grid_clb grid_clb_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1141 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[75] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1142 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[75] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1143 } ) , + .ccff_head ( cby_1__1__69_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_81_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_81_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_81_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_81_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_81_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_81_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_81_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_81_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[74] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1144 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[74] ) , + .ccff_tail ( grid_clb_81_ccff_tail ) , .SC_IN_TOP ( scff_Wires[164] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1145 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1146 ) , + .SC_OUT_BOT ( scff_Wires[165] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1147 ) , + .Test_en_W_in ( Test_enWires[233] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1148 ) , + .Test_en_E_out ( Test_enWires[234] ) , .pReset_N_in ( pResetWires[529] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1149 ) , + .Reset_W_in ( ResetWires[233] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1150 ) , + .Reset_E_out ( ResetWires[234] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1151 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[157] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[280] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[281] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1152 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1153 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1154 ) , + .clk_0_S_in ( clk_1_wires[157] ) ) ; +grid_clb grid_clb_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1155 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[76] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1156 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[76] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1157 } ) , + .ccff_head ( cby_1__1__70_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_82_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_82_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_82_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_82_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_82_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_82_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_82_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_82_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[75] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1158 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[75] ) , + .ccff_tail ( grid_clb_82_ccff_tail ) , .SC_IN_TOP ( scff_Wires[162] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1159 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1160 ) , + .SC_OUT_BOT ( scff_Wires[163] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1161 ) , + .Test_en_W_in ( Test_enWires[255] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1162 ) , + .Test_en_E_out ( Test_enWires[256] ) , .pReset_N_in ( pResetWires[578] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1163 ) , + .Reset_W_in ( ResetWires[255] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1164 ) , + .Reset_E_out ( ResetWires[256] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[165] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1165 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[283] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[284] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1166 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1167 ) , + .clk_0_N_in ( clk_1_wires[165] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1168 ) ) ; +grid_clb grid_clb_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1169 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1170 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_7__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1171 } ) , + .ccff_head ( cby_1__1__71_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_83_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_83_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_83_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_83_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_83_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_83_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_83_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_83_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[76] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1172 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[76] ) , + .ccff_tail ( grid_clb_83_ccff_tail ) , .SC_IN_TOP ( scff_Wires[160] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1173 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1174 ) , + .SC_OUT_BOT ( scff_Wires[161] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1175 ) , + .Test_en_W_in ( Test_enWires[277] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1176 ) , + .Test_en_E_out ( Test_enWires[278] ) , .pReset_N_in ( pResetWires[621] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1177 ) , + .Reset_W_in ( ResetWires[277] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1178 ) , + .Reset_E_out ( ResetWires[278] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1179 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[164] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[286] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[287] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1180 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[289] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1181 ) , + .clk_0_S_in ( clk_1_wires[164] ) ) ; +grid_clb grid_clb_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1182 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[77] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1183 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[77] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1184 } ) , + .ccff_head ( cby_1__1__72_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_84_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_84_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_84_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_84_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_84_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_84_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_84_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_84_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1185 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_8__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_84_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1186 ) , + .SC_IN_BOT ( scff_Wires[187] ) , .SC_OUT_TOP ( scff_Wires[188] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1187 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1188 ) , + .Test_en_W_in ( Test_enWires[37] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1189 ) , + .Test_en_E_out ( Test_enWires[38] ) , .pReset_N_in ( pResetWires[92] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1190 ) , + .Reset_W_in ( ResetWires[37] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1191 ) , + .Reset_E_out ( ResetWires[38] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[132] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1192 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[291] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[292] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1193 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1194 ) , + .clk_0_N_in ( clk_1_wires[132] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1195 ) ) ; +grid_clb grid_clb_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1196 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[78] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1197 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[78] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1198 } ) , + .ccff_head ( cby_1__1__73_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_85_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_85_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_85_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_85_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_85_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_85_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_85_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_85_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[77] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1199 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[77] ) , + .ccff_tail ( grid_clb_85_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1200 ) , + .SC_IN_BOT ( scff_Wires[189] ) , .SC_OUT_TOP ( scff_Wires[190] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1201 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1202 ) , + .Test_en_W_in ( Test_enWires[59] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1203 ) , + .Test_en_E_out ( Test_enWires[60] ) , .pReset_N_in ( pResetWires[141] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1204 ) , + .Reset_W_in ( ResetWires[59] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1205 ) , + .Reset_E_out ( ResetWires[60] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1206 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[131] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[294] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[295] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1207 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1208 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1209 ) , + .clk_0_S_in ( clk_1_wires[131] ) ) ; +grid_clb grid_clb_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1210 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[79] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1211 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[79] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1212 } ) , + .ccff_head ( cby_1__1__74_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_86_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_86_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_86_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_86_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_86_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_86_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_86_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_86_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[78] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1213 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[78] ) , + .ccff_tail ( grid_clb_86_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1214 ) , + .SC_IN_BOT ( scff_Wires[191] ) , .SC_OUT_TOP ( scff_Wires[192] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1215 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1216 ) , + .Test_en_W_in ( Test_enWires[81] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1217 ) , + .Test_en_E_out ( Test_enWires[82] ) , .pReset_N_in ( pResetWires[190] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1218 ) , + .Reset_W_in ( ResetWires[81] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1219 ) , + .Reset_E_out ( ResetWires[82] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[139] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1220 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[297] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[298] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1221 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1222 ) , + .clk_0_N_in ( clk_1_wires[139] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1223 ) ) ; +grid_clb grid_clb_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1224 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[80] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1225 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[80] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1226 } ) , + .ccff_head ( cby_1__1__75_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_87_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_87_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_87_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_87_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_87_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_87_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_87_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_87_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[79] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1227 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[79] ) , + .ccff_tail ( grid_clb_87_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1228 ) , + .SC_IN_BOT ( scff_Wires[193] ) , .SC_OUT_TOP ( scff_Wires[194] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1229 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1230 ) , + .Test_en_W_in ( Test_enWires[103] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1231 ) , + .Test_en_E_out ( Test_enWires[104] ) , .pReset_N_in ( pResetWires[239] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1232 ) , + .Reset_W_in ( ResetWires[103] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1233 ) , + .Reset_E_out ( ResetWires[104] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1234 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[138] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[300] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[301] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1235 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1236 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1237 ) , + .clk_0_S_in ( clk_1_wires[138] ) ) ; +grid_clb grid_clb_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1238 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[81] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1239 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[81] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1240 } ) , + .ccff_head ( cby_1__1__76_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_88_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_88_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_88_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_88_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_88_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_88_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_88_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_88_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[80] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1241 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[80] ) , + .ccff_tail ( grid_clb_88_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1242 ) , + .SC_IN_BOT ( scff_Wires[195] ) , .SC_OUT_TOP ( scff_Wires[196] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1243 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1244 ) , + .Test_en_W_in ( Test_enWires[125] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1245 ) , + .Test_en_E_out ( Test_enWires[126] ) , .pReset_N_in ( pResetWires[288] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1246 ) , + .Reset_W_in ( ResetWires[125] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1247 ) , + .Reset_E_out ( ResetWires[126] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[146] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1248 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[303] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[304] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1249 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1250 ) , + .clk_0_N_in ( clk_1_wires[146] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1251 ) ) ; +grid_clb grid_clb_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1252 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[82] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1253 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[82] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1254 } ) , + .ccff_head ( cby_1__1__77_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_89_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_89_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_89_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_89_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_89_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_89_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_89_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_89_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[81] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1255 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[81] ) , + .ccff_tail ( grid_clb_89_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1256 ) , + .SC_IN_BOT ( scff_Wires[197] ) , .SC_OUT_TOP ( scff_Wires[198] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1257 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1258 ) , + .Test_en_W_in ( Test_enWires[147] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1259 ) , + .Test_en_E_out ( Test_enWires[148] ) , .pReset_N_in ( pResetWires[337] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1260 ) , + .Reset_W_in ( ResetWires[147] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1261 ) , + .Reset_E_out ( ResetWires[148] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1262 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[145] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[306] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[307] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1263 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1264 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1265 ) , + .clk_0_S_in ( clk_1_wires[145] ) ) ; +grid_clb grid_clb_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1266 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[83] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1267 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[83] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1268 } ) , + .ccff_head ( cby_1__1__78_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_90_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_90_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_90_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_90_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_90_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_90_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_90_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_90_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[82] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1269 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[82] ) , + .ccff_tail ( grid_clb_90_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1270 ) , + .SC_IN_BOT ( scff_Wires[199] ) , .SC_OUT_TOP ( scff_Wires[200] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1272 ) , + .Test_en_W_in ( Test_enWires[169] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1273 ) , + .Test_en_E_out ( Test_enWires[170] ) , .pReset_N_in ( pResetWires[386] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1274 ) , + .Reset_W_in ( ResetWires[169] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1275 ) , + .Reset_E_out ( ResetWires[170] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[153] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1276 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[309] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[310] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1277 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1278 ) , + .clk_0_N_in ( clk_1_wires[153] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1279 ) ) ; +grid_clb grid_clb_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1280 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[84] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1281 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[84] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1282 } ) , + .ccff_head ( cby_1__1__79_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_91_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_91_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_91_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_91_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_91_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_91_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_91_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_91_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[83] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1283 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[83] ) , + .ccff_tail ( grid_clb_91_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1284 ) , + .SC_IN_BOT ( scff_Wires[201] ) , .SC_OUT_TOP ( scff_Wires[202] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1285 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1286 ) , + .Test_en_W_in ( Test_enWires[191] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1287 ) , + .Test_en_E_out ( Test_enWires[192] ) , .pReset_N_in ( pResetWires[435] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1288 ) , + .Reset_W_in ( ResetWires[191] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1289 ) , + .Reset_E_out ( ResetWires[192] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1290 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[152] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[312] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[313] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1291 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1292 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1293 ) , + .clk_0_S_in ( clk_1_wires[152] ) ) ; +grid_clb grid_clb_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1294 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[85] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1295 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[85] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1296 } ) , + .ccff_head ( cby_1__1__80_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_92_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_92_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_92_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_92_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_92_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_92_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_92_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_92_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[84] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1297 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[84] ) , + .ccff_tail ( grid_clb_92_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1298 ) , + .SC_IN_BOT ( scff_Wires[203] ) , .SC_OUT_TOP ( scff_Wires[204] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1299 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1300 ) , + .Test_en_W_in ( Test_enWires[213] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1301 ) , + .Test_en_E_out ( Test_enWires[214] ) , .pReset_N_in ( pResetWires[484] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1302 ) , + .Reset_W_in ( ResetWires[213] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1303 ) , + .Reset_E_out ( ResetWires[214] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[160] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1304 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[315] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[316] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1305 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1306 ) , + .clk_0_N_in ( clk_1_wires[160] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1307 ) ) ; +grid_clb grid_clb_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1308 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[86] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1309 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[86] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1310 } ) , + .ccff_head ( cby_1__1__81_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_93_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_93_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_93_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_93_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_93_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_93_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_93_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_93_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[85] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1311 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[85] ) , + .ccff_tail ( grid_clb_93_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1312 ) , + .SC_IN_BOT ( scff_Wires[205] ) , .SC_OUT_TOP ( scff_Wires[206] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1313 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1314 ) , + .Test_en_W_in ( Test_enWires[235] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1315 ) , + .Test_en_E_out ( Test_enWires[236] ) , .pReset_N_in ( pResetWires[533] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1316 ) , + .Reset_W_in ( ResetWires[235] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1317 ) , + .Reset_E_out ( ResetWires[236] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1318 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[159] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[318] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[319] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1319 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1320 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1321 ) , + .clk_0_S_in ( clk_1_wires[159] ) ) ; +grid_clb grid_clb_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1322 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[87] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1323 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[87] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1324 } ) , + .ccff_head ( cby_1__1__82_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_94_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_94_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_94_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_94_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_94_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_94_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_94_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_94_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[86] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1325 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[86] ) , + .ccff_tail ( grid_clb_94_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1326 ) , + .SC_IN_BOT ( scff_Wires[207] ) , .SC_OUT_TOP ( scff_Wires[208] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1327 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1328 ) , + .Test_en_W_in ( Test_enWires[257] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1329 ) , + .Test_en_E_out ( Test_enWires[258] ) , .pReset_N_in ( pResetWires[582] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1330 ) , + .Reset_W_in ( ResetWires[257] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1331 ) , + .Reset_E_out ( ResetWires[258] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[167] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1332 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[321] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[322] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1333 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1334 ) , + .clk_0_N_in ( clk_1_wires[167] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1335 ) ) ; +grid_clb grid_clb_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1336 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1337 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_8__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1338 } ) , + .ccff_head ( cby_1__1__83_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_95_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_95_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_95_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_95_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_95_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_95_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_95_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_95_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[87] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1339 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[87] ) , + .ccff_tail ( grid_clb_95_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1340 ) , + .SC_IN_BOT ( scff_Wires[209] ) , .SC_OUT_TOP ( scff_Wires[210] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1341 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1342 ) , + .Test_en_W_in ( Test_enWires[279] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1343 ) , + .Test_en_E_out ( Test_enWires[280] ) , .pReset_N_in ( pResetWires[624] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1344 ) , + .Reset_W_in ( ResetWires[279] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1345 ) , + .Reset_E_out ( ResetWires[280] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1346 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[166] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[324] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[325] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1347 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[327] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1348 ) , + .clk_0_S_in ( clk_1_wires[166] ) ) ; +grid_clb grid_clb_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1349 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[88] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1350 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[88] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1351 } ) , + .ccff_head ( cby_1__1__84_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_96_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_96_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_96_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_96_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_96_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_96_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_96_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_96_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1352 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_9__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[235] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1353 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1354 ) , + .SC_OUT_BOT ( scff_Wires[237] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1355 ) , + .Test_en_W_in ( Test_enWires[39] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1356 ) , + .Test_en_E_out ( Test_enWires[40] ) , .pReset_N_in ( pResetWires[96] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1357 ) , + .Reset_W_in ( ResetWires[39] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1358 ) , + .Reset_E_out ( ResetWires[40] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[172] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1359 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[329] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[330] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1360 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1361 ) , + .clk_0_N_in ( clk_1_wires[172] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1362 ) ) ; +grid_clb grid_clb_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1363 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[89] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1364 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[89] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1365 } ) , + .ccff_head ( cby_1__1__85_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_97_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_97_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_97_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_97_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_97_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_97_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_97_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_97_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[88] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1366 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[88] ) , + .ccff_tail ( grid_clb_97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[233] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1367 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1368 ) , + .SC_OUT_BOT ( scff_Wires[234] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1369 ) , + .Test_en_W_in ( Test_enWires[61] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1370 ) , + .Test_en_E_out ( Test_enWires[62] ) , .pReset_N_in ( pResetWires[145] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1371 ) , + .Reset_W_in ( ResetWires[61] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1372 ) , + .Reset_E_out ( ResetWires[62] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1373 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[171] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[332] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[333] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1374 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1375 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1376 ) , + .clk_0_S_in ( clk_1_wires[171] ) ) ; +grid_clb grid_clb_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1377 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[90] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1378 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[90] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1379 } ) , + .ccff_head ( cby_1__1__86_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_98_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_98_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_98_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_98_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_98_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_98_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_98_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_98_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[89] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1380 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[89] ) , + .ccff_tail ( grid_clb_98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[231] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1381 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1382 ) , + .SC_OUT_BOT ( scff_Wires[232] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1383 ) , + .Test_en_W_in ( Test_enWires[83] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1384 ) , + .Test_en_E_out ( Test_enWires[84] ) , .pReset_N_in ( pResetWires[194] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1385 ) , + .Reset_W_in ( ResetWires[83] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1386 ) , + .Reset_E_out ( ResetWires[84] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[179] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1387 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[335] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[336] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1388 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1389 ) , + .clk_0_N_in ( clk_1_wires[179] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1390 ) ) ; +grid_clb grid_clb_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1391 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[91] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1392 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[91] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1393 } ) , + .ccff_head ( cby_1__1__87_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_99_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_99_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_99_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_99_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_99_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_99_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_99_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_99_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[90] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1394 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[90] ) , + .ccff_tail ( grid_clb_99_ccff_tail ) , .SC_IN_TOP ( scff_Wires[229] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1395 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1396 ) , + .SC_OUT_BOT ( scff_Wires[230] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1397 ) , + .Test_en_W_in ( Test_enWires[105] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1398 ) , + .Test_en_E_out ( Test_enWires[106] ) , .pReset_N_in ( pResetWires[243] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1399 ) , + .Reset_W_in ( ResetWires[105] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1400 ) , + .Reset_E_out ( ResetWires[106] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1401 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[178] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[338] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[339] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1402 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1403 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1404 ) , + .clk_0_S_in ( clk_1_wires[178] ) ) ; +grid_clb grid_clb_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1405 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[92] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1406 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[92] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1407 } ) , + .ccff_head ( cby_1__1__88_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_100_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_100_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_100_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_100_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_100_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_100_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_100_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_100_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[91] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1408 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[91] ) , + .ccff_tail ( grid_clb_100_ccff_tail ) , .SC_IN_TOP ( scff_Wires[227] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1409 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1410 ) , + .SC_OUT_BOT ( scff_Wires[228] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1411 ) , + .Test_en_W_in ( Test_enWires[127] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1412 ) , + .Test_en_E_out ( Test_enWires[128] ) , .pReset_N_in ( pResetWires[292] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1413 ) , + .Reset_W_in ( ResetWires[127] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1414 ) , + .Reset_E_out ( ResetWires[128] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[186] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1415 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[341] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[342] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1416 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1417 ) , + .clk_0_N_in ( clk_1_wires[186] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1418 ) ) ; +grid_clb grid_clb_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1419 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[93] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1420 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[93] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1421 } ) , + .ccff_head ( cby_1__1__89_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_101_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_101_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_101_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_101_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_101_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_101_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_101_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_101_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[92] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1422 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[92] ) , + .ccff_tail ( grid_clb_101_ccff_tail ) , .SC_IN_TOP ( scff_Wires[225] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1423 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1424 ) , + .SC_OUT_BOT ( scff_Wires[226] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1425 ) , + .Test_en_W_in ( Test_enWires[149] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1426 ) , + .Test_en_E_out ( Test_enWires[150] ) , .pReset_N_in ( pResetWires[341] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1427 ) , + .Reset_W_in ( ResetWires[149] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1428 ) , + .Reset_E_out ( ResetWires[150] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1429 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[185] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[344] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[345] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1430 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1431 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1432 ) , + .clk_0_S_in ( clk_1_wires[185] ) ) ; +grid_clb grid_clb_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1433 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[94] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1434 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[94] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1435 } ) , + .ccff_head ( cby_1__1__90_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_102_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_102_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_102_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_102_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_102_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_102_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_102_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_102_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[93] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1436 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[93] ) , + .ccff_tail ( grid_clb_102_ccff_tail ) , .SC_IN_TOP ( scff_Wires[223] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1437 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1438 ) , + .SC_OUT_BOT ( scff_Wires[224] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1439 ) , + .Test_en_W_in ( Test_enWires[171] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1440 ) , + .Test_en_E_out ( Test_enWires[172] ) , .pReset_N_in ( pResetWires[390] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1441 ) , + .Reset_W_in ( ResetWires[171] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1442 ) , + .Reset_E_out ( ResetWires[172] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[193] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1443 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[347] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[348] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1444 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1445 ) , + .clk_0_N_in ( clk_1_wires[193] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1446 ) ) ; +grid_clb grid_clb_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1447 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[95] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1448 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[95] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1449 } ) , + .ccff_head ( cby_1__1__91_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_103_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_103_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_103_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_103_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_103_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_103_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_103_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_103_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[94] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1450 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[94] ) , + .ccff_tail ( grid_clb_103_ccff_tail ) , .SC_IN_TOP ( scff_Wires[221] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1451 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1452 ) , + .SC_OUT_BOT ( scff_Wires[222] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1453 ) , + .Test_en_W_in ( Test_enWires[193] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1454 ) , + .Test_en_E_out ( Test_enWires[194] ) , .pReset_N_in ( pResetWires[439] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1455 ) , + .Reset_W_in ( ResetWires[193] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1456 ) , + .Reset_E_out ( ResetWires[194] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1457 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[192] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[350] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[351] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1458 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1459 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1460 ) , + .clk_0_S_in ( clk_1_wires[192] ) ) ; +grid_clb grid_clb_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1461 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[96] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1462 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[96] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1463 } ) , + .ccff_head ( cby_1__1__92_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_104_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_104_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_104_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_104_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_104_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_104_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_104_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_104_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[95] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1464 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[95] ) , + .ccff_tail ( grid_clb_104_ccff_tail ) , .SC_IN_TOP ( scff_Wires[219] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1465 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1466 ) , + .SC_OUT_BOT ( scff_Wires[220] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1467 ) , + .Test_en_W_in ( Test_enWires[215] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1468 ) , + .Test_en_E_out ( Test_enWires[216] ) , .pReset_N_in ( pResetWires[488] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1469 ) , + .Reset_W_in ( ResetWires[215] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1470 ) , + .Reset_E_out ( ResetWires[216] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[200] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1471 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[353] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[354] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1472 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1473 ) , + .clk_0_N_in ( clk_1_wires[200] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1474 ) ) ; +grid_clb grid_clb_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1475 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[97] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1476 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[97] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1477 } ) , + .ccff_head ( cby_1__1__93_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_105_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_105_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_105_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_105_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_105_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_105_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_105_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_105_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[96] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1478 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[96] ) , + .ccff_tail ( grid_clb_105_ccff_tail ) , .SC_IN_TOP ( scff_Wires[217] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1479 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1480 ) , + .SC_OUT_BOT ( scff_Wires[218] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1481 ) , + .Test_en_W_in ( Test_enWires[237] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1482 ) , + .Test_en_E_out ( Test_enWires[238] ) , .pReset_N_in ( pResetWires[537] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1483 ) , + .Reset_W_in ( ResetWires[237] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1484 ) , + .Reset_E_out ( ResetWires[238] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1485 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[199] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[356] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[357] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1486 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1487 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1488 ) , + .clk_0_S_in ( clk_1_wires[199] ) ) ; +grid_clb grid_clb_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1489 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[98] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1490 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[98] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1491 } ) , + .ccff_head ( cby_1__1__94_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_106_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_106_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_106_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_106_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_106_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_106_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_106_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_106_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[97] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1492 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[97] ) , + .ccff_tail ( grid_clb_106_ccff_tail ) , .SC_IN_TOP ( scff_Wires[215] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1493 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1494 ) , + .SC_OUT_BOT ( scff_Wires[216] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1495 ) , + .Test_en_W_in ( Test_enWires[259] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1496 ) , + .Test_en_E_out ( Test_enWires[260] ) , .pReset_N_in ( pResetWires[586] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1497 ) , + .Reset_W_in ( ResetWires[259] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1498 ) , + .Reset_E_out ( ResetWires[260] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[207] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1499 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[359] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[360] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1500 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1501 ) , + .clk_0_N_in ( clk_1_wires[207] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1502 ) ) ; +grid_clb grid_clb_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1503 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1504 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_9__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1505 } ) , + .ccff_head ( cby_1__1__95_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_107_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_107_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_107_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_107_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_107_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_107_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_107_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_107_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[98] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1506 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[98] ) , + .ccff_tail ( grid_clb_107_ccff_tail ) , .SC_IN_TOP ( scff_Wires[213] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1507 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1508 ) , + .SC_OUT_BOT ( scff_Wires[214] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1509 ) , + .Test_en_W_in ( Test_enWires[281] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1510 ) , + .Test_en_E_out ( Test_enWires[282] ) , .pReset_N_in ( pResetWires[627] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1511 ) , + .Reset_W_in ( ResetWires[281] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1512 ) , + .Reset_E_out ( ResetWires[282] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1513 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[206] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[362] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[363] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1514 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[365] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1515 ) , + .clk_0_S_in ( clk_1_wires[206] ) ) ; +grid_clb grid_clb_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1516 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[99] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1517 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[99] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1518 } ) , + .ccff_head ( cby_1__1__96_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_108_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_108_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_108_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_108_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_108_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_108_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_108_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_108_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1519 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_10__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_108_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1520 ) , + .SC_IN_BOT ( scff_Wires[240] ) , .SC_OUT_TOP ( scff_Wires[241] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1521 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1522 ) , + .Test_en_W_in ( Test_enWires[41] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1523 ) , + .Test_en_E_out ( Test_enWires[42] ) , .pReset_N_in ( pResetWires[100] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1524 ) , + .Reset_W_in ( ResetWires[41] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1525 ) , + .Reset_E_out ( ResetWires[42] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[174] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1526 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[367] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[368] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1527 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1528 ) , + .clk_0_N_in ( clk_1_wires[174] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1529 ) ) ; +grid_clb grid_clb_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1530 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[100] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1531 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[100] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1532 } ) , + .ccff_head ( cby_1__1__97_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_109_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_109_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_109_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_109_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_109_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_109_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_109_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_109_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[99] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1533 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[99] ) , + .ccff_tail ( grid_clb_109_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1534 ) , + .SC_IN_BOT ( scff_Wires[242] ) , .SC_OUT_TOP ( scff_Wires[243] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1535 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1536 ) , + .Test_en_W_in ( Test_enWires[63] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1537 ) , + .Test_en_E_out ( Test_enWires[64] ) , .pReset_N_in ( pResetWires[149] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1538 ) , + .Reset_W_in ( ResetWires[63] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1539 ) , + .Reset_E_out ( ResetWires[64] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1540 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[173] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[370] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[371] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1541 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1542 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1543 ) , + .clk_0_S_in ( clk_1_wires[173] ) ) ; +grid_clb grid_clb_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1544 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[101] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1545 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[101] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1546 } ) , + .ccff_head ( cby_1__1__98_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_110_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_110_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_110_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_110_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_110_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_110_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_110_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_110_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[100] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1547 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[100] ) , + .ccff_tail ( grid_clb_110_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1548 ) , + .SC_IN_BOT ( scff_Wires[244] ) , .SC_OUT_TOP ( scff_Wires[245] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1549 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1550 ) , + .Test_en_W_in ( Test_enWires[85] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1551 ) , + .Test_en_E_out ( Test_enWires[86] ) , .pReset_N_in ( pResetWires[198] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1552 ) , + .Reset_W_in ( ResetWires[85] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1553 ) , + .Reset_E_out ( ResetWires[86] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[181] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1554 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[373] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[374] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1555 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1556 ) , + .clk_0_N_in ( clk_1_wires[181] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1557 ) ) ; +grid_clb grid_clb_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1558 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[102] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1559 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[102] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1560 } ) , + .ccff_head ( cby_1__1__99_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_111_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_111_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_111_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_111_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_111_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_111_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_111_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_111_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[101] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1561 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[101] ) , + .ccff_tail ( grid_clb_111_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1562 ) , + .SC_IN_BOT ( scff_Wires[246] ) , .SC_OUT_TOP ( scff_Wires[247] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1563 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1564 ) , + .Test_en_W_in ( Test_enWires[107] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1565 ) , + .Test_en_E_out ( Test_enWires[108] ) , .pReset_N_in ( pResetWires[247] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1566 ) , + .Reset_W_in ( ResetWires[107] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1567 ) , + .Reset_E_out ( ResetWires[108] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1568 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[180] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[376] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[377] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1569 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1570 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1571 ) , + .clk_0_S_in ( clk_1_wires[180] ) ) ; +grid_clb grid_clb_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1572 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[103] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1573 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[103] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1574 } ) , + .ccff_head ( cby_1__1__100_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_112_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_112_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_112_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_112_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_112_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_112_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_112_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_112_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[102] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1575 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[102] ) , + .ccff_tail ( grid_clb_112_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1576 ) , + .SC_IN_BOT ( scff_Wires[248] ) , .SC_OUT_TOP ( scff_Wires[249] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1577 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1578 ) , + .Test_en_W_in ( Test_enWires[129] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1579 ) , + .Test_en_E_out ( Test_enWires[130] ) , .pReset_N_in ( pResetWires[296] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1580 ) , + .Reset_W_in ( ResetWires[129] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1581 ) , + .Reset_E_out ( ResetWires[130] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[188] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1582 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[379] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[380] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1583 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1584 ) , + .clk_0_N_in ( clk_1_wires[188] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1585 ) ) ; +grid_clb grid_clb_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1586 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[104] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1587 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[104] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1588 } ) , + .ccff_head ( cby_1__1__101_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_113_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_113_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_113_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_113_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_113_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_113_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_113_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_113_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[103] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1589 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[103] ) , + .ccff_tail ( grid_clb_113_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1590 ) , + .SC_IN_BOT ( scff_Wires[250] ) , .SC_OUT_TOP ( scff_Wires[251] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1591 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1592 ) , + .Test_en_W_in ( Test_enWires[151] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1593 ) , + .Test_en_E_out ( Test_enWires[152] ) , .pReset_N_in ( pResetWires[345] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1594 ) , + .Reset_W_in ( ResetWires[151] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1595 ) , + .Reset_E_out ( ResetWires[152] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1596 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[187] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[382] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[383] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1597 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1598 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1599 ) , + .clk_0_S_in ( clk_1_wires[187] ) ) ; +grid_clb grid_clb_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1600 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[105] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1601 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[105] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1602 } ) , + .ccff_head ( cby_1__1__102_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_114_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_114_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_114_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_114_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_114_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_114_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_114_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_114_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[104] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1603 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[104] ) , + .ccff_tail ( grid_clb_114_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1604 ) , + .SC_IN_BOT ( scff_Wires[252] ) , .SC_OUT_TOP ( scff_Wires[253] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1605 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1606 ) , + .Test_en_W_in ( Test_enWires[173] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1607 ) , + .Test_en_E_out ( Test_enWires[174] ) , .pReset_N_in ( pResetWires[394] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1608 ) , + .Reset_W_in ( ResetWires[173] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1609 ) , + .Reset_E_out ( ResetWires[174] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[195] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1610 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[385] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[386] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1611 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1612 ) , + .clk_0_N_in ( clk_1_wires[195] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1613 ) ) ; +grid_clb grid_clb_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1614 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[106] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1615 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[106] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1616 } ) , + .ccff_head ( cby_1__1__103_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_115_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_115_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_115_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_115_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_115_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_115_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_115_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_115_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[105] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1617 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[105] ) , + .ccff_tail ( grid_clb_115_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1618 ) , + .SC_IN_BOT ( scff_Wires[254] ) , .SC_OUT_TOP ( scff_Wires[255] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1619 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1620 ) , + .Test_en_W_in ( Test_enWires[195] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1621 ) , + .Test_en_E_out ( Test_enWires[196] ) , .pReset_N_in ( pResetWires[443] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1622 ) , + .Reset_W_in ( ResetWires[195] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1623 ) , + .Reset_E_out ( ResetWires[196] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1624 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[194] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[388] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[389] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1625 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1626 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1627 ) , + .clk_0_S_in ( clk_1_wires[194] ) ) ; +grid_clb grid_clb_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1628 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[107] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1629 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[107] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1630 } ) , + .ccff_head ( cby_1__1__104_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_116_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_116_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_116_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_116_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_116_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_116_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_116_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_116_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[106] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1631 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[106] ) , + .ccff_tail ( grid_clb_116_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1632 ) , + .SC_IN_BOT ( scff_Wires[256] ) , .SC_OUT_TOP ( scff_Wires[257] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1633 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1634 ) , + .Test_en_W_in ( Test_enWires[217] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1635 ) , + .Test_en_E_out ( Test_enWires[218] ) , .pReset_N_in ( pResetWires[492] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1636 ) , + .Reset_W_in ( ResetWires[217] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1637 ) , + .Reset_E_out ( ResetWires[218] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[202] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1638 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[391] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[392] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1639 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1640 ) , + .clk_0_N_in ( clk_1_wires[202] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1641 ) ) ; +grid_clb grid_clb_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1642 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[108] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1643 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[108] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1644 } ) , + .ccff_head ( cby_1__1__105_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_117_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_117_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_117_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_117_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_117_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_117_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_117_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_117_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[107] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1645 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[107] ) , + .ccff_tail ( grid_clb_117_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1646 ) , + .SC_IN_BOT ( scff_Wires[258] ) , .SC_OUT_TOP ( scff_Wires[259] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1647 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1648 ) , + .Test_en_W_in ( Test_enWires[239] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1649 ) , + .Test_en_E_out ( Test_enWires[240] ) , .pReset_N_in ( pResetWires[541] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1650 ) , + .Reset_W_in ( ResetWires[239] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1651 ) , + .Reset_E_out ( ResetWires[240] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1652 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[201] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[394] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[395] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1653 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1654 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1655 ) , + .clk_0_S_in ( clk_1_wires[201] ) ) ; +grid_clb grid_clb_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1656 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[109] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1657 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[109] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1658 } ) , + .ccff_head ( cby_1__1__106_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_118_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_118_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_118_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_118_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_118_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_118_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_118_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_118_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[108] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1659 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[108] ) , + .ccff_tail ( grid_clb_118_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1660 ) , + .SC_IN_BOT ( scff_Wires[260] ) , .SC_OUT_TOP ( scff_Wires[261] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1661 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1662 ) , + .Test_en_W_in ( Test_enWires[261] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1663 ) , + .Test_en_E_out ( Test_enWires[262] ) , .pReset_N_in ( pResetWires[590] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1664 ) , + .Reset_W_in ( ResetWires[261] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1665 ) , + .Reset_E_out ( ResetWires[262] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[209] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1666 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[397] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[398] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1667 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1668 ) , + .clk_0_N_in ( clk_1_wires[209] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1669 ) ) ; +grid_clb grid_clb_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1670 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1671 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_10__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1672 } ) , + .ccff_head ( cby_1__1__107_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_119_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_119_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_119_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_119_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_119_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_119_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_119_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_119_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[109] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1673 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[109] ) , + .ccff_tail ( grid_clb_119_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1674 ) , + .SC_IN_BOT ( scff_Wires[262] ) , .SC_OUT_TOP ( scff_Wires[263] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1675 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1676 ) , + .Test_en_W_in ( Test_enWires[283] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1677 ) , + .Test_en_E_out ( Test_enWires[284] ) , .pReset_N_in ( pResetWires[630] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1678 ) , + .Reset_W_in ( ResetWires[283] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1679 ) , + .Reset_E_out ( ResetWires[284] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1680 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[208] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[400] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[401] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1681 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[403] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1682 ) , + .clk_0_S_in ( clk_1_wires[208] ) ) ; +grid_clb grid_clb_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1683 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[110] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1684 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[110] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1685 } ) , + .ccff_head ( cby_1__1__108_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_120_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_120_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_120_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_120_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_120_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_120_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_120_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_120_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1686 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_11__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[288] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1687 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1688 ) , + .SC_OUT_BOT ( scff_Wires[290] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1689 ) , + .Test_en_W_in ( Test_enWires[43] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1690 ) , + .Test_en_E_out ( Test_enWires[44] ) , .pReset_N_in ( pResetWires[104] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1691 ) , + .Reset_W_in ( ResetWires[43] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1692 ) , + .Reset_E_out ( ResetWires[44] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[214] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1693 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[405] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[406] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1694 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1695 ) , + .clk_0_N_in ( clk_1_wires[214] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1696 ) ) ; +grid_clb grid_clb_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1697 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[111] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1698 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[111] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1699 } ) , + .ccff_head ( cby_1__1__109_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_121_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_121_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_121_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_121_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_121_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_121_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_121_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_121_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[110] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1700 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[110] ) , + .ccff_tail ( grid_clb_121_ccff_tail ) , .SC_IN_TOP ( scff_Wires[286] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1701 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1702 ) , + .SC_OUT_BOT ( scff_Wires[287] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1703 ) , + .Test_en_W_in ( Test_enWires[65] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1704 ) , + .Test_en_E_out ( Test_enWires[66] ) , .pReset_N_in ( pResetWires[153] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1705 ) , + .Reset_W_in ( ResetWires[65] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1706 ) , + .Reset_E_out ( ResetWires[66] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1707 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[213] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[408] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[409] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1708 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1709 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1710 ) , + .clk_0_S_in ( clk_1_wires[213] ) ) ; +grid_clb grid_clb_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1711 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[112] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1712 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[112] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1713 } ) , + .ccff_head ( cby_1__1__110_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_122_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_122_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_122_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_122_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_122_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_122_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_122_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_122_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[111] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1714 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[111] ) , + .ccff_tail ( grid_clb_122_ccff_tail ) , .SC_IN_TOP ( scff_Wires[284] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1715 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1716 ) , + .SC_OUT_BOT ( scff_Wires[285] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1717 ) , + .Test_en_W_in ( Test_enWires[87] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1718 ) , + .Test_en_E_out ( Test_enWires[88] ) , .pReset_N_in ( pResetWires[202] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1719 ) , + .Reset_W_in ( ResetWires[87] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1720 ) , + .Reset_E_out ( ResetWires[88] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[221] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1721 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[411] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[412] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1722 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1723 ) , + .clk_0_N_in ( clk_1_wires[221] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1724 ) ) ; +grid_clb grid_clb_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1725 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[113] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1726 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[113] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1727 } ) , + .ccff_head ( cby_1__1__111_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_123_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_123_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_123_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_123_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_123_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_123_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_123_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_123_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[112] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1728 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[112] ) , + .ccff_tail ( grid_clb_123_ccff_tail ) , .SC_IN_TOP ( scff_Wires[282] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1729 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1730 ) , + .SC_OUT_BOT ( scff_Wires[283] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1731 ) , + .Test_en_W_in ( Test_enWires[109] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1732 ) , + .Test_en_E_out ( Test_enWires[110] ) , .pReset_N_in ( pResetWires[251] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1733 ) , + .Reset_W_in ( ResetWires[109] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1734 ) , + .Reset_E_out ( ResetWires[110] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1735 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[220] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[414] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[415] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1736 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1737 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1738 ) , + .clk_0_S_in ( clk_1_wires[220] ) ) ; +grid_clb grid_clb_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1739 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[114] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1740 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[114] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1741 } ) , + .ccff_head ( cby_1__1__112_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_124_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_124_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_124_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_124_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_124_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_124_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_124_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_124_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[113] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1742 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[113] ) , + .ccff_tail ( grid_clb_124_ccff_tail ) , .SC_IN_TOP ( scff_Wires[280] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1743 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1744 ) , + .SC_OUT_BOT ( scff_Wires[281] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1745 ) , + .Test_en_W_in ( Test_enWires[131] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1746 ) , + .Test_en_E_out ( Test_enWires[132] ) , .pReset_N_in ( pResetWires[300] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1747 ) , + .Reset_W_in ( ResetWires[131] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1748 ) , + .Reset_E_out ( ResetWires[132] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[228] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1749 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[417] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[418] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1750 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1751 ) , + .clk_0_N_in ( clk_1_wires[228] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1752 ) ) ; +grid_clb grid_clb_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1753 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[115] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1754 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[115] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1755 } ) , + .ccff_head ( cby_1__1__113_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_125_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_125_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_125_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_125_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_125_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_125_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_125_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_125_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[114] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1756 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[114] ) , + .ccff_tail ( grid_clb_125_ccff_tail ) , .SC_IN_TOP ( scff_Wires[278] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1757 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1758 ) , + .SC_OUT_BOT ( scff_Wires[279] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1759 ) , + .Test_en_W_in ( Test_enWires[153] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1760 ) , + .Test_en_E_out ( Test_enWires[154] ) , .pReset_N_in ( pResetWires[349] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1761 ) , + .Reset_W_in ( ResetWires[153] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1762 ) , + .Reset_E_out ( ResetWires[154] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1763 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[227] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[420] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[421] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1764 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1765 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1766 ) , + .clk_0_S_in ( clk_1_wires[227] ) ) ; +grid_clb grid_clb_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1767 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[116] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1768 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[116] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1769 } ) , + .ccff_head ( cby_1__1__114_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_126_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_126_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_126_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_126_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_126_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_126_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_126_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_126_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[115] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1770 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[115] ) , + .ccff_tail ( grid_clb_126_ccff_tail ) , .SC_IN_TOP ( scff_Wires[276] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1771 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1772 ) , + .SC_OUT_BOT ( scff_Wires[277] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1773 ) , + .Test_en_W_in ( Test_enWires[175] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1774 ) , + .Test_en_E_out ( Test_enWires[176] ) , .pReset_N_in ( pResetWires[398] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1775 ) , + .Reset_W_in ( ResetWires[175] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1776 ) , + .Reset_E_out ( ResetWires[176] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[235] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1777 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[423] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[424] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1778 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1779 ) , + .clk_0_N_in ( clk_1_wires[235] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1780 ) ) ; +grid_clb grid_clb_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1781 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[117] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1782 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[117] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1783 } ) , + .ccff_head ( cby_1__1__115_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_127_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_127_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_127_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_127_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_127_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_127_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_127_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_127_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[116] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1784 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[116] ) , + .ccff_tail ( grid_clb_127_ccff_tail ) , .SC_IN_TOP ( scff_Wires[274] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1785 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1786 ) , + .SC_OUT_BOT ( scff_Wires[275] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1787 ) , + .Test_en_W_in ( Test_enWires[197] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1788 ) , + .Test_en_E_out ( Test_enWires[198] ) , .pReset_N_in ( pResetWires[447] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1789 ) , + .Reset_W_in ( ResetWires[197] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1790 ) , + .Reset_E_out ( ResetWires[198] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1791 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[234] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[426] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[427] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1792 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1793 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1794 ) , + .clk_0_S_in ( clk_1_wires[234] ) ) ; +grid_clb grid_clb_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1795 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[118] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1796 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[118] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1797 } ) , + .ccff_head ( cby_1__1__116_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_128_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_128_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_128_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_128_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_128_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_128_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_128_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_128_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[117] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1798 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[117] ) , + .ccff_tail ( grid_clb_128_ccff_tail ) , .SC_IN_TOP ( scff_Wires[272] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1799 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1800 ) , + .SC_OUT_BOT ( scff_Wires[273] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1801 ) , + .Test_en_W_in ( Test_enWires[219] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1802 ) , + .Test_en_E_out ( Test_enWires[220] ) , .pReset_N_in ( pResetWires[496] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1803 ) , + .Reset_W_in ( ResetWires[219] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1804 ) , + .Reset_E_out ( ResetWires[220] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[242] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1805 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[429] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[430] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1806 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1807 ) , + .clk_0_N_in ( clk_1_wires[242] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1808 ) ) ; +grid_clb grid_clb_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1809 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[119] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1810 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[119] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1811 } ) , + .ccff_head ( cby_1__1__117_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_129_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_129_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_129_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_129_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_129_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_129_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_129_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_129_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[118] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1812 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[118] ) , + .ccff_tail ( grid_clb_129_ccff_tail ) , .SC_IN_TOP ( scff_Wires[270] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1813 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1814 ) , + .SC_OUT_BOT ( scff_Wires[271] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1815 ) , + .Test_en_W_in ( Test_enWires[241] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1816 ) , + .Test_en_E_out ( Test_enWires[242] ) , .pReset_N_in ( pResetWires[545] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1817 ) , + .Reset_W_in ( ResetWires[241] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1818 ) , + .Reset_E_out ( ResetWires[242] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1819 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[241] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[432] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[433] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1820 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1821 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1822 ) , + .clk_0_S_in ( clk_1_wires[241] ) ) ; +grid_clb grid_clb_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1823 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[120] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1824 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[120] ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1825 } ) , + .ccff_head ( cby_1__1__118_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_130_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_130_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_130_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_130_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_130_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_130_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_130_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_130_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[119] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1826 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[119] ) , + .ccff_tail ( grid_clb_130_ccff_tail ) , .SC_IN_TOP ( scff_Wires[268] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1827 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1828 ) , + .SC_OUT_BOT ( scff_Wires[269] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1829 ) , + .Test_en_W_in ( Test_enWires[263] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1830 ) , + .Test_en_E_out ( Test_enWires[264] ) , .pReset_N_in ( pResetWires[594] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1831 ) , + .Reset_W_in ( ResetWires[263] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1832 ) , + .Reset_E_out ( ResetWires[264] ) , + .prog_clk_0_N_in ( prog_clk_1_wires[249] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1833 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[435] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[436] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1834 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1835 ) , + .clk_0_N_in ( clk_1_wires[249] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1836 ) ) ; +grid_clb grid_clb_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1837 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1838 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_11__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1839 } ) , + .ccff_head ( cby_1__1__119_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_131_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_131_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_131_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_131_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_131_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_131_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_131_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_131_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[120] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1840 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[120] ) , + .ccff_tail ( grid_clb_131_ccff_tail ) , .SC_IN_TOP ( scff_Wires[266] ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1841 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_1842 ) , + .SC_OUT_BOT ( scff_Wires[267] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1843 ) , + .Test_en_W_in ( Test_enWires[285] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1844 ) , + .Test_en_E_out ( Test_enWires[286] ) , .pReset_N_in ( pResetWires[633] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1845 ) , + .Reset_W_in ( ResetWires[285] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1846 ) , + .Reset_E_out ( ResetWires[286] ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1847 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[248] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[438] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[439] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1848 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[441] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1849 ) , + .clk_0_S_in ( clk_1_wires[248] ) ) ; +grid_clb grid_clb_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1850 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[121] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1851 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[121] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1852 } ) , + .ccff_head ( cby_1__1__120_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_132_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_132_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_132_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_132_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_132_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_132_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_132_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_132_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_52_ ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1853 } ) , + + .bottom_width_0_height_0__pin_54_ ( grid_clb_12__1__undriven_bottom_width_0_height_0__pin_54_ ) , + .ccff_tail ( grid_clb_132_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1854 ) , + .SC_IN_BOT ( scff_Wires[293] ) , .SC_OUT_TOP ( scff_Wires[294] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1855 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1856 ) , + .Test_en_W_in ( Test_enWires[45] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1857 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1858 ) , + .pReset_N_in ( pResetWires[108] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1859 ) , + .Reset_W_in ( ResetWires[45] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1860 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1861 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[216] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1862 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[443] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[444] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1863 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1864 ) , + .clk_0_N_in ( clk_1_wires[216] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1865 ) ) ; +grid_clb grid_clb_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1866 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[122] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1867 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[122] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1868 } ) , + .ccff_head ( cby_1__1__121_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_133_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_133_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_133_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_133_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_133_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_133_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_133_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_133_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[121] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1869 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[121] ) , + .ccff_tail ( grid_clb_133_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1870 ) , + .SC_IN_BOT ( scff_Wires[295] ) , .SC_OUT_TOP ( scff_Wires[296] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1871 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1872 ) , + .Test_en_W_in ( Test_enWires[67] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1873 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1874 ) , + .pReset_N_in ( pResetWires[157] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1875 ) , + .Reset_W_in ( ResetWires[67] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1876 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1877 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1878 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[215] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[446] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[447] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1879 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1880 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1881 ) , + .clk_0_S_in ( clk_1_wires[215] ) ) ; +grid_clb grid_clb_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1882 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[123] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1883 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[123] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1884 } ) , + .ccff_head ( cby_1__1__122_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_134_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_134_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_134_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_134_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_134_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_134_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_134_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_134_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[122] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1885 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[122] ) , + .ccff_tail ( grid_clb_134_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1886 ) , + .SC_IN_BOT ( scff_Wires[297] ) , .SC_OUT_TOP ( scff_Wires[298] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1887 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1888 ) , + .Test_en_W_in ( Test_enWires[89] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1889 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1890 ) , + .pReset_N_in ( pResetWires[206] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1891 ) , + .Reset_W_in ( ResetWires[89] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1892 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1893 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[223] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1894 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[449] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[450] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1895 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1896 ) , + .clk_0_N_in ( clk_1_wires[223] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1897 ) ) ; +grid_clb grid_clb_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1898 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[124] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1899 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[124] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1900 } ) , + .ccff_head ( cby_1__1__123_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_135_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_135_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_135_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_135_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_135_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_135_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_135_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_135_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[123] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1901 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[123] ) , + .ccff_tail ( grid_clb_135_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1902 ) , + .SC_IN_BOT ( scff_Wires[299] ) , .SC_OUT_TOP ( scff_Wires[300] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1903 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1904 ) , + .Test_en_W_in ( Test_enWires[111] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1905 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1906 ) , + .pReset_N_in ( pResetWires[255] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1907 ) , + .Reset_W_in ( ResetWires[111] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1908 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1909 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1910 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[222] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[452] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[453] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1911 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1912 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1913 ) , + .clk_0_S_in ( clk_1_wires[222] ) ) ; +grid_clb grid_clb_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1914 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[125] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1915 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[125] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1916 } ) , + .ccff_head ( cby_1__1__124_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_136_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_136_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_136_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_136_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_136_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_136_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_136_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_136_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[124] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1917 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[124] ) , + .ccff_tail ( grid_clb_136_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1918 ) , + .SC_IN_BOT ( scff_Wires[301] ) , .SC_OUT_TOP ( scff_Wires[302] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1919 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1920 ) , + .Test_en_W_in ( Test_enWires[133] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1921 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1922 ) , + .pReset_N_in ( pResetWires[304] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1923 ) , + .Reset_W_in ( ResetWires[133] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1924 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1925 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[230] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1926 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[455] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[456] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1927 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1928 ) , + .clk_0_N_in ( clk_1_wires[230] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1929 ) ) ; +grid_clb grid_clb_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1930 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[126] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1931 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[126] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1932 } ) , + .ccff_head ( cby_1__1__125_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_137_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_137_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_137_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_137_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_137_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_137_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_137_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_137_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[125] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1933 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[125] ) , + .ccff_tail ( grid_clb_137_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1934 ) , + .SC_IN_BOT ( scff_Wires[303] ) , .SC_OUT_TOP ( scff_Wires[304] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1935 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1936 ) , + .Test_en_W_in ( Test_enWires[155] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1937 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1938 ) , + .pReset_N_in ( pResetWires[353] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1939 ) , + .Reset_W_in ( ResetWires[155] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1940 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1941 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1942 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[229] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[458] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[459] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1943 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1944 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1945 ) , + .clk_0_S_in ( clk_1_wires[229] ) ) ; +grid_clb grid_clb_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1946 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[127] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1947 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[127] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1948 } ) , + .ccff_head ( cby_1__1__126_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_138_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_138_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_138_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_138_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_138_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_138_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_138_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_138_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[126] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1949 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[126] ) , + .ccff_tail ( grid_clb_138_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1950 ) , + .SC_IN_BOT ( scff_Wires[305] ) , .SC_OUT_TOP ( scff_Wires[306] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1951 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1952 ) , + .Test_en_W_in ( Test_enWires[177] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1953 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1954 ) , + .pReset_N_in ( pResetWires[402] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1955 ) , + .Reset_W_in ( ResetWires[177] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1956 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1957 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[237] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1958 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[461] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[462] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1959 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1960 ) , + .clk_0_N_in ( clk_1_wires[237] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1961 ) ) ; +grid_clb grid_clb_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1962 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[128] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1963 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[128] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1964 } ) , + .ccff_head ( cby_1__1__127_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_139_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_139_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_139_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_139_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_139_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_139_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_139_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_139_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[127] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1965 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[127] ) , + .ccff_tail ( grid_clb_139_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1966 ) , + .SC_IN_BOT ( scff_Wires[307] ) , .SC_OUT_TOP ( scff_Wires[308] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1967 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1968 ) , + .Test_en_W_in ( Test_enWires[199] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1969 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1970 ) , + .pReset_N_in ( pResetWires[451] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1971 ) , + .Reset_W_in ( ResetWires[199] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1972 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1973 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_1974 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[236] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[464] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[465] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1975 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1976 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_1977 ) , + .clk_0_S_in ( clk_1_wires[236] ) ) ; +grid_clb grid_clb_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1978 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[129] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1979 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[129] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1980 } ) , + .ccff_head ( cby_1__1__128_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_140_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_140_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_140_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_140_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_140_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_140_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_140_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_140_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[128] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1981 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[128] ) , + .ccff_tail ( grid_clb_140_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1982 ) , + .SC_IN_BOT ( scff_Wires[309] ) , .SC_OUT_TOP ( scff_Wires[310] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1983 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_1984 ) , + .Test_en_W_in ( Test_enWires[221] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_1985 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_1986 ) , + .pReset_N_in ( pResetWires[500] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_1987 ) , + .Reset_W_in ( ResetWires[221] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_1988 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_1989 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[244] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_1990 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[467] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[468] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_1991 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_1992 ) , + .clk_0_N_in ( clk_1_wires[244] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_1993 ) ) ; +grid_clb grid_clb_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_1994 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[130] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1995 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[130] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_1996 } ) , + .ccff_head ( cby_1__1__129_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_141_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_141_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_141_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_141_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_141_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_141_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_141_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_141_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[129] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_1997 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[129] ) , + .ccff_tail ( grid_clb_141_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_1998 ) , + .SC_IN_BOT ( scff_Wires[311] ) , .SC_OUT_TOP ( scff_Wires[312] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_1999 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2000 ) , + .Test_en_W_in ( Test_enWires[243] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2001 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2002 ) , + .pReset_N_in ( pResetWires[549] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2003 ) , + .Reset_W_in ( ResetWires[243] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2004 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2005 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2006 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[243] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[470] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[471] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2007 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2008 ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2009 ) , + .clk_0_S_in ( clk_1_wires[243] ) ) ; +grid_clb grid_clb_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2010 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( regout_feedthrough_wires[131] ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2011 } ) , + .top_width_0_height_0__pin_34_ ( cout_feedthrough_wires[131] ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_2012 } ) , + .ccff_head ( cby_1__1__130_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_142_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_142_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_142_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_142_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_142_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_142_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_142_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_142_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[130] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2013 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[130] ) , + .ccff_tail ( grid_clb_142_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2014 ) , + .SC_IN_BOT ( scff_Wires[313] ) , .SC_OUT_TOP ( scff_Wires[314] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2015 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2016 ) , + .Test_en_W_in ( Test_enWires[265] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2017 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2018 ) , + .pReset_N_in ( pResetWires[598] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2019 ) , + .Reset_W_in ( ResetWires[265] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2020 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2021 ) , + .prog_clk_0_N_in ( prog_clk_1_wires[251] ) , + .prog_clk_0_S_in ( SYNOPSYS_UNCONNECTED_2022 ) , + .prog_clk_0_S_out ( prog_clk_0_wires[473] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[474] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2023 ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_2024 ) , + .clk_0_N_in ( clk_1_wires[251] ) , + .clk_0_S_in ( SYNOPSYS_UNCONNECTED_2025 ) ) ; +grid_clb grid_clb_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2026 } ) , + .top_width_0_height_0__pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_2027 } ) , + + .top_width_0_height_0__pin_34_ ( grid_clb_12__12__undriven_top_width_0_height_0__pin_34_ ) , + .right_width_0_height_0__pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , + .right_width_0_height_0__pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , + .right_width_0_height_0__pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , + .right_width_0_height_0__pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , + .right_width_0_height_0__pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , + .right_width_0_height_0__pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , + .right_width_0_height_0__pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , + .right_width_0_height_0__pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , + .right_width_0_height_0__pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , + .right_width_0_height_0__pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , + .right_width_0_height_0__pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , + .right_width_0_height_0__pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , + .right_width_0_height_0__pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , + .right_width_0_height_0__pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , + .right_width_0_height_0__pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , + .right_width_0_height_0__pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , + .Reset ( { SYNOPSYS_UNCONNECTED_2028 } ) , + .ccff_head ( cby_1__1__131_ccff_tail ) , + .top_width_0_height_0__pin_36_upper ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , + .top_width_0_height_0__pin_36_lower ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , + .top_width_0_height_0__pin_37_upper ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , + .top_width_0_height_0__pin_37_lower ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , + .top_width_0_height_0__pin_38_upper ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , + .top_width_0_height_0__pin_38_lower ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , + .top_width_0_height_0__pin_39_upper ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , + .top_width_0_height_0__pin_39_lower ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , + .top_width_0_height_0__pin_40_upper ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , + .top_width_0_height_0__pin_40_lower ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , + .top_width_0_height_0__pin_41_upper ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , + .top_width_0_height_0__pin_41_lower ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , + .top_width_0_height_0__pin_42_upper ( grid_clb_143_top_width_0_height_0__pin_42_upper ) , + .top_width_0_height_0__pin_42_lower ( grid_clb_143_top_width_0_height_0__pin_42_lower ) , + .top_width_0_height_0__pin_43_upper ( grid_clb_143_top_width_0_height_0__pin_43_upper ) , + .top_width_0_height_0__pin_43_lower ( grid_clb_143_top_width_0_height_0__pin_43_lower ) , + .right_width_0_height_0__pin_44_upper ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , + .right_width_0_height_0__pin_44_lower ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , + .right_width_0_height_0__pin_45_upper ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , + .right_width_0_height_0__pin_45_lower ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , + .right_width_0_height_0__pin_46_upper ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , + .right_width_0_height_0__pin_46_lower ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , + .right_width_0_height_0__pin_47_upper ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , + .right_width_0_height_0__pin_47_lower ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , + .right_width_0_height_0__pin_48_upper ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , + .right_width_0_height_0__pin_48_lower ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , + .right_width_0_height_0__pin_49_upper ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , + .right_width_0_height_0__pin_49_lower ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , + .right_width_0_height_0__pin_50_upper ( grid_clb_143_right_width_0_height_0__pin_50_upper ) , + .right_width_0_height_0__pin_50_lower ( grid_clb_143_right_width_0_height_0__pin_50_lower ) , + .right_width_0_height_0__pin_51_upper ( grid_clb_143_right_width_0_height_0__pin_51_upper ) , + .right_width_0_height_0__pin_51_lower ( grid_clb_143_right_width_0_height_0__pin_51_lower ) , + .bottom_width_0_height_0__pin_52_ ( regin_feedthrough_wires[131] ) , + .bottom_width_0_height_0__pin_53_ ( { SYNOPSYS_UNCONNECTED_2029 } ) , + .bottom_width_0_height_0__pin_54_ ( cin_feedthrough_wires[131] ) , + .ccff_tail ( grid_clb_143_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_2030 ) , + .SC_IN_BOT ( scff_Wires[315] ) , .SC_OUT_TOP ( scff_Wires[316] ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_2031 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_2032 ) , + .Test_en_W_in ( Test_enWires[287] ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_2033 ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_2034 ) , + .pReset_N_in ( pResetWires[636] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_2035 ) , + .Reset_W_in ( ResetWires[287] ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_2036 ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_2037 ) , + .prog_clk_0_N_in ( SYNOPSYS_UNCONNECTED_2038 ) , + .prog_clk_0_S_in ( prog_clk_1_wires[250] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[476] ) , + .prog_clk_0_E_out ( prog_clk_0_wires[477] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_2039 ) , + .prog_clk_0_N_out ( prog_clk_0_wires[479] ) , + .clk_0_N_in ( SYNOPSYS_UNCONNECTED_2040 ) , + .clk_0_S_in ( clk_1_wires[250] ) ) ; +sb_0__0_ sb_0__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2041 } ) , + .chany_top_in ( cby_0__1__0_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , + .ccff_head ( grid_io_bottom_11_ccff_tail ) , + .chany_top_out ( sb_0__0__0_chany_top_out ) , + .chanx_right_out ( sb_0__0__0_chanx_right_out ) , + .ccff_tail ( ccff_tail ) , .pReset_E_in ( pResetWires[25] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[5] ) ) ; +sb_0__1_ sb_0__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2042 } ) , + .chany_top_in ( cby_0__1__1_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__0_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__0_ccff_tail ) , + .chany_top_out ( sb_0__1__0_chany_top_out ) , + .chanx_right_out ( sb_0__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , .pReset_E_in ( pResetWires[61] ) , + .pReset_S_out ( pResetWires[64] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[4] ) ) ; +sb_0__1_ sb_0__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2043 } ) , + .chany_top_in ( cby_0__1__2_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__1_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__1_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__1_ccff_tail ) , + .chany_top_out ( sb_0__1__1_chany_top_out ) , + .chanx_right_out ( sb_0__1__1_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__1_chany_bottom_out ) , + .ccff_tail ( sb_0__1__1_ccff_tail ) , .pReset_E_in ( pResetWires[110] ) , + .pReset_S_out ( pResetWires[113] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[10] ) ) ; +sb_0__1_ sb_0__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2044 } ) , + .chany_top_in ( cby_0__1__3_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__2_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__2_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__2_ccff_tail ) , + .chany_top_out ( sb_0__1__2_chany_top_out ) , + .chanx_right_out ( sb_0__1__2_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__2_chany_bottom_out ) , + .ccff_tail ( sb_0__1__2_ccff_tail ) , .pReset_E_in ( pResetWires[159] ) , + .pReset_S_out ( pResetWires[162] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[15] ) ) ; +sb_0__1_ sb_0__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2045 } ) , + .chany_top_in ( cby_0__1__4_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__3_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__3_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__3_ccff_tail ) , + .chany_top_out ( sb_0__1__3_chany_top_out ) , + .chanx_right_out ( sb_0__1__3_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__3_chany_bottom_out ) , + .ccff_tail ( sb_0__1__3_ccff_tail ) , .pReset_E_in ( pResetWires[208] ) , + .pReset_S_out ( pResetWires[211] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[20] ) ) ; +sb_0__1_ sb_0__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2046 } ) , + .chany_top_in ( cby_0__1__5_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__4_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__4_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__4_ccff_tail ) , + .chany_top_out ( sb_0__1__4_chany_top_out ) , + .chanx_right_out ( sb_0__1__4_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__4_chany_bottom_out ) , + .ccff_tail ( sb_0__1__4_ccff_tail ) , .pReset_E_in ( pResetWires[257] ) , + .pReset_S_out ( pResetWires[260] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[25] ) ) ; +sb_0__1_ sb_0__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2047 } ) , + .chany_top_in ( cby_0__1__6_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__5_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__5_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__5_ccff_tail ) , + .chany_top_out ( sb_0__1__5_chany_top_out ) , + .chanx_right_out ( sb_0__1__5_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__5_chany_bottom_out ) , + .ccff_tail ( sb_0__1__5_ccff_tail ) , .pReset_E_in ( pResetWires[306] ) , + .pReset_S_out ( pResetWires[309] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[30] ) ) ; +sb_0__1_ sb_0__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2048 } ) , + .chany_top_in ( cby_0__1__7_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__6_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__6_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__6_ccff_tail ) , + .chany_top_out ( sb_0__1__6_chany_top_out ) , + .chanx_right_out ( sb_0__1__6_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__6_chany_bottom_out ) , + .ccff_tail ( sb_0__1__6_ccff_tail ) , .pReset_E_in ( pResetWires[355] ) , + .pReset_S_out ( pResetWires[358] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[35] ) ) ; +sb_0__1_ sb_0__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2049 } ) , + .chany_top_in ( cby_0__1__8_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__7_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__7_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__7_ccff_tail ) , + .chany_top_out ( sb_0__1__7_chany_top_out ) , + .chanx_right_out ( sb_0__1__7_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__7_chany_bottom_out ) , + .ccff_tail ( sb_0__1__7_ccff_tail ) , .pReset_E_in ( pResetWires[404] ) , + .pReset_S_out ( pResetWires[407] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[40] ) ) ; +sb_0__1_ sb_0__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2050 } ) , + .chany_top_in ( cby_0__1__9_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__8_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__8_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__8_ccff_tail ) , + .chany_top_out ( sb_0__1__8_chany_top_out ) , + .chanx_right_out ( sb_0__1__8_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__8_chany_bottom_out ) , + .ccff_tail ( sb_0__1__8_ccff_tail ) , .pReset_E_in ( pResetWires[453] ) , + .pReset_S_out ( pResetWires[456] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[45] ) ) ; +sb_0__1_ sb_0__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2051 } ) , + .chany_top_in ( cby_0__1__10_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__9_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__9_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__9_ccff_tail ) , + .chany_top_out ( sb_0__1__9_chany_top_out ) , + .chanx_right_out ( sb_0__1__9_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__9_chany_bottom_out ) , + .ccff_tail ( sb_0__1__9_ccff_tail ) , .pReset_E_in ( pResetWires[502] ) , + .pReset_S_out ( pResetWires[505] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[50] ) ) ; +sb_0__1_ sb_0__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2052 } ) , + .chany_top_in ( cby_0__1__11_chany_bottom_out ) , + .top_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , + .chanx_right_in ( cbx_1__1__10_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__10_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( cbx_1__1__10_ccff_tail ) , + .chany_top_out ( sb_0__1__10_chany_top_out ) , + .chanx_right_out ( sb_0__1__10_chanx_right_out ) , + .chany_bottom_out ( sb_0__1__10_chany_bottom_out ) , + .ccff_tail ( sb_0__1__10_ccff_tail ) , .pReset_E_in ( pResetWires[551] ) , + .pReset_S_out ( pResetWires[554] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[55] ) ) ; +sb_0__2_ sb_0__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2053 } ) , + .chanx_right_in ( cbx_1__12__0_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_0__1__11_chany_top_out ) , + .bottom_left_grid_pin_1_ ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , + .ccff_head ( grid_io_top_0_ccff_tail ) , + .chanx_right_out ( sb_0__12__0_chanx_right_out ) , + .chany_bottom_out ( sb_0__12__0_chany_bottom_out ) , + .ccff_tail ( sb_0__12__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , + .SC_OUT_BOT ( scff_Wires[0] ) , .pReset_E_in ( pResetWires[600] ) , + .pReset_S_out ( pResetWires[603] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[62] ) ) ; +sb_1__0_ sb_1__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2054 } ) , + .chany_top_in ( cby_1__1__0_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__1_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__0_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_10_ccff_tail ) , + .chany_top_out ( sb_1__0__0_chany_top_out ) , + .chanx_right_out ( sb_1__0__0_chanx_right_out ) , + .chanx_left_out ( sb_1__0__0_chanx_left_out ) , + .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[26] ) , + .SC_OUT_TOP ( scff_Wires[27] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2055 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2056 ) , + .pReset_E_in ( pResetWires[28] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2057 ) , + .pReset_N_out ( pResetWires[27] ) , .pReset_W_out ( pResetWires[26] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2058 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2059 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[2] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2060 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2061 ) ) ; +sb_1__0_ sb_2__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2062 } ) , + .chany_top_in ( cby_1__1__12_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__2_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__1_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_9_ccff_tail ) , + .chany_top_out ( sb_1__0__1_chany_top_out ) , + .chanx_right_out ( sb_1__0__1_chanx_right_out ) , + .chanx_left_out ( sb_1__0__1_chanx_left_out ) , + .ccff_tail ( sb_1__0__1_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2063 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2064 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2065 ) , + .pReset_E_in ( pResetWires[31] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2066 ) , + .pReset_N_out ( pResetWires[30] ) , .pReset_W_out ( pResetWires[29] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2067 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2068 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[65] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2069 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2070 ) ) ; +sb_1__0_ sb_3__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2071 } ) , + .chany_top_in ( cby_1__1__24_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__3_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__2_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_8_ccff_tail ) , + .chany_top_out ( sb_1__0__2_chany_top_out ) , + .chanx_right_out ( sb_1__0__2_chanx_right_out ) , + .chanx_left_out ( sb_1__0__2_chanx_left_out ) , + .ccff_tail ( sb_1__0__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[79] ) , + .SC_OUT_TOP ( scff_Wires[80] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2072 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2073 ) , + .pReset_E_in ( pResetWires[34] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2074 ) , + .pReset_N_out ( pResetWires[33] ) , .pReset_W_out ( pResetWires[32] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2075 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2076 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[103] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2077 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2078 ) ) ; +sb_1__0_ sb_4__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2079 } ) , + .chany_top_in ( cby_1__1__36_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__4_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__3_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_7_ccff_tail ) , + .chany_top_out ( sb_1__0__3_chany_top_out ) , + .chanx_right_out ( sb_1__0__3_chanx_right_out ) , + .chanx_left_out ( sb_1__0__3_chanx_left_out ) , + .ccff_tail ( sb_1__0__3_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2080 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2081 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2082 ) , + .pReset_E_in ( pResetWires[37] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2083 ) , + .pReset_N_out ( pResetWires[36] ) , .pReset_W_out ( pResetWires[35] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2084 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2085 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[141] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2086 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2087 ) ) ; +sb_1__0_ sb_5__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2088 } ) , + .chany_top_in ( cby_1__1__48_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__5_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__4_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_6_ccff_tail ) , + .chany_top_out ( sb_1__0__4_chany_top_out ) , + .chanx_right_out ( sb_1__0__4_chanx_right_out ) , + .chanx_left_out ( sb_1__0__4_chanx_left_out ) , + .ccff_tail ( sb_1__0__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[132] ) , + .SC_OUT_TOP ( scff_Wires[133] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2089 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2090 ) , + .pReset_E_in ( pResetWires[40] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2091 ) , + .pReset_N_out ( pResetWires[39] ) , .pReset_W_out ( pResetWires[38] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2092 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2093 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[179] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2094 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2095 ) ) ; +sb_1__0_ sb_6__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2096 } ) , + .chany_top_in ( cby_1__1__60_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__6_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__5_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_5_ccff_tail ) , + .chany_top_out ( sb_1__0__5_chany_top_out ) , + .chanx_right_out ( sb_1__0__5_chanx_right_out ) , + .chanx_left_out ( sb_1__0__5_chanx_left_out ) , + .ccff_tail ( sb_1__0__5_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2097 ) , .Test_en_S_in ( Test_en[0] ) , + .Test_en_N_out ( Test_enWires[1] ) , .pReset_S_in ( pReset[0] ) , + .pReset_E_in ( h_incr0 ) , .pReset_W_in ( h_incr0 ) , + .pReset_N_out ( pResetWires[42] ) , .pReset_W_out ( pResetWires[41] ) , + .pReset_E_out ( pResetWires[43] ) , .Reset_S_in ( Reset[0] ) , + .Reset_N_out ( ResetWires[1] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[217] ) , + .prog_clk_3_S_in ( prog_clk[0] ) , + .prog_clk_3_N_out ( prog_clk_3_wires[90] ) , .clk_3_S_in ( clk[0] ) , + .clk_3_N_out ( clk_3_wires[90] ) ) ; +sb_1__0_ sb_7__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2098 } ) , + .chany_top_in ( cby_1__1__72_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__7_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__6_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_4_ccff_tail ) , + .chany_top_out ( sb_1__0__6_chany_top_out ) , + .chanx_right_out ( sb_1__0__6_chanx_right_out ) , + .chanx_left_out ( sb_1__0__6_chanx_left_out ) , + .ccff_tail ( sb_1__0__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[185] ) , + .SC_OUT_TOP ( scff_Wires[186] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2099 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2100 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2101 ) , + .pReset_W_in ( pResetWires[44] ) , .pReset_N_out ( pResetWires[45] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2102 ) , + .pReset_E_out ( pResetWires[46] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2103 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[255] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2104 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2105 ) ) ; +sb_1__0_ sb_8__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2106 } ) , + .chany_top_in ( cby_1__1__84_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__8_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__7_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_3_ccff_tail ) , + .chany_top_out ( sb_1__0__7_chany_top_out ) , + .chanx_right_out ( sb_1__0__7_chanx_right_out ) , + .chanx_left_out ( sb_1__0__7_chanx_left_out ) , + .ccff_tail ( sb_1__0__7_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2107 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2108 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2109 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2110 ) , + .pReset_W_in ( pResetWires[47] ) , .pReset_N_out ( pResetWires[48] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2111 ) , + .pReset_E_out ( pResetWires[49] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2112 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[293] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2113 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2114 ) ) ; +sb_1__0_ sb_9__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2115 } ) , + .chany_top_in ( cby_1__1__96_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__9_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__8_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_2_ccff_tail ) , + .chany_top_out ( sb_1__0__8_chany_top_out ) , + .chanx_right_out ( sb_1__0__8_chanx_right_out ) , + .chanx_left_out ( sb_1__0__8_chanx_left_out ) , + .ccff_tail ( sb_1__0__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[238] ) , + .SC_OUT_TOP ( scff_Wires[239] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2116 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2117 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2118 ) , + .pReset_W_in ( pResetWires[50] ) , .pReset_N_out ( pResetWires[51] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2119 ) , + .pReset_E_out ( pResetWires[52] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2120 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[331] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2121 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2122 ) ) ; +sb_1__0_ sb_10__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2123 } ) , + .chany_top_in ( cby_1__1__108_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__10_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__9_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_1_ccff_tail ) , + .chany_top_out ( sb_1__0__9_chany_top_out ) , + .chanx_right_out ( sb_1__0__9_chanx_right_out ) , + .chanx_left_out ( sb_1__0__9_chanx_left_out ) , + .ccff_tail ( sb_1__0__9_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2124 ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2125 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2126 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2127 ) , + .pReset_W_in ( pResetWires[53] ) , .pReset_N_out ( pResetWires[54] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2128 ) , + .pReset_E_out ( pResetWires[55] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2129 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[369] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2130 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2131 ) ) ; +sb_1__0_ sb_11__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2132 } ) , + .chany_top_in ( cby_1__1__120_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__0__11_chanx_left_out ) , + .right_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .right_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .right_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .right_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .right_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .right_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) , + .right_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) , + .right_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , + .chanx_left_in ( cbx_1__0__10_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_bottom_0_ccff_tail ) , + .chany_top_out ( sb_1__0__10_chany_top_out ) , + .chanx_right_out ( sb_1__0__10_chanx_right_out ) , + .chanx_left_out ( sb_1__0__10_chanx_left_out ) , + .ccff_tail ( sb_1__0__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[291] ) , + .SC_OUT_TOP ( scff_Wires[292] ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2133 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2134 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_2135 ) , + .pReset_W_in ( pResetWires[56] ) , .pReset_N_out ( pResetWires[57] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_2136 ) , + .pReset_E_out ( pResetWires[58] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2137 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[407] ) , + .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2138 ) , + .clk_3_S_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2139 ) ) ; +sb_1__1_ sb_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2140 } ) , + .chany_top_in ( cby_1__1__1_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__11_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__0_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_0_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_0_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_0_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_0_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_0_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_0_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_0_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__0_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_0_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_0_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_0_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_0_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_0_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_0_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_0_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_0_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__11_ccff_tail ) , + .chany_top_out ( sb_1__1__0_chany_top_out ) , + .chanx_right_out ( sb_1__1__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__0_chanx_left_out ) , + .ccff_tail ( sb_1__1__0_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2141 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2142 ) , + .pReset_E_in ( pResetWires[66] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2143 ) , + .pReset_N_out ( pResetWires[65] ) , .pReset_W_out ( pResetWires[62] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2144 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2145 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[8] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[4] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2146 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[1] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[2] ) , .prog_clk_2_N_in ( h_incr0 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2147 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2148 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2149 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2150 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2151 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2152 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2154 ) , + .clk_1_N_in ( clk_2_wires[4] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2155 ) , + .clk_1_E_out ( clk_1_wires[1] ) , .clk_1_W_out ( clk_1_wires[2] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2156 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2157 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2158 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2159 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2160 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2161 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2162 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2163 ) ) ; +sb_1__1_ sb_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2164 } ) , + .chany_top_in ( cby_1__1__2_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__12_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__1_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_1_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_1_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_1_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_1_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_1_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_1_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_1_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__1_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_1_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_1_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_1_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_1_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_1_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_1_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_1_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_1_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__12_ccff_tail ) , + .chany_top_out ( sb_1__1__1_chany_top_out ) , + .chanx_right_out ( sb_1__1__1_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__1_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__1_chanx_left_out ) , + .ccff_tail ( sb_1__1__1_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2165 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2166 ) , + .pReset_E_in ( pResetWires[115] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2167 ) , + .pReset_N_out ( pResetWires[114] ) , .pReset_W_out ( pResetWires[111] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2168 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2169 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[13] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2170 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2171 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2172 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[1] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2173 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2174 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2175 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[3] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2176 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2177 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2178 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2179 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2180 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2181 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2182 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2183 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2184 ) , + .clk_2_E_in ( clk_2_wires[1] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2185 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2186 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2187 ) , + .clk_2_S_out ( clk_2_wires[3] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2188 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2189 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2190 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2191 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2192 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2193 ) ) ; +sb_1__1_ sb_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2194 } ) , + .chany_top_in ( cby_1__1__3_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__13_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__2_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_2_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_2_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_2_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_2_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_2_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_2_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_2_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__2_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_2_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_2_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_2_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_2_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_2_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_2_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_2_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_2_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__13_ccff_tail ) , + .chany_top_out ( sb_1__1__2_chany_top_out ) , + .chanx_right_out ( sb_1__1__2_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__2_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__2_chanx_left_out ) , + .ccff_tail ( sb_1__1__2_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2195 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2196 ) , + .pReset_E_in ( pResetWires[164] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2197 ) , + .pReset_N_out ( pResetWires[163] ) , .pReset_W_out ( pResetWires[160] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2198 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2199 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[18] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[11] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2200 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[8] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[9] ) , .prog_clk_2_N_in ( h_incr0 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2201 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2202 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2203 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2204 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2205 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2206 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2207 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2208 ) , + .clk_1_N_in ( clk_2_wires[11] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2209 ) , + .clk_1_E_out ( clk_1_wires[8] ) , .clk_1_W_out ( clk_1_wires[9] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2210 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2211 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2212 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2213 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2214 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2215 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2216 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2217 ) ) ; +sb_1__1_ sb_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2218 } ) , + .chany_top_in ( cby_1__1__4_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__14_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__3_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_3_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_3_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_3_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_3_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_3_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_3_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_3_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__3_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_3_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_3_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_3_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_3_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_3_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_3_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_3_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_3_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__14_ccff_tail ) , + .chany_top_out ( sb_1__1__3_chany_top_out ) , + .chanx_right_out ( sb_1__1__3_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__3_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__3_chanx_left_out ) , + .ccff_tail ( sb_1__1__3_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2219 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2220 ) , + .pReset_E_in ( pResetWires[213] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2221 ) , + .pReset_N_out ( pResetWires[212] ) , .pReset_W_out ( pResetWires[209] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2222 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2223 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[23] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2224 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2225 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2226 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[6] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2227 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2228 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2229 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[10] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[8] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2230 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2231 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2232 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2233 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2234 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2235 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2236 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2237 ) , + .clk_2_E_in ( clk_2_wires[6] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2238 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2239 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2240 ) , + .clk_2_S_out ( clk_2_wires[10] ) , .clk_2_N_out ( clk_2_wires[8] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2241 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2242 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2243 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2244 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2245 ) ) ; +sb_1__1_ sb_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2246 } ) , + .chany_top_in ( cby_1__1__5_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__15_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__4_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_4_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_4_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_4_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_4_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_4_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_4_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_4_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_4_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__4_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_4_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_4_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_4_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_4_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_4_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_4_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_4_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_4_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__15_ccff_tail ) , + .chany_top_out ( sb_1__1__4_chany_top_out ) , + .chanx_right_out ( sb_1__1__4_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__4_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__4_chanx_left_out ) , + .ccff_tail ( sb_1__1__4_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2247 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2248 ) , + .pReset_E_in ( pResetWires[262] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2249 ) , + .pReset_N_out ( pResetWires[261] ) , .pReset_W_out ( pResetWires[258] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2250 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2251 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[28] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2252 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[9] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[15] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[16] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2253 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2254 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2255 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2256 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2257 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2258 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2259 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2260 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2261 ) , + .clk_1_S_in ( clk_2_wires[9] ) , .clk_1_E_out ( clk_1_wires[15] ) , + .clk_1_W_out ( clk_1_wires[16] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2262 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2263 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2264 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2265 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2266 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2267 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2268 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2269 ) ) ; +sb_1__1_ sb_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2270 } ) , + .chany_top_in ( cby_1__1__6_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__16_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__5_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_5_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_5_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_5_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_5_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_5_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_5_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_5_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_5_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__5_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_5_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_5_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_5_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_5_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_5_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_5_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_5_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_5_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__16_ccff_tail ) , + .chany_top_out ( sb_1__1__5_chany_top_out ) , + .chanx_right_out ( sb_1__1__5_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__5_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__5_chanx_left_out ) , + .ccff_tail ( sb_1__1__5_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2271 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2272 ) , + .pReset_E_in ( pResetWires[311] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2273 ) , + .pReset_N_out ( pResetWires[310] ) , .pReset_W_out ( pResetWires[307] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2274 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2275 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[33] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2276 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2277 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2278 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2279 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2280 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2281 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2282 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2283 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2284 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2285 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2286 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2287 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2288 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2289 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2290 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2291 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2292 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2293 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2294 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2295 ) ) ; +sb_1__1_ sb_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2296 } ) , + .chany_top_in ( cby_1__1__7_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__17_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__6_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_6_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_6_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_6_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_6_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_6_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_6_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_6_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_6_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__6_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_6_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_6_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_6_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_6_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_6_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_6_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_6_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_6_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__17_ccff_tail ) , + .chany_top_out ( sb_1__1__6_chany_top_out ) , + .chanx_right_out ( sb_1__1__6_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__6_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__6_chanx_left_out ) , + .ccff_tail ( sb_1__1__6_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2297 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2298 ) , + .pReset_E_in ( pResetWires[360] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2299 ) , + .pReset_N_out ( pResetWires[359] ) , .pReset_W_out ( pResetWires[356] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2300 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2301 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[38] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[18] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2302 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[22] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[23] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2303 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2304 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2305 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2306 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2307 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2308 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2309 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2310 ) , + .clk_1_N_in ( clk_2_wires[18] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2311 ) , + .clk_1_E_out ( clk_1_wires[22] ) , .clk_1_W_out ( clk_1_wires[23] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2312 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2313 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2314 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2315 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2316 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2317 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2318 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2319 ) ) ; +sb_1__1_ sb_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2320 } ) , + .chany_top_in ( cby_1__1__8_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__18_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__7_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_7_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_7_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_7_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_7_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_7_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_7_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_7_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_7_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__7_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_7_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_7_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_7_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_7_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_7_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_7_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_7_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_7_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__18_ccff_tail ) , + .chany_top_out ( sb_1__1__7_chany_top_out ) , + .chanx_right_out ( sb_1__1__7_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__7_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__7_chanx_left_out ) , + .ccff_tail ( sb_1__1__7_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2321 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2322 ) , + .pReset_E_in ( pResetWires[409] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2323 ) , + .pReset_N_out ( pResetWires[408] ) , .pReset_W_out ( pResetWires[405] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2324 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2325 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[43] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2326 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2327 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2328 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[13] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2329 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2330 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2331 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[17] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[15] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2332 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2333 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2334 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2335 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2336 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2337 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2338 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2339 ) , + .clk_2_E_in ( clk_2_wires[13] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2340 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2341 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2342 ) , + .clk_2_S_out ( clk_2_wires[17] ) , .clk_2_N_out ( clk_2_wires[15] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2343 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2345 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2346 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2347 ) ) ; +sb_1__1_ sb_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2348 } ) , + .chany_top_in ( cby_1__1__9_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__19_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__8_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_8_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_8_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_8_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_8_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_8_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_8_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_8_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_8_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__8_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_8_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_8_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_8_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_8_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_8_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_8_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_8_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_8_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__19_ccff_tail ) , + .chany_top_out ( sb_1__1__8_chany_top_out ) , + .chanx_right_out ( sb_1__1__8_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__8_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__8_chanx_left_out ) , + .ccff_tail ( sb_1__1__8_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2349 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2350 ) , + .pReset_E_in ( pResetWires[458] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2351 ) , + .pReset_N_out ( pResetWires[457] ) , .pReset_W_out ( pResetWires[454] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2352 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2353 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[48] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2354 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[16] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[29] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[30] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2355 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2356 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2357 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2358 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2359 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2360 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2361 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2362 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2363 ) , + .clk_1_S_in ( clk_2_wires[16] ) , .clk_1_E_out ( clk_1_wires[29] ) , + .clk_1_W_out ( clk_1_wires[30] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2364 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2365 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2366 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2367 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2368 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2369 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2370 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2371 ) ) ; +sb_1__1_ sb_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2372 } ) , + .chany_top_in ( cby_1__1__10_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__20_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__9_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_9_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_9_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_9_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_9_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_9_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_9_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_9_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_9_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__9_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_9_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_9_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_9_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_9_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_9_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_9_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_9_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_9_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__20_ccff_tail ) , + .chany_top_out ( sb_1__1__9_chany_top_out ) , + .chanx_right_out ( sb_1__1__9_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__9_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__9_chanx_left_out ) , + .ccff_tail ( sb_1__1__9_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2373 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2374 ) , + .pReset_E_in ( pResetWires[507] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2375 ) , + .pReset_N_out ( pResetWires[506] ) , .pReset_W_out ( pResetWires[503] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2376 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2377 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[53] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2378 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2379 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2380 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[20] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2381 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2382 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2383 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2384 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[22] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2385 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2386 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2387 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2388 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2389 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2390 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2391 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2392 ) , + .clk_2_E_in ( clk_2_wires[20] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2393 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2394 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2395 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2396 ) , + .clk_2_N_out ( clk_2_wires[22] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2397 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2398 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2399 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2400 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2401 ) ) ; +sb_1__1_ sb_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2402 } ) , + .chany_top_in ( cby_1__1__11_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__21_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__10_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_10_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_10_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_10_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_10_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_10_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_10_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_10_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_10_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__10_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_10_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_10_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_10_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_10_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_10_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_10_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_10_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_10_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__21_ccff_tail ) , + .chany_top_out ( sb_1__1__10_chany_top_out ) , + .chanx_right_out ( sb_1__1__10_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__10_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__10_chanx_left_out ) , + .ccff_tail ( sb_1__1__10_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2403 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2404 ) , + .pReset_E_in ( pResetWires[556] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2405 ) , + .pReset_N_out ( pResetWires[555] ) , .pReset_W_out ( pResetWires[552] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2406 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2407 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[58] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2408 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[23] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[36] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[37] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2409 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2410 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2411 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2412 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2413 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2414 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2415 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2416 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2417 ) , + .clk_1_S_in ( clk_2_wires[23] ) , .clk_1_E_out ( clk_1_wires[36] ) , + .clk_1_W_out ( clk_1_wires[37] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2418 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2419 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2421 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2422 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2423 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2424 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2425 ) ) ; +sb_1__1_ sb_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2426 } ) , + .chany_top_in ( cby_1__1__13_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__22_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__12_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_12_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_12_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_12_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_12_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_12_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_12_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_12_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_12_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__11_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_12_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_12_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_12_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_12_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_12_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_12_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_12_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_12_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__22_ccff_tail ) , + .chany_top_out ( sb_1__1__11_chany_top_out ) , + .chanx_right_out ( sb_1__1__11_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__11_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__11_chanx_left_out ) , + .ccff_tail ( sb_1__1__11_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2427 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2428 ) , + .pReset_E_in ( pResetWires[70] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2429 ) , + .pReset_N_out ( pResetWires[69] ) , .pReset_W_out ( pResetWires[67] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2430 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2431 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[68] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2432 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2433 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2434 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2435 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2436 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2437 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2438 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2439 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2440 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2441 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2442 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2443 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2444 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2445 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2446 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2447 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2449 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2450 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2451 ) ) ; +sb_1__1_ sb_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2452 } ) , + .chany_top_in ( cby_1__1__14_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__23_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__13_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_13_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_13_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_13_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_13_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_13_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_13_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_13_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_13_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__12_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_13_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_13_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_13_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_13_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_13_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_13_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_13_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_13_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__23_ccff_tail ) , + .chany_top_out ( sb_1__1__12_chany_top_out ) , + .chanx_right_out ( sb_1__1__12_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__12_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__12_chanx_left_out ) , + .ccff_tail ( sb_1__1__12_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2453 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2454 ) , + .pReset_E_in ( pResetWires[119] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2455 ) , + .pReset_N_out ( pResetWires[118] ) , .pReset_W_out ( pResetWires[116] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2456 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2457 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[71] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2458 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2459 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[69] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2460 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2461 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2462 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[2] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2463 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2464 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2465 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2466 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2467 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2468 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2469 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2470 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2471 ) , + .clk_2_N_in ( clk_3_wires[69] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2472 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2473 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2474 ) , + .clk_2_W_out ( clk_2_wires[2] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2475 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2476 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2477 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2478 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2479 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2480 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2481 ) ) ; +sb_1__1_ sb_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2482 } ) , + .chany_top_in ( cby_1__1__15_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__24_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__14_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_14_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_14_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_14_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_14_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_14_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_14_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_14_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_14_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__13_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_14_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_14_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_14_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_14_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_14_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_14_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_14_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_14_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__24_ccff_tail ) , + .chany_top_out ( sb_1__1__13_chany_top_out ) , + .chanx_right_out ( sb_1__1__13_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__13_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__13_chanx_left_out ) , + .ccff_tail ( sb_1__1__13_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2483 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2484 ) , + .pReset_E_in ( pResetWires[168] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2485 ) , + .pReset_N_out ( pResetWires[167] ) , .pReset_W_out ( pResetWires[165] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2486 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2487 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[74] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2488 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2489 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2490 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2491 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2492 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2493 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2494 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2495 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2496 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[65] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2497 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2498 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2499 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[68] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2500 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2501 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2502 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2503 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2504 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2505 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2506 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2507 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2508 ) , + .clk_3_N_in ( clk_3_wires[65] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2509 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2510 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2511 ) , + .clk_3_S_out ( clk_3_wires[68] ) ) ; +sb_1__1_ sb_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2512 } ) , + .chany_top_in ( cby_1__1__16_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__25_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__15_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_15_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_15_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_15_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_15_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_15_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_15_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_15_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_15_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__14_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_15_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_15_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_15_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_15_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_15_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_15_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_15_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_15_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__25_ccff_tail ) , + .chany_top_out ( sb_1__1__14_chany_top_out ) , + .chanx_right_out ( sb_1__1__14_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__14_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__14_chanx_left_out ) , + .ccff_tail ( sb_1__1__14_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2513 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2514 ) , + .pReset_E_in ( pResetWires[217] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2515 ) , + .pReset_N_out ( pResetWires[216] ) , .pReset_W_out ( pResetWires[214] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2516 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2517 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[77] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2518 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2519 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[59] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2520 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2521 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2522 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[7] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2523 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2524 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2525 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2526 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2527 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2528 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[59] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2529 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2530 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2531 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[64] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2532 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2533 ) , + .clk_2_N_in ( clk_3_wires[59] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2534 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2535 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2536 ) , + .clk_2_W_out ( clk_2_wires[7] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2537 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2538 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2539 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2540 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2541 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2542 ) , + .clk_3_N_in ( clk_3_wires[59] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2543 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2544 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2545 ) , + .clk_3_S_out ( clk_3_wires[64] ) ) ; +sb_1__1_ sb_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2546 } ) , + .chany_top_in ( cby_1__1__17_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__26_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__16_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_16_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_16_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_16_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_16_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_16_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_16_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_16_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_16_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__15_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_16_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_16_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_16_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_16_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_16_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_16_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_16_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_16_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__26_ccff_tail ) , + .chany_top_out ( sb_1__1__15_chany_top_out ) , + .chanx_right_out ( sb_1__1__15_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__15_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__15_chanx_left_out ) , + .ccff_tail ( sb_1__1__15_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2547 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2548 ) , + .pReset_E_in ( pResetWires[266] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2549 ) , + .pReset_N_out ( pResetWires[265] ) , .pReset_W_out ( pResetWires[263] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2550 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2551 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[80] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2552 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2553 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2554 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2555 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2556 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2557 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2558 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2559 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2560 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[55] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2561 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2562 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2563 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[58] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2564 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2565 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2566 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2567 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2568 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2569 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2570 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2571 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2572 ) , + .clk_3_N_in ( clk_3_wires[55] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2573 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2574 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2575 ) , + .clk_3_S_out ( clk_3_wires[58] ) ) ; +sb_1__1_ sb_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2576 } ) , + .chany_top_in ( cby_1__1__18_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__27_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__17_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_17_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_17_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_17_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_17_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_17_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_17_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_17_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_17_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__16_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_17_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_17_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_17_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_17_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_17_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_17_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_17_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_17_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__27_ccff_tail ) , + .chany_top_out ( sb_1__1__16_chany_top_out ) , + .chanx_right_out ( sb_1__1__16_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__16_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__16_chanx_left_out ) , + .ccff_tail ( sb_1__1__16_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2577 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2578 ) , + .pReset_E_in ( pResetWires[315] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2579 ) , + .pReset_N_out ( pResetWires[314] ) , .pReset_W_out ( pResetWires[312] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2580 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2581 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[83] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2582 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2583 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2584 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2585 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2586 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2587 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2588 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[51] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2589 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2590 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2591 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2592 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[52] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[54] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2593 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2594 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2595 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2596 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2597 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2598 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2599 ) , + .clk_3_E_in ( clk_3_wires[51] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2600 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2601 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2603 ) , + .clk_3_N_out ( clk_3_wires[52] ) , .clk_3_S_out ( clk_3_wires[54] ) ) ; +sb_1__1_ sb_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2604 } ) , + .chany_top_in ( cby_1__1__19_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__28_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__18_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_18_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_18_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_18_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_18_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_18_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_18_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_18_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_18_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__17_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_18_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_18_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_18_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_18_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_18_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_18_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_18_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_18_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__28_ccff_tail ) , + .chany_top_out ( sb_1__1__17_chany_top_out ) , + .chanx_right_out ( sb_1__1__17_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__17_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__17_chanx_left_out ) , + .ccff_tail ( sb_1__1__17_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2605 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2606 ) , + .pReset_E_in ( pResetWires[364] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2607 ) , + .pReset_N_out ( pResetWires[363] ) , .pReset_W_out ( pResetWires[361] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2608 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2609 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[86] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2610 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2611 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2612 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2613 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2614 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2615 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2616 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2617 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[53] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2618 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2619 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2620 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[56] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2621 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2622 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2623 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2624 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2625 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2626 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2627 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2628 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2629 ) , + .clk_3_S_in ( clk_3_wires[53] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2630 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2631 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2632 ) , + .clk_3_N_out ( clk_3_wires[56] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2633 ) ) ; +sb_1__1_ sb_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2634 } ) , + .chany_top_in ( cby_1__1__20_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__29_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__19_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_19_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_19_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_19_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_19_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_19_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_19_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_19_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_19_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__18_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_19_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_19_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_19_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_19_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_19_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_19_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_19_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_19_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__29_ccff_tail ) , + .chany_top_out ( sb_1__1__18_chany_top_out ) , + .chanx_right_out ( sb_1__1__18_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__18_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__18_chanx_left_out ) , + .ccff_tail ( sb_1__1__18_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2635 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2636 ) , + .pReset_E_in ( pResetWires[413] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2637 ) , + .pReset_N_out ( pResetWires[412] ) , .pReset_W_out ( pResetWires[410] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2638 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2639 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[89] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2640 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2641 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2642 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2643 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[57] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2644 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[14] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2645 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2646 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2647 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2648 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2649 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[57] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2650 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2651 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2652 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[62] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2653 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2654 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2655 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2656 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2657 ) , + .clk_2_S_in ( clk_3_wires[57] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2658 ) , + .clk_2_W_out ( clk_2_wires[14] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2659 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2660 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2661 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2662 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2663 ) , + .clk_3_S_in ( clk_3_wires[57] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2664 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2665 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2666 ) , + .clk_3_N_out ( clk_3_wires[62] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2667 ) ) ; +sb_1__1_ sb_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2668 } ) , + .chany_top_in ( cby_1__1__21_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__30_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__20_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_20_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_20_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_20_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_20_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_20_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_20_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_20_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_20_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__19_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_20_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_20_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_20_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_20_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_20_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_20_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_20_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_20_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__30_ccff_tail ) , + .chany_top_out ( sb_1__1__19_chany_top_out ) , + .chanx_right_out ( sb_1__1__19_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__19_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__19_chanx_left_out ) , + .ccff_tail ( sb_1__1__19_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2669 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2670 ) , + .pReset_E_in ( pResetWires[462] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2671 ) , + .pReset_N_out ( pResetWires[461] ) , .pReset_W_out ( pResetWires[459] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2672 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2673 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[92] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2674 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2675 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2676 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2677 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2678 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2679 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2680 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_2681 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[63] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2682 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2683 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2684 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[66] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2685 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2686 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2687 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2688 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2689 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2691 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2692 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_2693 ) , + .clk_3_S_in ( clk_3_wires[63] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2694 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2695 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2696 ) , + .clk_3_N_out ( clk_3_wires[66] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2697 ) ) ; +sb_1__1_ sb_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2698 } ) , + .chany_top_in ( cby_1__1__22_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__31_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__21_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_21_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_21_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_21_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_21_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_21_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_21_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_21_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_21_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__20_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_21_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_21_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_21_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_21_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_21_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_21_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_21_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_21_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__31_ccff_tail ) , + .chany_top_out ( sb_1__1__20_chany_top_out ) , + .chanx_right_out ( sb_1__1__20_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__20_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__20_chanx_left_out ) , + .ccff_tail ( sb_1__1__20_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2699 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2700 ) , + .pReset_E_in ( pResetWires[511] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2701 ) , + .pReset_N_out ( pResetWires[510] ) , .pReset_W_out ( pResetWires[508] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2702 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2703 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[95] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2704 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2705 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2706 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_2707 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[67] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2708 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[21] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2709 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2710 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2711 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2712 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2713 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2714 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2715 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2716 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2717 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2718 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_2719 ) , + .clk_2_S_in ( clk_3_wires[67] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2720 ) , + .clk_2_W_out ( clk_2_wires[21] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2721 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2722 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2723 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2724 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2725 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2726 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2727 ) ) ; +sb_1__1_ sb_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2728 } ) , + .chany_top_in ( cby_1__1__23_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__32_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__22_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_22_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_22_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_22_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_22_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_22_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_22_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_22_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_22_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__21_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_22_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_22_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_22_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_22_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_22_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_22_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_22_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_22_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__32_ccff_tail ) , + .chany_top_out ( sb_1__1__21_chany_top_out ) , + .chanx_right_out ( sb_1__1__21_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__21_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__21_chanx_left_out ) , + .ccff_tail ( sb_1__1__21_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2729 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2730 ) , + .pReset_E_in ( pResetWires[560] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2731 ) , + .pReset_N_out ( pResetWires[559] ) , .pReset_W_out ( pResetWires[557] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2732 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2733 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[98] ) , .prog_clk_1_N_in ( h_incr0 ) , + .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2734 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2735 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2736 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2737 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2738 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2739 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2740 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2741 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2742 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2743 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2744 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2745 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2746 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2747 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2748 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2749 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2750 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2751 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2752 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2753 ) ) ; +sb_1__1_ sb_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2754 } ) , + .chany_top_in ( cby_1__1__25_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__33_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__24_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_24_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_24_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_24_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_24_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_24_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_24_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_24_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_24_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__22_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_24_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_24_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_24_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_24_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_24_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_24_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_24_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_24_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__33_ccff_tail ) , + .chany_top_out ( sb_1__1__22_chany_top_out ) , + .chanx_right_out ( sb_1__1__22_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__22_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__22_chanx_left_out ) , + .ccff_tail ( sb_1__1__22_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2755 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2756 ) , + .pReset_E_in ( pResetWires[74] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2757 ) , + .pReset_N_out ( pResetWires[73] ) , .pReset_W_out ( pResetWires[71] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2758 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[106] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[30] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2760 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[43] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[44] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2761 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2762 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2763 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2764 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2765 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2766 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2767 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2768 ) , + .clk_1_N_in ( clk_2_wires[30] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2769 ) , + .clk_1_E_out ( clk_1_wires[43] ) , .clk_1_W_out ( clk_1_wires[44] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2770 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2771 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2772 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2773 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2774 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2775 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2776 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2777 ) ) ; +sb_1__1_ sb_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2778 } ) , + .chany_top_in ( cby_1__1__26_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__34_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__25_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_25_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_25_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_25_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_25_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_25_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_25_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_25_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_25_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__23_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_25_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_25_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_25_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_25_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_25_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_25_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_25_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_25_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__34_ccff_tail ) , + .chany_top_out ( sb_1__1__23_chany_top_out ) , + .chanx_right_out ( sb_1__1__23_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__23_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__23_chanx_left_out ) , + .ccff_tail ( sb_1__1__23_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2779 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2780 ) , + .pReset_E_in ( pResetWires[123] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2781 ) , + .pReset_N_out ( pResetWires[122] ) , .pReset_W_out ( pResetWires[120] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2782 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2783 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[109] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2784 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2785 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2786 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[28] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2787 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2788 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2789 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[29] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2790 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2791 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2792 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2793 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2794 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2795 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2796 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2797 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2798 ) , + .clk_2_E_in ( clk_2_wires[28] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2799 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2800 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2801 ) , + .clk_2_S_out ( clk_2_wires[29] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2802 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2803 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2805 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2806 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2807 ) ) ; +sb_1__1_ sb_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2808 } ) , + .chany_top_in ( cby_1__1__27_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__35_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__26_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_26_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_26_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_26_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_26_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_26_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_26_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_26_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_26_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__24_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_26_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_26_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_26_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_26_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_26_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_26_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_26_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_26_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__35_ccff_tail ) , + .chany_top_out ( sb_1__1__24_chany_top_out ) , + .chanx_right_out ( sb_1__1__24_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__24_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__24_chanx_left_out ) , + .ccff_tail ( sb_1__1__24_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2809 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2810 ) , + .pReset_E_in ( pResetWires[172] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2811 ) , + .pReset_N_out ( pResetWires[171] ) , .pReset_W_out ( pResetWires[169] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2812 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2813 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[112] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[41] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2814 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[50] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[51] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2815 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2816 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2817 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2818 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2819 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2820 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2821 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2822 ) , + .clk_1_N_in ( clk_2_wires[41] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2823 ) , + .clk_1_E_out ( clk_1_wires[50] ) , .clk_1_W_out ( clk_1_wires[51] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2824 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2825 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2826 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2827 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2828 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2829 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2830 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2831 ) ) ; +sb_1__1_ sb_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2832 } ) , + .chany_top_in ( cby_1__1__28_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__36_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__27_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_27_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_27_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_27_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_27_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_27_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_27_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_27_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_27_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__25_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_27_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_27_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_27_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_27_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_27_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_27_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_27_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_27_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__36_ccff_tail ) , + .chany_top_out ( sb_1__1__25_chany_top_out ) , + .chanx_right_out ( sb_1__1__25_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__25_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__25_chanx_left_out ) , + .ccff_tail ( sb_1__1__25_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2833 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2834 ) , + .pReset_E_in ( pResetWires[221] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2835 ) , + .pReset_N_out ( pResetWires[220] ) , .pReset_W_out ( pResetWires[218] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2836 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2837 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[115] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2838 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2839 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2840 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[37] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2841 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2842 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2843 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[40] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[38] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2844 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2845 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2846 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2847 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2848 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2849 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2850 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2851 ) , + .clk_2_E_in ( clk_2_wires[37] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2852 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2853 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2854 ) , + .clk_2_S_out ( clk_2_wires[40] ) , .clk_2_N_out ( clk_2_wires[38] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2855 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2856 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2857 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2858 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2859 ) ) ; +sb_1__1_ sb_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2860 } ) , + .chany_top_in ( cby_1__1__29_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__37_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__28_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_28_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_28_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_28_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_28_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_28_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_28_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_28_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_28_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__26_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_28_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_28_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_28_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_28_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_28_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_28_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_28_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_28_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__37_ccff_tail ) , + .chany_top_out ( sb_1__1__26_chany_top_out ) , + .chanx_right_out ( sb_1__1__26_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__26_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__26_chanx_left_out ) , + .ccff_tail ( sb_1__1__26_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2861 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2862 ) , + .pReset_E_in ( pResetWires[270] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2863 ) , + .pReset_N_out ( pResetWires[269] ) , .pReset_W_out ( pResetWires[267] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2864 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2865 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[118] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2866 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[39] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[57] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[58] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2867 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2869 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2870 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2871 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2872 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2873 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2874 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2875 ) , + .clk_1_S_in ( clk_2_wires[39] ) , .clk_1_E_out ( clk_1_wires[57] ) , + .clk_1_W_out ( clk_1_wires[58] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2876 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2877 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2878 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2879 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2880 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2881 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2882 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2883 ) ) ; +sb_1__1_ sb_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2884 } ) , + .chany_top_in ( cby_1__1__30_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__38_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__29_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_29_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_29_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_29_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_29_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_29_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_29_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_29_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_29_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__27_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_29_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_29_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_29_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_29_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_29_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_29_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_29_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_29_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__38_ccff_tail ) , + .chany_top_out ( sb_1__1__27_chany_top_out ) , + .chanx_right_out ( sb_1__1__27_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__27_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__27_chanx_left_out ) , + .ccff_tail ( sb_1__1__27_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2885 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2886 ) , + .pReset_E_in ( pResetWires[319] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2887 ) , + .pReset_N_out ( pResetWires[318] ) , .pReset_W_out ( pResetWires[316] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2888 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2889 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[121] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2890 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2891 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2892 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2893 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2894 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2895 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_2896 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[47] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_2897 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_2898 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2899 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[50] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2900 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2901 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2902 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2903 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2904 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2905 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2906 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2907 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_2908 ) , + .clk_3_E_in ( clk_3_wires[47] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_2909 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_2910 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2911 ) , + .clk_3_W_out ( clk_3_wires[50] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2912 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2913 ) ) ; +sb_1__1_ sb_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2914 } ) , + .chany_top_in ( cby_1__1__31_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__39_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__30_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_30_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_30_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_30_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_30_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_30_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_30_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_30_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_30_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__28_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_30_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_30_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_30_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_30_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_30_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_30_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_30_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_30_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__39_ccff_tail ) , + .chany_top_out ( sb_1__1__28_chany_top_out ) , + .chanx_right_out ( sb_1__1__28_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__28_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__28_chanx_left_out ) , + .ccff_tail ( sb_1__1__28_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2915 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2916 ) , + .pReset_E_in ( pResetWires[368] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2917 ) , + .pReset_N_out ( pResetWires[367] ) , .pReset_W_out ( pResetWires[365] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2918 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2919 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[124] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[54] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_2920 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[64] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[65] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2921 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2922 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2923 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2924 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2925 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2926 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2927 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2928 ) , + .clk_1_N_in ( clk_2_wires[54] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_2929 ) , + .clk_1_E_out ( clk_1_wires[64] ) , .clk_1_W_out ( clk_1_wires[65] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2930 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2931 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2932 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2933 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2934 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2935 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2936 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2937 ) ) ; +sb_1__1_ sb_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2938 } ) , + .chany_top_in ( cby_1__1__32_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__40_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__31_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_31_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_31_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_31_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_31_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_31_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_31_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_31_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_31_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__29_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_31_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_31_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_31_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_31_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_31_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_31_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_31_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_31_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__40_ccff_tail ) , + .chany_top_out ( sb_1__1__29_chany_top_out ) , + .chanx_right_out ( sb_1__1__29_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__29_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__29_chanx_left_out ) , + .ccff_tail ( sb_1__1__29_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2939 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2940 ) , + .pReset_E_in ( pResetWires[417] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2941 ) , + .pReset_N_out ( pResetWires[416] ) , .pReset_W_out ( pResetWires[414] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2942 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2943 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[127] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2944 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2945 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2946 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[50] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2947 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_2948 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2949 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[53] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[51] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2950 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2951 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2952 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2953 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2954 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_2955 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_2956 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_2957 ) , + .clk_2_E_in ( clk_2_wires[50] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_2958 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_2959 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2960 ) , + .clk_2_S_out ( clk_2_wires[53] ) , .clk_2_N_out ( clk_2_wires[51] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2961 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2962 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2963 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2964 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2965 ) ) ; +sb_1__1_ sb_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2966 } ) , + .chany_top_in ( cby_1__1__33_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__41_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__32_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_32_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_32_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_32_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_32_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_32_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_32_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_32_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_32_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__30_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_32_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_32_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_32_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_32_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_32_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_32_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_32_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_32_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__41_ccff_tail ) , + .chany_top_out ( sb_1__1__30_chany_top_out ) , + .chanx_right_out ( sb_1__1__30_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__30_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__30_chanx_left_out ) , + .ccff_tail ( sb_1__1__30_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2967 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2968 ) , + .pReset_E_in ( pResetWires[466] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2969 ) , + .pReset_N_out ( pResetWires[465] ) , .pReset_W_out ( pResetWires[463] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2970 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2971 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[130] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_2972 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[52] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[71] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[72] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_2973 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_2974 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_2975 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_2976 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_2977 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_2978 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_2979 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_2980 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_2981 ) , + .clk_1_S_in ( clk_2_wires[52] ) , .clk_1_E_out ( clk_1_wires[71] ) , + .clk_1_W_out ( clk_1_wires[72] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_2982 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_2983 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_2984 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_2985 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_2986 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_2987 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_2988 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_2989 ) ) ; +sb_1__1_ sb_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_2990 } ) , + .chany_top_in ( cby_1__1__34_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__42_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__33_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_33_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_33_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_33_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_33_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_33_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_33_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_33_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_33_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__31_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_33_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_33_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_33_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_33_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_33_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_33_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_33_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_33_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__42_ccff_tail ) , + .chany_top_out ( sb_1__1__31_chany_top_out ) , + .chanx_right_out ( sb_1__1__31_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__31_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__31_chanx_left_out ) , + .ccff_tail ( sb_1__1__31_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_2991 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_2992 ) , + .pReset_E_in ( pResetWires[515] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_2993 ) , + .pReset_N_out ( pResetWires[514] ) , .pReset_W_out ( pResetWires[512] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_2994 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_2995 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[133] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_2996 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_2997 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_2998 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[63] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_2999 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3000 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3001 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3002 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[64] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3003 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3004 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3005 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3006 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3007 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3008 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3009 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3010 ) , + .clk_2_E_in ( clk_2_wires[63] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3011 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3012 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3013 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3014 ) , + .clk_2_N_out ( clk_2_wires[64] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3015 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3016 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3017 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3018 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3019 ) ) ; +sb_1__1_ sb_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3020 } ) , + .chany_top_in ( cby_1__1__35_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__43_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__34_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_34_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_34_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_34_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_34_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_34_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_34_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_34_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_34_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__32_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_34_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_34_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_34_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_34_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_34_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_34_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_34_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_34_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__43_ccff_tail ) , + .chany_top_out ( sb_1__1__32_chany_top_out ) , + .chanx_right_out ( sb_1__1__32_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__32_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__32_chanx_left_out ) , + .ccff_tail ( sb_1__1__32_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3021 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3022 ) , + .pReset_E_in ( pResetWires[564] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3023 ) , + .pReset_N_out ( pResetWires[563] ) , .pReset_W_out ( pResetWires[561] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3024 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3025 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[136] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3026 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[65] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[78] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[79] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3027 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3028 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3029 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3030 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3031 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3032 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3033 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3034 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3035 ) , + .clk_1_S_in ( clk_2_wires[65] ) , .clk_1_E_out ( clk_1_wires[78] ) , + .clk_1_W_out ( clk_1_wires[79] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3036 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3037 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3039 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3040 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3041 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3042 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3043 ) ) ; +sb_1__1_ sb_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3044 } ) , + .chany_top_in ( cby_1__1__37_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__44_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__36_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_36_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_36_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_36_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_36_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_36_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_36_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_36_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_36_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__33_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_36_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_36_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_36_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_36_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_36_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_36_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_36_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_36_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__44_ccff_tail ) , + .chany_top_out ( sb_1__1__33_chany_top_out ) , + .chanx_right_out ( sb_1__1__33_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__33_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__33_chanx_left_out ) , + .ccff_tail ( sb_1__1__33_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3045 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3046 ) , + .pReset_E_in ( pResetWires[78] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3047 ) , + .pReset_N_out ( pResetWires[77] ) , .pReset_W_out ( pResetWires[75] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3048 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3049 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[144] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3050 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3051 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3052 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3053 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3054 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3055 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3056 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3057 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3058 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3059 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3060 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3061 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3062 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3063 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3064 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3065 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3066 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3067 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3068 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3069 ) ) ; +sb_1__1_ sb_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3070 } ) , + .chany_top_in ( cby_1__1__38_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__45_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__37_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_37_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_37_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_37_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_37_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_37_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_37_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_37_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_37_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__34_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_37_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_37_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_37_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_37_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_37_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_37_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_37_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_37_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__45_ccff_tail ) , + .chany_top_out ( sb_1__1__34_chany_top_out ) , + .chanx_right_out ( sb_1__1__34_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__34_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__34_chanx_left_out ) , + .ccff_tail ( sb_1__1__34_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3071 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3072 ) , + .pReset_E_in ( pResetWires[127] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3073 ) , + .pReset_N_out ( pResetWires[126] ) , .pReset_W_out ( pResetWires[124] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3074 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3075 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[147] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3076 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3077 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[25] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3078 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3079 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3080 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[27] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3081 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3082 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[25] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3083 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3084 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3085 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3086 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3087 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3088 ) , + .clk_2_N_in ( clk_3_wires[25] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3089 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3090 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3091 ) , + .clk_2_W_out ( clk_2_wires[27] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3092 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3093 ) , + .clk_2_E_out ( clk_2_wires[25] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3094 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3095 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3096 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3097 ) ) ; +sb_1__1_ sb_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3098 } ) , + .chany_top_in ( cby_1__1__39_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__46_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__38_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_38_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_38_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_38_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_38_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_38_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_38_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_38_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_38_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__35_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_38_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_38_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_38_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_38_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_38_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_38_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_38_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_38_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__46_ccff_tail ) , + .chany_top_out ( sb_1__1__35_chany_top_out ) , + .chanx_right_out ( sb_1__1__35_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__35_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__35_chanx_left_out ) , + .ccff_tail ( sb_1__1__35_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3099 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3100 ) , + .pReset_E_in ( pResetWires[176] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3101 ) , + .pReset_N_out ( pResetWires[175] ) , .pReset_W_out ( pResetWires[173] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3102 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3103 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[150] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3104 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3105 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3106 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3107 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3108 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3109 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3110 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3111 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3112 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[21] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3113 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3114 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3115 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[24] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3116 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3117 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3118 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3119 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3120 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3121 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3122 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3123 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3124 ) , + .clk_3_N_in ( clk_3_wires[21] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3125 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3126 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3127 ) , + .clk_3_S_out ( clk_3_wires[24] ) ) ; +sb_1__1_ sb_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3128 } ) , + .chany_top_in ( cby_1__1__40_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__47_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__39_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_39_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_39_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_39_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_39_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_39_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_39_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_39_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_39_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__36_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_39_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_39_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_39_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_39_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_39_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_39_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_39_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_39_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__47_ccff_tail ) , + .chany_top_out ( sb_1__1__36_chany_top_out ) , + .chanx_right_out ( sb_1__1__36_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__36_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__36_chanx_left_out ) , + .ccff_tail ( sb_1__1__36_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3129 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3130 ) , + .pReset_E_in ( pResetWires[225] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3131 ) , + .pReset_N_out ( pResetWires[224] ) , .pReset_W_out ( pResetWires[222] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3132 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3133 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[153] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3134 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3135 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[15] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3136 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3137 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3138 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[36] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3139 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3140 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[34] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3141 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3142 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3143 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[15] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3144 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3145 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3146 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[20] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3147 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3148 ) , + .clk_2_N_in ( clk_3_wires[15] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3149 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3150 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3151 ) , + .clk_2_W_out ( clk_2_wires[36] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3152 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3153 ) , + .clk_2_E_out ( clk_2_wires[34] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3154 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3155 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3156 ) , + .clk_3_N_in ( clk_3_wires[15] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3157 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3158 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3159 ) , + .clk_3_S_out ( clk_3_wires[20] ) ) ; +sb_1__1_ sb_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3160 } ) , + .chany_top_in ( cby_1__1__41_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__48_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__40_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_40_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_40_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_40_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_40_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_40_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_40_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_40_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_40_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__37_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_40_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_40_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_40_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_40_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_40_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_40_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_40_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_40_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__48_ccff_tail ) , + .chany_top_out ( sb_1__1__37_chany_top_out ) , + .chanx_right_out ( sb_1__1__37_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__37_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__37_chanx_left_out ) , + .ccff_tail ( sb_1__1__37_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3161 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3162 ) , + .pReset_E_in ( pResetWires[274] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3163 ) , + .pReset_N_out ( pResetWires[273] ) , .pReset_W_out ( pResetWires[271] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3164 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3165 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[156] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3166 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3167 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3168 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3169 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3170 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3171 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3172 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3173 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3174 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[11] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3175 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3176 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3177 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[14] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3178 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3179 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3180 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3181 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3182 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3183 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3184 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3185 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3186 ) , + .clk_3_N_in ( clk_3_wires[11] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3187 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3188 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3189 ) , + .clk_3_S_out ( clk_3_wires[14] ) ) ; +sb_1__1_ sb_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3190 } ) , + .chany_top_in ( cby_1__1__42_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__49_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__41_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_41_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_41_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_41_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_41_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_41_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_41_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_41_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_41_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__38_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_41_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_41_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_41_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_41_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_41_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_41_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_41_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_41_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__49_ccff_tail ) , + .chany_top_out ( sb_1__1__38_chany_top_out ) , + .chanx_right_out ( sb_1__1__38_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__38_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__38_chanx_left_out ) , + .ccff_tail ( sb_1__1__38_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3191 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3192 ) , + .pReset_E_in ( pResetWires[323] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3193 ) , + .pReset_N_out ( pResetWires[322] ) , .pReset_W_out ( pResetWires[320] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3194 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3195 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[159] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3196 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3197 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3198 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3199 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3200 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3201 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3202 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[7] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3203 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3204 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3205 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[46] ) , + .prog_clk_3_N_out ( prog_clk_3_wires[8] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[10] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3206 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3207 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3208 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3209 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3210 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3211 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3212 ) , + .clk_3_E_in ( clk_3_wires[7] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3213 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3214 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3215 ) , + .clk_3_W_out ( clk_3_wires[46] ) , .clk_3_N_out ( clk_3_wires[8] ) , + .clk_3_S_out ( clk_3_wires[10] ) ) ; +sb_1__1_ sb_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3216 } ) , + .chany_top_in ( cby_1__1__43_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__50_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__42_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_42_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_42_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_42_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_42_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_42_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_42_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_42_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_42_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__39_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_42_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_42_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_42_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_42_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_42_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_42_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_42_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_42_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__50_ccff_tail ) , + .chany_top_out ( sb_1__1__39_chany_top_out ) , + .chanx_right_out ( sb_1__1__39_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__39_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__39_chanx_left_out ) , + .ccff_tail ( sb_1__1__39_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3217 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3218 ) , + .pReset_E_in ( pResetWires[372] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3219 ) , + .pReset_N_out ( pResetWires[371] ) , .pReset_W_out ( pResetWires[369] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3220 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3221 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[162] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3222 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3223 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3224 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3225 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3226 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3227 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3228 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3229 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[9] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3230 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3231 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3232 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[12] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3233 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3234 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3235 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3236 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3237 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3238 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3239 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3240 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3241 ) , + .clk_3_S_in ( clk_3_wires[9] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3242 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3243 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3244 ) , + .clk_3_N_out ( clk_3_wires[12] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3245 ) ) ; +sb_1__1_ sb_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3246 } ) , + .chany_top_in ( cby_1__1__44_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__51_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__43_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_43_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_43_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_43_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_43_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_43_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_43_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_43_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_43_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__40_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_43_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_43_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_43_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_43_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_43_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_43_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_43_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_43_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__51_ccff_tail ) , + .chany_top_out ( sb_1__1__40_chany_top_out ) , + .chanx_right_out ( sb_1__1__40_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__40_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__40_chanx_left_out ) , + .ccff_tail ( sb_1__1__40_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3247 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3248 ) , + .pReset_E_in ( pResetWires[421] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3249 ) , + .pReset_N_out ( pResetWires[420] ) , .pReset_W_out ( pResetWires[418] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3250 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3251 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[165] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3252 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3253 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3254 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3255 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[13] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3256 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[49] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3257 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3258 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[47] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3259 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3260 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[13] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3261 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3262 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3263 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[18] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3264 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3265 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3266 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3267 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3268 ) , + .clk_2_S_in ( clk_3_wires[13] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3269 ) , + .clk_2_W_out ( clk_2_wires[49] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3270 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3271 ) , + .clk_2_E_out ( clk_2_wires[47] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3272 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3273 ) , + .clk_3_S_in ( clk_3_wires[13] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3274 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3275 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3276 ) , + .clk_3_N_out ( clk_3_wires[18] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3277 ) ) ; +sb_1__1_ sb_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3278 } ) , + .chany_top_in ( cby_1__1__45_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__52_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__44_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_44_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_44_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_44_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_44_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_44_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_44_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_44_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_44_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__41_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_44_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_44_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_44_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_44_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_44_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_44_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_44_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_44_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__52_ccff_tail ) , + .chany_top_out ( sb_1__1__41_chany_top_out ) , + .chanx_right_out ( sb_1__1__41_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__41_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__41_chanx_left_out ) , + .ccff_tail ( sb_1__1__41_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3279 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3280 ) , + .pReset_E_in ( pResetWires[470] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3281 ) , + .pReset_N_out ( pResetWires[469] ) , .pReset_W_out ( pResetWires[467] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3282 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3283 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[168] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3284 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3285 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3286 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3287 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3288 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3289 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3290 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3291 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[19] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3292 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3293 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3294 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[22] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3295 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3296 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3297 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3298 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3299 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3300 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3301 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3302 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3303 ) , + .clk_3_S_in ( clk_3_wires[19] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3304 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3305 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3306 ) , + .clk_3_N_out ( clk_3_wires[22] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3307 ) ) ; +sb_1__1_ sb_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3308 } ) , + .chany_top_in ( cby_1__1__46_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__53_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__45_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_45_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_45_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_45_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_45_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_45_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_45_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_45_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_45_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__42_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_45_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_45_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_45_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_45_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_45_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_45_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_45_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_45_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__53_ccff_tail ) , + .chany_top_out ( sb_1__1__42_chany_top_out ) , + .chanx_right_out ( sb_1__1__42_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__42_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__42_chanx_left_out ) , + .ccff_tail ( sb_1__1__42_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3309 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3310 ) , + .pReset_E_in ( pResetWires[519] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3311 ) , + .pReset_N_out ( pResetWires[518] ) , .pReset_W_out ( pResetWires[516] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3312 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3313 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[171] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3314 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3315 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3316 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3317 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[23] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3318 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[62] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3319 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3320 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[60] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3322 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3323 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3324 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3325 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3326 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3327 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3328 ) , + .clk_2_S_in ( clk_3_wires[23] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3329 ) , + .clk_2_W_out ( clk_2_wires[62] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3330 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3331 ) , + .clk_2_E_out ( clk_2_wires[60] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3332 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3333 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3334 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3335 ) ) ; +sb_1__1_ sb_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3336 } ) , + .chany_top_in ( cby_1__1__47_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__54_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__46_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_46_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_46_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_46_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_46_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_46_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_46_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_46_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_46_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__43_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_46_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_46_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_46_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_46_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_46_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_46_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_46_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_46_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__54_ccff_tail ) , + .chany_top_out ( sb_1__1__43_chany_top_out ) , + .chanx_right_out ( sb_1__1__43_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__43_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__43_chanx_left_out ) , + .ccff_tail ( sb_1__1__43_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3337 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3338 ) , + .pReset_E_in ( pResetWires[568] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3339 ) , + .pReset_N_out ( pResetWires[567] ) , .pReset_W_out ( pResetWires[565] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3340 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3341 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[174] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3342 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3343 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3344 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3345 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3346 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3347 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3348 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3349 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3350 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3351 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3352 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3353 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3354 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3355 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3356 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3357 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3358 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3359 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3360 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3361 ) ) ; +sb_1__1_ sb_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3362 } ) , + .chany_top_in ( cby_1__1__49_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__55_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__48_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_48_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_48_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_48_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_48_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_48_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_48_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_48_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_48_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__44_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_48_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_48_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_48_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_48_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_48_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_48_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_48_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_48_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__55_ccff_tail ) , + .chany_top_out ( sb_1__1__44_chany_top_out ) , + .chanx_right_out ( sb_1__1__44_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__44_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__44_chanx_left_out ) , + .ccff_tail ( sb_1__1__44_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3363 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3364 ) , + .pReset_E_in ( pResetWires[82] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3365 ) , + .pReset_N_out ( pResetWires[81] ) , .pReset_W_out ( pResetWires[79] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3366 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3367 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[182] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[32] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3368 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[85] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[86] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3369 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3370 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3371 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3372 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3373 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3374 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3375 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3376 ) , + .clk_1_N_in ( clk_2_wires[32] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3377 ) , + .clk_1_E_out ( clk_1_wires[85] ) , .clk_1_W_out ( clk_1_wires[86] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3378 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3379 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3380 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3381 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3382 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3383 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3384 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3385 ) ) ; +sb_1__1_ sb_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3386 } ) , + .chany_top_in ( cby_1__1__50_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__56_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__49_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_49_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_49_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_49_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_49_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_49_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_49_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_49_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_49_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__45_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_49_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_49_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_49_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_49_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_49_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_49_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_49_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_49_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__56_ccff_tail ) , + .chany_top_out ( sb_1__1__45_chany_top_out ) , + .chanx_right_out ( sb_1__1__45_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__45_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__45_chanx_left_out ) , + .ccff_tail ( sb_1__1__45_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3387 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3388 ) , + .pReset_E_in ( pResetWires[131] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3389 ) , + .pReset_N_out ( pResetWires[130] ) , .pReset_W_out ( pResetWires[128] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3390 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3391 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[185] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3392 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3393 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3394 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3395 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3396 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[26] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3397 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[31] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3398 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3399 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3400 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3401 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3402 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3403 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3404 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3405 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3406 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3407 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3408 ) , + .clk_2_W_in ( clk_2_wires[26] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3409 ) , + .clk_2_S_out ( clk_2_wires[31] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3410 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3411 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3412 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3413 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3414 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3415 ) ) ; +sb_1__1_ sb_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3416 } ) , + .chany_top_in ( cby_1__1__51_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__57_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__50_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_50_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_50_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_50_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_50_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_50_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_50_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_50_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_50_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__46_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_50_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_50_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_50_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_50_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_50_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_50_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_50_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_50_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__57_ccff_tail ) , + .chany_top_out ( sb_1__1__46_chany_top_out ) , + .chanx_right_out ( sb_1__1__46_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__46_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__46_chanx_left_out ) , + .ccff_tail ( sb_1__1__46_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3417 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3418 ) , + .pReset_E_in ( pResetWires[180] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3419 ) , + .pReset_N_out ( pResetWires[179] ) , .pReset_W_out ( pResetWires[177] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3420 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3421 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[188] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[45] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3422 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[92] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[93] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3423 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3424 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3425 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3426 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3427 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3428 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3429 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3430 ) , + .clk_1_N_in ( clk_2_wires[45] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3431 ) , + .clk_1_E_out ( clk_1_wires[92] ) , .clk_1_W_out ( clk_1_wires[93] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3432 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3433 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3434 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3435 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3436 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3437 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3438 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3439 ) ) ; +sb_1__1_ sb_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3440 } ) , + .chany_top_in ( cby_1__1__52_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__58_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__51_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_51_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_51_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_51_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_51_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_51_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_51_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_51_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_51_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__47_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_51_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_51_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_51_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_51_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_51_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_51_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_51_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_51_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__58_ccff_tail ) , + .chany_top_out ( sb_1__1__47_chany_top_out ) , + .chanx_right_out ( sb_1__1__47_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__47_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__47_chanx_left_out ) , + .ccff_tail ( sb_1__1__47_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3441 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3442 ) , + .pReset_E_in ( pResetWires[229] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3443 ) , + .pReset_N_out ( pResetWires[228] ) , .pReset_W_out ( pResetWires[226] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3444 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3445 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[191] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3446 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3447 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3448 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3449 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3450 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[35] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3451 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[44] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[42] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3452 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3453 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3454 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3455 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3456 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3457 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3458 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3459 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3460 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3461 ) , + .clk_2_W_in ( clk_2_wires[35] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3462 ) , + .clk_2_S_out ( clk_2_wires[44] ) , .clk_2_N_out ( clk_2_wires[42] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3463 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3464 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3465 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3466 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3467 ) ) ; +sb_1__1_ sb_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3468 } ) , + .chany_top_in ( cby_1__1__53_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__59_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__52_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_52_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_52_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_52_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_52_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_52_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_52_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_52_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_52_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__48_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_52_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_52_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_52_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_52_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_52_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_52_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_52_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_52_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__59_ccff_tail ) , + .chany_top_out ( sb_1__1__48_chany_top_out ) , + .chanx_right_out ( sb_1__1__48_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__48_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__48_chanx_left_out ) , + .ccff_tail ( sb_1__1__48_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3469 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3470 ) , + .pReset_E_in ( pResetWires[278] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3471 ) , + .pReset_N_out ( pResetWires[277] ) , .pReset_W_out ( pResetWires[275] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3472 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3473 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[194] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3474 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[43] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[99] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[100] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3475 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3476 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3477 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3478 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3479 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3480 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3481 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3482 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3483 ) , + .clk_1_S_in ( clk_2_wires[43] ) , .clk_1_E_out ( clk_1_wires[99] ) , + .clk_1_W_out ( clk_1_wires[100] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3484 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3485 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3486 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3487 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3488 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3489 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3490 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3491 ) ) ; +sb_1__1_ sb_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3492 } ) , + .chany_top_in ( cby_1__1__54_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__60_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__53_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_53_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_53_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_53_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_53_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_53_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_53_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_53_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_53_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__49_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_53_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_53_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_53_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_53_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_53_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_53_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_53_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_53_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__60_ccff_tail ) , + .chany_top_out ( sb_1__1__49_chany_top_out ) , + .chanx_right_out ( sb_1__1__49_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__49_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__49_chanx_left_out ) , + .ccff_tail ( sb_1__1__49_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3493 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3494 ) , + .pReset_E_in ( pResetWires[327] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3495 ) , + .pReset_N_out ( pResetWires[326] ) , .pReset_W_out ( pResetWires[324] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3496 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3497 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[197] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3498 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3499 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3500 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3501 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3502 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3503 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3504 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[3] ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_3505 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3506 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3507 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[6] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3508 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3509 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3510 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3511 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3512 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3513 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3514 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3515 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3516 ) , + .clk_3_E_in ( clk_3_wires[3] ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_3517 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3518 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3519 ) , + .clk_3_W_out ( clk_3_wires[6] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3520 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3521 ) ) ; +sb_1__1_ sb_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3522 } ) , + .chany_top_in ( cby_1__1__55_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__61_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__54_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_54_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_54_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_54_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_54_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_54_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_54_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_54_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_54_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__50_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_54_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_54_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_54_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_54_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_54_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_54_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_54_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_54_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__61_ccff_tail ) , + .chany_top_out ( sb_1__1__50_chany_top_out ) , + .chanx_right_out ( sb_1__1__50_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__50_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__50_chanx_left_out ) , + .ccff_tail ( sb_1__1__50_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3523 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3524 ) , + .pReset_E_in ( pResetWires[376] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3525 ) , + .pReset_N_out ( pResetWires[375] ) , .pReset_W_out ( pResetWires[373] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3526 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3527 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[200] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[58] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3528 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[106] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[107] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3529 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3530 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3531 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3532 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3533 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3534 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3535 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3536 ) , + .clk_1_N_in ( clk_2_wires[58] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3537 ) , + .clk_1_E_out ( clk_1_wires[106] ) , .clk_1_W_out ( clk_1_wires[107] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3538 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3539 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3540 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3541 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3542 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3543 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3544 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3545 ) ) ; +sb_1__1_ sb_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3546 } ) , + .chany_top_in ( cby_1__1__56_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__62_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__55_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_55_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_55_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_55_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_55_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_55_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_55_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_55_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_55_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__51_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_55_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_55_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_55_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_55_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_55_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_55_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_55_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_55_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__62_ccff_tail ) , + .chany_top_out ( sb_1__1__51_chany_top_out ) , + .chanx_right_out ( sb_1__1__51_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__51_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__51_chanx_left_out ) , + .ccff_tail ( sb_1__1__51_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3547 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3548 ) , + .pReset_E_in ( pResetWires[425] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3549 ) , + .pReset_N_out ( pResetWires[424] ) , .pReset_W_out ( pResetWires[422] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3550 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3551 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[203] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3552 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3553 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3554 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3555 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3556 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[48] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3557 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[57] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[55] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3558 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3559 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3560 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3561 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3562 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3563 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3564 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3565 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3566 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3567 ) , + .clk_2_W_in ( clk_2_wires[48] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3568 ) , + .clk_2_S_out ( clk_2_wires[57] ) , .clk_2_N_out ( clk_2_wires[55] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3569 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3570 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3571 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3572 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3573 ) ) ; +sb_1__1_ sb_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3574 } ) , + .chany_top_in ( cby_1__1__57_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__63_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__56_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_56_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_56_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_56_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_56_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_56_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_56_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_56_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_56_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__52_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_56_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_56_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_56_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_56_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_56_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_56_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_56_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_56_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__63_ccff_tail ) , + .chany_top_out ( sb_1__1__52_chany_top_out ) , + .chanx_right_out ( sb_1__1__52_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__52_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__52_chanx_left_out ) , + .ccff_tail ( sb_1__1__52_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3575 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3576 ) , + .pReset_E_in ( pResetWires[474] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3577 ) , + .pReset_N_out ( pResetWires[473] ) , .pReset_W_out ( pResetWires[471] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3578 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3579 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[206] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3580 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[56] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[113] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[114] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3581 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3582 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3583 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3584 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3585 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3586 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3587 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3588 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3589 ) , + .clk_1_S_in ( clk_2_wires[56] ) , .clk_1_E_out ( clk_1_wires[113] ) , + .clk_1_W_out ( clk_1_wires[114] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3590 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3591 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3592 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3593 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3594 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3595 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3596 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3597 ) ) ; +sb_1__1_ sb_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3598 } ) , + .chany_top_in ( cby_1__1__58_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__64_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__57_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_57_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_57_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_57_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_57_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_57_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_57_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_57_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_57_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__53_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_57_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_57_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_57_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_57_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_57_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_57_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_57_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_57_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__64_ccff_tail ) , + .chany_top_out ( sb_1__1__53_chany_top_out ) , + .chanx_right_out ( sb_1__1__53_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__53_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__53_chanx_left_out ) , + .ccff_tail ( sb_1__1__53_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3599 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3600 ) , + .pReset_E_in ( pResetWires[523] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3601 ) , + .pReset_N_out ( pResetWires[522] ) , .pReset_W_out ( pResetWires[520] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3602 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3603 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[209] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3604 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3605 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3606 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_3607 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3608 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[61] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3609 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3610 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[66] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3611 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3612 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3613 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3614 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3615 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3616 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3617 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3618 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_3619 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3620 ) , + .clk_2_W_in ( clk_2_wires[61] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3621 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3622 ) , + .clk_2_N_out ( clk_2_wires[66] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3623 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3624 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3625 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3626 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3627 ) ) ; +sb_1__1_ sb_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3628 } ) , + .chany_top_in ( cby_1__1__59_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__65_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__58_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_58_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_58_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_58_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_58_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_58_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_58_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_58_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_58_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__54_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_58_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_58_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_58_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_58_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_58_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_58_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_58_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_58_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__65_ccff_tail ) , + .chany_top_out ( sb_1__1__54_chany_top_out ) , + .chanx_right_out ( sb_1__1__54_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__54_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__54_chanx_left_out ) , + .ccff_tail ( sb_1__1__54_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3629 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3630 ) , + .pReset_E_in ( pResetWires[572] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3631 ) , + .pReset_N_out ( pResetWires[571] ) , .pReset_W_out ( pResetWires[569] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_3632 ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3633 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[212] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_3634 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[67] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[120] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[121] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3635 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3636 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3637 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3638 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3639 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3640 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3641 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3642 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_3643 ) , + .clk_1_S_in ( clk_2_wires[67] ) , .clk_1_E_out ( clk_1_wires[120] ) , + .clk_1_W_out ( clk_1_wires[121] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3644 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3645 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3646 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3647 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3648 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3649 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3650 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3651 ) ) ; +sb_1__1_ sb_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3652 } ) , + .chany_top_in ( cby_1__1__61_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__66_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__60_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_60_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_60_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_60_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_60_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_60_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_60_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_60_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_60_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__55_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_60_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_60_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_60_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_60_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_60_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_60_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_60_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_60_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__66_ccff_tail ) , + .chany_top_out ( sb_1__1__55_chany_top_out ) , + .chanx_right_out ( sb_1__1__55_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__55_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__55_chanx_left_out ) , + .ccff_tail ( sb_1__1__55_ccff_tail ) , .Test_en_S_in ( Test_enWires[2] ) , + .Test_en_N_out ( Test_enWires[3] ) , .pReset_S_in ( pResetWires[2] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3653 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3654 ) , + .pReset_N_out ( pResetWires[85] ) , .pReset_W_out ( pResetWires[83] ) , + .pReset_E_out ( pResetWires[86] ) , .Reset_S_in ( ResetWires[2] ) , + .Reset_N_out ( ResetWires[3] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[220] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3655 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3656 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3657 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3658 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3659 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3660 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3661 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3662 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[89] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3663 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3664 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3665 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[92] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3666 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3667 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3668 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3669 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3670 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3671 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3672 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3673 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3674 ) , + .clk_3_S_in ( clk_3_wires[89] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3675 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3676 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3677 ) , + .clk_3_N_out ( clk_3_wires[92] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3678 ) ) ; +sb_1__1_ sb_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3679 } ) , + .chany_top_in ( cby_1__1__62_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__67_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__61_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_61_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_61_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_61_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_61_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_61_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_61_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_61_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_61_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__56_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_61_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_61_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_61_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_61_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_61_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_61_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_61_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_61_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__67_ccff_tail ) , + .chany_top_out ( sb_1__1__56_chany_top_out ) , + .chanx_right_out ( sb_1__1__56_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__56_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__56_chanx_left_out ) , + .ccff_tail ( sb_1__1__56_ccff_tail ) , .Test_en_S_in ( Test_enWires[4] ) , + .Test_en_N_out ( Test_enWires[5] ) , .pReset_S_in ( pResetWires[4] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3680 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3681 ) , + .pReset_N_out ( pResetWires[134] ) , .pReset_W_out ( pResetWires[132] ) , + .pReset_E_out ( pResetWires[135] ) , .Reset_S_in ( ResetWires[4] ) , + .Reset_N_out ( ResetWires[5] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[223] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3682 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3683 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3684 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3685 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3686 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3687 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3688 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3689 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[91] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3690 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3691 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3692 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[94] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3693 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3694 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3695 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3696 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3697 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3698 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3699 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3700 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3701 ) , + .clk_3_S_in ( clk_3_wires[91] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3702 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3703 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3704 ) , + .clk_3_N_out ( clk_3_wires[94] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3705 ) ) ; +sb_1__1_ sb_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3706 } ) , + .chany_top_in ( cby_1__1__63_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__68_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__62_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_62_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_62_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_62_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_62_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_62_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_62_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_62_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_62_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__57_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_62_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_62_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_62_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_62_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_62_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_62_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_62_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_62_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__68_ccff_tail ) , + .chany_top_out ( sb_1__1__57_chany_top_out ) , + .chanx_right_out ( sb_1__1__57_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__57_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__57_chanx_left_out ) , + .ccff_tail ( sb_1__1__57_ccff_tail ) , .Test_en_S_in ( Test_enWires[6] ) , + .Test_en_N_out ( Test_enWires[7] ) , .pReset_S_in ( pResetWires[6] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3707 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3708 ) , + .pReset_N_out ( pResetWires[183] ) , .pReset_W_out ( pResetWires[181] ) , + .pReset_E_out ( pResetWires[184] ) , .Reset_S_in ( ResetWires[6] ) , + .Reset_N_out ( ResetWires[7] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[226] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3709 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3710 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3711 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3712 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3713 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3714 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3715 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3716 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[93] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3717 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3718 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3719 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[96] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3720 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3721 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3722 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3723 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3724 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3725 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3726 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3727 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3728 ) , + .clk_3_S_in ( clk_3_wires[93] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3729 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3730 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3731 ) , + .clk_3_N_out ( clk_3_wires[96] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3732 ) ) ; +sb_1__1_ sb_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3733 } ) , + .chany_top_in ( cby_1__1__64_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__69_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__63_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_63_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_63_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_63_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_63_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_63_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_63_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_63_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_63_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__58_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_63_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_63_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_63_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_63_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_63_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_63_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_63_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_63_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__69_ccff_tail ) , + .chany_top_out ( sb_1__1__58_chany_top_out ) , + .chanx_right_out ( sb_1__1__58_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__58_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__58_chanx_left_out ) , + .ccff_tail ( sb_1__1__58_ccff_tail ) , .Test_en_S_in ( Test_enWires[8] ) , + .Test_en_N_out ( Test_enWires[9] ) , .pReset_S_in ( pResetWires[8] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3734 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3735 ) , + .pReset_N_out ( pResetWires[232] ) , .pReset_W_out ( pResetWires[230] ) , + .pReset_E_out ( pResetWires[233] ) , .Reset_S_in ( ResetWires[8] ) , + .Reset_N_out ( ResetWires[9] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[229] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3736 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3737 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3738 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3739 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3740 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3741 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3742 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3743 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[95] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3744 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3745 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3746 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[98] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3747 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3748 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3749 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3750 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3751 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3752 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3753 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3754 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3755 ) , + .clk_3_S_in ( clk_3_wires[95] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3756 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3757 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3758 ) , + .clk_3_N_out ( clk_3_wires[98] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3759 ) ) ; +sb_1__1_ sb_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3760 } ) , + .chany_top_in ( cby_1__1__65_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__70_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__64_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_64_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_64_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_64_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_64_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_64_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_64_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_64_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_64_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__59_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_64_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_64_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_64_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_64_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_64_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_64_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_64_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_64_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__70_ccff_tail ) , + .chany_top_out ( sb_1__1__59_chany_top_out ) , + .chanx_right_out ( sb_1__1__59_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__59_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__59_chanx_left_out ) , + .ccff_tail ( sb_1__1__59_ccff_tail ) , + .Test_en_S_in ( Test_enWires[10] ) , .Test_en_N_out ( Test_enWires[11] ) , + .pReset_S_in ( pResetWires[10] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3761 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3762 ) , + .pReset_N_out ( pResetWires[281] ) , .pReset_W_out ( pResetWires[279] ) , + .pReset_E_out ( pResetWires[282] ) , .Reset_S_in ( ResetWires[10] ) , + .Reset_N_out ( ResetWires[11] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[232] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3763 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3764 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3765 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3766 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3767 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3768 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3769 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3770 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[97] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3771 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3772 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3773 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[100] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3774 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3775 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3776 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3777 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3778 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3779 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3780 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3781 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3782 ) , + .clk_3_S_in ( clk_3_wires[97] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3783 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3784 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3785 ) , + .clk_3_N_out ( clk_3_wires[100] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3786 ) ) ; +sb_1__1_ sb_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3787 } ) , + .chany_top_in ( cby_1__1__66_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__71_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__65_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_65_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_65_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_65_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_65_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_65_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_65_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_65_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_65_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__60_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_65_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_65_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_65_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_65_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_65_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_65_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_65_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_65_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__71_ccff_tail ) , + .chany_top_out ( sb_1__1__60_chany_top_out ) , + .chanx_right_out ( sb_1__1__60_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__60_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__60_chanx_left_out ) , + .ccff_tail ( sb_1__1__60_ccff_tail ) , + .Test_en_S_in ( Test_enWires[12] ) , .Test_en_N_out ( Test_enWires[13] ) , + .pReset_S_in ( pResetWires[12] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3788 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3789 ) , + .pReset_N_out ( pResetWires[330] ) , .pReset_W_out ( pResetWires[328] ) , + .pReset_E_out ( pResetWires[331] ) , .Reset_S_in ( ResetWires[12] ) , + .Reset_N_out ( ResetWires[13] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[235] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3790 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3791 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3792 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3793 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3795 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_3796 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_3797 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[99] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_3798 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[0] ) , + .prog_clk_3_W_out ( prog_clk_3_wires[2] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3799 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3800 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3801 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3802 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3803 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3804 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3805 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3806 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_3807 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_3808 ) , + .clk_3_S_in ( clk_3_wires[99] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_3809 ) , + .clk_3_E_out ( clk_3_wires[0] ) , .clk_3_W_out ( clk_3_wires[2] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3810 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3811 ) ) ; +sb_1__1_ sb_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3812 } ) , + .chany_top_in ( cby_1__1__67_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__72_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__66_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_66_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_66_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_66_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_66_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_66_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_66_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_66_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_66_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__61_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_66_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_66_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_66_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_66_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_66_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_66_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_66_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_66_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__72_ccff_tail ) , + .chany_top_out ( sb_1__1__61_chany_top_out ) , + .chanx_right_out ( sb_1__1__61_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__61_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__61_chanx_left_out ) , + .ccff_tail ( sb_1__1__61_ccff_tail ) , + .Test_en_S_in ( Test_enWires[14] ) , .Test_en_N_out ( Test_enWires[15] ) , + .pReset_S_in ( pResetWires[14] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3813 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3814 ) , + .pReset_N_out ( pResetWires[379] ) , .pReset_W_out ( pResetWires[377] ) , + .pReset_E_out ( pResetWires[380] ) , .Reset_S_in ( ResetWires[14] ) , + .Reset_N_out ( ResetWires[15] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[238] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3815 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3816 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3817 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3818 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3819 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3820 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3821 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3822 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3823 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3824 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3825 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3826 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3827 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3828 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3829 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3830 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3831 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3832 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3833 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3834 ) ) ; +sb_1__1_ sb_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3835 } ) , + .chany_top_in ( cby_1__1__68_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__73_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__67_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_67_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_67_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_67_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_67_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_67_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_67_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_67_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_67_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__62_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_67_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_67_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_67_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_67_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_67_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_67_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_67_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_67_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__73_ccff_tail ) , + .chany_top_out ( sb_1__1__62_chany_top_out ) , + .chanx_right_out ( sb_1__1__62_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__62_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__62_chanx_left_out ) , + .ccff_tail ( sb_1__1__62_ccff_tail ) , + .Test_en_S_in ( Test_enWires[16] ) , .Test_en_N_out ( Test_enWires[17] ) , + .pReset_S_in ( pResetWires[16] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3836 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3837 ) , + .pReset_N_out ( pResetWires[428] ) , .pReset_W_out ( pResetWires[426] ) , + .pReset_E_out ( pResetWires[429] ) , .Reset_S_in ( ResetWires[16] ) , + .Reset_N_out ( ResetWires[17] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[241] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3838 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3839 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3840 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3841 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3842 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3843 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3844 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3845 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3846 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3847 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3848 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3849 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3850 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3852 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3853 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3854 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3855 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3856 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3857 ) ) ; +sb_1__1_ sb_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3858 } ) , + .chany_top_in ( cby_1__1__69_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__74_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__68_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_68_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_68_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_68_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_68_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_68_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_68_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_68_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_68_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__63_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_68_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_68_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_68_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_68_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_68_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_68_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_68_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_68_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__74_ccff_tail ) , + .chany_top_out ( sb_1__1__63_chany_top_out ) , + .chanx_right_out ( sb_1__1__63_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__63_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__63_chanx_left_out ) , + .ccff_tail ( sb_1__1__63_ccff_tail ) , + .Test_en_S_in ( Test_enWires[18] ) , .Test_en_N_out ( Test_enWires[19] ) , + .pReset_S_in ( pResetWires[18] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3859 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3860 ) , + .pReset_N_out ( pResetWires[477] ) , .pReset_W_out ( pResetWires[475] ) , + .pReset_E_out ( pResetWires[478] ) , .Reset_S_in ( ResetWires[18] ) , + .Reset_N_out ( ResetWires[19] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[244] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3861 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3862 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3863 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3864 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3865 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3866 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3867 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3868 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3869 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3870 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3871 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3872 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3873 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3874 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3875 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3876 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3878 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3879 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3880 ) ) ; +sb_1__1_ sb_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3881 } ) , + .chany_top_in ( cby_1__1__70_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__75_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__69_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_69_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_69_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_69_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_69_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_69_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_69_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_69_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_69_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__64_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_69_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_69_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_69_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_69_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_69_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_69_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_69_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_69_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__75_ccff_tail ) , + .chany_top_out ( sb_1__1__64_chany_top_out ) , + .chanx_right_out ( sb_1__1__64_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__64_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__64_chanx_left_out ) , + .ccff_tail ( sb_1__1__64_ccff_tail ) , + .Test_en_S_in ( Test_enWires[20] ) , .Test_en_N_out ( Test_enWires[21] ) , + .pReset_S_in ( pResetWires[20] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3882 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3883 ) , + .pReset_N_out ( pResetWires[526] ) , .pReset_W_out ( pResetWires[524] ) , + .pReset_E_out ( pResetWires[527] ) , .Reset_S_in ( ResetWires[20] ) , + .Reset_N_out ( ResetWires[21] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[247] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3884 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3885 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3886 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3887 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3888 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3889 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3890 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3891 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3892 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3893 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3894 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3895 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3896 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3897 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3898 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3899 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3901 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3902 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3903 ) ) ; +sb_1__1_ sb_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3904 } ) , + .chany_top_in ( cby_1__1__71_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__76_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__70_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_70_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_70_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_70_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_70_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_70_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_70_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_70_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_70_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__65_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_70_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_70_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_70_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_70_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_70_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_70_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_70_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_70_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__76_ccff_tail ) , + .chany_top_out ( sb_1__1__65_chany_top_out ) , + .chanx_right_out ( sb_1__1__65_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__65_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__65_chanx_left_out ) , + .ccff_tail ( sb_1__1__65_ccff_tail ) , + .Test_en_S_in ( Test_enWires[22] ) , .Test_en_N_out ( Test_enWires[23] ) , + .pReset_S_in ( pResetWires[22] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3905 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_3906 ) , + .pReset_N_out ( pResetWires[575] ) , .pReset_W_out ( pResetWires[573] ) , + .pReset_E_out ( pResetWires[576] ) , .Reset_S_in ( ResetWires[22] ) , + .Reset_N_out ( ResetWires[23] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[250] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3907 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3908 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3909 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3910 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3911 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3912 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3913 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3914 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3915 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3916 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3917 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3918 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3919 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3920 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3921 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3922 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3923 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3924 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3925 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3926 ) ) ; +sb_1__1_ sb_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3927 } ) , + .chany_top_in ( cby_1__1__73_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__77_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__72_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_72_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_72_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_72_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_72_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_72_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_72_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_72_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_72_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__66_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_72_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_72_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_72_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_72_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_72_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_72_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_72_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_72_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__77_ccff_tail ) , + .chany_top_out ( sb_1__1__66_chany_top_out ) , + .chanx_right_out ( sb_1__1__66_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__66_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__66_chanx_left_out ) , + .ccff_tail ( sb_1__1__66_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3928 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3929 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3930 ) , + .pReset_W_in ( pResetWires[87] ) , .pReset_N_out ( pResetWires[89] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3931 ) , + .pReset_E_out ( pResetWires[90] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3932 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[258] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[74] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3933 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[127] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[128] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3934 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3935 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3936 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3937 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3938 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3939 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3940 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3941 ) , + .clk_1_N_in ( clk_2_wires[74] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3942 ) , + .clk_1_E_out ( clk_1_wires[127] ) , .clk_1_W_out ( clk_1_wires[128] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3943 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3944 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3945 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3946 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3947 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3948 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3949 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3950 ) ) ; +sb_1__1_ sb_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3951 } ) , + .chany_top_in ( cby_1__1__74_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__78_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__73_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_73_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_73_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_73_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_73_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_73_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_73_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_73_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_73_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__67_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_73_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_73_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_73_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_73_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_73_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_73_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_73_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_73_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__78_ccff_tail ) , + .chany_top_out ( sb_1__1__67_chany_top_out ) , + .chanx_right_out ( sb_1__1__67_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__67_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__67_chanx_left_out ) , + .ccff_tail ( sb_1__1__67_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3952 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3953 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3954 ) , + .pReset_W_in ( pResetWires[136] ) , .pReset_N_out ( pResetWires[138] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3955 ) , + .pReset_E_out ( pResetWires[139] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3956 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[261] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_3957 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_3958 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_3959 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[72] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_3960 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_3961 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3962 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[73] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3963 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3964 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3965 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3966 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3967 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3968 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_3969 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_3970 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_3971 ) , + .clk_2_E_in ( clk_2_wires[72] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_3972 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_3973 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3974 ) , + .clk_2_S_out ( clk_2_wires[73] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3975 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_3976 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_3977 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_3978 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_3979 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_3980 ) ) ; +sb_1__1_ sb_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_3981 } ) , + .chany_top_in ( cby_1__1__75_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__79_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__74_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_74_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_74_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_74_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_74_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_74_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_74_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_74_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_74_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__68_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_74_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_74_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_74_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_74_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_74_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_74_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_74_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_74_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__79_ccff_tail ) , + .chany_top_out ( sb_1__1__68_chany_top_out ) , + .chanx_right_out ( sb_1__1__68_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__68_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__68_chanx_left_out ) , + .ccff_tail ( sb_1__1__68_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_3982 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_3983 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_3984 ) , + .pReset_W_in ( pResetWires[185] ) , .pReset_N_out ( pResetWires[187] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_3985 ) , + .pReset_E_out ( pResetWires[188] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_3986 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[264] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[85] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_3987 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[134] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[135] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_3988 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_3989 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_3990 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_3991 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_3992 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_3993 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_3994 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_3995 ) , + .clk_1_N_in ( clk_2_wires[85] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_3996 ) , + .clk_1_E_out ( clk_1_wires[134] ) , .clk_1_W_out ( clk_1_wires[135] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_3997 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_3998 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_3999 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4000 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4002 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4003 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4004 ) ) ; +sb_1__1_ sb_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4005 } ) , + .chany_top_in ( cby_1__1__76_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__80_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__75_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_75_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_75_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_75_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_75_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_75_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_75_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_75_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_75_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__69_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_75_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_75_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_75_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_75_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_75_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_75_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_75_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_75_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__80_ccff_tail ) , + .chany_top_out ( sb_1__1__69_chany_top_out ) , + .chanx_right_out ( sb_1__1__69_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__69_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__69_chanx_left_out ) , + .ccff_tail ( sb_1__1__69_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4006 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4007 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4008 ) , + .pReset_W_in ( pResetWires[234] ) , .pReset_N_out ( pResetWires[236] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4009 ) , + .pReset_E_out ( pResetWires[237] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4010 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[267] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4011 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4012 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4013 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[81] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4014 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4015 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4016 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[84] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[82] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4017 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4018 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4019 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4020 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4021 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4022 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4023 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4024 ) , + .clk_2_E_in ( clk_2_wires[81] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4025 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4026 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4027 ) , + .clk_2_S_out ( clk_2_wires[84] ) , .clk_2_N_out ( clk_2_wires[82] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4028 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4029 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4030 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4031 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4032 ) ) ; +sb_1__1_ sb_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4033 } ) , + .chany_top_in ( cby_1__1__77_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__81_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__76_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_76_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_76_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_76_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_76_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_76_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_76_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_76_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_76_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__70_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_76_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_76_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_76_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_76_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_76_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_76_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_76_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_76_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__81_ccff_tail ) , + .chany_top_out ( sb_1__1__70_chany_top_out ) , + .chanx_right_out ( sb_1__1__70_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__70_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__70_chanx_left_out ) , + .ccff_tail ( sb_1__1__70_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4034 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4035 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4036 ) , + .pReset_W_in ( pResetWires[283] ) , .pReset_N_out ( pResetWires[285] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4037 ) , + .pReset_E_out ( pResetWires[286] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4038 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[270] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4039 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[83] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[141] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[142] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4040 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4041 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4042 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4043 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4044 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4045 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4046 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4047 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4048 ) , + .clk_1_S_in ( clk_2_wires[83] ) , .clk_1_E_out ( clk_1_wires[141] ) , + .clk_1_W_out ( clk_1_wires[142] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4049 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4050 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4051 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4052 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4053 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4054 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4055 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4056 ) ) ; +sb_1__1_ sb_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4057 } ) , + .chany_top_in ( cby_1__1__78_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__82_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__77_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_77_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_77_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_77_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_77_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_77_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_77_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_77_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_77_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__71_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_77_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_77_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_77_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_77_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_77_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_77_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_77_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_77_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__82_ccff_tail ) , + .chany_top_out ( sb_1__1__71_chany_top_out ) , + .chanx_right_out ( sb_1__1__71_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__71_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__71_chanx_left_out ) , + .ccff_tail ( sb_1__1__71_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4058 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4059 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4060 ) , + .pReset_W_in ( pResetWires[332] ) , .pReset_N_out ( pResetWires[334] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4061 ) , + .pReset_E_out ( pResetWires[335] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4062 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[273] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4063 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4064 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4065 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4066 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4067 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4068 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[1] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4069 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4070 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4071 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[4] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4072 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4073 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4074 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4075 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4076 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4077 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4078 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4079 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4080 ) , + .clk_3_W_in ( clk_3_wires[1] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4081 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4082 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4083 ) , + .clk_3_E_out ( clk_3_wires[4] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4084 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4085 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4086 ) ) ; +sb_1__1_ sb_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4087 } ) , + .chany_top_in ( cby_1__1__79_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__83_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__78_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_78_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_78_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_78_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_78_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_78_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_78_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_78_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_78_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__72_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_78_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_78_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_78_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_78_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_78_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_78_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_78_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_78_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__83_ccff_tail ) , + .chany_top_out ( sb_1__1__72_chany_top_out ) , + .chanx_right_out ( sb_1__1__72_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__72_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__72_chanx_left_out ) , + .ccff_tail ( sb_1__1__72_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4088 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4089 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4090 ) , + .pReset_W_in ( pResetWires[381] ) , .pReset_N_out ( pResetWires[383] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4091 ) , + .pReset_E_out ( pResetWires[384] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4092 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[276] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[98] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4093 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[148] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[149] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4094 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4095 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4096 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4097 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4098 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4099 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4100 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4101 ) , + .clk_1_N_in ( clk_2_wires[98] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4102 ) , + .clk_1_E_out ( clk_1_wires[148] ) , .clk_1_W_out ( clk_1_wires[149] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4103 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4104 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4105 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4106 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4107 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4108 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4109 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4110 ) ) ; +sb_1__1_ sb_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4111 } ) , + .chany_top_in ( cby_1__1__80_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__84_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__79_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_79_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_79_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_79_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_79_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_79_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_79_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_79_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_79_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__73_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_79_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_79_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_79_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_79_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_79_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_79_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_79_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_79_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__84_ccff_tail ) , + .chany_top_out ( sb_1__1__73_chany_top_out ) , + .chanx_right_out ( sb_1__1__73_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__73_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__73_chanx_left_out ) , + .ccff_tail ( sb_1__1__73_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4112 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4113 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4114 ) , + .pReset_W_in ( pResetWires[430] ) , .pReset_N_out ( pResetWires[432] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4115 ) , + .pReset_E_out ( pResetWires[433] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4116 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[279] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4117 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4118 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4119 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[94] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4120 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4121 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4122 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[97] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[95] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4123 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4124 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4125 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4126 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4127 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4128 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4129 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4130 ) , + .clk_2_E_in ( clk_2_wires[94] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4131 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4132 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4133 ) , + .clk_2_S_out ( clk_2_wires[97] ) , .clk_2_N_out ( clk_2_wires[95] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4134 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4135 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4136 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4137 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4138 ) ) ; +sb_1__1_ sb_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4139 } ) , + .chany_top_in ( cby_1__1__81_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__85_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__80_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_80_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_80_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_80_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_80_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_80_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_80_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_80_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_80_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__74_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_80_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_80_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_80_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_80_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_80_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_80_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_80_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_80_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__85_ccff_tail ) , + .chany_top_out ( sb_1__1__74_chany_top_out ) , + .chanx_right_out ( sb_1__1__74_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__74_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__74_chanx_left_out ) , + .ccff_tail ( sb_1__1__74_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4140 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4141 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4142 ) , + .pReset_W_in ( pResetWires[479] ) , .pReset_N_out ( pResetWires[481] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4143 ) , + .pReset_E_out ( pResetWires[482] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4144 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[282] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4145 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[96] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[155] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[156] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4146 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4147 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4148 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4149 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4150 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4151 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4152 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4153 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4154 ) , + .clk_1_S_in ( clk_2_wires[96] ) , .clk_1_E_out ( clk_1_wires[155] ) , + .clk_1_W_out ( clk_1_wires[156] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4155 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4156 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4157 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4158 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4159 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4160 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4161 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4162 ) ) ; +sb_1__1_ sb_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4163 } ) , + .chany_top_in ( cby_1__1__82_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__86_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__81_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_81_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_81_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_81_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_81_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_81_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_81_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_81_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_81_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__75_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_81_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_81_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_81_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_81_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_81_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_81_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_81_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_81_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__86_ccff_tail ) , + .chany_top_out ( sb_1__1__75_chany_top_out ) , + .chanx_right_out ( sb_1__1__75_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__75_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__75_chanx_left_out ) , + .ccff_tail ( sb_1__1__75_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4164 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4165 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4166 ) , + .pReset_W_in ( pResetWires[528] ) , .pReset_N_out ( pResetWires[530] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4167 ) , + .pReset_E_out ( pResetWires[531] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4168 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[285] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4169 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4170 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4171 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[107] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4172 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4173 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4174 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4175 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[108] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4176 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4177 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4178 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4179 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4180 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4181 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4182 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4183 ) , + .clk_2_E_in ( clk_2_wires[107] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4184 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4185 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4186 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4187 ) , + .clk_2_N_out ( clk_2_wires[108] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4188 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4189 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4190 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4192 ) ) ; +sb_1__1_ sb_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4193 } ) , + .chany_top_in ( cby_1__1__83_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__87_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__82_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_82_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_82_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_82_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_82_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_82_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_82_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_82_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_82_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__76_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_82_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_82_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_82_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_82_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_82_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_82_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_82_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_82_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__87_ccff_tail ) , + .chany_top_out ( sb_1__1__76_chany_top_out ) , + .chanx_right_out ( sb_1__1__76_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__76_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__76_chanx_left_out ) , + .ccff_tail ( sb_1__1__76_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4194 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4195 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4196 ) , + .pReset_W_in ( pResetWires[577] ) , .pReset_N_out ( pResetWires[579] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4197 ) , + .pReset_E_out ( pResetWires[580] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4198 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[288] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4199 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[109] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[162] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[163] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4200 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4201 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4202 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4203 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4204 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4205 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4206 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4207 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4208 ) , + .clk_1_S_in ( clk_2_wires[109] ) , .clk_1_E_out ( clk_1_wires[162] ) , + .clk_1_W_out ( clk_1_wires[163] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4209 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4210 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4211 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4212 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4213 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4214 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4215 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4216 ) ) ; +sb_1__1_ sb_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4217 } ) , + .chany_top_in ( cby_1__1__85_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__88_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__84_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_84_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_84_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_84_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_84_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_84_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_84_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_84_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_84_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__77_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_84_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_84_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_84_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_84_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_84_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_84_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_84_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_84_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__88_ccff_tail ) , + .chany_top_out ( sb_1__1__77_chany_top_out ) , + .chanx_right_out ( sb_1__1__77_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__77_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__77_chanx_left_out ) , + .ccff_tail ( sb_1__1__77_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4218 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4219 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4220 ) , + .pReset_W_in ( pResetWires[91] ) , .pReset_N_out ( pResetWires[93] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4221 ) , + .pReset_E_out ( pResetWires[94] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4222 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[296] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4223 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4224 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4225 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4226 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4227 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4228 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4229 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4230 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4231 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4232 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4233 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4234 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4235 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4236 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4237 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4238 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4239 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4240 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4241 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4242 ) ) ; +sb_1__1_ sb_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4243 } ) , + .chany_top_in ( cby_1__1__86_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__89_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__85_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_85_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_85_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_85_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_85_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_85_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_85_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_85_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_85_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__78_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_85_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_85_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_85_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_85_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_85_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_85_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_85_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_85_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__89_ccff_tail ) , + .chany_top_out ( sb_1__1__78_chany_top_out ) , + .chanx_right_out ( sb_1__1__78_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__78_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__78_chanx_left_out ) , + .ccff_tail ( sb_1__1__78_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4244 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4245 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4246 ) , + .pReset_W_in ( pResetWires[140] ) , .pReset_N_out ( pResetWires[142] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4247 ) , + .pReset_E_out ( pResetWires[143] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4248 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[299] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4249 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4250 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[43] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4251 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4252 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4253 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[71] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4254 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4255 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[69] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4256 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4257 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4258 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4259 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4260 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4261 ) , + .clk_2_N_in ( clk_3_wires[43] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4262 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4263 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4264 ) , + .clk_2_W_out ( clk_2_wires[71] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4265 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4266 ) , + .clk_2_E_out ( clk_2_wires[69] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4267 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4268 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4269 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4270 ) ) ; +sb_1__1_ sb_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4271 } ) , + .chany_top_in ( cby_1__1__87_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__90_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__86_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_86_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_86_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_86_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_86_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_86_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_86_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_86_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_86_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__79_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_86_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_86_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_86_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_86_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_86_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_86_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_86_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_86_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__90_ccff_tail ) , + .chany_top_out ( sb_1__1__79_chany_top_out ) , + .chanx_right_out ( sb_1__1__79_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__79_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__79_chanx_left_out ) , + .ccff_tail ( sb_1__1__79_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4272 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4273 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4274 ) , + .pReset_W_in ( pResetWires[189] ) , .pReset_N_out ( pResetWires[191] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4275 ) , + .pReset_E_out ( pResetWires[192] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4276 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[302] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4277 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4278 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4279 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4280 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4281 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4282 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4283 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4284 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4285 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[39] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4286 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4287 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4288 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[42] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4289 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4290 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4291 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4292 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4293 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4294 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4295 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4296 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4297 ) , + .clk_3_N_in ( clk_3_wires[39] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4298 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4299 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4300 ) , + .clk_3_S_out ( clk_3_wires[42] ) ) ; +sb_1__1_ sb_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4301 } ) , + .chany_top_in ( cby_1__1__88_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__91_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__87_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_87_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_87_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_87_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_87_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_87_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_87_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_87_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_87_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__80_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_87_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_87_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_87_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_87_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_87_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_87_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_87_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_87_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__91_ccff_tail ) , + .chany_top_out ( sb_1__1__80_chany_top_out ) , + .chanx_right_out ( sb_1__1__80_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__80_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__80_chanx_left_out ) , + .ccff_tail ( sb_1__1__80_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4302 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4303 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4304 ) , + .pReset_W_in ( pResetWires[238] ) , .pReset_N_out ( pResetWires[240] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4305 ) , + .pReset_E_out ( pResetWires[241] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4306 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[305] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4307 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4308 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[33] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4309 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4310 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4311 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[80] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4312 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4313 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[78] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4314 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4315 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4316 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[33] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4317 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4318 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4319 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[38] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4320 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4321 ) , + .clk_2_N_in ( clk_3_wires[33] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4322 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4323 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4324 ) , + .clk_2_W_out ( clk_2_wires[80] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4325 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4326 ) , + .clk_2_E_out ( clk_2_wires[78] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4327 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4328 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4329 ) , + .clk_3_N_in ( clk_3_wires[33] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4330 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4331 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4332 ) , + .clk_3_S_out ( clk_3_wires[38] ) ) ; +sb_1__1_ sb_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4333 } ) , + .chany_top_in ( cby_1__1__89_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__92_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__88_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_88_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_88_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_88_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_88_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_88_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_88_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_88_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_88_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__81_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_88_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_88_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_88_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_88_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_88_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_88_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_88_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_88_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__92_ccff_tail ) , + .chany_top_out ( sb_1__1__81_chany_top_out ) , + .chanx_right_out ( sb_1__1__81_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__81_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__81_chanx_left_out ) , + .ccff_tail ( sb_1__1__81_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4334 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4335 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4336 ) , + .pReset_W_in ( pResetWires[287] ) , .pReset_N_out ( pResetWires[289] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4337 ) , + .pReset_E_out ( pResetWires[290] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4338 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[308] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4339 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4340 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4341 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4342 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4343 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4344 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4345 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4346 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4347 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[29] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4348 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4349 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4350 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[32] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4351 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4352 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4353 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4354 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4355 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4356 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4357 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4358 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4359 ) , + .clk_3_N_in ( clk_3_wires[29] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4360 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4361 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4362 ) , + .clk_3_S_out ( clk_3_wires[32] ) ) ; +sb_1__1_ sb_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4363 } ) , + .chany_top_in ( cby_1__1__90_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__93_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__89_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_89_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_89_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_89_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_89_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_89_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_89_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_89_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_89_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__82_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_89_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_89_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_89_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_89_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_89_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_89_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_89_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_89_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__93_ccff_tail ) , + .chany_top_out ( sb_1__1__82_chany_top_out ) , + .chanx_right_out ( sb_1__1__82_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__82_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__82_chanx_left_out ) , + .ccff_tail ( sb_1__1__82_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4364 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4365 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4366 ) , + .pReset_W_in ( pResetWires[336] ) , .pReset_N_out ( pResetWires[338] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4367 ) , + .pReset_E_out ( pResetWires[339] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4368 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[311] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4369 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4370 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4371 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4372 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4373 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4374 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[5] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4375 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4376 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4377 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[44] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4378 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[26] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[28] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4379 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4380 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4381 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4382 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4383 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4384 ) , + .clk_3_W_in ( clk_3_wires[5] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4385 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4386 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4387 ) , + .clk_3_E_out ( clk_3_wires[44] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4388 ) , + .clk_3_N_out ( clk_3_wires[26] ) , .clk_3_S_out ( clk_3_wires[28] ) ) ; +sb_1__1_ sb_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4389 } ) , + .chany_top_in ( cby_1__1__91_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__94_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__90_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_90_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_90_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_90_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_90_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_90_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_90_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_90_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_90_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__83_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_90_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_90_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_90_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_90_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_90_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_90_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_90_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_90_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__94_ccff_tail ) , + .chany_top_out ( sb_1__1__83_chany_top_out ) , + .chanx_right_out ( sb_1__1__83_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__83_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__83_chanx_left_out ) , + .ccff_tail ( sb_1__1__83_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4390 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4391 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4392 ) , + .pReset_W_in ( pResetWires[385] ) , .pReset_N_out ( pResetWires[387] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4393 ) , + .pReset_E_out ( pResetWires[388] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4394 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[314] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4395 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4396 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4397 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4398 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4399 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4400 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4401 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4402 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[27] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4403 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4404 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4405 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[30] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4406 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4407 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4408 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4409 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4410 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4411 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4412 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4413 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4414 ) , + .clk_3_S_in ( clk_3_wires[27] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4415 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4416 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4417 ) , + .clk_3_N_out ( clk_3_wires[30] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4418 ) ) ; +sb_1__1_ sb_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4419 } ) , + .chany_top_in ( cby_1__1__92_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__95_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__91_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_91_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_91_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_91_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_91_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_91_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_91_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_91_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_91_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__84_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_91_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_91_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_91_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_91_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_91_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_91_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_91_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_91_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__95_ccff_tail ) , + .chany_top_out ( sb_1__1__84_chany_top_out ) , + .chanx_right_out ( sb_1__1__84_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__84_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__84_chanx_left_out ) , + .ccff_tail ( sb_1__1__84_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4420 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4421 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4422 ) , + .pReset_W_in ( pResetWires[434] ) , .pReset_N_out ( pResetWires[436] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4423 ) , + .pReset_E_out ( pResetWires[437] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4424 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[317] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4425 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4426 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4427 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4428 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[31] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4429 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[93] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4430 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4431 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[91] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4432 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4433 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[31] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4434 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4436 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[36] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4437 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4438 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4439 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4440 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4441 ) , + .clk_2_S_in ( clk_3_wires[31] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4442 ) , + .clk_2_W_out ( clk_2_wires[93] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4443 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4444 ) , + .clk_2_E_out ( clk_2_wires[91] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4445 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4446 ) , + .clk_3_S_in ( clk_3_wires[31] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4447 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4448 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4449 ) , + .clk_3_N_out ( clk_3_wires[36] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4450 ) ) ; +sb_1__1_ sb_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4451 } ) , + .chany_top_in ( cby_1__1__93_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__96_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__92_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_92_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_92_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_92_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_92_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_92_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_92_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_92_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_92_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__85_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_92_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_92_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_92_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_92_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_92_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_92_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_92_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_92_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__96_ccff_tail ) , + .chany_top_out ( sb_1__1__85_chany_top_out ) , + .chanx_right_out ( sb_1__1__85_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__85_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__85_chanx_left_out ) , + .ccff_tail ( sb_1__1__85_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4452 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4453 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4454 ) , + .pReset_W_in ( pResetWires[483] ) , .pReset_N_out ( pResetWires[485] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4455 ) , + .pReset_E_out ( pResetWires[486] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4456 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[320] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4457 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4458 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4459 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4460 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4461 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4462 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4463 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4464 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[37] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4465 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4466 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4467 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[40] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4468 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4469 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4470 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4471 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4472 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4473 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4474 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4475 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4476 ) , + .clk_3_S_in ( clk_3_wires[37] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4477 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4478 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4479 ) , + .clk_3_N_out ( clk_3_wires[40] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4480 ) ) ; +sb_1__1_ sb_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4481 } ) , + .chany_top_in ( cby_1__1__94_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__97_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__93_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_93_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_93_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_93_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_93_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_93_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_93_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_93_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_93_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__86_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_93_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_93_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_93_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_93_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_93_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_93_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_93_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_93_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__97_ccff_tail ) , + .chany_top_out ( sb_1__1__86_chany_top_out ) , + .chanx_right_out ( sb_1__1__86_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__86_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__86_chanx_left_out ) , + .ccff_tail ( sb_1__1__86_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4482 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4483 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4484 ) , + .pReset_W_in ( pResetWires[532] ) , .pReset_N_out ( pResetWires[534] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4485 ) , + .pReset_E_out ( pResetWires[535] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4486 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[323] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4487 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4488 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4489 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4490 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[41] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4491 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[106] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4492 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4493 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[104] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4494 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4495 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4496 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4497 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4498 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4499 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4500 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4501 ) , + .clk_2_S_in ( clk_3_wires[41] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4502 ) , + .clk_2_W_out ( clk_2_wires[106] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4503 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4504 ) , + .clk_2_E_out ( clk_2_wires[104] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4505 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4506 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4507 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4508 ) ) ; +sb_1__1_ sb_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4509 } ) , + .chany_top_in ( cby_1__1__95_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__98_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__94_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_94_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_94_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_94_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_94_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_94_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_94_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_94_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_94_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__87_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_94_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_94_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_94_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_94_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_94_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_94_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_94_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_94_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__98_ccff_tail ) , + .chany_top_out ( sb_1__1__87_chany_top_out ) , + .chanx_right_out ( sb_1__1__87_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__87_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__87_chanx_left_out ) , + .ccff_tail ( sb_1__1__87_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4510 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4511 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4512 ) , + .pReset_W_in ( pResetWires[581] ) , .pReset_N_out ( pResetWires[583] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4513 ) , + .pReset_E_out ( pResetWires[584] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4514 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[326] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4515 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4516 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4517 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4518 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4519 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4520 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4521 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4522 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4523 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4524 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4525 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4526 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4527 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4528 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4529 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4530 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4531 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4532 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4533 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4534 ) ) ; +sb_1__1_ sb_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4535 } ) , + .chany_top_in ( cby_1__1__97_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__99_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__96_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_96_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_96_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_96_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_96_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_96_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_96_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_96_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_96_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__88_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_96_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_96_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_96_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_96_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_96_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_96_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_96_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_96_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__99_ccff_tail ) , + .chany_top_out ( sb_1__1__88_chany_top_out ) , + .chanx_right_out ( sb_1__1__88_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__88_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__88_chanx_left_out ) , + .ccff_tail ( sb_1__1__88_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4536 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4537 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4538 ) , + .pReset_W_in ( pResetWires[95] ) , .pReset_N_out ( pResetWires[97] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4539 ) , + .pReset_E_out ( pResetWires[98] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4540 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[334] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[76] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4541 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[169] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[170] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4542 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4543 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4544 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4545 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4546 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4547 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4548 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4549 ) , + .clk_1_N_in ( clk_2_wires[76] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4550 ) , + .clk_1_E_out ( clk_1_wires[169] ) , .clk_1_W_out ( clk_1_wires[170] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4551 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4552 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4553 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4554 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4555 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4556 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4557 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4558 ) ) ; +sb_1__1_ sb_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4559 } ) , + .chany_top_in ( cby_1__1__98_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__100_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__97_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_97_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_97_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_97_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_97_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_97_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_97_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_97_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_97_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__89_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_97_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_97_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_97_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_97_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_97_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_97_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_97_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_97_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__100_ccff_tail ) , + .chany_top_out ( sb_1__1__89_chany_top_out ) , + .chanx_right_out ( sb_1__1__89_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__89_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__89_chanx_left_out ) , + .ccff_tail ( sb_1__1__89_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4560 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4561 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4562 ) , + .pReset_W_in ( pResetWires[144] ) , .pReset_N_out ( pResetWires[146] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4563 ) , + .pReset_E_out ( pResetWires[147] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4564 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[337] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4565 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4566 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4567 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4568 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4569 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[70] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4570 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[75] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4571 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4572 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4573 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4574 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4575 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4576 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4577 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4578 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4579 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4580 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4581 ) , + .clk_2_W_in ( clk_2_wires[70] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4582 ) , + .clk_2_S_out ( clk_2_wires[75] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4583 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4584 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4585 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4586 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4587 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4588 ) ) ; +sb_1__1_ sb_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4589 } ) , + .chany_top_in ( cby_1__1__99_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__101_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__98_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_98_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_98_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_98_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_98_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_98_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_98_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_98_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_98_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__90_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_98_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_98_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_98_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_98_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_98_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_98_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_98_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_98_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__101_ccff_tail ) , + .chany_top_out ( sb_1__1__90_chany_top_out ) , + .chanx_right_out ( sb_1__1__90_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__90_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__90_chanx_left_out ) , + .ccff_tail ( sb_1__1__90_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4590 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4591 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4592 ) , + .pReset_W_in ( pResetWires[193] ) , .pReset_N_out ( pResetWires[195] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4593 ) , + .pReset_E_out ( pResetWires[196] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4594 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[340] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[89] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4595 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[176] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[177] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4596 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4597 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4598 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4599 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4600 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4601 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4602 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4603 ) , + .clk_1_N_in ( clk_2_wires[89] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4604 ) , + .clk_1_E_out ( clk_1_wires[176] ) , .clk_1_W_out ( clk_1_wires[177] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4605 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4606 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4607 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4608 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4609 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4610 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4611 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4612 ) ) ; +sb_1__1_ sb_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4613 } ) , + .chany_top_in ( cby_1__1__100_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__102_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__99_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_99_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_99_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_99_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_99_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_99_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_99_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_99_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_99_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__91_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_99_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_99_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_99_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_99_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_99_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_99_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_99_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_99_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__102_ccff_tail ) , + .chany_top_out ( sb_1__1__91_chany_top_out ) , + .chanx_right_out ( sb_1__1__91_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__91_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__91_chanx_left_out ) , + .ccff_tail ( sb_1__1__91_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4614 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4615 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4616 ) , + .pReset_W_in ( pResetWires[242] ) , .pReset_N_out ( pResetWires[244] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4617 ) , + .pReset_E_out ( pResetWires[245] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4618 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[343] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4619 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4620 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4621 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4622 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4623 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[79] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4624 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[88] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[86] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4625 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4626 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4627 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4628 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4629 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4630 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4631 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4632 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4633 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4634 ) , + .clk_2_W_in ( clk_2_wires[79] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4635 ) , + .clk_2_S_out ( clk_2_wires[88] ) , .clk_2_N_out ( clk_2_wires[86] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4636 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4637 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4638 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4639 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4640 ) ) ; +sb_1__1_ sb_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4641 } ) , + .chany_top_in ( cby_1__1__101_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__103_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__100_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_100_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_100_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_100_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_100_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_100_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_100_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_100_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_100_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__92_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_100_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_100_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_100_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_100_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_100_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_100_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_100_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_100_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__103_ccff_tail ) , + .chany_top_out ( sb_1__1__92_chany_top_out ) , + .chanx_right_out ( sb_1__1__92_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__92_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__92_chanx_left_out ) , + .ccff_tail ( sb_1__1__92_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4642 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4643 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4644 ) , + .pReset_W_in ( pResetWires[291] ) , .pReset_N_out ( pResetWires[293] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4645 ) , + .pReset_E_out ( pResetWires[294] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4646 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[346] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4647 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[87] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[183] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[184] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4648 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4649 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4650 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4651 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4652 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4653 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4654 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4655 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4656 ) , + .clk_1_S_in ( clk_2_wires[87] ) , .clk_1_E_out ( clk_1_wires[183] ) , + .clk_1_W_out ( clk_1_wires[184] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4657 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4658 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4659 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4660 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4661 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4662 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4663 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4664 ) ) ; +sb_1__1_ sb_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4665 } ) , + .chany_top_in ( cby_1__1__102_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__104_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__101_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_101_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_101_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_101_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_101_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_101_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_101_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_101_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_101_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__93_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_101_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_101_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_101_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_101_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_101_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_101_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_101_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_101_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__104_ccff_tail ) , + .chany_top_out ( sb_1__1__93_chany_top_out ) , + .chanx_right_out ( sb_1__1__93_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__93_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__93_chanx_left_out ) , + .ccff_tail ( sb_1__1__93_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4666 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4667 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4668 ) , + .pReset_W_in ( pResetWires[340] ) , .pReset_N_out ( pResetWires[342] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4669 ) , + .pReset_E_out ( pResetWires[343] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4670 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[349] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4671 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4672 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4673 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4674 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4675 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4676 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[45] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4677 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4678 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4679 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[48] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4680 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4682 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4683 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4684 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4685 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4686 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4687 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4688 ) , + .clk_3_W_in ( clk_3_wires[45] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4689 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4690 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_4691 ) , + .clk_3_E_out ( clk_3_wires[48] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4692 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4693 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4694 ) ) ; +sb_1__1_ sb_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4695 } ) , + .chany_top_in ( cby_1__1__103_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__105_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__102_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_102_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_102_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_102_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_102_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_102_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_102_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_102_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_102_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__94_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_102_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_102_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_102_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_102_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_102_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_102_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_102_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_102_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__105_ccff_tail ) , + .chany_top_out ( sb_1__1__94_chany_top_out ) , + .chanx_right_out ( sb_1__1__94_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__94_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__94_chanx_left_out ) , + .ccff_tail ( sb_1__1__94_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4696 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4697 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4698 ) , + .pReset_W_in ( pResetWires[389] ) , .pReset_N_out ( pResetWires[391] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4699 ) , + .pReset_E_out ( pResetWires[392] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4700 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[352] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[102] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_4701 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[190] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[191] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4702 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4703 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4704 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4705 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4706 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4707 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4708 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4709 ) , + .clk_1_N_in ( clk_2_wires[102] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_4710 ) , + .clk_1_E_out ( clk_1_wires[190] ) , .clk_1_W_out ( clk_1_wires[191] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4711 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4712 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4713 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4714 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4715 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4716 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4717 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4718 ) ) ; +sb_1__1_ sb_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4719 } ) , + .chany_top_in ( cby_1__1__104_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__106_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__103_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_103_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_103_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_103_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_103_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_103_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_103_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_103_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_103_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__95_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_103_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_103_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_103_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_103_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_103_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_103_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_103_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_103_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__106_ccff_tail ) , + .chany_top_out ( sb_1__1__95_chany_top_out ) , + .chanx_right_out ( sb_1__1__95_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__95_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__95_chanx_left_out ) , + .ccff_tail ( sb_1__1__95_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4720 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4721 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4722 ) , + .pReset_W_in ( pResetWires[438] ) , .pReset_N_out ( pResetWires[440] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4723 ) , + .pReset_E_out ( pResetWires[441] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4724 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[355] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4725 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4726 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4727 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4728 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4729 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[92] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4730 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[101] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[99] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4731 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4733 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4734 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4735 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4736 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4737 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4738 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4739 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4740 ) , + .clk_2_W_in ( clk_2_wires[92] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4741 ) , + .clk_2_S_out ( clk_2_wires[101] ) , .clk_2_N_out ( clk_2_wires[99] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4742 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4743 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4744 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4745 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4746 ) ) ; +sb_1__1_ sb_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4747 } ) , + .chany_top_in ( cby_1__1__105_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__107_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__104_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_104_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_104_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_104_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_104_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_104_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_104_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_104_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_104_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__96_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_104_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_104_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_104_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_104_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_104_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_104_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_104_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_104_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__107_ccff_tail ) , + .chany_top_out ( sb_1__1__96_chany_top_out ) , + .chanx_right_out ( sb_1__1__96_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__96_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__96_chanx_left_out ) , + .ccff_tail ( sb_1__1__96_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4748 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4749 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4750 ) , + .pReset_W_in ( pResetWires[487] ) , .pReset_N_out ( pResetWires[489] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4751 ) , + .pReset_E_out ( pResetWires[490] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4752 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[358] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4753 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[100] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[197] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[198] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4754 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4755 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4756 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4757 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4758 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4759 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4760 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4761 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4762 ) , + .clk_1_S_in ( clk_2_wires[100] ) , .clk_1_E_out ( clk_1_wires[197] ) , + .clk_1_W_out ( clk_1_wires[198] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4763 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4764 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4765 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4766 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4767 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4768 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4769 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4770 ) ) ; +sb_1__1_ sb_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4771 } ) , + .chany_top_in ( cby_1__1__106_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__108_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__105_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_105_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_105_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_105_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_105_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_105_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_105_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_105_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_105_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__97_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_105_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_105_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_105_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_105_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_105_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_105_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_105_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_105_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__108_ccff_tail ) , + .chany_top_out ( sb_1__1__97_chany_top_out ) , + .chanx_right_out ( sb_1__1__97_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__97_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__97_chanx_left_out ) , + .ccff_tail ( sb_1__1__97_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4772 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4773 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4774 ) , + .pReset_W_in ( pResetWires[536] ) , .pReset_N_out ( pResetWires[538] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4775 ) , + .pReset_E_out ( pResetWires[539] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4776 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[361] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4777 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4778 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_4779 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4780 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4781 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[105] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4782 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4783 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[110] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4784 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4785 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4786 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4787 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4788 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4789 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4790 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_4791 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4792 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4793 ) , + .clk_2_W_in ( clk_2_wires[105] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4794 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4795 ) , + .clk_2_N_out ( clk_2_wires[110] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4796 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4797 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4798 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4799 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4800 ) ) ; +sb_1__1_ sb_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4801 } ) , + .chany_top_in ( cby_1__1__107_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__109_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__106_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_106_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_106_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_106_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_106_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_106_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_106_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_106_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_106_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__98_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_106_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_106_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_106_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_106_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_106_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_106_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_106_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_106_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__109_ccff_tail ) , + .chany_top_out ( sb_1__1__98_chany_top_out ) , + .chanx_right_out ( sb_1__1__98_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__98_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__98_chanx_left_out ) , + .ccff_tail ( sb_1__1__98_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4802 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4803 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4804 ) , + .pReset_W_in ( pResetWires[585] ) , .pReset_N_out ( pResetWires[587] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4805 ) , + .pReset_E_out ( pResetWires[588] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4806 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[364] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_4807 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[111] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[204] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[205] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4808 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4809 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4810 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4811 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4812 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4813 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4814 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4815 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_4816 ) , + .clk_1_S_in ( clk_2_wires[111] ) , .clk_1_E_out ( clk_1_wires[204] ) , + .clk_1_W_out ( clk_1_wires[205] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4817 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4818 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4819 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4820 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4821 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4822 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4823 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4824 ) ) ; +sb_1__1_ sb_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4825 } ) , + .chany_top_in ( cby_1__1__109_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__110_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__108_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_108_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_108_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_108_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_108_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_108_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_108_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_108_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_108_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__99_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_108_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_108_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_108_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_108_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_108_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_108_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_108_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_108_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__110_ccff_tail ) , + .chany_top_out ( sb_1__1__99_chany_top_out ) , + .chanx_right_out ( sb_1__1__99_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__99_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__99_chanx_left_out ) , + .ccff_tail ( sb_1__1__99_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4826 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4827 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4828 ) , + .pReset_W_in ( pResetWires[99] ) , .pReset_N_out ( pResetWires[101] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4829 ) , + .pReset_E_out ( pResetWires[102] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4830 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[372] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4831 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4832 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4833 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4834 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4835 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4836 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4837 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4838 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4839 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4840 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4841 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4842 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4843 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4844 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4845 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4846 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4847 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4848 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4849 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4850 ) ) ; +sb_1__1_ sb_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4851 } ) , + .chany_top_in ( cby_1__1__110_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__111_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__109_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_109_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_109_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_109_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_109_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_109_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_109_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_109_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_109_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__100_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_109_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_109_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_109_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_109_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_109_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_109_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_109_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_109_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__111_ccff_tail ) , + .chany_top_out ( sb_1__1__100_chany_top_out ) , + .chanx_right_out ( sb_1__1__100_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__100_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__100_chanx_left_out ) , + .ccff_tail ( sb_1__1__100_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4852 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4853 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4854 ) , + .pReset_W_in ( pResetWires[148] ) , .pReset_N_out ( pResetWires[150] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4855 ) , + .pReset_E_out ( pResetWires[151] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4856 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[375] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4857 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4858 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[87] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4859 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4860 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4861 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4862 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4863 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4864 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[114] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4865 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4866 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4867 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_4868 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4869 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4870 ) , + .clk_2_N_in ( clk_3_wires[87] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4871 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4872 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4873 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4874 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4875 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4876 ) , + .clk_2_E_out ( clk_2_wires[114] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4877 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4878 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4879 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_4880 ) ) ; +sb_1__1_ sb_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4881 } ) , + .chany_top_in ( cby_1__1__111_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__112_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__110_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_110_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_110_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_110_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_110_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_110_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_110_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_110_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_110_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__101_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_110_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_110_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_110_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_110_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_110_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_110_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_110_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_110_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__112_ccff_tail ) , + .chany_top_out ( sb_1__1__101_chany_top_out ) , + .chanx_right_out ( sb_1__1__101_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__101_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__101_chanx_left_out ) , + .ccff_tail ( sb_1__1__101_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4882 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4883 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4884 ) , + .pReset_W_in ( pResetWires[197] ) , .pReset_N_out ( pResetWires[199] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4885 ) , + .pReset_E_out ( pResetWires[200] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4886 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[378] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4887 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4888 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4889 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4890 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4891 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4892 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4893 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4894 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4895 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[83] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4896 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4897 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4898 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[86] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4899 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4900 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4901 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4902 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4903 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4904 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4905 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4906 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4907 ) , + .clk_3_N_in ( clk_3_wires[83] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4908 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4909 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4910 ) , + .clk_3_S_out ( clk_3_wires[86] ) ) ; +sb_1__1_ sb_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4911 } ) , + .chany_top_in ( cby_1__1__112_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__113_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__111_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_111_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_111_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_111_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_111_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_111_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_111_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_111_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_111_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__102_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_111_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_111_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_111_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_111_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_111_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_111_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_111_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_111_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__113_ccff_tail ) , + .chany_top_out ( sb_1__1__102_chany_top_out ) , + .chanx_right_out ( sb_1__1__102_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__102_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__102_chanx_left_out ) , + .ccff_tail ( sb_1__1__102_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4912 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4913 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4914 ) , + .pReset_W_in ( pResetWires[246] ) , .pReset_N_out ( pResetWires[248] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4915 ) , + .pReset_E_out ( pResetWires[249] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4916 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[381] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4917 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4918 ) , + .prog_clk_2_N_in ( prog_clk_3_wires[77] ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_4919 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_4920 ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_4921 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4922 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4923 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4924 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[119] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4925 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4926 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4927 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[77] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4928 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4929 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4930 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[82] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4931 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4932 ) , + .clk_2_N_in ( clk_3_wires[77] ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_4933 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_4934 ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_4935 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4936 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4937 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4938 ) , + .clk_2_E_out ( clk_2_wires[119] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4939 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4940 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4941 ) , + .clk_3_N_in ( clk_3_wires[77] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4942 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4943 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4944 ) , + .clk_3_S_out ( clk_3_wires[82] ) ) ; +sb_1__1_ sb_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4945 } ) , + .chany_top_in ( cby_1__1__113_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__114_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__112_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_112_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_112_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_112_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_112_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_112_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_112_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_112_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_112_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__103_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_112_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_112_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_112_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_112_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_112_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_112_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_112_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_112_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__114_ccff_tail ) , + .chany_top_out ( sb_1__1__103_chany_top_out ) , + .chanx_right_out ( sb_1__1__103_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__103_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__103_chanx_left_out ) , + .ccff_tail ( sb_1__1__103_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4946 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4947 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4948 ) , + .pReset_W_in ( pResetWires[295] ) , .pReset_N_out ( pResetWires[297] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4949 ) , + .pReset_E_out ( pResetWires[298] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4950 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[384] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4951 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4952 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4953 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4954 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4955 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4956 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_4957 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4958 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4959 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[73] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4960 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4961 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_4962 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[76] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4963 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4964 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4965 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4966 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4967 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4968 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_4969 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4970 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4971 ) , + .clk_3_N_in ( clk_3_wires[73] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_4972 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_4973 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_4974 ) , + .clk_3_S_out ( clk_3_wires[76] ) ) ; +sb_1__1_ sb_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_4975 } ) , + .chany_top_in ( cby_1__1__114_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__115_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__113_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_113_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_113_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_113_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_113_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_113_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_113_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_113_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_113_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__104_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_113_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_113_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_113_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_113_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_113_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_113_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_113_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_113_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__115_ccff_tail ) , + .chany_top_out ( sb_1__1__104_chany_top_out ) , + .chanx_right_out ( sb_1__1__104_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__104_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__104_chanx_left_out ) , + .ccff_tail ( sb_1__1__104_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_4976 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_4977 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_4978 ) , + .pReset_W_in ( pResetWires[344] ) , .pReset_N_out ( pResetWires[346] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_4979 ) , + .pReset_E_out ( pResetWires[347] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_4980 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[387] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_4981 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_4982 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_4983 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_4984 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_4985 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_4986 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[49] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_4987 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_4988 ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_4989 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_4990 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_4991 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[70] ) , + .prog_clk_3_S_out ( prog_clk_3_wires[72] ) , .clk_1_N_in ( h_incr0 ) , + .clk_1_S_in ( h_incr0 ) , .clk_1_E_out ( SYNOPSYS_UNCONNECTED_4992 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_4993 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_4994 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_4995 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_4996 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_4997 ) , + .clk_3_W_in ( clk_3_wires[49] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_4998 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_4999 ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5000 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5001 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5002 ) , + .clk_3_N_out ( clk_3_wires[70] ) , .clk_3_S_out ( clk_3_wires[72] ) ) ; +sb_1__1_ sb_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5003 } ) , + .chany_top_in ( cby_1__1__115_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__116_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__114_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_114_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_114_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_114_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_114_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_114_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_114_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_114_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_114_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__105_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_114_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_114_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_114_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_114_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_114_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_114_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_114_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_114_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__116_ccff_tail ) , + .chany_top_out ( sb_1__1__105_chany_top_out ) , + .chanx_right_out ( sb_1__1__105_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__105_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__105_chanx_left_out ) , + .ccff_tail ( sb_1__1__105_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5004 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5005 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5006 ) , + .pReset_W_in ( pResetWires[393] ) , .pReset_N_out ( pResetWires[395] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5007 ) , + .pReset_E_out ( pResetWires[396] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5008 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[390] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5009 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5010 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5011 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5012 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5013 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5014 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5015 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5016 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[71] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5017 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5018 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5019 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[74] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5020 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5021 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5022 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5023 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5024 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5025 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5026 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5027 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5028 ) , + .clk_3_S_in ( clk_3_wires[71] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5029 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5030 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5031 ) , + .clk_3_N_out ( clk_3_wires[74] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5032 ) ) ; +sb_1__1_ sb_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5033 } ) , + .chany_top_in ( cby_1__1__116_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__117_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__115_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_115_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_115_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_115_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_115_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_115_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_115_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_115_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_115_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__106_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_115_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_115_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_115_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_115_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_115_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_115_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_115_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_115_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__117_ccff_tail ) , + .chany_top_out ( sb_1__1__106_chany_top_out ) , + .chanx_right_out ( sb_1__1__106_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__106_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__106_chanx_left_out ) , + .ccff_tail ( sb_1__1__106_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5034 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5035 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5036 ) , + .pReset_W_in ( pResetWires[442] ) , .pReset_N_out ( pResetWires[444] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5037 ) , + .pReset_E_out ( pResetWires[445] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5038 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[393] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5039 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5040 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5041 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5042 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[75] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5043 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5044 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5045 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5046 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[126] ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5047 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5048 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[75] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5049 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5050 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5051 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[80] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5052 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5053 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5054 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5055 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5056 ) , + .clk_2_S_in ( clk_3_wires[75] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5057 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5058 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5059 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5060 ) , + .clk_2_E_out ( clk_2_wires[126] ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5061 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5062 ) , + .clk_3_S_in ( clk_3_wires[75] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5063 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5064 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5065 ) , + .clk_3_N_out ( clk_3_wires[80] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5066 ) ) ; +sb_1__1_ sb_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5067 } ) , + .chany_top_in ( cby_1__1__117_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__118_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__116_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_116_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_116_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_116_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_116_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_116_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_116_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_116_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_116_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__107_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_116_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_116_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_116_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_116_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_116_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_116_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_116_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_116_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__118_ccff_tail ) , + .chany_top_out ( sb_1__1__107_chany_top_out ) , + .chanx_right_out ( sb_1__1__107_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__107_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__107_chanx_left_out ) , + .ccff_tail ( sb_1__1__107_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5068 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5069 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5070 ) , + .pReset_W_in ( pResetWires[491] ) , .pReset_N_out ( pResetWires[493] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5071 ) , + .pReset_E_out ( pResetWires[494] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5072 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[396] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5073 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5074 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5075 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5076 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5077 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5078 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5079 ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_5080 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[81] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_5081 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5082 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5083 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[84] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5084 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5085 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5086 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5087 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5088 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5089 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5090 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5091 ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_5092 ) , + .clk_3_S_in ( clk_3_wires[81] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_5093 ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5094 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5095 ) , + .clk_3_N_out ( clk_3_wires[84] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5096 ) ) ; +sb_1__1_ sb_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5097 } ) , + .chany_top_in ( cby_1__1__118_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__119_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__117_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_117_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_117_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_117_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_117_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_117_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_117_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_117_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_117_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__108_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_117_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_117_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_117_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_117_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_117_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_117_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_117_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_117_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__119_ccff_tail ) , + .chany_top_out ( sb_1__1__108_chany_top_out ) , + .chanx_right_out ( sb_1__1__108_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__108_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__108_chanx_left_out ) , + .ccff_tail ( sb_1__1__108_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5098 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5099 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5100 ) , + .pReset_W_in ( pResetWires[540] ) , .pReset_N_out ( pResetWires[542] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5101 ) , + .pReset_E_out ( pResetWires[543] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5102 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[399] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5103 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5104 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5105 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5106 ) , + .prog_clk_2_S_in ( prog_clk_3_wires[85] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5107 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5108 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5109 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5110 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[133] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5111 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5112 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5113 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5114 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5115 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5116 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5117 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5118 ) , + .clk_2_S_in ( clk_3_wires[85] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5119 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5120 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5121 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5122 ) , + .clk_2_E_out ( clk_2_wires[133] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5123 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5124 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5125 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5126 ) ) ; +sb_1__1_ sb_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5127 } ) , + .chany_top_in ( cby_1__1__119_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__120_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__118_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_118_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_118_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_118_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_118_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_118_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_118_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_118_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_118_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__109_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_118_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_118_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_118_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_118_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_118_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_118_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_118_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_118_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__120_ccff_tail ) , + .chany_top_out ( sb_1__1__109_chany_top_out ) , + .chanx_right_out ( sb_1__1__109_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__109_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__109_chanx_left_out ) , + .ccff_tail ( sb_1__1__109_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5128 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5129 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5130 ) , + .pReset_W_in ( pResetWires[589] ) , .pReset_N_out ( pResetWires[591] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5131 ) , + .pReset_E_out ( pResetWires[592] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5132 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[402] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5133 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5134 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5135 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5136 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5137 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5138 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5139 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5140 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5141 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5142 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5143 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5144 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5145 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5146 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5147 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5148 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5149 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5150 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5151 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5152 ) ) ; +sb_1__1_ sb_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5153 } ) , + .chany_top_in ( cby_1__1__121_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__121_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__120_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_120_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_120_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_120_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_120_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_120_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_120_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_120_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_120_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__110_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_120_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_120_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_120_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_120_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_120_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_120_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_120_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_120_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__121_ccff_tail ) , + .chany_top_out ( sb_1__1__110_chany_top_out ) , + .chanx_right_out ( sb_1__1__110_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__110_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__110_chanx_left_out ) , + .ccff_tail ( sb_1__1__110_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5154 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5155 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5156 ) , + .pReset_W_in ( pResetWires[103] ) , .pReset_N_out ( pResetWires[105] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5157 ) , + .pReset_E_out ( pResetWires[106] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5158 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[410] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[116] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5159 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[211] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[212] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5160 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5161 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5162 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5163 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5164 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5165 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5166 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5167 ) , + .clk_1_N_in ( clk_2_wires[116] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5168 ) , + .clk_1_E_out ( clk_1_wires[211] ) , .clk_1_W_out ( clk_1_wires[212] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5169 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5170 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5171 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5172 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5173 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5174 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5175 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5176 ) ) ; +sb_1__1_ sb_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5177 } ) , + .chany_top_in ( cby_1__1__122_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__122_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__121_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_121_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_121_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_121_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_121_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_121_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_121_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_121_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_121_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__111_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_121_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_121_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_121_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_121_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_121_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_121_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_121_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_121_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__122_ccff_tail ) , + .chany_top_out ( sb_1__1__111_chany_top_out ) , + .chanx_right_out ( sb_1__1__111_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__111_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__111_chanx_left_out ) , + .ccff_tail ( sb_1__1__111_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5178 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5179 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5180 ) , + .pReset_W_in ( pResetWires[152] ) , .pReset_N_out ( pResetWires[154] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5181 ) , + .pReset_E_out ( pResetWires[155] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5182 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[413] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5183 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5184 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5185 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5186 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5187 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[113] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5188 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[115] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5189 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5190 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5191 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5192 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5193 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5194 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5195 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5196 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5197 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5198 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5199 ) , + .clk_2_W_in ( clk_2_wires[113] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5200 ) , + .clk_2_S_out ( clk_2_wires[115] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5201 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5202 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5203 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5204 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5205 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5206 ) ) ; +sb_1__1_ sb_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5207 } ) , + .chany_top_in ( cby_1__1__123_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__123_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__122_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_122_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_122_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_122_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_122_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_122_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_122_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_122_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_122_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__112_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_122_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_122_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_122_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_122_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_122_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_122_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_122_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_122_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__123_ccff_tail ) , + .chany_top_out ( sb_1__1__112_chany_top_out ) , + .chanx_right_out ( sb_1__1__112_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__112_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__112_chanx_left_out ) , + .ccff_tail ( sb_1__1__112_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5208 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5209 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5210 ) , + .pReset_W_in ( pResetWires[201] ) , .pReset_N_out ( pResetWires[203] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5211 ) , + .pReset_E_out ( pResetWires[204] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5212 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[416] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[123] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5213 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[218] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[219] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5214 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5215 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5216 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5217 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5218 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5219 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5220 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5221 ) , + .clk_1_N_in ( clk_2_wires[123] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5222 ) , + .clk_1_E_out ( clk_1_wires[218] ) , .clk_1_W_out ( clk_1_wires[219] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5223 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5224 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5225 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5226 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5227 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5228 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5229 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5230 ) ) ; +sb_1__1_ sb_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5231 } ) , + .chany_top_in ( cby_1__1__124_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__124_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__123_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_123_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_123_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_123_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_123_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_123_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_123_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_123_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_123_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__113_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_123_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_123_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_123_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_123_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_123_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_123_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_123_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_123_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__124_ccff_tail ) , + .chany_top_out ( sb_1__1__113_chany_top_out ) , + .chanx_right_out ( sb_1__1__113_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__113_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__113_chanx_left_out ) , + .ccff_tail ( sb_1__1__113_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5232 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5233 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5234 ) , + .pReset_W_in ( pResetWires[250] ) , .pReset_N_out ( pResetWires[252] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5235 ) , + .pReset_E_out ( pResetWires[253] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5236 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[419] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5237 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5238 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5239 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5240 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5241 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[118] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5242 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[122] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[120] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5243 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5245 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5246 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5247 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5248 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5249 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5250 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5251 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5252 ) , + .clk_2_W_in ( clk_2_wires[118] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5253 ) , + .clk_2_S_out ( clk_2_wires[122] ) , .clk_2_N_out ( clk_2_wires[120] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5254 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5255 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5256 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5257 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5258 ) ) ; +sb_1__1_ sb_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5259 } ) , + .chany_top_in ( cby_1__1__125_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__125_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__124_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_124_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_124_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_124_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_124_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_124_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_124_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_124_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_124_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__114_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_124_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_124_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_124_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_124_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_124_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_124_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_124_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_124_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__125_ccff_tail ) , + .chany_top_out ( sb_1__1__114_chany_top_out ) , + .chanx_right_out ( sb_1__1__114_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__114_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__114_chanx_left_out ) , + .ccff_tail ( sb_1__1__114_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5260 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5261 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5262 ) , + .pReset_W_in ( pResetWires[299] ) , .pReset_N_out ( pResetWires[301] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5263 ) , + .pReset_E_out ( pResetWires[302] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5264 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[422] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5265 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[121] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[225] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[226] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5266 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5267 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5268 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5269 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5270 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5271 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5272 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5273 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5274 ) , + .clk_1_S_in ( clk_2_wires[121] ) , .clk_1_E_out ( clk_1_wires[225] ) , + .clk_1_W_out ( clk_1_wires[226] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5275 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5276 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5277 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5278 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5279 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5280 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5281 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5282 ) ) ; +sb_1__1_ sb_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5283 } ) , + .chany_top_in ( cby_1__1__126_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__126_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__125_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_125_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_125_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_125_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_125_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_125_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_125_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_125_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_125_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__115_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_125_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_125_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_125_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_125_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_125_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_125_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_125_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_125_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__126_ccff_tail ) , + .chany_top_out ( sb_1__1__115_chany_top_out ) , + .chanx_right_out ( sb_1__1__115_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__115_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__115_chanx_left_out ) , + .ccff_tail ( sb_1__1__115_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5284 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5285 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5286 ) , + .pReset_W_in ( pResetWires[348] ) , .pReset_N_out ( pResetWires[350] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5287 ) , + .pReset_E_out ( pResetWires[351] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5288 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[425] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5289 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5290 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5291 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5292 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5293 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5294 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5295 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5296 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5297 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5298 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5299 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5300 ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5301 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5302 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5303 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5304 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5305 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5306 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5307 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5308 ) ) ; +sb_1__1_ sb_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5309 } ) , + .chany_top_in ( cby_1__1__127_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__127_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__126_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_126_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_126_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_126_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_126_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_126_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_126_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_126_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_126_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__116_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_126_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_126_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_126_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_126_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_126_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_126_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_126_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_126_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__127_ccff_tail ) , + .chany_top_out ( sb_1__1__116_chany_top_out ) , + .chanx_right_out ( sb_1__1__116_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__116_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__116_chanx_left_out ) , + .ccff_tail ( sb_1__1__116_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5310 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5311 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5312 ) , + .pReset_W_in ( pResetWires[397] ) , .pReset_N_out ( pResetWires[399] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5313 ) , + .pReset_E_out ( pResetWires[400] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5314 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[428] ) , + .prog_clk_1_N_in ( prog_clk_2_wires[130] ) , + .prog_clk_1_S_in ( SYNOPSYS_UNCONNECTED_5315 ) , + .prog_clk_1_E_out ( prog_clk_1_wires[232] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[233] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5316 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5317 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5318 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5319 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5320 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5321 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5322 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5323 ) , + .clk_1_N_in ( clk_2_wires[130] ) , + .clk_1_S_in ( SYNOPSYS_UNCONNECTED_5324 ) , + .clk_1_E_out ( clk_1_wires[232] ) , .clk_1_W_out ( clk_1_wires[233] ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5325 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5326 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5327 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5328 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5329 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5330 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5331 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5332 ) ) ; +sb_1__1_ sb_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5333 } ) , + .chany_top_in ( cby_1__1__128_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__128_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__127_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_127_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_127_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_127_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_127_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_127_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_127_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_127_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_127_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__117_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_127_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_127_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_127_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_127_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_127_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_127_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_127_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_127_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__128_ccff_tail ) , + .chany_top_out ( sb_1__1__117_chany_top_out ) , + .chanx_right_out ( sb_1__1__117_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__117_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__117_chanx_left_out ) , + .ccff_tail ( sb_1__1__117_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5334 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5335 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5336 ) , + .pReset_W_in ( pResetWires[446] ) , .pReset_N_out ( pResetWires[448] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5337 ) , + .pReset_E_out ( pResetWires[449] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5338 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[431] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5339 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5340 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5341 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5342 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5343 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[125] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5344 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[129] ) , + .prog_clk_2_N_out ( prog_clk_2_wires[127] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5345 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5346 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5347 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5348 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5349 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5350 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5351 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5352 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5353 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5354 ) , + .clk_2_W_in ( clk_2_wires[125] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5355 ) , + .clk_2_S_out ( clk_2_wires[129] ) , .clk_2_N_out ( clk_2_wires[127] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5356 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5357 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5358 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5359 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5360 ) ) ; +sb_1__1_ sb_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5361 } ) , + .chany_top_in ( cby_1__1__129_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__129_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__128_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_128_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_128_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_128_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_128_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_128_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_128_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_128_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_128_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__118_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_128_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_128_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_128_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_128_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_128_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_128_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_128_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_128_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__129_ccff_tail ) , + .chany_top_out ( sb_1__1__118_chany_top_out ) , + .chanx_right_out ( sb_1__1__118_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__118_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__118_chanx_left_out ) , + .ccff_tail ( sb_1__1__118_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5362 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5363 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5364 ) , + .pReset_W_in ( pResetWires[495] ) , .pReset_N_out ( pResetWires[497] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5365 ) , + .pReset_E_out ( pResetWires[498] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5366 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[434] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5367 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[128] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[239] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[240] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5368 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5369 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5370 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5371 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5372 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5373 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5374 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5375 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5376 ) , + .clk_1_S_in ( clk_2_wires[128] ) , .clk_1_E_out ( clk_1_wires[239] ) , + .clk_1_W_out ( clk_1_wires[240] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5377 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5378 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5379 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5380 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5381 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5382 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5383 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5384 ) ) ; +sb_1__1_ sb_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5385 } ) , + .chany_top_in ( cby_1__1__130_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__130_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__129_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_129_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_129_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_129_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_129_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_129_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_129_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_129_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_129_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__119_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_129_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_129_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_129_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_129_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_129_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_129_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_129_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_129_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__130_ccff_tail ) , + .chany_top_out ( sb_1__1__119_chany_top_out ) , + .chanx_right_out ( sb_1__1__119_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__119_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__119_chanx_left_out ) , + .ccff_tail ( sb_1__1__119_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5386 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5387 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5388 ) , + .pReset_W_in ( pResetWires[544] ) , .pReset_N_out ( pResetWires[546] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5389 ) , + .pReset_E_out ( pResetWires[547] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5390 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[437] ) , + .prog_clk_1_N_in ( h_incr0 ) , .prog_clk_1_S_in ( h_incr0 ) , + .prog_clk_1_E_out ( SYNOPSYS_UNCONNECTED_5391 ) , + .prog_clk_1_W_out ( SYNOPSYS_UNCONNECTED_5392 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_5393 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_5394 ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_5395 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[132] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5396 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5397 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[134] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5398 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5399 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5400 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5401 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5402 ) , + .clk_1_N_in ( h_incr0 ) , .clk_1_S_in ( h_incr0 ) , + .clk_1_E_out ( SYNOPSYS_UNCONNECTED_5403 ) , + .clk_1_W_out ( SYNOPSYS_UNCONNECTED_5404 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_5405 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_5406 ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_5407 ) , + .clk_2_W_in ( clk_2_wires[132] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5408 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5409 ) , + .clk_2_N_out ( clk_2_wires[134] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5410 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5411 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5412 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5413 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5414 ) ) ; +sb_1__1_ sb_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5415 } ) , + .chany_top_in ( cby_1__1__131_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_lower ) , + .chanx_right_in ( cbx_1__1__131_chanx_left_out ) , + .right_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__130_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_130_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_130_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_130_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_130_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_130_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_130_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_130_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_130_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__120_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_130_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_130_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_130_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_130_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_130_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_130_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_130_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_130_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( cbx_1__1__131_ccff_tail ) , + .chany_top_out ( sb_1__1__120_chany_top_out ) , + .chanx_right_out ( sb_1__1__120_chanx_right_out ) , + .chany_bottom_out ( sb_1__1__120_chany_bottom_out ) , + .chanx_left_out ( sb_1__1__120_chanx_left_out ) , + .ccff_tail ( sb_1__1__120_ccff_tail ) , .Test_en_S_in ( h_incr0 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_5416 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5417 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5418 ) , + .pReset_W_in ( pResetWires[593] ) , .pReset_N_out ( pResetWires[595] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5419 ) , + .pReset_E_out ( pResetWires[596] ) , .Reset_S_in ( h_incr0 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_5420 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[440] ) , + .prog_clk_1_N_in ( SYNOPSYS_UNCONNECTED_5421 ) , + .prog_clk_1_S_in ( prog_clk_2_wires[135] ) , + .prog_clk_1_E_out ( prog_clk_1_wires[246] ) , + .prog_clk_1_W_out ( prog_clk_1_wires[247] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_S_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5422 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_5423 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_5424 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5425 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5426 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5427 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_5428 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_5429 ) , + .clk_1_N_in ( SYNOPSYS_UNCONNECTED_5430 ) , + .clk_1_S_in ( clk_2_wires[135] ) , .clk_1_E_out ( clk_1_wires[246] ) , + .clk_1_W_out ( clk_1_wires[247] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5431 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_5432 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_5433 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5434 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5435 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5436 ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_5437 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_5438 ) ) ; +sb_1__2_ sb_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5439 } ) , + .chanx_right_in ( cbx_1__12__1_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__11_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_11_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_11_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_11_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_11_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_11_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_11_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_11_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_11_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__0_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_11_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_11_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_11_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_11_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_11_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_11_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_11_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_11_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_1_ccff_tail ) , + .chanx_right_out ( sb_1__12__0_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__0_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__0_chanx_left_out ) , + .ccff_tail ( sb_1__12__0_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5440 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5441 ) , + .pReset_E_in ( pResetWires[604] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5442 ) , + .pReset_W_out ( pResetWires[601] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5443 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[60] ) ) ; +sb_1__2_ sb_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5444 } ) , + .chanx_right_in ( cbx_1__12__2_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__23_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_23_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_23_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_23_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_23_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_23_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_23_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_23_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_23_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__1_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_23_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_23_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_23_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_23_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_23_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_23_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_23_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_23_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_2_ccff_tail ) , + .chanx_right_out ( sb_1__12__1_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__1_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__1_chanx_left_out ) , + .ccff_tail ( sb_1__12__1_ccff_tail ) , .SC_IN_BOT ( scff_Wires[52] ) , + .SC_OUT_BOT ( scff_Wires[53] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5445 ) , + .pReset_E_in ( pResetWires[607] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5446 ) , + .pReset_W_out ( pResetWires[605] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5447 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[100] ) ) ; +sb_1__2_ sb_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5448 } ) , + .chanx_right_in ( cbx_1__12__3_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__35_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_35_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_35_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_35_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_35_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_35_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_35_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_35_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_35_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__2_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_35_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_35_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_35_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_35_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_35_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_35_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_35_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_35_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_3_ccff_tail ) , + .chanx_right_out ( sb_1__12__2_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__2_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__2_chanx_left_out ) , + .ccff_tail ( sb_1__12__2_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5449 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5450 ) , + .pReset_E_in ( pResetWires[610] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5451 ) , + .pReset_W_out ( pResetWires[608] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5452 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[138] ) ) ; +sb_1__2_ sb_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5453 } ) , + .chanx_right_in ( cbx_1__12__4_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__47_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_47_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_47_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_47_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_47_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_47_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_47_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_47_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_47_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__3_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_47_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_47_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_47_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_47_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_47_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_47_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_47_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_47_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_4_ccff_tail ) , + .chanx_right_out ( sb_1__12__3_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__3_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__3_chanx_left_out ) , + .ccff_tail ( sb_1__12__3_ccff_tail ) , .SC_IN_BOT ( scff_Wires[105] ) , + .SC_OUT_BOT ( scff_Wires[106] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5454 ) , + .pReset_E_in ( pResetWires[613] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5455 ) , + .pReset_W_out ( pResetWires[611] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5456 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[176] ) ) ; +sb_1__2_ sb_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5457 } ) , + .chanx_right_in ( cbx_1__12__5_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__59_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_59_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_59_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_59_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_59_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_59_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_59_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_59_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_59_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__4_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_59_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_59_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_59_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_59_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_59_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_59_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_59_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_59_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_5_ccff_tail ) , + .chanx_right_out ( sb_1__12__4_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__4_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__4_chanx_left_out ) , + .ccff_tail ( sb_1__12__4_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5458 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5459 ) , + .pReset_E_in ( pResetWires[616] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5460 ) , + .pReset_W_out ( pResetWires[614] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5461 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[214] ) ) ; +sb_1__2_ sb_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5462 } ) , + .chanx_right_in ( cbx_1__12__6_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__71_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_71_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_71_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_71_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_71_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_71_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_71_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_71_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_71_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__5_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_71_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_71_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_71_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_71_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_71_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_71_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_71_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_71_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_6_ccff_tail ) , + .chanx_right_out ( sb_1__12__5_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__5_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__5_chanx_left_out ) , + .ccff_tail ( sb_1__12__5_ccff_tail ) , .SC_IN_BOT ( scff_Wires[158] ) , + .SC_OUT_BOT ( scff_Wires[159] ) , .pReset_S_in ( pResetWires[24] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5463 ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5464 ) , + .pReset_W_out ( pResetWires[617] ) , .pReset_E_out ( pResetWires[619] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[252] ) ) ; +sb_1__2_ sb_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5465 } ) , + .chanx_right_in ( cbx_1__12__7_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__83_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_83_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_83_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_83_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_83_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_83_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_83_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_83_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_83_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__6_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_83_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_83_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_83_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_83_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_83_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_83_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_83_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_83_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_7_ccff_tail ) , + .chanx_right_out ( sb_1__12__6_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__6_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__6_chanx_left_out ) , + .ccff_tail ( sb_1__12__6_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5466 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5467 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5468 ) , + .pReset_W_in ( pResetWires[620] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5469 ) , + .pReset_E_out ( pResetWires[622] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[290] ) ) ; +sb_1__2_ sb_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5470 } ) , + .chanx_right_in ( cbx_1__12__8_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__95_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_95_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_95_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_95_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_95_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_95_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_95_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_95_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_95_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__7_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_95_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_95_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_95_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_95_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_95_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_95_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_95_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_95_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_8_ccff_tail ) , + .chanx_right_out ( sb_1__12__7_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__7_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__7_chanx_left_out ) , + .ccff_tail ( sb_1__12__7_ccff_tail ) , .SC_IN_BOT ( scff_Wires[211] ) , + .SC_OUT_BOT ( scff_Wires[212] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5471 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5472 ) , + .pReset_W_in ( pResetWires[623] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5473 ) , + .pReset_E_out ( pResetWires[625] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[328] ) ) ; +sb_1__2_ sb_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5474 } ) , + .chanx_right_in ( cbx_1__12__9_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__107_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_107_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_107_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_107_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_107_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_107_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_107_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_107_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_107_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__8_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_107_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_107_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_107_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_107_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_107_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_107_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_107_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_107_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_9_ccff_tail ) , + .chanx_right_out ( sb_1__12__8_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__8_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__8_chanx_left_out ) , + .ccff_tail ( sb_1__12__8_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5475 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5476 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5477 ) , + .pReset_W_in ( pResetWires[626] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5478 ) , + .pReset_E_out ( pResetWires[628] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[366] ) ) ; +sb_1__2_ sb_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5479 } ) , + .chanx_right_in ( cbx_1__12__10_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__119_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_119_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_119_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_119_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_119_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_119_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_119_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_119_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_119_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__9_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_119_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_119_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_119_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_119_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_119_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_119_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_119_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_119_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_10_ccff_tail ) , + .chanx_right_out ( sb_1__12__9_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__9_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__9_chanx_left_out ) , + .ccff_tail ( sb_1__12__9_ccff_tail ) , .SC_IN_BOT ( scff_Wires[264] ) , + .SC_OUT_BOT ( scff_Wires[265] ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5480 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5481 ) , + .pReset_W_in ( pResetWires[629] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5482 ) , + .pReset_E_out ( pResetWires[631] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[404] ) ) ; +sb_1__2_ sb_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5483 } ) , + .chanx_right_in ( cbx_1__12__11_chanx_left_out ) , + .right_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , + .right_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_upper ) , + .right_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_upper ) , + .right_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_upper ) , + .right_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_upper ) , + .right_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_upper ) , + .right_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_upper ) , + .right_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_upper ) , + .right_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_upper ) , + .chany_bottom_in ( cby_1__1__131_chany_top_out ) , + .bottom_left_grid_pin_44_ ( grid_clb_131_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_131_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_131_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_131_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_131_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_131_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_131_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_131_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__10_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_131_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_131_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_131_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_131_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_131_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_131_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_131_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_131_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_top_11_ccff_tail ) , + .chanx_right_out ( sb_1__12__10_chanx_right_out ) , + .chany_bottom_out ( sb_1__12__10_chany_bottom_out ) , + .chanx_left_out ( sb_1__12__10_chanx_left_out ) , + .ccff_tail ( sb_1__12__10_ccff_tail ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5484 ) , + .pReset_S_in ( SYNOPSYS_UNCONNECTED_5485 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5486 ) , + .pReset_W_in ( pResetWires[632] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5487 ) , + .pReset_E_out ( pResetWires[634] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[442] ) ) ; +sb_2__0_ sb_12__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5488 } ) , + .chany_top_in ( cby_12__1__0_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , + .chanx_left_in ( cbx_1__0__11_chanx_right_out ) , + .left_bottom_grid_pin_1_ ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_3_ ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .left_bottom_grid_pin_5_ ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .left_bottom_grid_pin_7_ ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .left_bottom_grid_pin_9_ ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .left_bottom_grid_pin_11_ ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .left_bottom_grid_pin_13_ ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) , + .left_bottom_grid_pin_15_ ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , + .left_bottom_grid_pin_17_ ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , + .ccff_head ( grid_io_right_11_ccff_tail ) , + .chany_top_out ( sb_12__0__0_chany_top_out ) , + .chanx_left_out ( sb_12__0__0_chanx_left_out ) , + .ccff_tail ( sb_12__0__0_ccff_tail ) , .pReset_W_in ( pResetWires[59] ) , + .pReset_N_out ( pResetWires[60] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[445] ) ) ; +sb_2__1_ sb_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5489 } ) , + .chany_top_in ( cby_12__1__1_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__0_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_132_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_132_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_132_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_132_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_132_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_132_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_132_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_132_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__121_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_132_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_132_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_132_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_132_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_132_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_132_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_132_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_132_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_10_ccff_tail ) , + .chany_top_out ( sb_12__1__0_chany_top_out ) , + .chany_bottom_out ( sb_12__1__0_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__0_chanx_left_out ) , + .ccff_tail ( sb_12__1__0_ccff_tail ) , .pReset_W_in ( pResetWires[107] ) , + .pReset_N_out ( pResetWires[109] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[448] ) ) ; +sb_2__1_ sb_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5490 } ) , + .chany_top_in ( cby_12__1__2_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__1_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_133_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_133_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_133_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_133_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_133_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_133_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_133_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_133_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__122_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_133_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_133_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_133_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_133_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_133_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_133_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_133_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_133_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_9_ccff_tail ) , + .chany_top_out ( sb_12__1__1_chany_top_out ) , + .chany_bottom_out ( sb_12__1__1_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__1_chanx_left_out ) , + .ccff_tail ( sb_12__1__1_ccff_tail ) , .pReset_W_in ( pResetWires[156] ) , + .pReset_N_out ( pResetWires[158] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[451] ) ) ; +sb_2__1_ sb_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5491 } ) , + .chany_top_in ( cby_12__1__3_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__2_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_134_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_134_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_134_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_134_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_134_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_134_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_134_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_134_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__123_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_134_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_134_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_134_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_134_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_134_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_134_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_134_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_134_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_8_ccff_tail ) , + .chany_top_out ( sb_12__1__2_chany_top_out ) , + .chany_bottom_out ( sb_12__1__2_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__2_chanx_left_out ) , + .ccff_tail ( sb_12__1__2_ccff_tail ) , .pReset_W_in ( pResetWires[205] ) , + .pReset_N_out ( pResetWires[207] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[454] ) ) ; +sb_2__1_ sb_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5492 } ) , + .chany_top_in ( cby_12__1__4_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__3_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_135_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_135_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_135_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_135_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_135_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_135_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_135_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_135_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__124_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_135_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_135_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_135_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_135_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_135_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_135_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_135_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_135_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_7_ccff_tail ) , + .chany_top_out ( sb_12__1__3_chany_top_out ) , + .chany_bottom_out ( sb_12__1__3_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__3_chanx_left_out ) , + .ccff_tail ( sb_12__1__3_ccff_tail ) , .pReset_W_in ( pResetWires[254] ) , + .pReset_N_out ( pResetWires[256] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[457] ) ) ; +sb_2__1_ sb_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5493 } ) , + .chany_top_in ( cby_12__1__5_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__4_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_136_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_136_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_136_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_136_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_136_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_136_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_136_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_136_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__125_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_136_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_136_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_136_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_136_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_136_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_136_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_136_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_136_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_6_ccff_tail ) , + .chany_top_out ( sb_12__1__4_chany_top_out ) , + .chany_bottom_out ( sb_12__1__4_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__4_chanx_left_out ) , + .ccff_tail ( sb_12__1__4_ccff_tail ) , .pReset_W_in ( pResetWires[303] ) , + .pReset_N_out ( pResetWires[305] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[460] ) ) ; +sb_2__1_ sb_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5494 } ) , + .chany_top_in ( cby_12__1__6_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__5_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_137_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_137_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_137_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_137_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_137_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_137_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_137_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_137_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__126_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_137_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_137_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_137_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_137_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_137_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_137_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_137_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_137_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_5_ccff_tail ) , + .chany_top_out ( sb_12__1__5_chany_top_out ) , + .chany_bottom_out ( sb_12__1__5_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__5_chanx_left_out ) , + .ccff_tail ( sb_12__1__5_ccff_tail ) , .pReset_W_in ( pResetWires[352] ) , + .pReset_N_out ( pResetWires[354] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[463] ) ) ; +sb_2__1_ sb_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5495 } ) , + .chany_top_in ( cby_12__1__7_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__6_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_138_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_138_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_138_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_138_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_138_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_138_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_138_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_138_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__127_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_138_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_138_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_138_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_138_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_138_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_138_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_138_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_138_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_4_ccff_tail ) , + .chany_top_out ( sb_12__1__6_chany_top_out ) , + .chany_bottom_out ( sb_12__1__6_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__6_chanx_left_out ) , + .ccff_tail ( sb_12__1__6_ccff_tail ) , .pReset_W_in ( pResetWires[401] ) , + .pReset_N_out ( pResetWires[403] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[466] ) ) ; +sb_2__1_ sb_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5496 } ) , + .chany_top_in ( cby_12__1__8_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__7_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_139_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_139_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_139_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_139_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_139_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_139_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_139_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_139_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__128_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_139_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_139_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_139_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_139_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_139_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_139_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_139_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_139_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_3_ccff_tail ) , + .chany_top_out ( sb_12__1__7_chany_top_out ) , + .chany_bottom_out ( sb_12__1__7_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__7_chanx_left_out ) , + .ccff_tail ( sb_12__1__7_ccff_tail ) , .pReset_W_in ( pResetWires[450] ) , + .pReset_N_out ( pResetWires[452] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[469] ) ) ; +sb_2__1_ sb_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5497 } ) , + .chany_top_in ( cby_12__1__9_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__8_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_140_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_140_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_140_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_140_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_140_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_140_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_140_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_140_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__129_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_140_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_140_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_140_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_140_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_140_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_140_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_140_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_140_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_2_ccff_tail ) , + .chany_top_out ( sb_12__1__8_chany_top_out ) , + .chany_bottom_out ( sb_12__1__8_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__8_chanx_left_out ) , + .ccff_tail ( sb_12__1__8_ccff_tail ) , .pReset_W_in ( pResetWires[499] ) , + .pReset_N_out ( pResetWires[501] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[472] ) ) ; +sb_2__1_ sb_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5498 } ) , + .chany_top_in ( cby_12__1__10_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__9_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_141_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_141_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_141_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_141_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_141_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_141_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_141_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_141_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__130_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_141_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_141_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_141_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_141_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_141_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_141_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_141_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_141_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_1_ccff_tail ) , + .chany_top_out ( sb_12__1__9_chany_top_out ) , + .chany_bottom_out ( sb_12__1__9_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__9_chanx_left_out ) , + .ccff_tail ( sb_12__1__9_ccff_tail ) , .pReset_W_in ( pResetWires[548] ) , + .pReset_N_out ( pResetWires[550] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[475] ) ) ; +sb_2__1_ sb_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5499 } ) , + .chany_top_in ( cby_12__1__11_chany_bottom_out ) , + .top_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_lower ) , + .top_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_lower ) , + .top_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_lower ) , + .top_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_lower ) , + .top_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_lower ) , + .top_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_lower ) , + .top_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_lower ) , + .top_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_lower ) , + .top_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .chany_bottom_in ( cby_12__1__10_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_142_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_142_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_142_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_142_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_142_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_142_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_142_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_142_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__1__131_chanx_right_out ) , + .left_bottom_grid_pin_36_ ( grid_clb_142_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_142_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_142_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_142_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_142_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_142_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_142_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_142_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( grid_io_right_0_ccff_tail ) , + .chany_top_out ( sb_12__1__10_chany_top_out ) , + .chany_bottom_out ( sb_12__1__10_chany_bottom_out ) , + .chanx_left_out ( sb_12__1__10_chanx_left_out ) , + .ccff_tail ( sb_12__1__10_ccff_tail ) , + .pReset_W_in ( pResetWires[597] ) , .pReset_N_out ( pResetWires[599] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[478] ) ) ; +sb_2__2_ sb_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5500 } ) , + .chany_bottom_in ( cby_12__1__11_chany_top_out ) , + .bottom_right_grid_pin_1_ ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .bottom_left_grid_pin_44_ ( grid_clb_143_right_width_0_height_0__pin_44_upper ) , + .bottom_left_grid_pin_45_ ( grid_clb_143_right_width_0_height_0__pin_45_upper ) , + .bottom_left_grid_pin_46_ ( grid_clb_143_right_width_0_height_0__pin_46_upper ) , + .bottom_left_grid_pin_47_ ( grid_clb_143_right_width_0_height_0__pin_47_upper ) , + .bottom_left_grid_pin_48_ ( grid_clb_143_right_width_0_height_0__pin_48_upper ) , + .bottom_left_grid_pin_49_ ( grid_clb_143_right_width_0_height_0__pin_49_upper ) , + .bottom_left_grid_pin_50_ ( grid_clb_143_right_width_0_height_0__pin_50_upper ) , + .bottom_left_grid_pin_51_ ( grid_clb_143_right_width_0_height_0__pin_51_upper ) , + .chanx_left_in ( cbx_1__12__11_chanx_right_out ) , + .left_top_grid_pin_1_ ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , + .left_bottom_grid_pin_36_ ( grid_clb_143_top_width_0_height_0__pin_36_lower ) , + .left_bottom_grid_pin_37_ ( grid_clb_143_top_width_0_height_0__pin_37_lower ) , + .left_bottom_grid_pin_38_ ( grid_clb_143_top_width_0_height_0__pin_38_lower ) , + .left_bottom_grid_pin_39_ ( grid_clb_143_top_width_0_height_0__pin_39_lower ) , + .left_bottom_grid_pin_40_ ( grid_clb_143_top_width_0_height_0__pin_40_lower ) , + .left_bottom_grid_pin_41_ ( grid_clb_143_top_width_0_height_0__pin_41_lower ) , + .left_bottom_grid_pin_42_ ( grid_clb_143_top_width_0_height_0__pin_42_lower ) , + .left_bottom_grid_pin_43_ ( grid_clb_143_top_width_0_height_0__pin_43_lower ) , + .ccff_head ( ccff_head ) , + .chany_bottom_out ( sb_12__12__0_chany_bottom_out ) , + .chanx_left_out ( sb_12__12__0_chanx_left_out ) , + .ccff_tail ( sb_12__12__0_ccff_tail ) , .SC_IN_BOT ( scff_Wires[317] ) , + .SC_OUT_BOT ( sc_tail ) , .pReset_W_in ( pResetWires[635] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[480] ) ) ; +cbx_1__0_ cbx_1__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5501 } ) , + .chanx_left_in ( sb_0__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__0_chanx_left_out ) , + .ccff_head ( sb_1__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__0_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123:131] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123:131] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123:131] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__0_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__0_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__0_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__0_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__0_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__0_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__0_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__0_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__0_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_11_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_11_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_11_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_11_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_11_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_11_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_11_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_11_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_11_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_11_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_11_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_11_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_11_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_11_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_11_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_11_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_11_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_11_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[25] ) , .SC_OUT_BOT ( scff_Wires[26] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5502 ) , + .pReset_E_in ( pResetWires[26] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5503 ) , + .pReset_W_out ( pResetWires[25] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5504 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[0] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[5] ) ) ; +cbx_1__0_ cbx_2__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5505 } ) , + .chanx_left_in ( sb_1__0__0_chanx_right_out ) , + .chanx_right_in ( sb_1__0__1_chanx_left_out ) , + .ccff_head ( sb_1__0__1_ccff_tail ) , + .chanx_left_out ( cbx_1__0__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__1_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114:122] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114:122] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114:122] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__1_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__1_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__1_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__1_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__1_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__1_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__1_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__1_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__1_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_10_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_10_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_10_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_10_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_10_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_10_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_10_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_10_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_10_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_10_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_10_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_10_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_10_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_10_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_10_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_10_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_10_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_10_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5506 ) , + .SC_IN_BOT ( scff_Wires[27] ) , .SC_OUT_TOP ( scff_Wires[28] ) , + .pReset_E_in ( pResetWires[29] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5507 ) , + .pReset_W_out ( pResetWires[28] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5508 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[63] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5509 ) ) ; +cbx_1__0_ cbx_3__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5510 } ) , + .chanx_left_in ( sb_1__0__1_chanx_right_out ) , + .chanx_right_in ( sb_1__0__2_chanx_left_out ) , + .ccff_head ( sb_1__0__2_ccff_tail ) , + .chanx_left_out ( cbx_1__0__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__2_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105:113] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105:113] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105:113] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__2_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__2_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__2_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__2_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__2_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__2_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__2_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__2_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__2_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_9_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_9_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_9_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_9_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_9_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_9_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_9_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_9_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_9_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_9_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_9_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_9_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_9_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_9_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_9_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_9_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_9_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_9_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[78] ) , .SC_OUT_BOT ( scff_Wires[79] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5511 ) , + .pReset_E_in ( pResetWires[32] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5512 ) , + .pReset_W_out ( pResetWires[31] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5513 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[101] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5514 ) ) ; +cbx_1__0_ cbx_4__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5515 } ) , + .chanx_left_in ( sb_1__0__2_chanx_right_out ) , + .chanx_right_in ( sb_1__0__3_chanx_left_out ) , + .ccff_head ( sb_1__0__3_ccff_tail ) , + .chanx_left_out ( cbx_1__0__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__3_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96:104] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96:104] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96:104] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__3_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__3_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__3_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__3_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__3_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__3_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__3_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__3_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__3_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_8_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_8_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_8_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_8_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_8_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_8_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_8_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_8_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_8_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_8_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_8_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_8_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_8_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_8_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_8_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_8_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_8_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_8_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5516 ) , + .SC_IN_BOT ( scff_Wires[80] ) , .SC_OUT_TOP ( scff_Wires[81] ) , + .pReset_E_in ( pResetWires[35] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5517 ) , + .pReset_W_out ( pResetWires[34] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5518 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[139] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5519 ) ) ; +cbx_1__0_ cbx_5__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5520 } ) , + .chanx_left_in ( sb_1__0__3_chanx_right_out ) , + .chanx_right_in ( sb_1__0__4_chanx_left_out ) , + .ccff_head ( sb_1__0__4_ccff_tail ) , + .chanx_left_out ( cbx_1__0__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__4_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87:95] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87:95] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87:95] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__4_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__4_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__4_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__4_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__4_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__4_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__4_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__4_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__4_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_7_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_7_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_7_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_7_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_7_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_7_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_7_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_7_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_7_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_7_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_7_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_7_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_7_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_7_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_7_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_7_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_7_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_7_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[131] ) , .SC_OUT_BOT ( scff_Wires[132] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5521 ) , + .pReset_E_in ( pResetWires[38] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5522 ) , + .pReset_W_out ( pResetWires[37] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[177] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5524 ) ) ; +cbx_1__0_ cbx_6__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5525 } ) , + .chanx_left_in ( sb_1__0__4_chanx_right_out ) , + .chanx_right_in ( sb_1__0__5_chanx_left_out ) , + .ccff_head ( sb_1__0__5_ccff_tail ) , + .chanx_left_out ( cbx_1__0__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__5_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78:86] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78:86] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78:86] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__5_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__5_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__5_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__5_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__5_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__5_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__5_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__5_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__5_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_6_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_6_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_6_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_6_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_6_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_6_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_6_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_6_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_6_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_6_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_6_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_6_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_6_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_6_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_6_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_6_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_6_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_6_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5526 ) , + .SC_IN_BOT ( scff_Wires[133] ) , .SC_OUT_TOP ( scff_Wires[134] ) , + .pReset_E_in ( pResetWires[41] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5527 ) , + .pReset_W_out ( pResetWires[40] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5528 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[215] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5529 ) ) ; +cbx_1__0_ cbx_7__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5530 } ) , + .chanx_left_in ( sb_1__0__5_chanx_right_out ) , + .chanx_right_in ( sb_1__0__6_chanx_left_out ) , + .ccff_head ( sb_1__0__6_ccff_tail ) , + .chanx_left_out ( cbx_1__0__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__6_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69:77] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69:77] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69:77] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__6_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__6_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__6_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__6_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__6_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__6_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__6_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__6_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__6_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_5_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_5_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_5_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_5_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_5_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_5_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_5_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_5_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_5_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_5_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_5_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_5_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_5_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_5_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_5_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_5_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_5_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_5_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[184] ) , .SC_OUT_BOT ( scff_Wires[185] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5531 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5532 ) , + .pReset_W_in ( pResetWires[43] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5533 ) , + .pReset_E_out ( pResetWires[44] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[253] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5534 ) ) ; +cbx_1__0_ cbx_8__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5535 } ) , + .chanx_left_in ( sb_1__0__6_chanx_right_out ) , + .chanx_right_in ( sb_1__0__7_chanx_left_out ) , + .ccff_head ( sb_1__0__7_ccff_tail ) , + .chanx_left_out ( cbx_1__0__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__7_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60:68] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60:68] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60:68] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__7_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__7_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__7_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__7_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__7_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__7_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__7_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__7_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__7_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_4_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_4_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_4_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_4_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_4_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_4_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_4_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_4_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_4_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_4_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_4_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_4_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_4_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_4_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_4_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_4_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_4_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_4_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5536 ) , + .SC_IN_BOT ( scff_Wires[186] ) , .SC_OUT_TOP ( scff_Wires[187] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5537 ) , + .pReset_W_in ( pResetWires[46] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5538 ) , + .pReset_E_out ( pResetWires[47] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[291] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5539 ) ) ; +cbx_1__0_ cbx_9__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5540 } ) , + .chanx_left_in ( sb_1__0__7_chanx_right_out ) , + .chanx_right_in ( sb_1__0__8_chanx_left_out ) , + .ccff_head ( sb_1__0__8_ccff_tail ) , + .chanx_left_out ( cbx_1__0__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__8_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51:59] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51:59] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51:59] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__8_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__8_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__8_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__8_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__8_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__8_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__8_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__8_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__8_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_3_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_3_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_3_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_3_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_3_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_3_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_3_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_3_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_3_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_3_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_3_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_3_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_3_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_3_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_3_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_3_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_3_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_3_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[237] ) , .SC_OUT_BOT ( scff_Wires[238] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5541 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5542 ) , + .pReset_W_in ( pResetWires[49] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5543 ) , + .pReset_E_out ( pResetWires[50] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[329] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5544 ) ) ; +cbx_1__0_ cbx_10__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5545 } ) , + .chanx_left_in ( sb_1__0__8_chanx_right_out ) , + .chanx_right_in ( sb_1__0__9_chanx_left_out ) , + .ccff_head ( sb_1__0__9_ccff_tail ) , + .chanx_left_out ( cbx_1__0__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__9_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42:50] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42:50] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42:50] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__9_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__9_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__9_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__9_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__9_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__9_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__9_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__9_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__9_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_2_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_2_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_2_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_2_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_2_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_2_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_2_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_2_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_2_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_2_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_2_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_2_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_2_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_2_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_2_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_2_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_2_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_2_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5546 ) , + .SC_IN_BOT ( scff_Wires[239] ) , .SC_OUT_TOP ( scff_Wires[240] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5547 ) , + .pReset_W_in ( pResetWires[52] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5548 ) , + .pReset_E_out ( pResetWires[53] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[367] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5549 ) ) ; +cbx_1__0_ cbx_11__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5550 } ) , + .chanx_left_in ( sb_1__0__9_chanx_right_out ) , + .chanx_right_in ( sb_1__0__10_chanx_left_out ) , + .ccff_head ( sb_1__0__10_ccff_tail ) , + .chanx_left_out ( cbx_1__0__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__10_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33:41] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33:41] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33:41] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__10_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__10_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__10_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__10_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__10_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__10_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__10_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__10_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__10_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_1_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_1_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_1_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_1_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_1_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_1_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_1_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_1_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_1_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_1_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_1_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_1_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_1_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_1_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_1_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( scff_Wires[290] ) , .SC_OUT_BOT ( scff_Wires[291] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5551 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5552 ) , + .pReset_W_in ( pResetWires[55] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5553 ) , + .pReset_E_out ( pResetWires[56] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[405] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5554 ) ) ; +cbx_1__0_ cbx_12__0_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5555 } ) , + .chanx_left_in ( sb_1__0__10_chanx_right_out ) , + .chanx_right_in ( sb_12__0__0_chanx_left_out ) , + .ccff_head ( sb_12__0__0_ccff_tail ) , + .chanx_left_out ( cbx_1__0__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__0__11_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) , + .ccff_tail ( grid_io_bottom_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24:32] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24:32] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24:32] ) , + .top_width_0_height_0__pin_0_ ( cbx_1__0__11_bottom_grid_pin_0_ ) , + .top_width_0_height_0__pin_2_ ( cbx_1__0__11_bottom_grid_pin_2_ ) , + .top_width_0_height_0__pin_4_ ( cbx_1__0__11_bottom_grid_pin_4_ ) , + .top_width_0_height_0__pin_6_ ( cbx_1__0__11_bottom_grid_pin_6_ ) , + .top_width_0_height_0__pin_8_ ( cbx_1__0__11_bottom_grid_pin_8_ ) , + .top_width_0_height_0__pin_10_ ( cbx_1__0__11_bottom_grid_pin_10_ ) , + .top_width_0_height_0__pin_12_ ( cbx_1__0__11_bottom_grid_pin_12_ ) , + .top_width_0_height_0__pin_14_ ( cbx_1__0__11_bottom_grid_pin_14_ ) , + .top_width_0_height_0__pin_16_ ( cbx_1__0__11_bottom_grid_pin_16_ ) , + .top_width_0_height_0__pin_1_upper ( grid_io_bottom_0_top_width_0_height_0__pin_1_upper ) , + .top_width_0_height_0__pin_1_lower ( grid_io_bottom_0_top_width_0_height_0__pin_1_lower ) , + .top_width_0_height_0__pin_3_upper ( grid_io_bottom_0_top_width_0_height_0__pin_3_upper ) , + .top_width_0_height_0__pin_3_lower ( grid_io_bottom_0_top_width_0_height_0__pin_3_lower ) , + .top_width_0_height_0__pin_5_upper ( grid_io_bottom_0_top_width_0_height_0__pin_5_upper ) , + .top_width_0_height_0__pin_5_lower ( grid_io_bottom_0_top_width_0_height_0__pin_5_lower ) , + .top_width_0_height_0__pin_7_upper ( grid_io_bottom_0_top_width_0_height_0__pin_7_upper ) , + .top_width_0_height_0__pin_7_lower ( grid_io_bottom_0_top_width_0_height_0__pin_7_lower ) , + .top_width_0_height_0__pin_9_upper ( grid_io_bottom_0_top_width_0_height_0__pin_9_upper ) , + .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , + .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , + .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , + .top_width_0_height_0__pin_13_upper ( grid_io_bottom_0_top_width_0_height_0__pin_13_upper ) , + .top_width_0_height_0__pin_13_lower ( grid_io_bottom_0_top_width_0_height_0__pin_13_lower ) , + .top_width_0_height_0__pin_15_upper ( grid_io_bottom_0_top_width_0_height_0__pin_15_upper ) , + .top_width_0_height_0__pin_15_lower ( grid_io_bottom_0_top_width_0_height_0__pin_15_lower ) , + .top_width_0_height_0__pin_17_upper ( grid_io_bottom_0_top_width_0_height_0__pin_17_upper ) , + .top_width_0_height_0__pin_17_lower ( grid_io_bottom_0_top_width_0_height_0__pin_17_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5556 ) , + .SC_IN_BOT ( scff_Wires[292] ) , .SC_OUT_TOP ( scff_Wires[293] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_5557 ) , + .pReset_W_in ( pResetWires[58] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_5558 ) , + .pReset_E_out ( pResetWires[59] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[443] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5559 ) ) ; +cbx_1__1_ cbx_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5560 } ) , + .chanx_left_in ( sb_0__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__0_chanx_left_out ) , + .ccff_head ( sb_1__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__0_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires[22] ) , + .SC_OUT_BOT ( scff_Wires[23] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5561 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[0] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[0] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[0] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[0] ) , + .pReset_E_in ( pResetWires[62] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5562 ) , + .pReset_W_out ( pResetWires[61] ) , .pReset_S_out ( pResetWires[63] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5563 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[6] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[4] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5564 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[2] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[3] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[4] ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5565 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5566 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5567 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5568 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5569 ) , + .clk_1_E_in ( clk_1_wires[2] ) , .clk_1_N_out ( clk_1_wires[3] ) , + .clk_1_S_out ( clk_1_wires[4] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5570 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5571 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5572 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5573 ) ) ; +cbx_1__1_ cbx_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5574 } ) , + .chanx_left_in ( sb_0__1__1_chanx_right_out ) , + .chanx_right_in ( sb_1__1__1_chanx_left_out ) , + .ccff_head ( sb_1__1__1_ccff_tail ) , + .chanx_left_out ( cbx_1__1__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__1_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , .SC_IN_TOP ( scff_Wires[20] ) , + .SC_OUT_BOT ( scff_Wires[21] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5575 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[1] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[1] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[1] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[1] ) , + .pReset_E_in ( pResetWires[111] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5576 ) , + .pReset_W_out ( pResetWires[110] ) , .pReset_S_out ( pResetWires[112] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5577 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[11] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[10] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5578 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5579 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5580 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5581 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5582 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5583 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5584 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5585 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5586 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5587 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5588 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5589 ) ) ; +cbx_1__1_ cbx_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5590 } ) , + .chanx_left_in ( sb_0__1__2_chanx_right_out ) , + .chanx_right_in ( sb_1__1__2_chanx_left_out ) , + .ccff_head ( sb_1__1__2_ccff_tail ) , + .chanx_left_out ( cbx_1__1__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__2_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__2_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__2_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__2_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__2_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__2_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__2_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__2_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__2_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__2_ccff_tail ) , .SC_IN_TOP ( scff_Wires[18] ) , + .SC_OUT_BOT ( scff_Wires[19] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5591 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[2] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[2] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[2] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[2] ) , + .pReset_E_in ( pResetWires[160] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5592 ) , + .pReset_W_out ( pResetWires[159] ) , .pReset_S_out ( pResetWires[161] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5593 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[16] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[15] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5594 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[9] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[10] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[11] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5595 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5596 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5597 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5598 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5599 ) , + .clk_1_E_in ( clk_1_wires[9] ) , .clk_1_N_out ( clk_1_wires[10] ) , + .clk_1_S_out ( clk_1_wires[11] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5600 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5601 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5602 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5603 ) ) ; +cbx_1__1_ cbx_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5604 } ) , + .chanx_left_in ( sb_0__1__3_chanx_right_out ) , + .chanx_right_in ( sb_1__1__3_chanx_left_out ) , + .ccff_head ( sb_1__1__3_ccff_tail ) , + .chanx_left_out ( cbx_1__1__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__3_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__3_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__3_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__3_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__3_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__3_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__3_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__3_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__3_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__3_ccff_tail ) , .SC_IN_TOP ( scff_Wires[16] ) , + .SC_OUT_BOT ( scff_Wires[17] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5605 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[3] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[3] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[3] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[3] ) , + .pReset_E_in ( pResetWires[209] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5606 ) , + .pReset_W_out ( pResetWires[208] ) , .pReset_S_out ( pResetWires[210] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5607 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[21] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[20] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5608 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5609 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5610 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5611 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5612 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5613 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5614 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5615 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5616 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5617 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5618 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5619 ) ) ; +cbx_1__1_ cbx_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5620 } ) , + .chanx_left_in ( sb_0__1__4_chanx_right_out ) , + .chanx_right_in ( sb_1__1__4_chanx_left_out ) , + .ccff_head ( sb_1__1__4_ccff_tail ) , + .chanx_left_out ( cbx_1__1__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__4_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__4_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__4_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__4_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__4_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__4_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__4_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__4_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__4_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__4_ccff_tail ) , .SC_IN_TOP ( scff_Wires[14] ) , + .SC_OUT_BOT ( scff_Wires[15] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5621 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[4] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[4] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[4] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[4] ) , + .pReset_E_in ( pResetWires[258] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5622 ) , + .pReset_W_out ( pResetWires[257] ) , .pReset_S_out ( pResetWires[259] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5623 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[26] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[25] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5624 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[16] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[17] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[18] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5625 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5626 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5627 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5628 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5629 ) , + .clk_1_E_in ( clk_1_wires[16] ) , .clk_1_N_out ( clk_1_wires[17] ) , + .clk_1_S_out ( clk_1_wires[18] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5631 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5632 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5633 ) ) ; +cbx_1__1_ cbx_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5634 } ) , + .chanx_left_in ( sb_0__1__5_chanx_right_out ) , + .chanx_right_in ( sb_1__1__5_chanx_left_out ) , + .ccff_head ( sb_1__1__5_ccff_tail ) , + .chanx_left_out ( cbx_1__1__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__5_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__5_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__5_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__5_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__5_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__5_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__5_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__5_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__5_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__5_ccff_tail ) , .SC_IN_TOP ( scff_Wires[12] ) , + .SC_OUT_BOT ( scff_Wires[13] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5635 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[5] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[5] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[5] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[5] ) , + .pReset_E_in ( pResetWires[307] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5636 ) , + .pReset_W_out ( pResetWires[306] ) , .pReset_S_out ( pResetWires[308] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5637 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[31] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[30] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5638 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5639 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5640 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5641 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5642 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5643 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5644 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5645 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5646 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5647 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5648 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5649 ) ) ; +cbx_1__1_ cbx_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5650 } ) , + .chanx_left_in ( sb_0__1__6_chanx_right_out ) , + .chanx_right_in ( sb_1__1__6_chanx_left_out ) , + .ccff_head ( sb_1__1__6_ccff_tail ) , + .chanx_left_out ( cbx_1__1__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__6_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__6_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__6_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__6_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__6_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__6_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__6_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__6_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__6_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__6_ccff_tail ) , .SC_IN_TOP ( scff_Wires[10] ) , + .SC_OUT_BOT ( scff_Wires[11] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5651 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[6] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[6] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[6] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[6] ) , + .pReset_E_in ( pResetWires[356] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5652 ) , + .pReset_W_out ( pResetWires[355] ) , .pReset_S_out ( pResetWires[357] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5653 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[36] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[35] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5654 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[23] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[24] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[25] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5655 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5656 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5657 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5658 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5659 ) , + .clk_1_E_in ( clk_1_wires[23] ) , .clk_1_N_out ( clk_1_wires[24] ) , + .clk_1_S_out ( clk_1_wires[25] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5660 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5661 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5662 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5663 ) ) ; +cbx_1__1_ cbx_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5664 } ) , + .chanx_left_in ( sb_0__1__7_chanx_right_out ) , + .chanx_right_in ( sb_1__1__7_chanx_left_out ) , + .ccff_head ( sb_1__1__7_ccff_tail ) , + .chanx_left_out ( cbx_1__1__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__7_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__7_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__7_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__7_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__7_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__7_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__7_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__7_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__7_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__7_ccff_tail ) , .SC_IN_TOP ( scff_Wires[8] ) , + .SC_OUT_BOT ( scff_Wires[9] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5665 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[7] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[7] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[7] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[7] ) , + .pReset_E_in ( pResetWires[405] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5666 ) , + .pReset_W_out ( pResetWires[404] ) , .pReset_S_out ( pResetWires[406] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5667 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[41] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[40] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5668 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5669 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5670 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5671 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5672 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5673 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5674 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5675 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5676 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5677 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5678 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5679 ) ) ; +cbx_1__1_ cbx_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5680 } ) , + .chanx_left_in ( sb_0__1__8_chanx_right_out ) , + .chanx_right_in ( sb_1__1__8_chanx_left_out ) , + .ccff_head ( sb_1__1__8_ccff_tail ) , + .chanx_left_out ( cbx_1__1__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__8_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__8_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__8_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__8_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__8_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__8_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__8_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__8_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__8_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__8_ccff_tail ) , .SC_IN_TOP ( scff_Wires[6] ) , + .SC_OUT_BOT ( scff_Wires[7] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5681 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[8] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[8] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[8] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[8] ) , + .pReset_E_in ( pResetWires[454] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5682 ) , + .pReset_W_out ( pResetWires[453] ) , .pReset_S_out ( pResetWires[455] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5683 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[46] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[45] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5684 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[30] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[31] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[32] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5686 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5687 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5688 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5689 ) , + .clk_1_E_in ( clk_1_wires[30] ) , .clk_1_N_out ( clk_1_wires[31] ) , + .clk_1_S_out ( clk_1_wires[32] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5690 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5691 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5692 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5693 ) ) ; +cbx_1__1_ cbx_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5694 } ) , + .chanx_left_in ( sb_0__1__9_chanx_right_out ) , + .chanx_right_in ( sb_1__1__9_chanx_left_out ) , + .ccff_head ( sb_1__1__9_ccff_tail ) , + .chanx_left_out ( cbx_1__1__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__9_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__9_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__9_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__9_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__9_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__9_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__9_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__9_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__9_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__9_ccff_tail ) , .SC_IN_TOP ( scff_Wires[4] ) , + .SC_OUT_BOT ( scff_Wires[5] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5695 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[9] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[9] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[9] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[9] ) , + .pReset_E_in ( pResetWires[503] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5696 ) , + .pReset_W_out ( pResetWires[502] ) , .pReset_S_out ( pResetWires[504] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5697 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[51] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[50] ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5698 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5699 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5700 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5701 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5702 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5703 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5704 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5705 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5706 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5707 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5708 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5709 ) ) ; +cbx_1__1_ cbx_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5710 } ) , + .chanx_left_in ( sb_0__1__10_chanx_right_out ) , + .chanx_right_in ( sb_1__1__10_chanx_left_out ) , + .ccff_head ( sb_1__1__10_ccff_tail ) , + .chanx_left_out ( cbx_1__1__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__10_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__10_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__10_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__10_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__10_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__10_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__10_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__10_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__10_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__10_ccff_tail ) , .SC_IN_TOP ( scff_Wires[2] ) , + .SC_OUT_BOT ( scff_Wires[3] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5711 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[10] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[10] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[10] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[10] ) , + .pReset_E_in ( pResetWires[552] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5712 ) , + .pReset_W_out ( pResetWires[551] ) , .pReset_S_out ( pResetWires[553] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5713 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[56] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[55] ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5714 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[37] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[38] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[39] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5715 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5716 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5717 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5718 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5719 ) , + .clk_1_E_in ( clk_1_wires[37] ) , .clk_1_N_out ( clk_1_wires[38] ) , + .clk_1_S_out ( clk_1_wires[39] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5720 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5721 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5722 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5723 ) ) ; +cbx_1__1_ cbx_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5724 } ) , + .chanx_left_in ( sb_1__1__0_chanx_right_out ) , + .chanx_right_in ( sb_1__1__11_chanx_left_out ) , + .ccff_head ( sb_1__1__11_ccff_tail ) , + .chanx_left_out ( cbx_1__1__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__11_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__11_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__11_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__11_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__11_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__11_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__11_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__11_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__11_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__11_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5725 ) , + .SC_IN_BOT ( scff_Wires[29] ) , .SC_OUT_TOP ( scff_Wires[30] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[11] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[11] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[11] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[11] ) , + .pReset_E_in ( pResetWires[67] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5726 ) , + .pReset_W_out ( pResetWires[66] ) , .pReset_S_out ( pResetWires[68] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5727 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[66] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5728 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[1] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5729 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[5] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[6] ) , .prog_clk_2_E_in ( h_incr0 ) , + .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5730 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5731 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5732 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5733 ) , + .clk_1_W_in ( clk_1_wires[1] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5734 ) , + .clk_1_N_out ( clk_1_wires[5] ) , .clk_1_S_out ( clk_1_wires[6] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5735 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5736 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5737 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5738 ) ) ; +cbx_1__1_ cbx_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5739 } ) , + .chanx_left_in ( sb_1__1__1_chanx_right_out ) , + .chanx_right_in ( sb_1__1__12_chanx_left_out ) , + .ccff_head ( sb_1__1__12_ccff_tail ) , + .chanx_left_out ( cbx_1__1__12_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__12_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__12_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__12_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__12_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__12_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__12_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__12_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__12_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__12_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__12_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__12_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__12_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__12_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__12_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__12_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__12_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__12_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__12_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5740 ) , + .SC_IN_BOT ( scff_Wires[31] ) , .SC_OUT_TOP ( scff_Wires[32] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[12] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[12] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[12] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[12] ) , + .pReset_E_in ( pResetWires[116] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5741 ) , + .pReset_W_out ( pResetWires[115] ) , .pReset_S_out ( pResetWires[117] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5742 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[69] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5743 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5744 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5745 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[2] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5746 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[1] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5747 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5748 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5749 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5750 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5751 ) , + .clk_2_E_in ( clk_2_wires[2] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5752 ) , + .clk_2_W_out ( clk_2_wires[1] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5753 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5754 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5755 ) ) ; +cbx_1__1_ cbx_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5756 } ) , + .chanx_left_in ( sb_1__1__2_chanx_right_out ) , + .chanx_right_in ( sb_1__1__13_chanx_left_out ) , + .ccff_head ( sb_1__1__13_ccff_tail ) , + .chanx_left_out ( cbx_1__1__13_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__13_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__13_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__13_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__13_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__13_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__13_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__13_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__13_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__13_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__13_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__13_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__13_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__13_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__13_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__13_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__13_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__13_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__13_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5757 ) , + .SC_IN_BOT ( scff_Wires[33] ) , .SC_OUT_TOP ( scff_Wires[34] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[13] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[13] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[13] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[13] ) , + .pReset_E_in ( pResetWires[165] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5758 ) , + .pReset_W_out ( pResetWires[164] ) , .pReset_S_out ( pResetWires[166] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5759 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[72] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5760 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[8] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5761 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[12] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[13] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5762 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5763 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5764 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5765 ) , + .clk_1_W_in ( clk_1_wires[8] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5766 ) , + .clk_1_N_out ( clk_1_wires[12] ) , .clk_1_S_out ( clk_1_wires[13] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5767 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5768 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5769 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5770 ) ) ; +cbx_1__1_ cbx_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5771 } ) , + .chanx_left_in ( sb_1__1__3_chanx_right_out ) , + .chanx_right_in ( sb_1__1__14_chanx_left_out ) , + .ccff_head ( sb_1__1__14_ccff_tail ) , + .chanx_left_out ( cbx_1__1__14_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__14_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__14_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__14_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__14_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__14_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__14_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__14_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__14_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__14_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__14_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__14_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__14_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__14_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__14_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__14_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__14_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__14_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__14_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5772 ) , + .SC_IN_BOT ( scff_Wires[35] ) , .SC_OUT_TOP ( scff_Wires[36] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[14] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[14] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[14] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[14] ) , + .pReset_E_in ( pResetWires[214] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5773 ) , + .pReset_W_out ( pResetWires[213] ) , .pReset_S_out ( pResetWires[215] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5774 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[75] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5775 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5776 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5777 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[7] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5778 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[6] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5779 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5780 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5781 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5782 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5783 ) , + .clk_2_E_in ( clk_2_wires[7] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5784 ) , + .clk_2_W_out ( clk_2_wires[6] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5785 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5786 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5787 ) ) ; +cbx_1__1_ cbx_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5788 } ) , + .chanx_left_in ( sb_1__1__4_chanx_right_out ) , + .chanx_right_in ( sb_1__1__15_chanx_left_out ) , + .ccff_head ( sb_1__1__15_ccff_tail ) , + .chanx_left_out ( cbx_1__1__15_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__15_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__15_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__15_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__15_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__15_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__15_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__15_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__15_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__15_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__15_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__15_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__15_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__15_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__15_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__15_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__15_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__15_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__15_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5789 ) , + .SC_IN_BOT ( scff_Wires[37] ) , .SC_OUT_TOP ( scff_Wires[38] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[15] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[15] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[15] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[15] ) , + .pReset_E_in ( pResetWires[263] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5790 ) , + .pReset_W_out ( pResetWires[262] ) , .pReset_S_out ( pResetWires[264] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5791 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[78] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5792 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[15] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5793 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[19] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[20] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5794 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5795 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5796 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5797 ) , + .clk_1_W_in ( clk_1_wires[15] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5798 ) , + .clk_1_N_out ( clk_1_wires[19] ) , .clk_1_S_out ( clk_1_wires[20] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5799 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5800 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5801 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5802 ) ) ; +cbx_1__1_ cbx_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5803 } ) , + .chanx_left_in ( sb_1__1__5_chanx_right_out ) , + .chanx_right_in ( sb_1__1__16_chanx_left_out ) , + .ccff_head ( sb_1__1__16_ccff_tail ) , + .chanx_left_out ( cbx_1__1__16_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__16_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__16_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__16_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__16_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__16_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__16_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__16_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__16_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__16_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__16_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__16_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__16_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__16_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__16_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__16_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__16_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__16_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__16_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5804 ) , + .SC_IN_BOT ( scff_Wires[39] ) , .SC_OUT_TOP ( scff_Wires[40] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[16] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[16] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[16] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[16] ) , + .pReset_E_in ( pResetWires[312] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5805 ) , + .pReset_W_out ( pResetWires[311] ) , .pReset_S_out ( pResetWires[313] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5806 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[81] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5807 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5808 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5809 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5810 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5811 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5812 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5813 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5814 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5815 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5816 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5817 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5818 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5819 ) ) ; +cbx_1__1_ cbx_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5820 } ) , + .chanx_left_in ( sb_1__1__6_chanx_right_out ) , + .chanx_right_in ( sb_1__1__17_chanx_left_out ) , + .ccff_head ( sb_1__1__17_ccff_tail ) , + .chanx_left_out ( cbx_1__1__17_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__17_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__17_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__17_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__17_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__17_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__17_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__17_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__17_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__17_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__17_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__17_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__17_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__17_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__17_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__17_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__17_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__17_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__17_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5821 ) , + .SC_IN_BOT ( scff_Wires[41] ) , .SC_OUT_TOP ( scff_Wires[42] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[17] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[17] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[17] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[17] ) , + .pReset_E_in ( pResetWires[361] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5822 ) , + .pReset_W_out ( pResetWires[360] ) , .pReset_S_out ( pResetWires[362] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5823 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[84] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5824 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[22] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5825 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[26] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[27] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5826 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5827 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5828 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5829 ) , + .clk_1_W_in ( clk_1_wires[22] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5830 ) , + .clk_1_N_out ( clk_1_wires[26] ) , .clk_1_S_out ( clk_1_wires[27] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5831 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5832 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5833 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5834 ) ) ; +cbx_1__1_ cbx_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5835 } ) , + .chanx_left_in ( sb_1__1__7_chanx_right_out ) , + .chanx_right_in ( sb_1__1__18_chanx_left_out ) , + .ccff_head ( sb_1__1__18_ccff_tail ) , + .chanx_left_out ( cbx_1__1__18_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__18_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__18_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__18_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__18_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__18_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__18_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__18_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__18_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__18_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__18_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__18_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__18_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__18_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__18_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__18_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__18_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__18_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__18_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5836 ) , + .SC_IN_BOT ( scff_Wires[43] ) , .SC_OUT_TOP ( scff_Wires[44] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[18] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[18] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[18] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[18] ) , + .pReset_E_in ( pResetWires[410] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5837 ) , + .pReset_W_out ( pResetWires[409] ) , .pReset_S_out ( pResetWires[411] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5838 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[87] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5839 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5840 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5841 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[14] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5842 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[13] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5843 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5844 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5845 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5846 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5847 ) , + .clk_2_E_in ( clk_2_wires[14] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5848 ) , + .clk_2_W_out ( clk_2_wires[13] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5849 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5850 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5851 ) ) ; +cbx_1__1_ cbx_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5852 } ) , + .chanx_left_in ( sb_1__1__8_chanx_right_out ) , + .chanx_right_in ( sb_1__1__19_chanx_left_out ) , + .ccff_head ( sb_1__1__19_ccff_tail ) , + .chanx_left_out ( cbx_1__1__19_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__19_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__19_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__19_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__19_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__19_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__19_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__19_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__19_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__19_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__19_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__19_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__19_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__19_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__19_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__19_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__19_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__19_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__19_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5853 ) , + .SC_IN_BOT ( scff_Wires[45] ) , .SC_OUT_TOP ( scff_Wires[46] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[19] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[19] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[19] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[19] ) , + .pReset_E_in ( pResetWires[459] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5854 ) , + .pReset_W_out ( pResetWires[458] ) , .pReset_S_out ( pResetWires[460] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5855 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[90] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5856 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[29] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5857 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[33] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[34] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5858 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5859 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5860 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5861 ) , + .clk_1_W_in ( clk_1_wires[29] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5862 ) , + .clk_1_N_out ( clk_1_wires[33] ) , .clk_1_S_out ( clk_1_wires[34] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5863 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5864 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5865 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5866 ) ) ; +cbx_1__1_ cbx_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5867 } ) , + .chanx_left_in ( sb_1__1__9_chanx_right_out ) , + .chanx_right_in ( sb_1__1__20_chanx_left_out ) , + .ccff_head ( sb_1__1__20_ccff_tail ) , + .chanx_left_out ( cbx_1__1__20_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__20_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__20_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__20_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__20_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__20_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__20_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__20_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__20_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__20_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__20_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__20_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__20_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__20_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__20_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__20_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__20_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__20_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__20_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5868 ) , + .SC_IN_BOT ( scff_Wires[47] ) , .SC_OUT_TOP ( scff_Wires[48] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[20] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[20] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[20] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[20] ) , + .pReset_E_in ( pResetWires[508] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5869 ) , + .pReset_W_out ( pResetWires[507] ) , .pReset_S_out ( pResetWires[509] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5870 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[93] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5871 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5872 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5873 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[21] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_5874 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[20] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5875 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5876 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5877 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5878 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5879 ) , + .clk_2_E_in ( clk_2_wires[21] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_5880 ) , + .clk_2_W_out ( clk_2_wires[20] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5881 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5882 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5883 ) ) ; +cbx_1__1_ cbx_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5884 } ) , + .chanx_left_in ( sb_1__1__10_chanx_right_out ) , + .chanx_right_in ( sb_1__1__21_chanx_left_out ) , + .ccff_head ( sb_1__1__21_ccff_tail ) , + .chanx_left_out ( cbx_1__1__21_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__21_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__21_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__21_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__21_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__21_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__21_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__21_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__21_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__21_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__21_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__21_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__21_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__21_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__21_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__21_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__21_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__21_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__21_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_5885 ) , + .SC_IN_BOT ( scff_Wires[49] ) , .SC_OUT_TOP ( scff_Wires[50] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[21] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[21] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[21] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[21] ) , + .pReset_E_in ( pResetWires[557] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5886 ) , + .pReset_W_out ( pResetWires[556] ) , .pReset_S_out ( pResetWires[558] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5887 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[96] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5888 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[36] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_5889 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[40] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[41] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5890 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5891 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5892 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5893 ) , + .clk_1_W_in ( clk_1_wires[36] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_5894 ) , + .clk_1_N_out ( clk_1_wires[40] ) , .clk_1_S_out ( clk_1_wires[41] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5895 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5896 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5897 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5898 ) ) ; +cbx_1__1_ cbx_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5899 } ) , + .chanx_left_in ( sb_1__1__11_chanx_right_out ) , + .chanx_right_in ( sb_1__1__22_chanx_left_out ) , + .ccff_head ( sb_1__1__22_ccff_tail ) , + .chanx_left_out ( cbx_1__1__22_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__22_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__22_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__22_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__22_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__22_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__22_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__22_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__22_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__22_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__22_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__22_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__22_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__22_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__22_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__22_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__22_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__22_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__22_ccff_tail ) , .SC_IN_TOP ( scff_Wires[75] ) , + .SC_OUT_BOT ( scff_Wires[76] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5900 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[22] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[22] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[22] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[22] ) , + .pReset_E_in ( pResetWires[71] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5901 ) , + .pReset_W_out ( pResetWires[70] ) , .pReset_S_out ( pResetWires[72] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5902 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[104] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5903 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5904 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[44] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[45] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[46] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5905 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5906 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5907 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5908 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5909 ) , + .clk_1_E_in ( clk_1_wires[44] ) , .clk_1_N_out ( clk_1_wires[45] ) , + .clk_1_S_out ( clk_1_wires[46] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5910 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5911 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5912 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5913 ) ) ; +cbx_1__1_ cbx_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5914 } ) , + .chanx_left_in ( sb_1__1__12_chanx_right_out ) , + .chanx_right_in ( sb_1__1__23_chanx_left_out ) , + .ccff_head ( sb_1__1__23_ccff_tail ) , + .chanx_left_out ( cbx_1__1__23_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__23_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__23_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__23_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__23_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__23_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__23_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__23_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__23_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__23_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__23_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__23_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__23_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__23_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__23_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__23_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__23_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__23_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__23_ccff_tail ) , .SC_IN_TOP ( scff_Wires[73] ) , + .SC_OUT_BOT ( scff_Wires[74] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5915 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[23] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[23] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[23] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[23] ) , + .pReset_E_in ( pResetWires[120] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5916 ) , + .pReset_W_out ( pResetWires[119] ) , .pReset_S_out ( pResetWires[121] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5917 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[107] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5918 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5919 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5920 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5921 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5922 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5923 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5924 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5925 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5926 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5927 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5928 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5929 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5930 ) ) ; +cbx_1__1_ cbx_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5931 } ) , + .chanx_left_in ( sb_1__1__13_chanx_right_out ) , + .chanx_right_in ( sb_1__1__24_chanx_left_out ) , + .ccff_head ( sb_1__1__24_ccff_tail ) , + .chanx_left_out ( cbx_1__1__24_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__24_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__24_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__24_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__24_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__24_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__24_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__24_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__24_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__24_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__24_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__24_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__24_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__24_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__24_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__24_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__24_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__24_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__24_ccff_tail ) , .SC_IN_TOP ( scff_Wires[71] ) , + .SC_OUT_BOT ( scff_Wires[72] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5932 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[24] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[24] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[24] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[24] ) , + .pReset_E_in ( pResetWires[169] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5933 ) , + .pReset_W_out ( pResetWires[168] ) , .pReset_S_out ( pResetWires[170] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5934 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[110] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5935 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5936 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[51] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[52] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[53] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5937 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5938 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5939 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5940 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5941 ) , + .clk_1_E_in ( clk_1_wires[51] ) , .clk_1_N_out ( clk_1_wires[52] ) , + .clk_1_S_out ( clk_1_wires[53] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5942 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5943 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5944 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5945 ) ) ; +cbx_1__1_ cbx_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5946 } ) , + .chanx_left_in ( sb_1__1__14_chanx_right_out ) , + .chanx_right_in ( sb_1__1__25_chanx_left_out ) , + .ccff_head ( sb_1__1__25_ccff_tail ) , + .chanx_left_out ( cbx_1__1__25_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__25_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__25_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__25_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__25_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__25_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__25_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__25_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__25_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__25_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__25_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__25_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__25_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__25_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__25_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__25_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__25_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__25_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__25_ccff_tail ) , .SC_IN_TOP ( scff_Wires[69] ) , + .SC_OUT_BOT ( scff_Wires[70] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5947 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[25] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[25] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[25] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[25] ) , + .pReset_E_in ( pResetWires[218] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5948 ) , + .pReset_W_out ( pResetWires[217] ) , .pReset_S_out ( pResetWires[219] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5949 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[113] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5950 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5951 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5952 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5953 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5954 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5955 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5956 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5957 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5958 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5959 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5960 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5961 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5962 ) ) ; +cbx_1__1_ cbx_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5963 } ) , + .chanx_left_in ( sb_1__1__15_chanx_right_out ) , + .chanx_right_in ( sb_1__1__26_chanx_left_out ) , + .ccff_head ( sb_1__1__26_ccff_tail ) , + .chanx_left_out ( cbx_1__1__26_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__26_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__26_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__26_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__26_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__26_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__26_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__26_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__26_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__26_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__26_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__26_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__26_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__26_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__26_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__26_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__26_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__26_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__26_ccff_tail ) , .SC_IN_TOP ( scff_Wires[67] ) , + .SC_OUT_BOT ( scff_Wires[68] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5964 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[26] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[26] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[26] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[26] ) , + .pReset_E_in ( pResetWires[267] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5965 ) , + .pReset_W_out ( pResetWires[266] ) , .pReset_S_out ( pResetWires[268] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5966 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[116] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5967 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_5968 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[58] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[59] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[60] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5969 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5970 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5971 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_5972 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_5973 ) , + .clk_1_E_in ( clk_1_wires[58] ) , .clk_1_N_out ( clk_1_wires[59] ) , + .clk_1_S_out ( clk_1_wires[60] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5974 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5975 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5976 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_5977 ) ) ; +cbx_1__1_ cbx_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5978 } ) , + .chanx_left_in ( sb_1__1__16_chanx_right_out ) , + .chanx_right_in ( sb_1__1__27_chanx_left_out ) , + .ccff_head ( sb_1__1__27_ccff_tail ) , + .chanx_left_out ( cbx_1__1__27_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__27_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__27_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__27_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__27_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__27_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__27_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__27_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__27_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__27_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__27_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__27_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__27_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__27_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__27_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__27_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__27_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__27_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__27_ccff_tail ) , .SC_IN_TOP ( scff_Wires[65] ) , + .SC_OUT_BOT ( scff_Wires[66] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5979 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[27] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[27] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[27] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[27] ) , + .pReset_E_in ( pResetWires[316] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5980 ) , + .pReset_W_out ( pResetWires[315] ) , .pReset_S_out ( pResetWires[317] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5981 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[119] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5982 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_5983 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_5984 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_5985 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_5986 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_5987 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[50] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_5988 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[51] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_5989 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_5990 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_5991 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_5992 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_5993 ) , + .clk_3_E_in ( clk_3_wires[50] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_5994 ) , + .clk_3_W_out ( clk_3_wires[51] ) ) ; +cbx_1__1_ cbx_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_5995 } ) , + .chanx_left_in ( sb_1__1__17_chanx_right_out ) , + .chanx_right_in ( sb_1__1__28_chanx_left_out ) , + .ccff_head ( sb_1__1__28_ccff_tail ) , + .chanx_left_out ( cbx_1__1__28_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__28_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__28_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__28_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__28_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__28_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__28_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__28_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__28_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__28_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__28_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__28_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__28_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__28_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__28_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__28_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__28_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__28_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__28_ccff_tail ) , .SC_IN_TOP ( scff_Wires[63] ) , + .SC_OUT_BOT ( scff_Wires[64] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_5996 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[28] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[28] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[28] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[28] ) , + .pReset_E_in ( pResetWires[365] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_5997 ) , + .pReset_W_out ( pResetWires[364] ) , .pReset_S_out ( pResetWires[366] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_5998 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[122] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_5999 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6000 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[65] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[66] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[67] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6001 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6002 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6003 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6004 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6005 ) , + .clk_1_E_in ( clk_1_wires[65] ) , .clk_1_N_out ( clk_1_wires[66] ) , + .clk_1_S_out ( clk_1_wires[67] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6006 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6007 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6008 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6009 ) ) ; +cbx_1__1_ cbx_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6010 } ) , + .chanx_left_in ( sb_1__1__18_chanx_right_out ) , + .chanx_right_in ( sb_1__1__29_chanx_left_out ) , + .ccff_head ( sb_1__1__29_ccff_tail ) , + .chanx_left_out ( cbx_1__1__29_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__29_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__29_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__29_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__29_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__29_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__29_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__29_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__29_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__29_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__29_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__29_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__29_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__29_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__29_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__29_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__29_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__29_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__29_ccff_tail ) , .SC_IN_TOP ( scff_Wires[61] ) , + .SC_OUT_BOT ( scff_Wires[62] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6011 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[29] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[29] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[29] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[29] ) , + .pReset_E_in ( pResetWires[414] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6012 ) , + .pReset_W_out ( pResetWires[413] ) , .pReset_S_out ( pResetWires[415] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6013 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[125] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6014 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6015 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6016 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6017 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6018 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6019 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6020 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6021 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6022 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6023 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6024 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6025 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6026 ) ) ; +cbx_1__1_ cbx_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6027 } ) , + .chanx_left_in ( sb_1__1__19_chanx_right_out ) , + .chanx_right_in ( sb_1__1__30_chanx_left_out ) , + .ccff_head ( sb_1__1__30_ccff_tail ) , + .chanx_left_out ( cbx_1__1__30_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__30_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__30_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__30_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__30_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__30_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__30_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__30_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__30_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__30_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__30_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__30_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__30_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__30_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__30_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__30_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__30_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__30_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__30_ccff_tail ) , .SC_IN_TOP ( scff_Wires[59] ) , + .SC_OUT_BOT ( scff_Wires[60] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6028 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[30] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[30] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[30] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[30] ) , + .pReset_E_in ( pResetWires[463] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6029 ) , + .pReset_W_out ( pResetWires[462] ) , .pReset_S_out ( pResetWires[464] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6030 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[128] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6031 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6032 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[72] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[73] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[74] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6033 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6034 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6035 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6036 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6037 ) , + .clk_1_E_in ( clk_1_wires[72] ) , .clk_1_N_out ( clk_1_wires[73] ) , + .clk_1_S_out ( clk_1_wires[74] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6038 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6039 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6040 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6041 ) ) ; +cbx_1__1_ cbx_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6042 } ) , + .chanx_left_in ( sb_1__1__20_chanx_right_out ) , + .chanx_right_in ( sb_1__1__31_chanx_left_out ) , + .ccff_head ( sb_1__1__31_ccff_tail ) , + .chanx_left_out ( cbx_1__1__31_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__31_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__31_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__31_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__31_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__31_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__31_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__31_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__31_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__31_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__31_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__31_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__31_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__31_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__31_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__31_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__31_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__31_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__31_ccff_tail ) , .SC_IN_TOP ( scff_Wires[57] ) , + .SC_OUT_BOT ( scff_Wires[58] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6043 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[31] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[31] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[31] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[31] ) , + .pReset_E_in ( pResetWires[512] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6044 ) , + .pReset_W_out ( pResetWires[511] ) , .pReset_S_out ( pResetWires[513] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6045 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[131] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6046 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6047 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6048 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6049 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6050 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6051 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6052 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6053 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6054 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6055 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6056 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6057 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6058 ) ) ; +cbx_1__1_ cbx_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6059 } ) , + .chanx_left_in ( sb_1__1__21_chanx_right_out ) , + .chanx_right_in ( sb_1__1__32_chanx_left_out ) , + .ccff_head ( sb_1__1__32_ccff_tail ) , + .chanx_left_out ( cbx_1__1__32_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__32_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__32_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__32_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__32_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__32_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__32_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__32_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__32_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__32_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__32_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__32_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__32_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__32_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__32_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__32_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__32_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__32_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__32_ccff_tail ) , .SC_IN_TOP ( scff_Wires[55] ) , + .SC_OUT_BOT ( scff_Wires[56] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6060 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[32] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[32] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[32] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[32] ) , + .pReset_E_in ( pResetWires[561] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6061 ) , + .pReset_W_out ( pResetWires[560] ) , .pReset_S_out ( pResetWires[562] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6062 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[134] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6063 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6064 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[79] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[80] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[81] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6065 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6066 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6067 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6068 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6069 ) , + .clk_1_E_in ( clk_1_wires[79] ) , .clk_1_N_out ( clk_1_wires[80] ) , + .clk_1_S_out ( clk_1_wires[81] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6070 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6071 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6072 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6073 ) ) ; +cbx_1__1_ cbx_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6074 } ) , + .chanx_left_in ( sb_1__1__22_chanx_right_out ) , + .chanx_right_in ( sb_1__1__33_chanx_left_out ) , + .ccff_head ( sb_1__1__33_ccff_tail ) , + .chanx_left_out ( cbx_1__1__33_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__33_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__33_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__33_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__33_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__33_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__33_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__33_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__33_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__33_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__33_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__33_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__33_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__33_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__33_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__33_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__33_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__33_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__33_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6075 ) , + .SC_IN_BOT ( scff_Wires[82] ) , .SC_OUT_TOP ( scff_Wires[83] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[33] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[33] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[33] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[33] ) , + .pReset_E_in ( pResetWires[75] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6076 ) , + .pReset_W_out ( pResetWires[74] ) , .pReset_S_out ( pResetWires[76] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6077 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[142] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6078 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[43] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6079 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[47] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[48] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6080 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6081 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6082 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6083 ) , + .clk_1_W_in ( clk_1_wires[43] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6084 ) , + .clk_1_N_out ( clk_1_wires[47] ) , .clk_1_S_out ( clk_1_wires[48] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6085 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6086 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6087 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6088 ) ) ; +cbx_1__1_ cbx_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6089 } ) , + .chanx_left_in ( sb_1__1__23_chanx_right_out ) , + .chanx_right_in ( sb_1__1__34_chanx_left_out ) , + .ccff_head ( sb_1__1__34_ccff_tail ) , + .chanx_left_out ( cbx_1__1__34_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__34_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__34_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__34_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__34_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__34_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__34_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__34_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__34_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__34_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__34_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__34_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__34_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__34_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__34_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__34_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__34_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__34_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__34_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6090 ) , + .SC_IN_BOT ( scff_Wires[84] ) , .SC_OUT_TOP ( scff_Wires[85] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[34] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[34] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[34] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[34] ) , + .pReset_E_in ( pResetWires[124] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6091 ) , + .pReset_W_out ( pResetWires[123] ) , .pReset_S_out ( pResetWires[125] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6092 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[145] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6093 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6094 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6095 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[27] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6096 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[28] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6097 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6098 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6099 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6100 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6101 ) , + .clk_2_E_in ( clk_2_wires[27] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6102 ) , + .clk_2_W_out ( clk_2_wires[28] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6103 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6104 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6105 ) ) ; +cbx_1__1_ cbx_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6106 } ) , + .chanx_left_in ( sb_1__1__24_chanx_right_out ) , + .chanx_right_in ( sb_1__1__35_chanx_left_out ) , + .ccff_head ( sb_1__1__35_ccff_tail ) , + .chanx_left_out ( cbx_1__1__35_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__35_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__35_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__35_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__35_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__35_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__35_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__35_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__35_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__35_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__35_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__35_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__35_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__35_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__35_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__35_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__35_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__35_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__35_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6107 ) , + .SC_IN_BOT ( scff_Wires[86] ) , .SC_OUT_TOP ( scff_Wires[87] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[35] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[35] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[35] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[35] ) , + .pReset_E_in ( pResetWires[173] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6108 ) , + .pReset_W_out ( pResetWires[172] ) , .pReset_S_out ( pResetWires[174] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6109 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[148] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6110 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[50] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6111 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[54] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[55] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6112 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6113 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6114 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6115 ) , + .clk_1_W_in ( clk_1_wires[50] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6116 ) , + .clk_1_N_out ( clk_1_wires[54] ) , .clk_1_S_out ( clk_1_wires[55] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6117 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6118 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6119 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6120 ) ) ; +cbx_1__1_ cbx_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6121 } ) , + .chanx_left_in ( sb_1__1__25_chanx_right_out ) , + .chanx_right_in ( sb_1__1__36_chanx_left_out ) , + .ccff_head ( sb_1__1__36_ccff_tail ) , + .chanx_left_out ( cbx_1__1__36_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__36_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__36_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__36_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__36_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__36_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__36_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__36_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__36_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__36_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__36_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__36_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__36_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__36_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__36_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__36_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__36_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__36_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__36_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6122 ) , + .SC_IN_BOT ( scff_Wires[88] ) , .SC_OUT_TOP ( scff_Wires[89] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[36] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[36] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[36] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[36] ) , + .pReset_E_in ( pResetWires[222] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6123 ) , + .pReset_W_out ( pResetWires[221] ) , .pReset_S_out ( pResetWires[223] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6124 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[151] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6125 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6126 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6127 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[36] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6128 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[37] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6129 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6130 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6131 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6132 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6133 ) , + .clk_2_E_in ( clk_2_wires[36] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6134 ) , + .clk_2_W_out ( clk_2_wires[37] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6135 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6136 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6137 ) ) ; +cbx_1__1_ cbx_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6138 } ) , + .chanx_left_in ( sb_1__1__26_chanx_right_out ) , + .chanx_right_in ( sb_1__1__37_chanx_left_out ) , + .ccff_head ( sb_1__1__37_ccff_tail ) , + .chanx_left_out ( cbx_1__1__37_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__37_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__37_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__37_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__37_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__37_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__37_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__37_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__37_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__37_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__37_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__37_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__37_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__37_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__37_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__37_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__37_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__37_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__37_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6139 ) , + .SC_IN_BOT ( scff_Wires[90] ) , .SC_OUT_TOP ( scff_Wires[91] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[37] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[37] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[37] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[37] ) , + .pReset_E_in ( pResetWires[271] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6140 ) , + .pReset_W_out ( pResetWires[270] ) , .pReset_S_out ( pResetWires[272] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6141 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[154] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6142 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[57] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6143 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[61] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[62] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6144 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6145 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6146 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6147 ) , + .clk_1_W_in ( clk_1_wires[57] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6148 ) , + .clk_1_N_out ( clk_1_wires[61] ) , .clk_1_S_out ( clk_1_wires[62] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6149 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6150 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6151 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6152 ) ) ; +cbx_1__1_ cbx_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6153 } ) , + .chanx_left_in ( sb_1__1__27_chanx_right_out ) , + .chanx_right_in ( sb_1__1__38_chanx_left_out ) , + .ccff_head ( sb_1__1__38_ccff_tail ) , + .chanx_left_out ( cbx_1__1__38_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__38_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__38_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__38_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__38_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__38_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__38_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__38_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__38_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__38_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__38_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__38_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__38_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__38_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__38_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__38_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__38_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__38_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__38_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6154 ) , + .SC_IN_BOT ( scff_Wires[92] ) , .SC_OUT_TOP ( scff_Wires[93] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[38] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[38] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[38] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[38] ) , + .pReset_E_in ( pResetWires[320] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6155 ) , + .pReset_W_out ( pResetWires[319] ) , .pReset_S_out ( pResetWires[321] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6156 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[157] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6157 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6158 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6159 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6160 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6161 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6162 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[46] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6163 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[47] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6164 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6165 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6166 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6167 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6168 ) , + .clk_3_E_in ( clk_3_wires[46] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6169 ) , + .clk_3_W_out ( clk_3_wires[47] ) ) ; +cbx_1__1_ cbx_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6170 } ) , + .chanx_left_in ( sb_1__1__28_chanx_right_out ) , + .chanx_right_in ( sb_1__1__39_chanx_left_out ) , + .ccff_head ( sb_1__1__39_ccff_tail ) , + .chanx_left_out ( cbx_1__1__39_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__39_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__39_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__39_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__39_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__39_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__39_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__39_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__39_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__39_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__39_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__39_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__39_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__39_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__39_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__39_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__39_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__39_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__39_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6171 ) , + .SC_IN_BOT ( scff_Wires[94] ) , .SC_OUT_TOP ( scff_Wires[95] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[39] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[39] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[39] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[39] ) , + .pReset_E_in ( pResetWires[369] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6172 ) , + .pReset_W_out ( pResetWires[368] ) , .pReset_S_out ( pResetWires[370] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6173 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[160] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6174 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[64] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6175 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[68] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[69] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6176 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6177 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6178 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6179 ) , + .clk_1_W_in ( clk_1_wires[64] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6180 ) , + .clk_1_N_out ( clk_1_wires[68] ) , .clk_1_S_out ( clk_1_wires[69] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6181 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6182 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6183 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6184 ) ) ; +cbx_1__1_ cbx_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6185 } ) , + .chanx_left_in ( sb_1__1__29_chanx_right_out ) , + .chanx_right_in ( sb_1__1__40_chanx_left_out ) , + .ccff_head ( sb_1__1__40_ccff_tail ) , + .chanx_left_out ( cbx_1__1__40_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__40_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__40_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__40_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__40_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__40_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__40_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__40_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__40_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__40_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__40_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__40_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__40_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__40_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__40_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__40_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__40_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__40_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__40_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6186 ) , + .SC_IN_BOT ( scff_Wires[96] ) , .SC_OUT_TOP ( scff_Wires[97] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[40] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[40] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[40] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[40] ) , + .pReset_E_in ( pResetWires[418] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6187 ) , + .pReset_W_out ( pResetWires[417] ) , .pReset_S_out ( pResetWires[419] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6188 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[163] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6189 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6190 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6191 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[49] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6192 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[50] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6193 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6194 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6195 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6196 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6197 ) , + .clk_2_E_in ( clk_2_wires[49] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6198 ) , + .clk_2_W_out ( clk_2_wires[50] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6199 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6200 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6201 ) ) ; +cbx_1__1_ cbx_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6202 } ) , + .chanx_left_in ( sb_1__1__30_chanx_right_out ) , + .chanx_right_in ( sb_1__1__41_chanx_left_out ) , + .ccff_head ( sb_1__1__41_ccff_tail ) , + .chanx_left_out ( cbx_1__1__41_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__41_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__41_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__41_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__41_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__41_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__41_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__41_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__41_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__41_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__41_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__41_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__41_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__41_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__41_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__41_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__41_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__41_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__41_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6203 ) , + .SC_IN_BOT ( scff_Wires[98] ) , .SC_OUT_TOP ( scff_Wires[99] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[41] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[41] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[41] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[41] ) , + .pReset_E_in ( pResetWires[467] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6204 ) , + .pReset_W_out ( pResetWires[466] ) , .pReset_S_out ( pResetWires[468] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6205 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[166] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6206 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[71] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6207 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[75] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[76] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6208 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6209 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6210 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6211 ) , + .clk_1_W_in ( clk_1_wires[71] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6212 ) , + .clk_1_N_out ( clk_1_wires[75] ) , .clk_1_S_out ( clk_1_wires[76] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6213 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6214 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6215 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6216 ) ) ; +cbx_1__1_ cbx_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6217 } ) , + .chanx_left_in ( sb_1__1__31_chanx_right_out ) , + .chanx_right_in ( sb_1__1__42_chanx_left_out ) , + .ccff_head ( sb_1__1__42_ccff_tail ) , + .chanx_left_out ( cbx_1__1__42_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__42_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__42_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__42_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__42_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__42_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__42_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__42_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__42_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__42_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__42_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__42_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__42_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__42_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__42_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__42_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__42_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__42_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__42_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6218 ) , + .SC_IN_BOT ( scff_Wires[100] ) , .SC_OUT_TOP ( scff_Wires[101] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[42] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[42] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[42] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[42] ) , + .pReset_E_in ( pResetWires[516] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6219 ) , + .pReset_W_out ( pResetWires[515] ) , .pReset_S_out ( pResetWires[517] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6220 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[169] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6221 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6222 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6223 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[62] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6224 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[63] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6225 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6226 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6227 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6228 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6229 ) , + .clk_2_E_in ( clk_2_wires[62] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6230 ) , + .clk_2_W_out ( clk_2_wires[63] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6231 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6232 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6233 ) ) ; +cbx_1__1_ cbx_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6234 } ) , + .chanx_left_in ( sb_1__1__32_chanx_right_out ) , + .chanx_right_in ( sb_1__1__43_chanx_left_out ) , + .ccff_head ( sb_1__1__43_ccff_tail ) , + .chanx_left_out ( cbx_1__1__43_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__43_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__43_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__43_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__43_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__43_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__43_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__43_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__43_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__43_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__43_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__43_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__43_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__43_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__43_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__43_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__43_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__43_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__43_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6235 ) , + .SC_IN_BOT ( scff_Wires[102] ) , .SC_OUT_TOP ( scff_Wires[103] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[43] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[43] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[43] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[43] ) , + .pReset_E_in ( pResetWires[565] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6236 ) , + .pReset_W_out ( pResetWires[564] ) , .pReset_S_out ( pResetWires[566] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6237 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[172] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6238 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[78] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6239 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[82] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[83] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6240 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6241 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6242 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6243 ) , + .clk_1_W_in ( clk_1_wires[78] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6244 ) , + .clk_1_N_out ( clk_1_wires[82] ) , .clk_1_S_out ( clk_1_wires[83] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6245 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6246 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6247 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6248 ) ) ; +cbx_1__1_ cbx_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6249 } ) , + .chanx_left_in ( sb_1__1__33_chanx_right_out ) , + .chanx_right_in ( sb_1__1__44_chanx_left_out ) , + .ccff_head ( sb_1__1__44_ccff_tail ) , + .chanx_left_out ( cbx_1__1__44_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__44_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__44_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__44_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__44_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__44_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__44_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__44_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__44_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__44_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__44_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__44_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__44_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__44_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__44_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__44_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__44_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__44_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__44_ccff_tail ) , .SC_IN_TOP ( scff_Wires[128] ) , + .SC_OUT_BOT ( scff_Wires[129] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6250 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[44] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[44] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[44] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[44] ) , + .pReset_E_in ( pResetWires[79] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6251 ) , + .pReset_W_out ( pResetWires[78] ) , .pReset_S_out ( pResetWires[80] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6252 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[180] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6253 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6254 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[86] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[87] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[88] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6255 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6256 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6257 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6258 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6259 ) , + .clk_1_E_in ( clk_1_wires[86] ) , .clk_1_N_out ( clk_1_wires[87] ) , + .clk_1_S_out ( clk_1_wires[88] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6260 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6261 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6262 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6263 ) ) ; +cbx_1__1_ cbx_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6264 } ) , + .chanx_left_in ( sb_1__1__34_chanx_right_out ) , + .chanx_right_in ( sb_1__1__45_chanx_left_out ) , + .ccff_head ( sb_1__1__45_ccff_tail ) , + .chanx_left_out ( cbx_1__1__45_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__45_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__45_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__45_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__45_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__45_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__45_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__45_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__45_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__45_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__45_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__45_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__45_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__45_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__45_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__45_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__45_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__45_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__45_ccff_tail ) , .SC_IN_TOP ( scff_Wires[126] ) , + .SC_OUT_BOT ( scff_Wires[127] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6265 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[45] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[45] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[45] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[45] ) , + .pReset_E_in ( pResetWires[128] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6266 ) , + .pReset_W_out ( pResetWires[127] ) , .pReset_S_out ( pResetWires[129] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6267 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[183] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6268 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6269 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6270 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6271 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[25] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6272 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[26] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6273 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6274 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6275 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6276 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6277 ) , + .clk_2_W_in ( clk_2_wires[25] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6278 ) , + .clk_2_E_out ( clk_2_wires[26] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6279 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6280 ) ) ; +cbx_1__1_ cbx_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6281 } ) , + .chanx_left_in ( sb_1__1__35_chanx_right_out ) , + .chanx_right_in ( sb_1__1__46_chanx_left_out ) , + .ccff_head ( sb_1__1__46_ccff_tail ) , + .chanx_left_out ( cbx_1__1__46_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__46_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__46_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__46_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__46_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__46_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__46_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__46_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__46_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__46_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__46_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__46_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__46_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__46_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__46_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__46_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__46_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__46_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__46_ccff_tail ) , .SC_IN_TOP ( scff_Wires[124] ) , + .SC_OUT_BOT ( scff_Wires[125] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6282 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[46] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[46] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[46] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[46] ) , + .pReset_E_in ( pResetWires[177] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6283 ) , + .pReset_W_out ( pResetWires[176] ) , .pReset_S_out ( pResetWires[178] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6284 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[186] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6285 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6286 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[93] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[94] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[95] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6287 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6288 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6289 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6290 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6291 ) , + .clk_1_E_in ( clk_1_wires[93] ) , .clk_1_N_out ( clk_1_wires[94] ) , + .clk_1_S_out ( clk_1_wires[95] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6292 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6293 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6294 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6295 ) ) ; +cbx_1__1_ cbx_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6296 } ) , + .chanx_left_in ( sb_1__1__36_chanx_right_out ) , + .chanx_right_in ( sb_1__1__47_chanx_left_out ) , + .ccff_head ( sb_1__1__47_ccff_tail ) , + .chanx_left_out ( cbx_1__1__47_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__47_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__47_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__47_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__47_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__47_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__47_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__47_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__47_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__47_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__47_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__47_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__47_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__47_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__47_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__47_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__47_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__47_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__47_ccff_tail ) , .SC_IN_TOP ( scff_Wires[122] ) , + .SC_OUT_BOT ( scff_Wires[123] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6297 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[47] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[47] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[47] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[47] ) , + .pReset_E_in ( pResetWires[226] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6298 ) , + .pReset_W_out ( pResetWires[225] ) , .pReset_S_out ( pResetWires[227] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6299 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[189] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6300 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6301 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6302 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6303 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[34] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6304 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[35] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6305 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6306 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6307 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6308 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6309 ) , + .clk_2_W_in ( clk_2_wires[34] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6310 ) , + .clk_2_E_out ( clk_2_wires[35] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6311 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6312 ) ) ; +cbx_1__1_ cbx_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6313 } ) , + .chanx_left_in ( sb_1__1__37_chanx_right_out ) , + .chanx_right_in ( sb_1__1__48_chanx_left_out ) , + .ccff_head ( sb_1__1__48_ccff_tail ) , + .chanx_left_out ( cbx_1__1__48_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__48_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__48_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__48_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__48_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__48_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__48_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__48_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__48_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__48_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__48_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__48_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__48_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__48_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__48_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__48_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__48_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__48_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__48_ccff_tail ) , .SC_IN_TOP ( scff_Wires[120] ) , + .SC_OUT_BOT ( scff_Wires[121] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6314 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[48] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[48] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[48] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[48] ) , + .pReset_E_in ( pResetWires[275] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6315 ) , + .pReset_W_out ( pResetWires[274] ) , .pReset_S_out ( pResetWires[276] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6316 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[192] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6317 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6318 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[100] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[101] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[102] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6319 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6320 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6321 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6322 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6323 ) , + .clk_1_E_in ( clk_1_wires[100] ) , .clk_1_N_out ( clk_1_wires[101] ) , + .clk_1_S_out ( clk_1_wires[102] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6324 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6325 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6326 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6327 ) ) ; +cbx_1__1_ cbx_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6328 } ) , + .chanx_left_in ( sb_1__1__38_chanx_right_out ) , + .chanx_right_in ( sb_1__1__49_chanx_left_out ) , + .ccff_head ( sb_1__1__49_ccff_tail ) , + .chanx_left_out ( cbx_1__1__49_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__49_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__49_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__49_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__49_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__49_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__49_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__49_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__49_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__49_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__49_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__49_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__49_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__49_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__49_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__49_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__49_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__49_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__49_ccff_tail ) , .SC_IN_TOP ( scff_Wires[118] ) , + .SC_OUT_BOT ( scff_Wires[119] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6329 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[49] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[49] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[49] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[49] ) , + .pReset_E_in ( pResetWires[324] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6330 ) , + .pReset_W_out ( pResetWires[323] ) , .pReset_S_out ( pResetWires[325] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6331 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[195] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6332 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6333 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6334 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6335 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6336 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6337 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[6] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6338 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[7] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6339 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6340 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6341 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6342 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6343 ) , + .clk_3_E_in ( clk_3_wires[6] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6344 ) , + .clk_3_W_out ( clk_3_wires[7] ) ) ; +cbx_1__1_ cbx_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6345 } ) , + .chanx_left_in ( sb_1__1__39_chanx_right_out ) , + .chanx_right_in ( sb_1__1__50_chanx_left_out ) , + .ccff_head ( sb_1__1__50_ccff_tail ) , + .chanx_left_out ( cbx_1__1__50_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__50_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__50_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__50_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__50_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__50_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__50_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__50_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__50_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__50_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__50_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__50_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__50_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__50_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__50_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__50_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__50_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__50_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__50_ccff_tail ) , .SC_IN_TOP ( scff_Wires[116] ) , + .SC_OUT_BOT ( scff_Wires[117] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6346 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[50] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[50] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[50] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[50] ) , + .pReset_E_in ( pResetWires[373] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6347 ) , + .pReset_W_out ( pResetWires[372] ) , .pReset_S_out ( pResetWires[374] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6348 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[198] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6349 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6350 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[107] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[108] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[109] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6351 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6352 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6353 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6354 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6355 ) , + .clk_1_E_in ( clk_1_wires[107] ) , .clk_1_N_out ( clk_1_wires[108] ) , + .clk_1_S_out ( clk_1_wires[109] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6356 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6357 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6358 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6359 ) ) ; +cbx_1__1_ cbx_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6360 } ) , + .chanx_left_in ( sb_1__1__40_chanx_right_out ) , + .chanx_right_in ( sb_1__1__51_chanx_left_out ) , + .ccff_head ( sb_1__1__51_ccff_tail ) , + .chanx_left_out ( cbx_1__1__51_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__51_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__51_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__51_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__51_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__51_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__51_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__51_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__51_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__51_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__51_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__51_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__51_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__51_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__51_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__51_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__51_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__51_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__51_ccff_tail ) , .SC_IN_TOP ( scff_Wires[114] ) , + .SC_OUT_BOT ( scff_Wires[115] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6361 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[51] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[51] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[51] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[51] ) , + .pReset_E_in ( pResetWires[422] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6362 ) , + .pReset_W_out ( pResetWires[421] ) , .pReset_S_out ( pResetWires[423] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6363 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[201] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6364 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6365 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6366 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6367 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[47] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6368 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[48] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6369 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6370 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6371 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6372 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6373 ) , + .clk_2_W_in ( clk_2_wires[47] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6374 ) , + .clk_2_E_out ( clk_2_wires[48] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6375 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6376 ) ) ; +cbx_1__1_ cbx_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6377 } ) , + .chanx_left_in ( sb_1__1__41_chanx_right_out ) , + .chanx_right_in ( sb_1__1__52_chanx_left_out ) , + .ccff_head ( sb_1__1__52_ccff_tail ) , + .chanx_left_out ( cbx_1__1__52_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__52_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__52_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__52_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__52_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__52_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__52_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__52_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__52_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__52_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__52_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__52_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__52_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__52_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__52_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__52_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__52_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__52_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__52_ccff_tail ) , .SC_IN_TOP ( scff_Wires[112] ) , + .SC_OUT_BOT ( scff_Wires[113] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6378 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[52] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[52] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[52] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[52] ) , + .pReset_E_in ( pResetWires[471] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6379 ) , + .pReset_W_out ( pResetWires[470] ) , .pReset_S_out ( pResetWires[472] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6380 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[204] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6381 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6382 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[114] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[115] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[116] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6383 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6384 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6385 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6386 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6387 ) , + .clk_1_E_in ( clk_1_wires[114] ) , .clk_1_N_out ( clk_1_wires[115] ) , + .clk_1_S_out ( clk_1_wires[116] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6388 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6389 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6390 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6391 ) ) ; +cbx_1__1_ cbx_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6392 } ) , + .chanx_left_in ( sb_1__1__42_chanx_right_out ) , + .chanx_right_in ( sb_1__1__53_chanx_left_out ) , + .ccff_head ( sb_1__1__53_ccff_tail ) , + .chanx_left_out ( cbx_1__1__53_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__53_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__53_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__53_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__53_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__53_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__53_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__53_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__53_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__53_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__53_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__53_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__53_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__53_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__53_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__53_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__53_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__53_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__53_ccff_tail ) , .SC_IN_TOP ( scff_Wires[110] ) , + .SC_OUT_BOT ( scff_Wires[111] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6393 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[53] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[53] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[53] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[53] ) , + .pReset_E_in ( pResetWires[520] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6394 ) , + .pReset_W_out ( pResetWires[519] ) , .pReset_S_out ( pResetWires[521] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6395 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[207] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6396 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6397 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6398 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6399 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[60] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6400 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[61] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6401 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6402 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6403 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6404 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6405 ) , + .clk_2_W_in ( clk_2_wires[60] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6406 ) , + .clk_2_E_out ( clk_2_wires[61] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6407 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6408 ) ) ; +cbx_1__1_ cbx_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6409 } ) , + .chanx_left_in ( sb_1__1__43_chanx_right_out ) , + .chanx_right_in ( sb_1__1__54_chanx_left_out ) , + .ccff_head ( sb_1__1__54_ccff_tail ) , + .chanx_left_out ( cbx_1__1__54_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__54_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__54_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__54_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__54_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__54_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__54_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__54_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__54_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__54_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__54_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__54_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__54_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__54_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__54_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__54_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__54_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__54_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__54_ccff_tail ) , .SC_IN_TOP ( scff_Wires[108] ) , + .SC_OUT_BOT ( scff_Wires[109] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6410 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[54] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[54] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[54] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[54] ) , + .pReset_E_in ( pResetWires[569] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6411 ) , + .pReset_W_out ( pResetWires[568] ) , .pReset_S_out ( pResetWires[570] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6412 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[210] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6413 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6414 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[121] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[122] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[123] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6415 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6416 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6417 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6418 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6419 ) , + .clk_1_E_in ( clk_1_wires[121] ) , .clk_1_N_out ( clk_1_wires[122] ) , + .clk_1_S_out ( clk_1_wires[123] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6420 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6421 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6422 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6423 ) ) ; +cbx_1__1_ cbx_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6424 } ) , + .chanx_left_in ( sb_1__1__44_chanx_right_out ) , + .chanx_right_in ( sb_1__1__55_chanx_left_out ) , + .ccff_head ( sb_1__1__55_ccff_tail ) , + .chanx_left_out ( cbx_1__1__55_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__55_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__55_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__55_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__55_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__55_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__55_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__55_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__55_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__55_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__55_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__55_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__55_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__55_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__55_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__55_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__55_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__55_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__55_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6425 ) , + .SC_IN_BOT ( scff_Wires[135] ) , .SC_OUT_TOP ( scff_Wires[136] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[55] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[55] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[55] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[55] ) , + .pReset_E_in ( pResetWires[83] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6426 ) , + .pReset_W_out ( pResetWires[82] ) , .pReset_S_out ( pResetWires[84] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6427 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[218] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6428 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[85] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6429 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[89] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[90] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6430 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6431 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6432 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6433 ) , + .clk_1_W_in ( clk_1_wires[85] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6434 ) , + .clk_1_N_out ( clk_1_wires[89] ) , .clk_1_S_out ( clk_1_wires[90] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6435 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6436 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6437 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6438 ) ) ; +cbx_1__1_ cbx_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6439 } ) , + .chanx_left_in ( sb_1__1__45_chanx_right_out ) , + .chanx_right_in ( sb_1__1__56_chanx_left_out ) , + .ccff_head ( sb_1__1__56_ccff_tail ) , + .chanx_left_out ( cbx_1__1__56_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__56_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__56_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__56_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__56_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__56_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__56_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__56_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__56_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__56_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__56_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__56_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__56_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__56_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__56_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__56_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__56_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__56_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__56_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6440 ) , + .SC_IN_BOT ( scff_Wires[137] ) , .SC_OUT_TOP ( scff_Wires[138] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[56] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[56] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[56] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[56] ) , + .pReset_E_in ( pResetWires[132] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6441 ) , + .pReset_W_out ( pResetWires[131] ) , .pReset_S_out ( pResetWires[133] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6442 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[221] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6443 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6444 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6445 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6446 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6447 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6448 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6449 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6450 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6451 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6452 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6453 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6454 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6455 ) ) ; +cbx_1__1_ cbx_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6456 } ) , + .chanx_left_in ( sb_1__1__46_chanx_right_out ) , + .chanx_right_in ( sb_1__1__57_chanx_left_out ) , + .ccff_head ( sb_1__1__57_ccff_tail ) , + .chanx_left_out ( cbx_1__1__57_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__57_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__57_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__57_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__57_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__57_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__57_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__57_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__57_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__57_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__57_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__57_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__57_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__57_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__57_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__57_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__57_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__57_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__57_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6457 ) , + .SC_IN_BOT ( scff_Wires[139] ) , .SC_OUT_TOP ( scff_Wires[140] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[57] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[57] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[57] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[57] ) , + .pReset_E_in ( pResetWires[181] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6458 ) , + .pReset_W_out ( pResetWires[180] ) , .pReset_S_out ( pResetWires[182] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6459 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[224] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6460 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[92] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6461 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[96] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[97] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6462 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6463 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6464 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6465 ) , + .clk_1_W_in ( clk_1_wires[92] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6466 ) , + .clk_1_N_out ( clk_1_wires[96] ) , .clk_1_S_out ( clk_1_wires[97] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6467 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6468 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6469 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6470 ) ) ; +cbx_1__1_ cbx_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6471 } ) , + .chanx_left_in ( sb_1__1__47_chanx_right_out ) , + .chanx_right_in ( sb_1__1__58_chanx_left_out ) , + .ccff_head ( sb_1__1__58_ccff_tail ) , + .chanx_left_out ( cbx_1__1__58_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__58_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__58_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__58_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__58_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__58_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__58_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__58_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__58_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__58_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__58_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__58_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__58_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__58_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__58_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__58_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__58_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__58_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__58_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6472 ) , + .SC_IN_BOT ( scff_Wires[141] ) , .SC_OUT_TOP ( scff_Wires[142] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[58] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[58] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[58] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[58] ) , + .pReset_E_in ( pResetWires[230] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6473 ) , + .pReset_W_out ( pResetWires[229] ) , .pReset_S_out ( pResetWires[231] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6474 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[227] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6475 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6476 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6477 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6478 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6479 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6480 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6481 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6482 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6483 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6484 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6485 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6486 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6487 ) ) ; +cbx_1__1_ cbx_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6488 } ) , + .chanx_left_in ( sb_1__1__48_chanx_right_out ) , + .chanx_right_in ( sb_1__1__59_chanx_left_out ) , + .ccff_head ( sb_1__1__59_ccff_tail ) , + .chanx_left_out ( cbx_1__1__59_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__59_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__59_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__59_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__59_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__59_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__59_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__59_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__59_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__59_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__59_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__59_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__59_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__59_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__59_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__59_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__59_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__59_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__59_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6489 ) , + .SC_IN_BOT ( scff_Wires[143] ) , .SC_OUT_TOP ( scff_Wires[144] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[59] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[59] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[59] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[59] ) , + .pReset_E_in ( pResetWires[279] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6490 ) , + .pReset_W_out ( pResetWires[278] ) , .pReset_S_out ( pResetWires[280] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6491 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[230] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6492 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[99] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6493 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[103] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[104] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6494 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6495 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6496 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6497 ) , + .clk_1_W_in ( clk_1_wires[99] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6498 ) , + .clk_1_N_out ( clk_1_wires[103] ) , .clk_1_S_out ( clk_1_wires[104] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6499 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6500 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6501 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6502 ) ) ; +cbx_1__1_ cbx_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6503 } ) , + .chanx_left_in ( sb_1__1__49_chanx_right_out ) , + .chanx_right_in ( sb_1__1__60_chanx_left_out ) , + .ccff_head ( sb_1__1__60_ccff_tail ) , + .chanx_left_out ( cbx_1__1__60_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__60_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__60_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__60_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__60_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__60_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__60_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__60_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__60_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__60_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__60_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__60_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__60_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__60_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__60_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__60_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__60_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__60_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__60_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6504 ) , + .SC_IN_BOT ( scff_Wires[145] ) , .SC_OUT_TOP ( scff_Wires[146] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[60] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[60] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[60] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[60] ) , + .pReset_E_in ( pResetWires[328] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6505 ) , + .pReset_W_out ( pResetWires[327] ) , .pReset_S_out ( pResetWires[329] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6506 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[233] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6507 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6508 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6509 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6510 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6511 ) , + .prog_clk_3_W_in ( SYNOPSYS_UNCONNECTED_6512 ) , + .prog_clk_3_E_in ( prog_clk_3_wires[2] ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6513 ) , + .prog_clk_3_W_out ( prog_clk_3_wires[3] ) , .clk_1_W_in ( h_incr0 ) , + .clk_1_E_in ( h_incr0 ) , .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6514 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6515 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6516 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6517 ) , + .clk_3_W_in ( SYNOPSYS_UNCONNECTED_6518 ) , + .clk_3_E_in ( clk_3_wires[2] ) , + .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6519 ) , + .clk_3_W_out ( clk_3_wires[3] ) ) ; +cbx_1__1_ cbx_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6520 } ) , + .chanx_left_in ( sb_1__1__50_chanx_right_out ) , + .chanx_right_in ( sb_1__1__61_chanx_left_out ) , + .ccff_head ( sb_1__1__61_ccff_tail ) , + .chanx_left_out ( cbx_1__1__61_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__61_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__61_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__61_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__61_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__61_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__61_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__61_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__61_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__61_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__61_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__61_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__61_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__61_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__61_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__61_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__61_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__61_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__61_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6521 ) , + .SC_IN_BOT ( scff_Wires[147] ) , .SC_OUT_TOP ( scff_Wires[148] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[61] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[61] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[61] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[61] ) , + .pReset_E_in ( pResetWires[377] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6522 ) , + .pReset_W_out ( pResetWires[376] ) , .pReset_S_out ( pResetWires[378] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6523 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[236] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6524 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[106] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6525 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[110] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[111] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6526 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6527 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6528 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6529 ) , + .clk_1_W_in ( clk_1_wires[106] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6530 ) , + .clk_1_N_out ( clk_1_wires[110] ) , .clk_1_S_out ( clk_1_wires[111] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6531 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6532 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6533 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6534 ) ) ; +cbx_1__1_ cbx_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6535 } ) , + .chanx_left_in ( sb_1__1__51_chanx_right_out ) , + .chanx_right_in ( sb_1__1__62_chanx_left_out ) , + .ccff_head ( sb_1__1__62_ccff_tail ) , + .chanx_left_out ( cbx_1__1__62_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__62_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__62_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__62_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__62_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__62_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__62_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__62_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__62_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__62_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__62_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__62_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__62_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__62_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__62_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__62_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__62_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__62_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__62_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6536 ) , + .SC_IN_BOT ( scff_Wires[149] ) , .SC_OUT_TOP ( scff_Wires[150] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[62] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[62] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[62] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[62] ) , + .pReset_E_in ( pResetWires[426] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6537 ) , + .pReset_W_out ( pResetWires[425] ) , .pReset_S_out ( pResetWires[427] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6538 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[239] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6539 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6540 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6541 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6542 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6543 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6544 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6545 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6546 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6547 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6548 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6549 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6550 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6551 ) ) ; +cbx_1__1_ cbx_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6552 } ) , + .chanx_left_in ( sb_1__1__52_chanx_right_out ) , + .chanx_right_in ( sb_1__1__63_chanx_left_out ) , + .ccff_head ( sb_1__1__63_ccff_tail ) , + .chanx_left_out ( cbx_1__1__63_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__63_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__63_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__63_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__63_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__63_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__63_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__63_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__63_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__63_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__63_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__63_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__63_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__63_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__63_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__63_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__63_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__63_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__63_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6553 ) , + .SC_IN_BOT ( scff_Wires[151] ) , .SC_OUT_TOP ( scff_Wires[152] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[63] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[63] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[63] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[63] ) , + .pReset_E_in ( pResetWires[475] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6554 ) , + .pReset_W_out ( pResetWires[474] ) , .pReset_S_out ( pResetWires[476] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6555 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[242] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6556 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[113] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6557 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[117] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[118] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6558 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6559 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6560 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6561 ) , + .clk_1_W_in ( clk_1_wires[113] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6562 ) , + .clk_1_N_out ( clk_1_wires[117] ) , .clk_1_S_out ( clk_1_wires[118] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6563 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6564 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6565 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6566 ) ) ; +cbx_1__1_ cbx_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6567 } ) , + .chanx_left_in ( sb_1__1__53_chanx_right_out ) , + .chanx_right_in ( sb_1__1__64_chanx_left_out ) , + .ccff_head ( sb_1__1__64_ccff_tail ) , + .chanx_left_out ( cbx_1__1__64_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__64_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__64_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__64_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__64_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__64_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__64_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__64_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__64_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__64_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__64_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__64_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__64_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__64_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__64_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__64_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__64_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__64_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__64_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6568 ) , + .SC_IN_BOT ( scff_Wires[153] ) , .SC_OUT_TOP ( scff_Wires[154] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[64] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[64] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[64] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[64] ) , + .pReset_E_in ( pResetWires[524] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6569 ) , + .pReset_W_out ( pResetWires[523] ) , .pReset_S_out ( pResetWires[525] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6570 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[245] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6571 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6572 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6573 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6574 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6575 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6576 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6577 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6578 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6579 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6580 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6581 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6582 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6583 ) ) ; +cbx_1__1_ cbx_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6584 } ) , + .chanx_left_in ( sb_1__1__54_chanx_right_out ) , + .chanx_right_in ( sb_1__1__65_chanx_left_out ) , + .ccff_head ( sb_1__1__65_ccff_tail ) , + .chanx_left_out ( cbx_1__1__65_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__65_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__65_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__65_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__65_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__65_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__65_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__65_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__65_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__65_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__65_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__65_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__65_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__65_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__65_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__65_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__65_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__65_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__65_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6585 ) , + .SC_IN_BOT ( scff_Wires[155] ) , .SC_OUT_TOP ( scff_Wires[156] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[65] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[65] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[65] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[65] ) , + .pReset_E_in ( pResetWires[573] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_6586 ) , + .pReset_W_out ( pResetWires[572] ) , .pReset_S_out ( pResetWires[574] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_6587 ) , + .prog_clk_0_N_in ( prog_clk_0_wires[248] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6588 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[120] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6589 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[124] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[125] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6590 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6591 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6592 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6593 ) , + .clk_1_W_in ( clk_1_wires[120] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6594 ) , + .clk_1_N_out ( clk_1_wires[124] ) , .clk_1_S_out ( clk_1_wires[125] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6595 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6596 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6597 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6598 ) ) ; +cbx_1__1_ cbx_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6599 } ) , + .chanx_left_in ( sb_1__1__55_chanx_right_out ) , + .chanx_right_in ( sb_1__1__66_chanx_left_out ) , + .ccff_head ( sb_1__1__66_ccff_tail ) , + .chanx_left_out ( cbx_1__1__66_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__66_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__66_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__66_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__66_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__66_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__66_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__66_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__66_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__66_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__66_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__66_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__66_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__66_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__66_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__66_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__66_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__66_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__66_ccff_tail ) , .SC_IN_TOP ( scff_Wires[181] ) , + .SC_OUT_BOT ( scff_Wires[182] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6600 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[66] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[66] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[66] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[66] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6601 ) , + .pReset_W_in ( pResetWires[86] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6602 ) , + .pReset_S_out ( pResetWires[88] ) , .pReset_E_out ( pResetWires[87] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[256] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6603 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6604 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[128] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[129] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[130] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6605 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6606 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6607 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6608 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6609 ) , + .clk_1_E_in ( clk_1_wires[128] ) , .clk_1_N_out ( clk_1_wires[129] ) , + .clk_1_S_out ( clk_1_wires[130] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6610 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6611 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6612 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6613 ) ) ; +cbx_1__1_ cbx_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6614 } ) , + .chanx_left_in ( sb_1__1__56_chanx_right_out ) , + .chanx_right_in ( sb_1__1__67_chanx_left_out ) , + .ccff_head ( sb_1__1__67_ccff_tail ) , + .chanx_left_out ( cbx_1__1__67_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__67_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__67_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__67_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__67_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__67_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__67_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__67_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__67_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__67_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__67_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__67_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__67_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__67_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__67_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__67_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__67_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__67_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__67_ccff_tail ) , .SC_IN_TOP ( scff_Wires[179] ) , + .SC_OUT_BOT ( scff_Wires[180] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6615 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[67] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[67] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[67] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[67] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6616 ) , + .pReset_W_in ( pResetWires[135] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6617 ) , + .pReset_S_out ( pResetWires[137] ) , .pReset_E_out ( pResetWires[136] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[259] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6618 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6619 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6620 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6621 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6622 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6623 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6624 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6625 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6626 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6627 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6628 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6629 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6630 ) ) ; +cbx_1__1_ cbx_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6631 } ) , + .chanx_left_in ( sb_1__1__57_chanx_right_out ) , + .chanx_right_in ( sb_1__1__68_chanx_left_out ) , + .ccff_head ( sb_1__1__68_ccff_tail ) , + .chanx_left_out ( cbx_1__1__68_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__68_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__68_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__68_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__68_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__68_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__68_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__68_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__68_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__68_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__68_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__68_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__68_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__68_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__68_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__68_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__68_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__68_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__68_ccff_tail ) , .SC_IN_TOP ( scff_Wires[177] ) , + .SC_OUT_BOT ( scff_Wires[178] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6632 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[68] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[68] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[68] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[68] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6633 ) , + .pReset_W_in ( pResetWires[184] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6634 ) , + .pReset_S_out ( pResetWires[186] ) , .pReset_E_out ( pResetWires[185] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[262] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6635 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6636 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[135] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[136] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[137] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6637 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6638 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6639 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6640 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6641 ) , + .clk_1_E_in ( clk_1_wires[135] ) , .clk_1_N_out ( clk_1_wires[136] ) , + .clk_1_S_out ( clk_1_wires[137] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6642 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6643 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6644 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6645 ) ) ; +cbx_1__1_ cbx_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6646 } ) , + .chanx_left_in ( sb_1__1__58_chanx_right_out ) , + .chanx_right_in ( sb_1__1__69_chanx_left_out ) , + .ccff_head ( sb_1__1__69_ccff_tail ) , + .chanx_left_out ( cbx_1__1__69_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__69_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__69_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__69_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__69_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__69_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__69_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__69_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__69_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__69_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__69_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__69_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__69_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__69_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__69_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__69_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__69_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__69_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__69_ccff_tail ) , .SC_IN_TOP ( scff_Wires[175] ) , + .SC_OUT_BOT ( scff_Wires[176] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6647 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[69] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[69] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[69] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[69] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6648 ) , + .pReset_W_in ( pResetWires[233] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6649 ) , + .pReset_S_out ( pResetWires[235] ) , .pReset_E_out ( pResetWires[234] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[265] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6650 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6651 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6652 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6653 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6654 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6655 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6656 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6657 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6658 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6659 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6660 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6661 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6662 ) ) ; +cbx_1__1_ cbx_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6663 } ) , + .chanx_left_in ( sb_1__1__59_chanx_right_out ) , + .chanx_right_in ( sb_1__1__70_chanx_left_out ) , + .ccff_head ( sb_1__1__70_ccff_tail ) , + .chanx_left_out ( cbx_1__1__70_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__70_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__70_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__70_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__70_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__70_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__70_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__70_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__70_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__70_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__70_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__70_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__70_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__70_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__70_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__70_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__70_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__70_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__70_ccff_tail ) , .SC_IN_TOP ( scff_Wires[173] ) , + .SC_OUT_BOT ( scff_Wires[174] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6664 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[70] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[70] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[70] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[70] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6665 ) , + .pReset_W_in ( pResetWires[282] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6666 ) , + .pReset_S_out ( pResetWires[284] ) , .pReset_E_out ( pResetWires[283] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[268] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6667 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6668 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[142] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[143] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[144] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6669 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6670 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6671 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6672 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6673 ) , + .clk_1_E_in ( clk_1_wires[142] ) , .clk_1_N_out ( clk_1_wires[143] ) , + .clk_1_S_out ( clk_1_wires[144] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6674 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6675 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6676 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6677 ) ) ; +cbx_1__1_ cbx_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6678 } ) , + .chanx_left_in ( sb_1__1__60_chanx_right_out ) , + .chanx_right_in ( sb_1__1__71_chanx_left_out ) , + .ccff_head ( sb_1__1__71_ccff_tail ) , + .chanx_left_out ( cbx_1__1__71_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__71_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__71_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__71_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__71_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__71_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__71_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__71_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__71_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__71_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__71_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__71_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__71_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__71_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__71_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__71_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__71_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__71_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__71_ccff_tail ) , .SC_IN_TOP ( scff_Wires[171] ) , + .SC_OUT_BOT ( scff_Wires[172] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6679 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[71] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[71] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[71] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[71] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6680 ) , + .pReset_W_in ( pResetWires[331] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6681 ) , + .pReset_S_out ( pResetWires[333] ) , .pReset_E_out ( pResetWires[332] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[271] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6682 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6683 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6684 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6685 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6686 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[0] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6687 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[1] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6688 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6689 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6690 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6691 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6692 ) , + .clk_3_W_in ( clk_3_wires[0] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6693 ) , + .clk_3_E_out ( clk_3_wires[1] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6694 ) ) ; +cbx_1__1_ cbx_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6695 } ) , + .chanx_left_in ( sb_1__1__61_chanx_right_out ) , + .chanx_right_in ( sb_1__1__72_chanx_left_out ) , + .ccff_head ( sb_1__1__72_ccff_tail ) , + .chanx_left_out ( cbx_1__1__72_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__72_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__72_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__72_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__72_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__72_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__72_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__72_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__72_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__72_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__72_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__72_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__72_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__72_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__72_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__72_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__72_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__72_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__72_ccff_tail ) , .SC_IN_TOP ( scff_Wires[169] ) , + .SC_OUT_BOT ( scff_Wires[170] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6696 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[72] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[72] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[72] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[72] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6697 ) , + .pReset_W_in ( pResetWires[380] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6698 ) , + .pReset_S_out ( pResetWires[382] ) , .pReset_E_out ( pResetWires[381] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[274] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6699 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6700 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[149] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[150] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[151] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6701 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6702 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6703 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6704 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6705 ) , + .clk_1_E_in ( clk_1_wires[149] ) , .clk_1_N_out ( clk_1_wires[150] ) , + .clk_1_S_out ( clk_1_wires[151] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6706 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6707 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6708 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6709 ) ) ; +cbx_1__1_ cbx_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6710 } ) , + .chanx_left_in ( sb_1__1__62_chanx_right_out ) , + .chanx_right_in ( sb_1__1__73_chanx_left_out ) , + .ccff_head ( sb_1__1__73_ccff_tail ) , + .chanx_left_out ( cbx_1__1__73_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__73_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__73_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__73_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__73_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__73_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__73_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__73_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__73_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__73_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__73_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__73_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__73_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__73_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__73_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__73_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__73_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__73_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__73_ccff_tail ) , .SC_IN_TOP ( scff_Wires[167] ) , + .SC_OUT_BOT ( scff_Wires[168] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6711 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[73] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[73] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[73] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[73] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6712 ) , + .pReset_W_in ( pResetWires[429] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6713 ) , + .pReset_S_out ( pResetWires[431] ) , .pReset_E_out ( pResetWires[430] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[277] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6714 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6715 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6716 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6717 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6718 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6719 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6720 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6721 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6722 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6723 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6724 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6725 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6726 ) ) ; +cbx_1__1_ cbx_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6727 } ) , + .chanx_left_in ( sb_1__1__63_chanx_right_out ) , + .chanx_right_in ( sb_1__1__74_chanx_left_out ) , + .ccff_head ( sb_1__1__74_ccff_tail ) , + .chanx_left_out ( cbx_1__1__74_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__74_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__74_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__74_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__74_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__74_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__74_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__74_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__74_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__74_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__74_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__74_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__74_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__74_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__74_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__74_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__74_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__74_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__74_ccff_tail ) , .SC_IN_TOP ( scff_Wires[165] ) , + .SC_OUT_BOT ( scff_Wires[166] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6728 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[74] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[74] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[74] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[74] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6729 ) , + .pReset_W_in ( pResetWires[478] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6730 ) , + .pReset_S_out ( pResetWires[480] ) , .pReset_E_out ( pResetWires[479] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[280] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6731 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6732 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[156] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[157] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[158] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6733 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6734 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6735 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6736 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6737 ) , + .clk_1_E_in ( clk_1_wires[156] ) , .clk_1_N_out ( clk_1_wires[157] ) , + .clk_1_S_out ( clk_1_wires[158] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6738 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6739 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6740 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6741 ) ) ; +cbx_1__1_ cbx_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6742 } ) , + .chanx_left_in ( sb_1__1__64_chanx_right_out ) , + .chanx_right_in ( sb_1__1__75_chanx_left_out ) , + .ccff_head ( sb_1__1__75_ccff_tail ) , + .chanx_left_out ( cbx_1__1__75_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__75_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__75_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__75_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__75_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__75_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__75_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__75_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__75_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__75_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__75_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__75_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__75_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__75_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__75_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__75_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__75_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__75_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__75_ccff_tail ) , .SC_IN_TOP ( scff_Wires[163] ) , + .SC_OUT_BOT ( scff_Wires[164] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6743 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[75] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[75] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[75] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[75] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6744 ) , + .pReset_W_in ( pResetWires[527] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6745 ) , + .pReset_S_out ( pResetWires[529] ) , .pReset_E_out ( pResetWires[528] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[283] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6746 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6747 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6748 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6749 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6750 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6751 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6752 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6753 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6754 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6755 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6756 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6757 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6758 ) ) ; +cbx_1__1_ cbx_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6759 } ) , + .chanx_left_in ( sb_1__1__65_chanx_right_out ) , + .chanx_right_in ( sb_1__1__76_chanx_left_out ) , + .ccff_head ( sb_1__1__76_ccff_tail ) , + .chanx_left_out ( cbx_1__1__76_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__76_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__76_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__76_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__76_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__76_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__76_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__76_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__76_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__76_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__76_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__76_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__76_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__76_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__76_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__76_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__76_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__76_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__76_ccff_tail ) , .SC_IN_TOP ( scff_Wires[161] ) , + .SC_OUT_BOT ( scff_Wires[162] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6760 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[76] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[76] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[76] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[76] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6761 ) , + .pReset_W_in ( pResetWires[576] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6762 ) , + .pReset_S_out ( pResetWires[578] ) , .pReset_E_out ( pResetWires[577] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[286] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6763 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6764 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[163] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[164] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[165] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6765 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6766 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6767 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6768 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6769 ) , + .clk_1_E_in ( clk_1_wires[163] ) , .clk_1_N_out ( clk_1_wires[164] ) , + .clk_1_S_out ( clk_1_wires[165] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6770 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6771 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6772 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6773 ) ) ; +cbx_1__1_ cbx_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6774 } ) , + .chanx_left_in ( sb_1__1__66_chanx_right_out ) , + .chanx_right_in ( sb_1__1__77_chanx_left_out ) , + .ccff_head ( sb_1__1__77_ccff_tail ) , + .chanx_left_out ( cbx_1__1__77_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__77_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__77_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__77_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__77_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__77_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__77_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__77_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__77_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__77_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__77_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__77_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__77_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__77_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__77_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__77_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__77_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__77_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__77_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6775 ) , + .SC_IN_BOT ( scff_Wires[188] ) , .SC_OUT_TOP ( scff_Wires[189] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[77] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[77] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[77] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[77] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6776 ) , + .pReset_W_in ( pResetWires[90] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6777 ) , + .pReset_S_out ( pResetWires[92] ) , .pReset_E_out ( pResetWires[91] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[294] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6778 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[127] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6779 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[131] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[132] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6780 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6781 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6782 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6783 ) , + .clk_1_W_in ( clk_1_wires[127] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6784 ) , + .clk_1_N_out ( clk_1_wires[131] ) , .clk_1_S_out ( clk_1_wires[132] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6785 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6786 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6787 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6788 ) ) ; +cbx_1__1_ cbx_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6789 } ) , + .chanx_left_in ( sb_1__1__67_chanx_right_out ) , + .chanx_right_in ( sb_1__1__78_chanx_left_out ) , + .ccff_head ( sb_1__1__78_ccff_tail ) , + .chanx_left_out ( cbx_1__1__78_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__78_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__78_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__78_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__78_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__78_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__78_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__78_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__78_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__78_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__78_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__78_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__78_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__78_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__78_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__78_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__78_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__78_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__78_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6790 ) , + .SC_IN_BOT ( scff_Wires[190] ) , .SC_OUT_TOP ( scff_Wires[191] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[78] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[78] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[78] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[78] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6791 ) , + .pReset_W_in ( pResetWires[139] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6792 ) , + .pReset_S_out ( pResetWires[141] ) , .pReset_E_out ( pResetWires[140] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[297] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6793 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6794 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6795 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[71] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6796 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[72] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6797 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6798 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6799 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6800 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6801 ) , + .clk_2_E_in ( clk_2_wires[71] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6802 ) , + .clk_2_W_out ( clk_2_wires[72] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6803 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6804 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6805 ) ) ; +cbx_1__1_ cbx_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6806 } ) , + .chanx_left_in ( sb_1__1__68_chanx_right_out ) , + .chanx_right_in ( sb_1__1__79_chanx_left_out ) , + .ccff_head ( sb_1__1__79_ccff_tail ) , + .chanx_left_out ( cbx_1__1__79_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__79_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__79_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__79_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__79_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__79_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__79_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__79_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__79_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__79_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__79_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__79_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__79_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__79_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__79_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__79_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__79_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__79_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__79_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6807 ) , + .SC_IN_BOT ( scff_Wires[192] ) , .SC_OUT_TOP ( scff_Wires[193] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[79] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[79] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[79] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[79] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6808 ) , + .pReset_W_in ( pResetWires[188] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6809 ) , + .pReset_S_out ( pResetWires[190] ) , .pReset_E_out ( pResetWires[189] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[300] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6810 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[134] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6811 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[138] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[139] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6812 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6813 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6814 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6815 ) , + .clk_1_W_in ( clk_1_wires[134] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6816 ) , + .clk_1_N_out ( clk_1_wires[138] ) , .clk_1_S_out ( clk_1_wires[139] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6817 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6818 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6819 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6820 ) ) ; +cbx_1__1_ cbx_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6821 } ) , + .chanx_left_in ( sb_1__1__69_chanx_right_out ) , + .chanx_right_in ( sb_1__1__80_chanx_left_out ) , + .ccff_head ( sb_1__1__80_ccff_tail ) , + .chanx_left_out ( cbx_1__1__80_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__80_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__80_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__80_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__80_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__80_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__80_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__80_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__80_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__80_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__80_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__80_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__80_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__80_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__80_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__80_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__80_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__80_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__80_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6822 ) , + .SC_IN_BOT ( scff_Wires[194] ) , .SC_OUT_TOP ( scff_Wires[195] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[80] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[80] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[80] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[80] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6823 ) , + .pReset_W_in ( pResetWires[237] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6824 ) , + .pReset_S_out ( pResetWires[239] ) , .pReset_E_out ( pResetWires[238] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[303] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6825 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6826 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6827 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[80] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6828 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[81] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6829 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6830 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6831 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6832 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6833 ) , + .clk_2_E_in ( clk_2_wires[80] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6834 ) , + .clk_2_W_out ( clk_2_wires[81] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6835 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6836 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6837 ) ) ; +cbx_1__1_ cbx_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6838 } ) , + .chanx_left_in ( sb_1__1__70_chanx_right_out ) , + .chanx_right_in ( sb_1__1__81_chanx_left_out ) , + .ccff_head ( sb_1__1__81_ccff_tail ) , + .chanx_left_out ( cbx_1__1__81_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__81_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__81_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__81_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__81_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__81_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__81_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__81_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__81_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__81_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__81_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__81_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__81_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__81_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__81_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__81_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__81_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__81_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__81_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6839 ) , + .SC_IN_BOT ( scff_Wires[196] ) , .SC_OUT_TOP ( scff_Wires[197] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[81] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[81] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[81] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[81] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6840 ) , + .pReset_W_in ( pResetWires[286] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6841 ) , + .pReset_S_out ( pResetWires[288] ) , .pReset_E_out ( pResetWires[287] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[306] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6842 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[141] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6843 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[145] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[146] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6844 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6845 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6846 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6847 ) , + .clk_1_W_in ( clk_1_wires[141] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6848 ) , + .clk_1_N_out ( clk_1_wires[145] ) , .clk_1_S_out ( clk_1_wires[146] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6849 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6850 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6851 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6852 ) ) ; +cbx_1__1_ cbx_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6853 } ) , + .chanx_left_in ( sb_1__1__71_chanx_right_out ) , + .chanx_right_in ( sb_1__1__82_chanx_left_out ) , + .ccff_head ( sb_1__1__82_ccff_tail ) , + .chanx_left_out ( cbx_1__1__82_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__82_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__82_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__82_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__82_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__82_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__82_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__82_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__82_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__82_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__82_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__82_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__82_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__82_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__82_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__82_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__82_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__82_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__82_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6854 ) , + .SC_IN_BOT ( scff_Wires[198] ) , .SC_OUT_TOP ( scff_Wires[199] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[82] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[82] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[82] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[82] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6855 ) , + .pReset_W_in ( pResetWires[335] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6856 ) , + .pReset_S_out ( pResetWires[337] ) , .pReset_E_out ( pResetWires[336] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[309] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6857 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6858 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6859 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6860 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6861 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[4] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_6862 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[5] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6863 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6864 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6865 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6866 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6867 ) , + .clk_3_W_in ( clk_3_wires[4] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_6868 ) , + .clk_3_E_out ( clk_3_wires[5] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6869 ) ) ; +cbx_1__1_ cbx_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6870 } ) , + .chanx_left_in ( sb_1__1__72_chanx_right_out ) , + .chanx_right_in ( sb_1__1__83_chanx_left_out ) , + .ccff_head ( sb_1__1__83_ccff_tail ) , + .chanx_left_out ( cbx_1__1__83_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__83_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__83_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__83_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__83_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__83_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__83_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__83_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__83_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__83_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__83_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__83_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__83_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__83_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__83_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__83_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__83_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__83_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__83_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6871 ) , + .SC_IN_BOT ( scff_Wires[200] ) , .SC_OUT_TOP ( scff_Wires[201] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[83] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[83] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[83] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[83] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6872 ) , + .pReset_W_in ( pResetWires[384] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6873 ) , + .pReset_S_out ( pResetWires[386] ) , .pReset_E_out ( pResetWires[385] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[312] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6874 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[148] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6875 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[152] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[153] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6876 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6877 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6878 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6879 ) , + .clk_1_W_in ( clk_1_wires[148] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6880 ) , + .clk_1_N_out ( clk_1_wires[152] ) , .clk_1_S_out ( clk_1_wires[153] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6881 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6882 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6883 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6884 ) ) ; +cbx_1__1_ cbx_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6885 } ) , + .chanx_left_in ( sb_1__1__73_chanx_right_out ) , + .chanx_right_in ( sb_1__1__84_chanx_left_out ) , + .ccff_head ( sb_1__1__84_ccff_tail ) , + .chanx_left_out ( cbx_1__1__84_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__84_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__84_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__84_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__84_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__84_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__84_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__84_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__84_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__84_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__84_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__84_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__84_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__84_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__84_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__84_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__84_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__84_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__84_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6886 ) , + .SC_IN_BOT ( scff_Wires[202] ) , .SC_OUT_TOP ( scff_Wires[203] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[84] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[84] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[84] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[84] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6887 ) , + .pReset_W_in ( pResetWires[433] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6888 ) , + .pReset_S_out ( pResetWires[435] ) , .pReset_E_out ( pResetWires[434] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[315] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6889 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6890 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6891 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[93] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6892 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[94] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6893 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6894 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6895 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6896 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6897 ) , + .clk_2_E_in ( clk_2_wires[93] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6898 ) , + .clk_2_W_out ( clk_2_wires[94] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6899 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6900 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6901 ) ) ; +cbx_1__1_ cbx_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6902 } ) , + .chanx_left_in ( sb_1__1__74_chanx_right_out ) , + .chanx_right_in ( sb_1__1__85_chanx_left_out ) , + .ccff_head ( sb_1__1__85_ccff_tail ) , + .chanx_left_out ( cbx_1__1__85_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__85_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__85_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__85_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__85_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__85_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__85_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__85_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__85_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__85_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__85_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__85_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__85_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__85_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__85_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__85_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__85_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__85_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__85_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6903 ) , + .SC_IN_BOT ( scff_Wires[204] ) , .SC_OUT_TOP ( scff_Wires[205] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[85] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[85] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[85] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[85] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6904 ) , + .pReset_W_in ( pResetWires[482] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6905 ) , + .pReset_S_out ( pResetWires[484] ) , .pReset_E_out ( pResetWires[483] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[318] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6906 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[155] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6907 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[159] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[160] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6908 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6909 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6910 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6911 ) , + .clk_1_W_in ( clk_1_wires[155] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6912 ) , + .clk_1_N_out ( clk_1_wires[159] ) , .clk_1_S_out ( clk_1_wires[160] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6913 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6914 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6915 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6916 ) ) ; +cbx_1__1_ cbx_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6917 } ) , + .chanx_left_in ( sb_1__1__75_chanx_right_out ) , + .chanx_right_in ( sb_1__1__86_chanx_left_out ) , + .ccff_head ( sb_1__1__86_ccff_tail ) , + .chanx_left_out ( cbx_1__1__86_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__86_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__86_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__86_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__86_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__86_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__86_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__86_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__86_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__86_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__86_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__86_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__86_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__86_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__86_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__86_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__86_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__86_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__86_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6918 ) , + .SC_IN_BOT ( scff_Wires[206] ) , .SC_OUT_TOP ( scff_Wires[207] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[86] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[86] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[86] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[86] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6919 ) , + .pReset_W_in ( pResetWires[531] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6920 ) , + .pReset_S_out ( pResetWires[533] ) , .pReset_E_out ( pResetWires[532] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[321] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6921 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6922 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6923 ) , + .prog_clk_2_E_in ( prog_clk_2_wires[106] ) , + .prog_clk_2_W_in ( SYNOPSYS_UNCONNECTED_6924 ) , + .prog_clk_2_W_out ( prog_clk_2_wires[107] ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6925 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6926 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6927 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6928 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6929 ) , + .clk_2_E_in ( clk_2_wires[106] ) , + .clk_2_W_in ( SYNOPSYS_UNCONNECTED_6930 ) , + .clk_2_W_out ( clk_2_wires[107] ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6931 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6932 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6933 ) ) ; +cbx_1__1_ cbx_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6934 } ) , + .chanx_left_in ( sb_1__1__76_chanx_right_out ) , + .chanx_right_in ( sb_1__1__87_chanx_left_out ) , + .ccff_head ( sb_1__1__87_ccff_tail ) , + .chanx_left_out ( cbx_1__1__87_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__87_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__87_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__87_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__87_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__87_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__87_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__87_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__87_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__87_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__87_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__87_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__87_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__87_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__87_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__87_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__87_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__87_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__87_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6935 ) , + .SC_IN_BOT ( scff_Wires[208] ) , .SC_OUT_TOP ( scff_Wires[209] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[87] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[87] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[87] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[87] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6936 ) , + .pReset_W_in ( pResetWires[580] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6937 ) , + .pReset_S_out ( pResetWires[582] ) , .pReset_E_out ( pResetWires[581] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[324] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6938 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[162] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_6939 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[166] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[167] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6940 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6941 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6942 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6943 ) , + .clk_1_W_in ( clk_1_wires[162] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_6944 ) , + .clk_1_N_out ( clk_1_wires[166] ) , .clk_1_S_out ( clk_1_wires[167] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6945 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6946 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6947 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6948 ) ) ; +cbx_1__1_ cbx_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6949 } ) , + .chanx_left_in ( sb_1__1__77_chanx_right_out ) , + .chanx_right_in ( sb_1__1__88_chanx_left_out ) , + .ccff_head ( sb_1__1__88_ccff_tail ) , + .chanx_left_out ( cbx_1__1__88_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__88_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__88_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__88_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__88_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__88_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__88_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__88_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__88_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__88_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__88_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__88_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__88_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__88_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__88_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__88_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__88_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__88_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__88_ccff_tail ) , .SC_IN_TOP ( scff_Wires[234] ) , + .SC_OUT_BOT ( scff_Wires[235] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6950 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[88] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[88] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[88] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[88] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6951 ) , + .pReset_W_in ( pResetWires[94] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6952 ) , + .pReset_S_out ( pResetWires[96] ) , .pReset_E_out ( pResetWires[95] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[332] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6953 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6954 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[170] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[171] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[172] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6955 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6956 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6957 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6958 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6959 ) , + .clk_1_E_in ( clk_1_wires[170] ) , .clk_1_N_out ( clk_1_wires[171] ) , + .clk_1_S_out ( clk_1_wires[172] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6960 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6961 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6962 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6963 ) ) ; +cbx_1__1_ cbx_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6964 } ) , + .chanx_left_in ( sb_1__1__78_chanx_right_out ) , + .chanx_right_in ( sb_1__1__89_chanx_left_out ) , + .ccff_head ( sb_1__1__89_ccff_tail ) , + .chanx_left_out ( cbx_1__1__89_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__89_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__89_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__89_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__89_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__89_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__89_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__89_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__89_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__89_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__89_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__89_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__89_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__89_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__89_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__89_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__89_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__89_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__89_ccff_tail ) , .SC_IN_TOP ( scff_Wires[232] ) , + .SC_OUT_BOT ( scff_Wires[233] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6965 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[89] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[89] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[89] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[89] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6966 ) , + .pReset_W_in ( pResetWires[143] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6967 ) , + .pReset_S_out ( pResetWires[145] ) , .pReset_E_out ( pResetWires[144] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[335] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6968 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_6969 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_6970 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_6971 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[69] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6972 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[70] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6973 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6974 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_6975 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_6976 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_6977 ) , + .clk_2_W_in ( clk_2_wires[69] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6978 ) , + .clk_2_E_out ( clk_2_wires[70] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6979 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6980 ) ) ; +cbx_1__1_ cbx_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6981 } ) , + .chanx_left_in ( sb_1__1__79_chanx_right_out ) , + .chanx_right_in ( sb_1__1__90_chanx_left_out ) , + .ccff_head ( sb_1__1__90_ccff_tail ) , + .chanx_left_out ( cbx_1__1__90_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__90_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__90_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__90_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__90_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__90_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__90_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__90_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__90_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__90_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__90_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__90_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__90_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__90_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__90_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__90_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__90_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__90_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__90_ccff_tail ) , .SC_IN_TOP ( scff_Wires[230] ) , + .SC_OUT_BOT ( scff_Wires[231] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6982 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[90] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[90] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[90] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[90] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6983 ) , + .pReset_W_in ( pResetWires[192] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6984 ) , + .pReset_S_out ( pResetWires[194] ) , .pReset_E_out ( pResetWires[193] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[338] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_6985 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_6986 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[177] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[178] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[179] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_6987 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_6988 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_6989 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_6990 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_6991 ) , + .clk_1_E_in ( clk_1_wires[177] ) , .clk_1_N_out ( clk_1_wires[178] ) , + .clk_1_S_out ( clk_1_wires[179] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_6992 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_6993 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_6994 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_6995 ) ) ; +cbx_1__1_ cbx_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_6996 } ) , + .chanx_left_in ( sb_1__1__80_chanx_right_out ) , + .chanx_right_in ( sb_1__1__91_chanx_left_out ) , + .ccff_head ( sb_1__1__91_ccff_tail ) , + .chanx_left_out ( cbx_1__1__91_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__91_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__91_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__91_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__91_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__91_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__91_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__91_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__91_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__91_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__91_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__91_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__91_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__91_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__91_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__91_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__91_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__91_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__91_ccff_tail ) , .SC_IN_TOP ( scff_Wires[228] ) , + .SC_OUT_BOT ( scff_Wires[229] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_6997 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[91] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[91] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[91] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[91] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_6998 ) , + .pReset_W_in ( pResetWires[241] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_6999 ) , + .pReset_S_out ( pResetWires[243] ) , .pReset_E_out ( pResetWires[242] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[341] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7000 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7001 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7002 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7003 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[78] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7004 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[79] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7005 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7006 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7007 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7008 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7009 ) , + .clk_2_W_in ( clk_2_wires[78] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7010 ) , + .clk_2_E_out ( clk_2_wires[79] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7011 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7012 ) ) ; +cbx_1__1_ cbx_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7013 } ) , + .chanx_left_in ( sb_1__1__81_chanx_right_out ) , + .chanx_right_in ( sb_1__1__92_chanx_left_out ) , + .ccff_head ( sb_1__1__92_ccff_tail ) , + .chanx_left_out ( cbx_1__1__92_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__92_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__92_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__92_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__92_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__92_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__92_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__92_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__92_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__92_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__92_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__92_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__92_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__92_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__92_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__92_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__92_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__92_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__92_ccff_tail ) , .SC_IN_TOP ( scff_Wires[226] ) , + .SC_OUT_BOT ( scff_Wires[227] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7014 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[92] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[92] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[92] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[92] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7015 ) , + .pReset_W_in ( pResetWires[290] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7016 ) , + .pReset_S_out ( pResetWires[292] ) , .pReset_E_out ( pResetWires[291] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[344] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7017 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7018 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[184] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[185] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[186] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7019 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7020 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7021 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7022 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7023 ) , + .clk_1_E_in ( clk_1_wires[184] ) , .clk_1_N_out ( clk_1_wires[185] ) , + .clk_1_S_out ( clk_1_wires[186] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7024 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7025 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7026 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7027 ) ) ; +cbx_1__1_ cbx_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7028 } ) , + .chanx_left_in ( sb_1__1__82_chanx_right_out ) , + .chanx_right_in ( sb_1__1__93_chanx_left_out ) , + .ccff_head ( sb_1__1__93_ccff_tail ) , + .chanx_left_out ( cbx_1__1__93_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__93_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__93_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__93_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__93_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__93_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__93_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__93_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__93_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__93_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__93_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__93_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__93_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__93_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__93_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__93_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__93_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__93_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__93_ccff_tail ) , .SC_IN_TOP ( scff_Wires[224] ) , + .SC_OUT_BOT ( scff_Wires[225] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7029 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[93] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[93] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[93] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[93] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7030 ) , + .pReset_W_in ( pResetWires[339] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7031 ) , + .pReset_S_out ( pResetWires[341] ) , .pReset_E_out ( pResetWires[340] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[347] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7032 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7033 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7034 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7035 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7036 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[44] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7037 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[45] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7038 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7039 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7040 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7041 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7042 ) , + .clk_3_W_in ( clk_3_wires[44] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7043 ) , + .clk_3_E_out ( clk_3_wires[45] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7044 ) ) ; +cbx_1__1_ cbx_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7045 } ) , + .chanx_left_in ( sb_1__1__83_chanx_right_out ) , + .chanx_right_in ( sb_1__1__94_chanx_left_out ) , + .ccff_head ( sb_1__1__94_ccff_tail ) , + .chanx_left_out ( cbx_1__1__94_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__94_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__94_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__94_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__94_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__94_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__94_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__94_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__94_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__94_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__94_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__94_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__94_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__94_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__94_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__94_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__94_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__94_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__94_ccff_tail ) , .SC_IN_TOP ( scff_Wires[222] ) , + .SC_OUT_BOT ( scff_Wires[223] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7046 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[94] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[94] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[94] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[94] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7047 ) , + .pReset_W_in ( pResetWires[388] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7048 ) , + .pReset_S_out ( pResetWires[390] ) , .pReset_E_out ( pResetWires[389] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[350] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7049 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7050 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[191] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[192] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[193] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7051 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7052 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7053 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7054 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7055 ) , + .clk_1_E_in ( clk_1_wires[191] ) , .clk_1_N_out ( clk_1_wires[192] ) , + .clk_1_S_out ( clk_1_wires[193] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7056 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7057 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7058 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7059 ) ) ; +cbx_1__1_ cbx_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7060 } ) , + .chanx_left_in ( sb_1__1__84_chanx_right_out ) , + .chanx_right_in ( sb_1__1__95_chanx_left_out ) , + .ccff_head ( sb_1__1__95_ccff_tail ) , + .chanx_left_out ( cbx_1__1__95_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__95_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__95_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__95_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__95_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__95_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__95_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__95_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__95_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__95_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__95_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__95_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__95_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__95_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__95_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__95_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__95_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__95_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__95_ccff_tail ) , .SC_IN_TOP ( scff_Wires[220] ) , + .SC_OUT_BOT ( scff_Wires[221] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7061 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[95] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[95] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[95] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[95] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7062 ) , + .pReset_W_in ( pResetWires[437] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7063 ) , + .pReset_S_out ( pResetWires[439] ) , .pReset_E_out ( pResetWires[438] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[353] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7064 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7065 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7066 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7067 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[91] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7068 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[92] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7069 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7070 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7071 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7072 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7073 ) , + .clk_2_W_in ( clk_2_wires[91] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7074 ) , + .clk_2_E_out ( clk_2_wires[92] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7075 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7076 ) ) ; +cbx_1__1_ cbx_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7077 } ) , + .chanx_left_in ( sb_1__1__85_chanx_right_out ) , + .chanx_right_in ( sb_1__1__96_chanx_left_out ) , + .ccff_head ( sb_1__1__96_ccff_tail ) , + .chanx_left_out ( cbx_1__1__96_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__96_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__96_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__96_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__96_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__96_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__96_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__96_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__96_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__96_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__96_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__96_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__96_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__96_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__96_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__96_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__96_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__96_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__96_ccff_tail ) , .SC_IN_TOP ( scff_Wires[218] ) , + .SC_OUT_BOT ( scff_Wires[219] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7078 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[96] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[96] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[96] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[96] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7079 ) , + .pReset_W_in ( pResetWires[486] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7080 ) , + .pReset_S_out ( pResetWires[488] ) , .pReset_E_out ( pResetWires[487] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[356] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7081 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7082 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[198] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[199] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[200] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7083 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7084 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7085 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7086 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7087 ) , + .clk_1_E_in ( clk_1_wires[198] ) , .clk_1_N_out ( clk_1_wires[199] ) , + .clk_1_S_out ( clk_1_wires[200] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7088 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7089 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7090 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7091 ) ) ; +cbx_1__1_ cbx_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7092 } ) , + .chanx_left_in ( sb_1__1__86_chanx_right_out ) , + .chanx_right_in ( sb_1__1__97_chanx_left_out ) , + .ccff_head ( sb_1__1__97_ccff_tail ) , + .chanx_left_out ( cbx_1__1__97_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__97_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__97_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__97_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__97_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__97_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__97_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__97_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__97_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__97_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__97_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__97_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__97_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__97_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__97_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__97_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__97_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__97_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__97_ccff_tail ) , .SC_IN_TOP ( scff_Wires[216] ) , + .SC_OUT_BOT ( scff_Wires[217] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7093 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[97] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[97] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[97] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[97] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7094 ) , + .pReset_W_in ( pResetWires[535] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7095 ) , + .pReset_S_out ( pResetWires[537] ) , .pReset_E_out ( pResetWires[536] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[359] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7096 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7097 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7098 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7099 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[104] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7100 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[105] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7101 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7102 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7103 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7104 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7105 ) , + .clk_2_W_in ( clk_2_wires[104] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7106 ) , + .clk_2_E_out ( clk_2_wires[105] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7107 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7108 ) ) ; +cbx_1__1_ cbx_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7109 } ) , + .chanx_left_in ( sb_1__1__87_chanx_right_out ) , + .chanx_right_in ( sb_1__1__98_chanx_left_out ) , + .ccff_head ( sb_1__1__98_ccff_tail ) , + .chanx_left_out ( cbx_1__1__98_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__98_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__98_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__98_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__98_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__98_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__98_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__98_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__98_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__98_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__98_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__98_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__98_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__98_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__98_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__98_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__98_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__98_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__98_ccff_tail ) , .SC_IN_TOP ( scff_Wires[214] ) , + .SC_OUT_BOT ( scff_Wires[215] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7110 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[98] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[98] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[98] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[98] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7111 ) , + .pReset_W_in ( pResetWires[584] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7112 ) , + .pReset_S_out ( pResetWires[586] ) , .pReset_E_out ( pResetWires[585] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[362] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7113 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7114 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[205] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[206] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[207] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7115 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7116 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7117 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7118 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7119 ) , + .clk_1_E_in ( clk_1_wires[205] ) , .clk_1_N_out ( clk_1_wires[206] ) , + .clk_1_S_out ( clk_1_wires[207] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7120 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7121 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7122 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7123 ) ) ; +cbx_1__1_ cbx_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7124 } ) , + .chanx_left_in ( sb_1__1__88_chanx_right_out ) , + .chanx_right_in ( sb_1__1__99_chanx_left_out ) , + .ccff_head ( sb_1__1__99_ccff_tail ) , + .chanx_left_out ( cbx_1__1__99_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__99_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__99_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__99_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__99_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__99_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__99_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__99_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__99_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__99_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__99_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__99_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__99_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__99_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__99_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__99_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__99_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__99_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__99_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7125 ) , + .SC_IN_BOT ( scff_Wires[241] ) , .SC_OUT_TOP ( scff_Wires[242] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[99] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[99] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[99] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[99] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7126 ) , + .pReset_W_in ( pResetWires[98] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7127 ) , + .pReset_S_out ( pResetWires[100] ) , .pReset_E_out ( pResetWires[99] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[370] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7128 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[169] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7129 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[173] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[174] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7130 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7131 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7132 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7133 ) , + .clk_1_W_in ( clk_1_wires[169] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7134 ) , + .clk_1_N_out ( clk_1_wires[173] ) , .clk_1_S_out ( clk_1_wires[174] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7135 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7136 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7137 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7138 ) ) ; +cbx_1__1_ cbx_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7139 } ) , + .chanx_left_in ( sb_1__1__89_chanx_right_out ) , + .chanx_right_in ( sb_1__1__100_chanx_left_out ) , + .ccff_head ( sb_1__1__100_ccff_tail ) , + .chanx_left_out ( cbx_1__1__100_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__100_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__100_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__100_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__100_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__100_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__100_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__100_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__100_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__100_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__100_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__100_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__100_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__100_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__100_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__100_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__100_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__100_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__100_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7140 ) , + .SC_IN_BOT ( scff_Wires[243] ) , .SC_OUT_TOP ( scff_Wires[244] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[100] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[100] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[100] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[100] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7141 ) , + .pReset_W_in ( pResetWires[147] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7142 ) , + .pReset_S_out ( pResetWires[149] ) , .pReset_E_out ( pResetWires[148] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[373] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7143 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7144 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7145 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7146 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7147 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7148 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7149 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7150 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7151 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7152 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7153 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7154 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7155 ) ) ; +cbx_1__1_ cbx_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7156 } ) , + .chanx_left_in ( sb_1__1__90_chanx_right_out ) , + .chanx_right_in ( sb_1__1__101_chanx_left_out ) , + .ccff_head ( sb_1__1__101_ccff_tail ) , + .chanx_left_out ( cbx_1__1__101_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__101_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__101_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__101_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__101_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__101_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__101_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__101_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__101_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__101_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__101_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__101_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__101_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__101_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__101_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__101_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__101_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__101_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__101_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7157 ) , + .SC_IN_BOT ( scff_Wires[245] ) , .SC_OUT_TOP ( scff_Wires[246] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[101] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[101] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[101] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[101] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7158 ) , + .pReset_W_in ( pResetWires[196] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7159 ) , + .pReset_S_out ( pResetWires[198] ) , .pReset_E_out ( pResetWires[197] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[376] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7160 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[176] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7161 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[180] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[181] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7162 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7163 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7164 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7165 ) , + .clk_1_W_in ( clk_1_wires[176] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7166 ) , + .clk_1_N_out ( clk_1_wires[180] ) , .clk_1_S_out ( clk_1_wires[181] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7167 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7168 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7169 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7170 ) ) ; +cbx_1__1_ cbx_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7171 } ) , + .chanx_left_in ( sb_1__1__91_chanx_right_out ) , + .chanx_right_in ( sb_1__1__102_chanx_left_out ) , + .ccff_head ( sb_1__1__102_ccff_tail ) , + .chanx_left_out ( cbx_1__1__102_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__102_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__102_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__102_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__102_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__102_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__102_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__102_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__102_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__102_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__102_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__102_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__102_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__102_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__102_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__102_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__102_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__102_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__102_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7172 ) , + .SC_IN_BOT ( scff_Wires[247] ) , .SC_OUT_TOP ( scff_Wires[248] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[102] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[102] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[102] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[102] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7173 ) , + .pReset_W_in ( pResetWires[245] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7174 ) , + .pReset_S_out ( pResetWires[247] ) , .pReset_E_out ( pResetWires[246] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[379] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7175 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7176 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7177 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7178 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7179 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7180 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7181 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7182 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7183 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7184 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7185 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7186 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7187 ) ) ; +cbx_1__1_ cbx_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7188 } ) , + .chanx_left_in ( sb_1__1__92_chanx_right_out ) , + .chanx_right_in ( sb_1__1__103_chanx_left_out ) , + .ccff_head ( sb_1__1__103_ccff_tail ) , + .chanx_left_out ( cbx_1__1__103_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__103_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__103_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__103_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__103_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__103_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__103_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__103_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__103_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__103_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__103_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__103_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__103_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__103_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__103_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__103_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__103_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__103_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__103_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7189 ) , + .SC_IN_BOT ( scff_Wires[249] ) , .SC_OUT_TOP ( scff_Wires[250] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[103] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[103] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[103] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[103] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7190 ) , + .pReset_W_in ( pResetWires[294] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7191 ) , + .pReset_S_out ( pResetWires[296] ) , .pReset_E_out ( pResetWires[295] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[382] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7192 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[183] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7193 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[187] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[188] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7194 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7195 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7196 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7197 ) , + .clk_1_W_in ( clk_1_wires[183] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7198 ) , + .clk_1_N_out ( clk_1_wires[187] ) , .clk_1_S_out ( clk_1_wires[188] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7199 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7200 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7201 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7202 ) ) ; +cbx_1__1_ cbx_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7203 } ) , + .chanx_left_in ( sb_1__1__93_chanx_right_out ) , + .chanx_right_in ( sb_1__1__104_chanx_left_out ) , + .ccff_head ( sb_1__1__104_ccff_tail ) , + .chanx_left_out ( cbx_1__1__104_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__104_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__104_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__104_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__104_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__104_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__104_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__104_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__104_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__104_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__104_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__104_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__104_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__104_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__104_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__104_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__104_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__104_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__104_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7204 ) , + .SC_IN_BOT ( scff_Wires[251] ) , .SC_OUT_TOP ( scff_Wires[252] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[104] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[104] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[104] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[104] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7205 ) , + .pReset_W_in ( pResetWires[343] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7206 ) , + .pReset_S_out ( pResetWires[345] ) , .pReset_E_out ( pResetWires[344] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[385] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7207 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7208 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7209 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7210 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7211 ) , + .prog_clk_3_W_in ( prog_clk_3_wires[48] ) , + .prog_clk_3_E_in ( SYNOPSYS_UNCONNECTED_7212 ) , + .prog_clk_3_E_out ( prog_clk_3_wires[49] ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7213 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7214 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7215 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7216 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7217 ) , + .clk_3_W_in ( clk_3_wires[48] ) , + .clk_3_E_in ( SYNOPSYS_UNCONNECTED_7218 ) , + .clk_3_E_out ( clk_3_wires[49] ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7219 ) ) ; +cbx_1__1_ cbx_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7220 } ) , + .chanx_left_in ( sb_1__1__94_chanx_right_out ) , + .chanx_right_in ( sb_1__1__105_chanx_left_out ) , + .ccff_head ( sb_1__1__105_ccff_tail ) , + .chanx_left_out ( cbx_1__1__105_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__105_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__105_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__105_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__105_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__105_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__105_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__105_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__105_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__105_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__105_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__105_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__105_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__105_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__105_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__105_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__105_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__105_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__105_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7221 ) , + .SC_IN_BOT ( scff_Wires[253] ) , .SC_OUT_TOP ( scff_Wires[254] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[105] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[105] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[105] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[105] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7222 ) , + .pReset_W_in ( pResetWires[392] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7223 ) , + .pReset_S_out ( pResetWires[394] ) , .pReset_E_out ( pResetWires[393] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[388] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7224 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[190] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7225 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[194] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[195] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7226 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7227 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7228 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7229 ) , + .clk_1_W_in ( clk_1_wires[190] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7230 ) , + .clk_1_N_out ( clk_1_wires[194] ) , .clk_1_S_out ( clk_1_wires[195] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7231 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7232 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7233 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7234 ) ) ; +cbx_1__1_ cbx_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7235 } ) , + .chanx_left_in ( sb_1__1__95_chanx_right_out ) , + .chanx_right_in ( sb_1__1__106_chanx_left_out ) , + .ccff_head ( sb_1__1__106_ccff_tail ) , + .chanx_left_out ( cbx_1__1__106_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__106_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__106_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__106_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__106_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__106_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__106_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__106_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__106_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__106_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__106_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__106_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__106_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__106_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__106_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__106_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__106_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__106_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__106_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7236 ) , + .SC_IN_BOT ( scff_Wires[255] ) , .SC_OUT_TOP ( scff_Wires[256] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[106] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[106] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[106] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[106] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7237 ) , + .pReset_W_in ( pResetWires[441] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7238 ) , + .pReset_S_out ( pResetWires[443] ) , .pReset_E_out ( pResetWires[442] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[391] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7239 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7240 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7241 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7242 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7243 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7244 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7245 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7246 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7247 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7248 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7249 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7250 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7251 ) ) ; +cbx_1__1_ cbx_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7252 } ) , + .chanx_left_in ( sb_1__1__96_chanx_right_out ) , + .chanx_right_in ( sb_1__1__107_chanx_left_out ) , + .ccff_head ( sb_1__1__107_ccff_tail ) , + .chanx_left_out ( cbx_1__1__107_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__107_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__107_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__107_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__107_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__107_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__107_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__107_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__107_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__107_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__107_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__107_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__107_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__107_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__107_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__107_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__107_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__107_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__107_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7253 ) , + .SC_IN_BOT ( scff_Wires[257] ) , .SC_OUT_TOP ( scff_Wires[258] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[107] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[107] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[107] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[107] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7254 ) , + .pReset_W_in ( pResetWires[490] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7255 ) , + .pReset_S_out ( pResetWires[492] ) , .pReset_E_out ( pResetWires[491] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[394] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7256 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[197] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7257 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[201] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[202] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7258 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7259 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7260 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7261 ) , + .clk_1_W_in ( clk_1_wires[197] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7262 ) , + .clk_1_N_out ( clk_1_wires[201] ) , .clk_1_S_out ( clk_1_wires[202] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7263 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7264 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7265 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7266 ) ) ; +cbx_1__1_ cbx_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7267 } ) , + .chanx_left_in ( sb_1__1__97_chanx_right_out ) , + .chanx_right_in ( sb_1__1__108_chanx_left_out ) , + .ccff_head ( sb_1__1__108_ccff_tail ) , + .chanx_left_out ( cbx_1__1__108_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__108_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__108_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__108_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__108_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__108_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__108_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__108_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__108_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__108_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__108_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__108_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__108_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__108_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__108_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__108_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__108_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__108_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__108_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7268 ) , + .SC_IN_BOT ( scff_Wires[259] ) , .SC_OUT_TOP ( scff_Wires[260] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[108] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[108] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[108] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[108] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7269 ) , + .pReset_W_in ( pResetWires[539] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7270 ) , + .pReset_S_out ( pResetWires[541] ) , .pReset_E_out ( pResetWires[540] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[397] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7271 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7272 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7273 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7274 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7275 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7276 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7277 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7278 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7279 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7280 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7281 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7282 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7283 ) ) ; +cbx_1__1_ cbx_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7284 } ) , + .chanx_left_in ( sb_1__1__98_chanx_right_out ) , + .chanx_right_in ( sb_1__1__109_chanx_left_out ) , + .ccff_head ( sb_1__1__109_ccff_tail ) , + .chanx_left_out ( cbx_1__1__109_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__109_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__109_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__109_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__109_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__109_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__109_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__109_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__109_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__109_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__109_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__109_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__109_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__109_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__109_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__109_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__109_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__109_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__109_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7285 ) , + .SC_IN_BOT ( scff_Wires[261] ) , .SC_OUT_TOP ( scff_Wires[262] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[109] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[109] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[109] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[109] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7286 ) , + .pReset_W_in ( pResetWires[588] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7287 ) , + .pReset_S_out ( pResetWires[590] ) , .pReset_E_out ( pResetWires[589] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[400] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7288 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[204] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7289 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[208] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[209] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7290 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7291 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7292 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7293 ) , + .clk_1_W_in ( clk_1_wires[204] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7294 ) , + .clk_1_N_out ( clk_1_wires[208] ) , .clk_1_S_out ( clk_1_wires[209] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7295 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7296 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7297 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7298 ) ) ; +cbx_1__1_ cbx_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7299 } ) , + .chanx_left_in ( sb_1__1__99_chanx_right_out ) , + .chanx_right_in ( sb_1__1__110_chanx_left_out ) , + .ccff_head ( sb_1__1__110_ccff_tail ) , + .chanx_left_out ( cbx_1__1__110_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__110_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__110_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__110_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__110_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__110_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__110_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__110_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__110_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__110_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__110_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__110_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__110_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__110_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__110_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__110_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__110_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__110_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__110_ccff_tail ) , .SC_IN_TOP ( scff_Wires[287] ) , + .SC_OUT_BOT ( scff_Wires[288] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7300 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[110] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[110] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[110] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[110] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7301 ) , + .pReset_W_in ( pResetWires[102] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7302 ) , + .pReset_S_out ( pResetWires[104] ) , .pReset_E_out ( pResetWires[103] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[408] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7303 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7304 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[212] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[213] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[214] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7305 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7306 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7307 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7308 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7309 ) , + .clk_1_E_in ( clk_1_wires[212] ) , .clk_1_N_out ( clk_1_wires[213] ) , + .clk_1_S_out ( clk_1_wires[214] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7310 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7311 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7312 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7313 ) ) ; +cbx_1__1_ cbx_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7314 } ) , + .chanx_left_in ( sb_1__1__100_chanx_right_out ) , + .chanx_right_in ( sb_1__1__111_chanx_left_out ) , + .ccff_head ( sb_1__1__111_ccff_tail ) , + .chanx_left_out ( cbx_1__1__111_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__111_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__111_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__111_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__111_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__111_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__111_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__111_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__111_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__111_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__111_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__111_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__111_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__111_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__111_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__111_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__111_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__111_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__111_ccff_tail ) , .SC_IN_TOP ( scff_Wires[285] ) , + .SC_OUT_BOT ( scff_Wires[286] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7315 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[111] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[111] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[111] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[111] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7316 ) , + .pReset_W_in ( pResetWires[151] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7317 ) , + .pReset_S_out ( pResetWires[153] ) , .pReset_E_out ( pResetWires[152] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[411] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7318 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7319 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7320 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7321 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[114] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7322 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[113] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7323 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7324 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7325 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7326 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7327 ) , + .clk_2_W_in ( clk_2_wires[114] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7328 ) , + .clk_2_E_out ( clk_2_wires[113] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7329 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7330 ) ) ; +cbx_1__1_ cbx_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7331 } ) , + .chanx_left_in ( sb_1__1__101_chanx_right_out ) , + .chanx_right_in ( sb_1__1__112_chanx_left_out ) , + .ccff_head ( sb_1__1__112_ccff_tail ) , + .chanx_left_out ( cbx_1__1__112_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__112_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__112_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__112_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__112_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__112_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__112_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__112_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__112_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__112_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__112_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__112_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__112_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__112_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__112_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__112_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__112_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__112_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__112_ccff_tail ) , .SC_IN_TOP ( scff_Wires[283] ) , + .SC_OUT_BOT ( scff_Wires[284] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7332 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[112] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[112] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[112] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[112] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7333 ) , + .pReset_W_in ( pResetWires[200] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7334 ) , + .pReset_S_out ( pResetWires[202] ) , .pReset_E_out ( pResetWires[201] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[414] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7335 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7336 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[219] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[220] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[221] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7337 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7338 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7339 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7340 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7341 ) , + .clk_1_E_in ( clk_1_wires[219] ) , .clk_1_N_out ( clk_1_wires[220] ) , + .clk_1_S_out ( clk_1_wires[221] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7342 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7343 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7344 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7345 ) ) ; +cbx_1__1_ cbx_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7346 } ) , + .chanx_left_in ( sb_1__1__102_chanx_right_out ) , + .chanx_right_in ( sb_1__1__113_chanx_left_out ) , + .ccff_head ( sb_1__1__113_ccff_tail ) , + .chanx_left_out ( cbx_1__1__113_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__113_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__113_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__113_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__113_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__113_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__113_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__113_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__113_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__113_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__113_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__113_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__113_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__113_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__113_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__113_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__113_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__113_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__113_ccff_tail ) , .SC_IN_TOP ( scff_Wires[281] ) , + .SC_OUT_BOT ( scff_Wires[282] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7347 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[113] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[113] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[113] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[113] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7348 ) , + .pReset_W_in ( pResetWires[249] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7349 ) , + .pReset_S_out ( pResetWires[251] ) , .pReset_E_out ( pResetWires[250] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[417] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7350 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7351 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7352 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7353 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[119] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7354 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[118] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7355 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7356 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7357 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7358 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7359 ) , + .clk_2_W_in ( clk_2_wires[119] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7360 ) , + .clk_2_E_out ( clk_2_wires[118] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7361 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7362 ) ) ; +cbx_1__1_ cbx_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7363 } ) , + .chanx_left_in ( sb_1__1__103_chanx_right_out ) , + .chanx_right_in ( sb_1__1__114_chanx_left_out ) , + .ccff_head ( sb_1__1__114_ccff_tail ) , + .chanx_left_out ( cbx_1__1__114_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__114_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__114_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__114_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__114_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__114_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__114_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__114_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__114_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__114_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__114_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__114_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__114_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__114_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__114_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__114_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__114_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__114_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__114_ccff_tail ) , .SC_IN_TOP ( scff_Wires[279] ) , + .SC_OUT_BOT ( scff_Wires[280] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7364 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[114] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[114] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[114] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[114] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7365 ) , + .pReset_W_in ( pResetWires[298] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7366 ) , + .pReset_S_out ( pResetWires[300] ) , .pReset_E_out ( pResetWires[299] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[420] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7367 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7368 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[226] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[227] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[228] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7369 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7370 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7371 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7372 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7373 ) , + .clk_1_E_in ( clk_1_wires[226] ) , .clk_1_N_out ( clk_1_wires[227] ) , + .clk_1_S_out ( clk_1_wires[228] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7374 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7375 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7376 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7377 ) ) ; +cbx_1__1_ cbx_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7378 } ) , + .chanx_left_in ( sb_1__1__104_chanx_right_out ) , + .chanx_right_in ( sb_1__1__115_chanx_left_out ) , + .ccff_head ( sb_1__1__115_ccff_tail ) , + .chanx_left_out ( cbx_1__1__115_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__115_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__115_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__115_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__115_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__115_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__115_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__115_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__115_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__115_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__115_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__115_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__115_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__115_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__115_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__115_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__115_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__115_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__115_ccff_tail ) , .SC_IN_TOP ( scff_Wires[277] ) , + .SC_OUT_BOT ( scff_Wires[278] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7379 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[115] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[115] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[115] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[115] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7380 ) , + .pReset_W_in ( pResetWires[347] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7381 ) , + .pReset_S_out ( pResetWires[349] ) , .pReset_E_out ( pResetWires[348] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[423] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7382 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7383 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7384 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7385 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7386 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7387 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7388 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7389 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7390 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7391 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7392 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7393 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7394 ) ) ; +cbx_1__1_ cbx_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7395 } ) , + .chanx_left_in ( sb_1__1__105_chanx_right_out ) , + .chanx_right_in ( sb_1__1__116_chanx_left_out ) , + .ccff_head ( sb_1__1__116_ccff_tail ) , + .chanx_left_out ( cbx_1__1__116_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__116_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__116_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__116_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__116_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__116_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__116_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__116_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__116_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__116_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__116_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__116_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__116_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__116_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__116_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__116_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__116_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__116_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__116_ccff_tail ) , .SC_IN_TOP ( scff_Wires[275] ) , + .SC_OUT_BOT ( scff_Wires[276] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7396 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[116] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[116] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[116] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[116] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7397 ) , + .pReset_W_in ( pResetWires[396] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7398 ) , + .pReset_S_out ( pResetWires[398] ) , .pReset_E_out ( pResetWires[397] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[426] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7399 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7400 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[233] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[234] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[235] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7401 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7402 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7403 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7404 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7405 ) , + .clk_1_E_in ( clk_1_wires[233] ) , .clk_1_N_out ( clk_1_wires[234] ) , + .clk_1_S_out ( clk_1_wires[235] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7406 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7407 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7408 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7409 ) ) ; +cbx_1__1_ cbx_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7410 } ) , + .chanx_left_in ( sb_1__1__106_chanx_right_out ) , + .chanx_right_in ( sb_1__1__117_chanx_left_out ) , + .ccff_head ( sb_1__1__117_ccff_tail ) , + .chanx_left_out ( cbx_1__1__117_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__117_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__117_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__117_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__117_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__117_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__117_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__117_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__117_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__117_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__117_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__117_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__117_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__117_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__117_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__117_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__117_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__117_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__117_ccff_tail ) , .SC_IN_TOP ( scff_Wires[273] ) , + .SC_OUT_BOT ( scff_Wires[274] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7411 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[117] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[117] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[117] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[117] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7412 ) , + .pReset_W_in ( pResetWires[445] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7413 ) , + .pReset_S_out ( pResetWires[447] ) , .pReset_E_out ( pResetWires[446] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[429] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7414 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7415 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7416 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7417 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[126] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7418 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[125] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7419 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7420 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7421 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7422 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7423 ) , + .clk_2_W_in ( clk_2_wires[126] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7424 ) , + .clk_2_E_out ( clk_2_wires[125] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7425 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7426 ) ) ; +cbx_1__1_ cbx_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7427 } ) , + .chanx_left_in ( sb_1__1__107_chanx_right_out ) , + .chanx_right_in ( sb_1__1__118_chanx_left_out ) , + .ccff_head ( sb_1__1__118_ccff_tail ) , + .chanx_left_out ( cbx_1__1__118_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__118_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__118_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__118_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__118_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__118_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__118_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__118_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__118_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__118_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__118_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__118_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__118_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__118_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__118_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__118_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__118_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__118_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__118_ccff_tail ) , .SC_IN_TOP ( scff_Wires[271] ) , + .SC_OUT_BOT ( scff_Wires[272] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7428 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[118] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[118] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[118] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[118] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7429 ) , + .pReset_W_in ( pResetWires[494] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7430 ) , + .pReset_S_out ( pResetWires[496] ) , .pReset_E_out ( pResetWires[495] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[432] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7431 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7432 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[240] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[241] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[242] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7433 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7434 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7435 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7436 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7437 ) , + .clk_1_E_in ( clk_1_wires[240] ) , .clk_1_N_out ( clk_1_wires[241] ) , + .clk_1_S_out ( clk_1_wires[242] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7438 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7439 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7440 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7441 ) ) ; +cbx_1__1_ cbx_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7442 } ) , + .chanx_left_in ( sb_1__1__108_chanx_right_out ) , + .chanx_right_in ( sb_1__1__119_chanx_left_out ) , + .ccff_head ( sb_1__1__119_ccff_tail ) , + .chanx_left_out ( cbx_1__1__119_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__119_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__119_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__119_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__119_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__119_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__119_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__119_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__119_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__119_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__119_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__119_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__119_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__119_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__119_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__119_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__119_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__119_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__119_ccff_tail ) , .SC_IN_TOP ( scff_Wires[269] ) , + .SC_OUT_BOT ( scff_Wires[270] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7443 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[119] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[119] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[119] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[119] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7444 ) , + .pReset_W_in ( pResetWires[543] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7445 ) , + .pReset_S_out ( pResetWires[545] ) , .pReset_E_out ( pResetWires[544] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[435] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7446 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7447 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7448 ) , + .prog_clk_2_E_in ( SYNOPSYS_UNCONNECTED_7449 ) , + .prog_clk_2_W_in ( prog_clk_2_wires[133] ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7450 ) , + .prog_clk_2_E_out ( prog_clk_2_wires[132] ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7451 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7452 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7453 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7454 ) , + .clk_2_E_in ( SYNOPSYS_UNCONNECTED_7455 ) , + .clk_2_W_in ( clk_2_wires[133] ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7456 ) , + .clk_2_E_out ( clk_2_wires[132] ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7457 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7458 ) ) ; +cbx_1__1_ cbx_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7459 } ) , + .chanx_left_in ( sb_1__1__109_chanx_right_out ) , + .chanx_right_in ( sb_1__1__120_chanx_left_out ) , + .ccff_head ( sb_1__1__120_ccff_tail ) , + .chanx_left_out ( cbx_1__1__120_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__120_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__120_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__120_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__120_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__120_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__120_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__120_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__120_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__120_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__120_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__120_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__120_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__120_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__120_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__120_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__120_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__120_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__120_ccff_tail ) , .SC_IN_TOP ( scff_Wires[267] ) , + .SC_OUT_BOT ( scff_Wires[268] ) , .SC_IN_BOT ( h_incr0 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7460 ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[120] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[120] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[120] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[120] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7461 ) , + .pReset_W_in ( pResetWires[592] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7462 ) , + .pReset_S_out ( pResetWires[594] ) , .pReset_E_out ( pResetWires[593] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[438] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7463 ) , + .prog_clk_1_W_in ( SYNOPSYS_UNCONNECTED_7464 ) , + .prog_clk_1_E_in ( prog_clk_1_wires[247] ) , + .prog_clk_1_N_out ( prog_clk_1_wires[248] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[249] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7465 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7466 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7467 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7468 ) , + .clk_1_W_in ( SYNOPSYS_UNCONNECTED_7469 ) , + .clk_1_E_in ( clk_1_wires[247] ) , .clk_1_N_out ( clk_1_wires[248] ) , + .clk_1_S_out ( clk_1_wires[249] ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7470 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7471 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7472 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7473 ) ) ; +cbx_1__1_ cbx_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7474 } ) , + .chanx_left_in ( sb_1__1__110_chanx_right_out ) , + .chanx_right_in ( sb_12__1__0_chanx_left_out ) , + .ccff_head ( sb_12__1__0_ccff_tail ) , + .chanx_left_out ( cbx_1__1__121_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__121_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__121_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__121_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__121_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__121_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__121_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__121_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__121_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__121_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__121_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__121_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__121_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__121_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__121_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__121_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__121_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__121_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__121_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7475 ) , + .SC_IN_BOT ( scff_Wires[294] ) , .SC_OUT_TOP ( scff_Wires[295] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[121] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[121] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[121] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[121] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7476 ) , + .pReset_W_in ( pResetWires[106] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7477 ) , + .pReset_S_out ( pResetWires[108] ) , .pReset_E_out ( pResetWires[107] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[446] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7478 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[211] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7479 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[215] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[216] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7480 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7481 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7482 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7483 ) , + .clk_1_W_in ( clk_1_wires[211] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7484 ) , + .clk_1_N_out ( clk_1_wires[215] ) , .clk_1_S_out ( clk_1_wires[216] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7485 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7486 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7487 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7488 ) ) ; +cbx_1__1_ cbx_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7489 } ) , + .chanx_left_in ( sb_1__1__111_chanx_right_out ) , + .chanx_right_in ( sb_12__1__1_chanx_left_out ) , + .ccff_head ( sb_12__1__1_ccff_tail ) , + .chanx_left_out ( cbx_1__1__122_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__122_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__122_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__122_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__122_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__122_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__122_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__122_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__122_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__122_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__122_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__122_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__122_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__122_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__122_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__122_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__122_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__122_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__122_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7490 ) , + .SC_IN_BOT ( scff_Wires[296] ) , .SC_OUT_TOP ( scff_Wires[297] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[122] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[122] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[122] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[122] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7491 ) , + .pReset_W_in ( pResetWires[155] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7492 ) , + .pReset_S_out ( pResetWires[157] ) , .pReset_E_out ( pResetWires[156] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[449] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7493 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7494 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7495 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7496 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7497 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7498 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7499 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7500 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7501 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7502 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7503 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7504 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7505 ) ) ; +cbx_1__1_ cbx_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7506 } ) , + .chanx_left_in ( sb_1__1__112_chanx_right_out ) , + .chanx_right_in ( sb_12__1__2_chanx_left_out ) , + .ccff_head ( sb_12__1__2_ccff_tail ) , + .chanx_left_out ( cbx_1__1__123_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__123_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__123_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__123_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__123_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__123_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__123_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__123_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__123_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__123_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__123_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__123_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__123_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__123_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__123_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__123_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__123_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__123_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__123_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7507 ) , + .SC_IN_BOT ( scff_Wires[298] ) , .SC_OUT_TOP ( scff_Wires[299] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[123] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[123] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[123] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[123] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7508 ) , + .pReset_W_in ( pResetWires[204] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7509 ) , + .pReset_S_out ( pResetWires[206] ) , .pReset_E_out ( pResetWires[205] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[452] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7510 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[218] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7511 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[222] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[223] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7512 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7513 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7514 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7515 ) , + .clk_1_W_in ( clk_1_wires[218] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7516 ) , + .clk_1_N_out ( clk_1_wires[222] ) , .clk_1_S_out ( clk_1_wires[223] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7517 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7518 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7519 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7520 ) ) ; +cbx_1__1_ cbx_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7521 } ) , + .chanx_left_in ( sb_1__1__113_chanx_right_out ) , + .chanx_right_in ( sb_12__1__3_chanx_left_out ) , + .ccff_head ( sb_12__1__3_ccff_tail ) , + .chanx_left_out ( cbx_1__1__124_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__124_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__124_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__124_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__124_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__124_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__124_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__124_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__124_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__124_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__124_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__124_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__124_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__124_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__124_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__124_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__124_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__124_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__124_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7522 ) , + .SC_IN_BOT ( scff_Wires[300] ) , .SC_OUT_TOP ( scff_Wires[301] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[124] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[124] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[124] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[124] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7523 ) , + .pReset_W_in ( pResetWires[253] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7524 ) , + .pReset_S_out ( pResetWires[255] ) , .pReset_E_out ( pResetWires[254] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[455] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7525 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7526 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7527 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7528 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7529 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7530 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7531 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7532 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7533 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7534 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7535 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7536 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7537 ) ) ; +cbx_1__1_ cbx_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7538 } ) , + .chanx_left_in ( sb_1__1__114_chanx_right_out ) , + .chanx_right_in ( sb_12__1__4_chanx_left_out ) , + .ccff_head ( sb_12__1__4_ccff_tail ) , + .chanx_left_out ( cbx_1__1__125_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__125_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__125_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__125_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__125_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__125_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__125_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__125_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__125_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__125_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__125_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__125_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__125_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__125_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__125_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__125_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__125_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__125_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__125_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7539 ) , + .SC_IN_BOT ( scff_Wires[302] ) , .SC_OUT_TOP ( scff_Wires[303] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[125] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[125] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[125] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[125] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7540 ) , + .pReset_W_in ( pResetWires[302] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7541 ) , + .pReset_S_out ( pResetWires[304] ) , .pReset_E_out ( pResetWires[303] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[458] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7542 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[225] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7543 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[229] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[230] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7544 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7545 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7546 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7547 ) , + .clk_1_W_in ( clk_1_wires[225] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7548 ) , + .clk_1_N_out ( clk_1_wires[229] ) , .clk_1_S_out ( clk_1_wires[230] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7549 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7550 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7551 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7552 ) ) ; +cbx_1__1_ cbx_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7553 } ) , + .chanx_left_in ( sb_1__1__115_chanx_right_out ) , + .chanx_right_in ( sb_12__1__5_chanx_left_out ) , + .ccff_head ( sb_12__1__5_ccff_tail ) , + .chanx_left_out ( cbx_1__1__126_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__126_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__126_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__126_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__126_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__126_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__126_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__126_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__126_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__126_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__126_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__126_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__126_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__126_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__126_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__126_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__126_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__126_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__126_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7554 ) , + .SC_IN_BOT ( scff_Wires[304] ) , .SC_OUT_TOP ( scff_Wires[305] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[126] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[126] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[126] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[126] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7555 ) , + .pReset_W_in ( pResetWires[351] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7556 ) , + .pReset_S_out ( pResetWires[353] ) , .pReset_E_out ( pResetWires[352] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[461] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7557 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7558 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7559 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7560 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7561 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7562 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7563 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7564 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7565 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7566 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7567 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7568 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7569 ) ) ; +cbx_1__1_ cbx_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7570 } ) , + .chanx_left_in ( sb_1__1__116_chanx_right_out ) , + .chanx_right_in ( sb_12__1__6_chanx_left_out ) , + .ccff_head ( sb_12__1__6_ccff_tail ) , + .chanx_left_out ( cbx_1__1__127_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__127_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__127_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__127_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__127_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__127_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__127_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__127_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__127_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__127_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__127_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__127_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__127_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__127_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__127_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__127_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__127_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__127_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__127_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7571 ) , + .SC_IN_BOT ( scff_Wires[306] ) , .SC_OUT_TOP ( scff_Wires[307] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[127] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[127] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[127] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[127] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7572 ) , + .pReset_W_in ( pResetWires[400] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7573 ) , + .pReset_S_out ( pResetWires[402] ) , .pReset_E_out ( pResetWires[401] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[464] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7574 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[232] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7575 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[236] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[237] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7576 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7577 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7578 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7579 ) , + .clk_1_W_in ( clk_1_wires[232] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7580 ) , + .clk_1_N_out ( clk_1_wires[236] ) , .clk_1_S_out ( clk_1_wires[237] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7581 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7582 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7583 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7584 ) ) ; +cbx_1__1_ cbx_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7585 } ) , + .chanx_left_in ( sb_1__1__117_chanx_right_out ) , + .chanx_right_in ( sb_12__1__7_chanx_left_out ) , + .ccff_head ( sb_12__1__7_ccff_tail ) , + .chanx_left_out ( cbx_1__1__128_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__128_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__128_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__128_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__128_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__128_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__128_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__128_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__128_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__128_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__128_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__128_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__128_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__128_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__128_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__128_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__128_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__128_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__128_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7586 ) , + .SC_IN_BOT ( scff_Wires[308] ) , .SC_OUT_TOP ( scff_Wires[309] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[128] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[128] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[128] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[128] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7587 ) , + .pReset_W_in ( pResetWires[449] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7588 ) , + .pReset_S_out ( pResetWires[451] ) , .pReset_E_out ( pResetWires[450] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[467] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7589 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7590 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7591 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7592 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7593 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7594 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7595 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7596 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7597 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7598 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7599 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7600 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7601 ) ) ; +cbx_1__1_ cbx_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7602 } ) , + .chanx_left_in ( sb_1__1__118_chanx_right_out ) , + .chanx_right_in ( sb_12__1__8_chanx_left_out ) , + .ccff_head ( sb_12__1__8_ccff_tail ) , + .chanx_left_out ( cbx_1__1__129_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__129_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__129_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__129_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__129_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__129_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__129_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__129_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__129_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__129_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__129_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__129_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__129_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__129_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__129_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__129_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__129_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__129_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__129_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7603 ) , + .SC_IN_BOT ( scff_Wires[310] ) , .SC_OUT_TOP ( scff_Wires[311] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[129] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[129] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[129] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[129] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7604 ) , + .pReset_W_in ( pResetWires[498] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7605 ) , + .pReset_S_out ( pResetWires[500] ) , .pReset_E_out ( pResetWires[499] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[470] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7606 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[239] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7607 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[243] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[244] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7608 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7609 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7610 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7611 ) , + .clk_1_W_in ( clk_1_wires[239] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7612 ) , + .clk_1_N_out ( clk_1_wires[243] ) , .clk_1_S_out ( clk_1_wires[244] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7613 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7614 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7615 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7616 ) ) ; +cbx_1__1_ cbx_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7617 } ) , + .chanx_left_in ( sb_1__1__119_chanx_right_out ) , + .chanx_right_in ( sb_12__1__9_chanx_left_out ) , + .ccff_head ( sb_12__1__9_ccff_tail ) , + .chanx_left_out ( cbx_1__1__130_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__130_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__130_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__130_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__130_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__130_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__130_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__130_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__130_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__130_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__130_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__130_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__130_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__130_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__130_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__130_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__130_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__130_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__130_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7618 ) , + .SC_IN_BOT ( scff_Wires[312] ) , .SC_OUT_TOP ( scff_Wires[313] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[130] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[130] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[130] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[130] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7619 ) , + .pReset_W_in ( pResetWires[547] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7620 ) , + .pReset_S_out ( pResetWires[549] ) , .pReset_E_out ( pResetWires[548] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[473] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7621 ) , + .prog_clk_1_W_in ( h_incr0 ) , .prog_clk_1_E_in ( h_incr0 ) , + .prog_clk_1_N_out ( SYNOPSYS_UNCONNECTED_7622 ) , + .prog_clk_1_S_out ( SYNOPSYS_UNCONNECTED_7623 ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7624 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7625 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7626 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7627 ) , + .clk_1_W_in ( h_incr0 ) , .clk_1_E_in ( h_incr0 ) , + .clk_1_N_out ( SYNOPSYS_UNCONNECTED_7628 ) , + .clk_1_S_out ( SYNOPSYS_UNCONNECTED_7629 ) , .clk_2_E_in ( h_incr0 ) , + .clk_2_W_in ( h_incr0 ) , .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7630 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7631 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7632 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7633 ) ) ; +cbx_1__1_ cbx_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7634 } ) , + .chanx_left_in ( sb_1__1__120_chanx_right_out ) , + .chanx_right_in ( sb_12__1__10_chanx_left_out ) , + .ccff_head ( sb_12__1__10_ccff_tail ) , + .chanx_left_out ( cbx_1__1__131_chanx_left_out ) , + .chanx_right_out ( cbx_1__1__131_chanx_right_out ) , + .bottom_grid_pin_0_ ( cbx_1__1__131_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__1__131_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__1__131_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__1__131_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__1__131_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__1__131_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__1__131_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__1__131_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__1__131_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__1__131_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__1__131_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__1__131_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__1__131_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__1__131_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__1__131_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__1__131_bottom_grid_pin_15_ ) , + .ccff_tail ( cbx_1__1__131_ccff_tail ) , .SC_IN_TOP ( h_incr0 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7635 ) , + .SC_IN_BOT ( scff_Wires[314] ) , .SC_OUT_TOP ( scff_Wires[315] ) , + .REGIN_FEEDTHROUGH ( regin_feedthrough_wires[131] ) , + .REGOUT_FEEDTHROUGH ( regout_feedthrough_wires[131] ) , + .CIN_FEEDTHROUGH ( cin_feedthrough_wires[131] ) , + .COUT_FEEDTHROUGH ( cout_feedthrough_wires[131] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7636 ) , + .pReset_W_in ( pResetWires[596] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7637 ) , + .pReset_S_out ( pResetWires[598] ) , .pReset_E_out ( pResetWires[597] ) , + .prog_clk_0_N_in ( prog_clk_0_wires[476] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7638 ) , + .prog_clk_1_W_in ( prog_clk_1_wires[246] ) , + .prog_clk_1_E_in ( SYNOPSYS_UNCONNECTED_7639 ) , + .prog_clk_1_N_out ( prog_clk_1_wires[250] ) , + .prog_clk_1_S_out ( prog_clk_1_wires[251] ) , + .prog_clk_2_E_in ( h_incr0 ) , .prog_clk_2_W_in ( h_incr0 ) , + .prog_clk_2_W_out ( SYNOPSYS_UNCONNECTED_7640 ) , + .prog_clk_2_E_out ( SYNOPSYS_UNCONNECTED_7641 ) , + .prog_clk_3_W_in ( h_incr0 ) , .prog_clk_3_E_in ( h_incr0 ) , + .prog_clk_3_E_out ( SYNOPSYS_UNCONNECTED_7642 ) , + .prog_clk_3_W_out ( SYNOPSYS_UNCONNECTED_7643 ) , + .clk_1_W_in ( clk_1_wires[246] ) , + .clk_1_E_in ( SYNOPSYS_UNCONNECTED_7644 ) , + .clk_1_N_out ( clk_1_wires[250] ) , .clk_1_S_out ( clk_1_wires[251] ) , + .clk_2_E_in ( h_incr0 ) , .clk_2_W_in ( h_incr0 ) , + .clk_2_W_out ( SYNOPSYS_UNCONNECTED_7645 ) , + .clk_2_E_out ( SYNOPSYS_UNCONNECTED_7646 ) , .clk_3_W_in ( h_incr0 ) , + .clk_3_E_in ( h_incr0 ) , .clk_3_E_out ( SYNOPSYS_UNCONNECTED_7647 ) , + .clk_3_W_out ( SYNOPSYS_UNCONNECTED_7648 ) ) ; +cbx_1__2_ cbx_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7649 } ) , + .chanx_left_in ( sb_0__12__0_chanx_right_out ) , + .chanx_right_in ( sb_1__12__0_chanx_left_out ) , + .ccff_head ( sb_1__12__0_ccff_tail ) , + .chanx_left_out ( cbx_1__12__0_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__0_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__0_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__0_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__0_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__0_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__0_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__0_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__0_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__0_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__0_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__0_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__0_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__0_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__0_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__0_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__0_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__0_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__0_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[0] ) , .SC_OUT_BOT ( scff_Wires[1] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7650 ) , + .pReset_E_in ( pResetWires[601] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7651 ) , + .pReset_W_out ( pResetWires[600] ) , .pReset_S_out ( pResetWires[602] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7652 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[59] ) , + .prog_clk_0_W_out ( prog_clk_0_wires[62] ) ) ; +cbx_1__2_ cbx_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7653 } ) , + .chanx_left_in ( sb_1__12__0_chanx_right_out ) , + .chanx_right_in ( sb_1__12__1_chanx_left_out ) , + .ccff_head ( sb_1__12__1_ccff_tail ) , + .chanx_left_out ( cbx_1__12__1_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__1_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__1_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__1_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__1_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__1_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__1_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__1_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__1_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__1_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__1_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__1_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__1_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__1_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__1_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__1_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__1_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__1_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__1_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7654 ) , + .SC_IN_BOT ( scff_Wires[51] ) , .SC_OUT_TOP ( scff_Wires[52] ) , + .pReset_E_in ( pResetWires[605] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7655 ) , + .pReset_W_out ( pResetWires[604] ) , .pReset_S_out ( pResetWires[606] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7656 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[99] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7657 ) ) ; +cbx_1__2_ cbx_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7658 } ) , + .chanx_left_in ( sb_1__12__1_chanx_right_out ) , + .chanx_right_in ( sb_1__12__2_chanx_left_out ) , + .ccff_head ( sb_1__12__2_ccff_tail ) , + .chanx_left_out ( cbx_1__12__2_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__2_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__2_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__2_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__2_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__2_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__2_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__2_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__2_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__2_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__2_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__2_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__2_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__2_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__2_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__2_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__2_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__2_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__2_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_2_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_2_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[53] ) , .SC_OUT_BOT ( scff_Wires[54] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7659 ) , + .pReset_E_in ( pResetWires[608] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7660 ) , + .pReset_W_out ( pResetWires[607] ) , .pReset_S_out ( pResetWires[609] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7661 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[137] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7662 ) ) ; +cbx_1__2_ cbx_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7663 } ) , + .chanx_left_in ( sb_1__12__2_chanx_right_out ) , + .chanx_right_in ( sb_1__12__3_chanx_left_out ) , + .ccff_head ( sb_1__12__3_ccff_tail ) , + .chanx_left_out ( cbx_1__12__3_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__3_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__3_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__3_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__3_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__3_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__3_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__3_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__3_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__3_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__3_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__3_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__3_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__3_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__3_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__3_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__3_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__3_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__3_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_3_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_3_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7664 ) , + .SC_IN_BOT ( scff_Wires[104] ) , .SC_OUT_TOP ( scff_Wires[105] ) , + .pReset_E_in ( pResetWires[611] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7665 ) , + .pReset_W_out ( pResetWires[610] ) , .pReset_S_out ( pResetWires[612] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7666 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[175] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7667 ) ) ; +cbx_1__2_ cbx_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7668 } ) , + .chanx_left_in ( sb_1__12__3_chanx_right_out ) , + .chanx_right_in ( sb_1__12__4_chanx_left_out ) , + .ccff_head ( sb_1__12__4_ccff_tail ) , + .chanx_left_out ( cbx_1__12__4_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__4_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__4_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__4_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__4_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__4_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__4_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__4_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__4_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__4_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__4_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__4_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__4_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__4_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__4_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__4_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__4_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__4_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__4_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_4_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_4_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[106] ) , .SC_OUT_BOT ( scff_Wires[107] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7669 ) , + .pReset_E_in ( pResetWires[614] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7670 ) , + .pReset_W_out ( pResetWires[613] ) , .pReset_S_out ( pResetWires[615] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7671 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[213] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7672 ) ) ; +cbx_1__2_ cbx_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7673 } ) , + .chanx_left_in ( sb_1__12__4_chanx_right_out ) , + .chanx_right_in ( sb_1__12__5_chanx_left_out ) , + .ccff_head ( sb_1__12__5_ccff_tail ) , + .chanx_left_out ( cbx_1__12__5_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__5_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__5_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__5_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__5_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__5_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__5_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__5_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__5_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__5_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__5_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__5_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__5_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__5_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__5_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__5_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__5_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__5_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__5_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_5_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_5_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7674 ) , + .SC_IN_BOT ( scff_Wires[157] ) , .SC_OUT_TOP ( scff_Wires[158] ) , + .pReset_E_in ( pResetWires[617] ) , + .pReset_W_in ( SYNOPSYS_UNCONNECTED_7675 ) , + .pReset_W_out ( pResetWires[616] ) , .pReset_S_out ( pResetWires[618] ) , + .pReset_E_out ( SYNOPSYS_UNCONNECTED_7676 ) , + .prog_clk_0_S_in ( prog_clk_0_wires[251] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7677 ) ) ; +cbx_1__2_ cbx_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7678 } ) , + .chanx_left_in ( sb_1__12__5_chanx_right_out ) , + .chanx_right_in ( sb_1__12__6_chanx_left_out ) , + .ccff_head ( sb_1__12__6_ccff_tail ) , + .chanx_left_out ( cbx_1__12__6_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__6_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__6_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__6_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__6_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__6_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__6_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__6_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__6_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__6_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__6_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__6_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__6_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__6_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__6_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__6_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__6_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__6_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__6_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_6_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_6_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[159] ) , .SC_OUT_BOT ( scff_Wires[160] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7679 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7680 ) , + .pReset_W_in ( pResetWires[619] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7681 ) , + .pReset_S_out ( pResetWires[621] ) , .pReset_E_out ( pResetWires[620] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[289] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7682 ) ) ; +cbx_1__2_ cbx_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7683 } ) , + .chanx_left_in ( sb_1__12__6_chanx_right_out ) , + .chanx_right_in ( sb_1__12__7_chanx_left_out ) , + .ccff_head ( sb_1__12__7_ccff_tail ) , + .chanx_left_out ( cbx_1__12__7_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__7_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__7_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__7_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__7_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__7_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__7_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__7_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__7_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__7_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__7_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__7_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__7_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__7_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__7_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__7_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__7_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__7_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__7_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_7_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_7_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7684 ) , + .SC_IN_BOT ( scff_Wires[210] ) , .SC_OUT_TOP ( scff_Wires[211] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7685 ) , + .pReset_W_in ( pResetWires[622] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7686 ) , + .pReset_S_out ( pResetWires[624] ) , .pReset_E_out ( pResetWires[623] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[327] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7687 ) ) ; +cbx_1__2_ cbx_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7688 } ) , + .chanx_left_in ( sb_1__12__7_chanx_right_out ) , + .chanx_right_in ( sb_1__12__8_chanx_left_out ) , + .ccff_head ( sb_1__12__8_ccff_tail ) , + .chanx_left_out ( cbx_1__12__8_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__8_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__8_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__8_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__8_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__8_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__8_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__8_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__8_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__8_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__8_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__8_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__8_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__8_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__8_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__8_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__8_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__8_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__8_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_8_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_8_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[212] ) , .SC_OUT_BOT ( scff_Wires[213] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7689 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7690 ) , + .pReset_W_in ( pResetWires[625] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7691 ) , + .pReset_S_out ( pResetWires[627] ) , .pReset_E_out ( pResetWires[626] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[365] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7692 ) ) ; +cbx_1__2_ cbx_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7693 } ) , + .chanx_left_in ( sb_1__12__8_chanx_right_out ) , + .chanx_right_in ( sb_1__12__9_chanx_left_out ) , + .ccff_head ( sb_1__12__9_ccff_tail ) , + .chanx_left_out ( cbx_1__12__9_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__9_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__9_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__9_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__9_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__9_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__9_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__9_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__9_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__9_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__9_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__9_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__9_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__9_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__9_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__9_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__9_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__9_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__9_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_9_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_9_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7694 ) , + .SC_IN_BOT ( scff_Wires[263] ) , .SC_OUT_TOP ( scff_Wires[264] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7695 ) , + .pReset_W_in ( pResetWires[628] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7696 ) , + .pReset_S_out ( pResetWires[630] ) , .pReset_E_out ( pResetWires[629] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[403] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7697 ) ) ; +cbx_1__2_ cbx_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7698 } ) , + .chanx_left_in ( sb_1__12__9_chanx_right_out ) , + .chanx_right_in ( sb_1__12__10_chanx_left_out ) , + .ccff_head ( sb_1__12__10_ccff_tail ) , + .chanx_left_out ( cbx_1__12__10_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__10_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__10_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__10_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__10_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__10_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__10_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__10_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__10_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__10_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__10_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__10_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__10_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__10_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__10_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__10_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__10_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__10_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__10_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_10_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_10_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( scff_Wires[265] ) , .SC_OUT_BOT ( scff_Wires[266] ) , + .SC_IN_BOT ( h_incr0 ) , .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_7699 ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7700 ) , + .pReset_W_in ( pResetWires[631] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7701 ) , + .pReset_S_out ( pResetWires[633] ) , .pReset_E_out ( pResetWires[632] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[441] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7702 ) ) ; +cbx_1__2_ cbx_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7703 } ) , + .chanx_left_in ( sb_1__12__10_chanx_right_out ) , + .chanx_right_in ( sb_12__12__0_chanx_left_out ) , + .ccff_head ( sb_12__12__0_ccff_tail ) , + .chanx_left_out ( cbx_1__12__11_chanx_left_out ) , + .chanx_right_out ( cbx_1__12__11_chanx_right_out ) , + .top_grid_pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , + .bottom_grid_pin_0_ ( cbx_1__12__11_bottom_grid_pin_0_ ) , + .bottom_grid_pin_1_ ( cbx_1__12__11_bottom_grid_pin_1_ ) , + .bottom_grid_pin_2_ ( cbx_1__12__11_bottom_grid_pin_2_ ) , + .bottom_grid_pin_3_ ( cbx_1__12__11_bottom_grid_pin_3_ ) , + .bottom_grid_pin_4_ ( cbx_1__12__11_bottom_grid_pin_4_ ) , + .bottom_grid_pin_5_ ( cbx_1__12__11_bottom_grid_pin_5_ ) , + .bottom_grid_pin_6_ ( cbx_1__12__11_bottom_grid_pin_6_ ) , + .bottom_grid_pin_7_ ( cbx_1__12__11_bottom_grid_pin_7_ ) , + .bottom_grid_pin_8_ ( cbx_1__12__11_bottom_grid_pin_8_ ) , + .bottom_grid_pin_9_ ( cbx_1__12__11_bottom_grid_pin_9_ ) , + .bottom_grid_pin_10_ ( cbx_1__12__11_bottom_grid_pin_10_ ) , + .bottom_grid_pin_11_ ( cbx_1__12__11_bottom_grid_pin_11_ ) , + .bottom_grid_pin_12_ ( cbx_1__12__11_bottom_grid_pin_12_ ) , + .bottom_grid_pin_13_ ( cbx_1__12__11_bottom_grid_pin_13_ ) , + .bottom_grid_pin_14_ ( cbx_1__12__11_bottom_grid_pin_14_ ) , + .bottom_grid_pin_15_ ( cbx_1__12__11_bottom_grid_pin_15_ ) , + .ccff_tail ( grid_io_top_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] ) , + .bottom_width_0_height_0__pin_0_ ( cbx_1__12__11_top_grid_pin_0_ ) , + .bottom_width_0_height_0__pin_1_upper ( grid_io_top_11_bottom_width_0_height_0__pin_1_upper ) , + .bottom_width_0_height_0__pin_1_lower ( grid_io_top_11_bottom_width_0_height_0__pin_1_lower ) , + .SC_IN_TOP ( h_incr0 ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_7704 ) , + .SC_IN_BOT ( scff_Wires[316] ) , .SC_OUT_TOP ( scff_Wires[317] ) , + .pReset_E_in ( SYNOPSYS_UNCONNECTED_7705 ) , + .pReset_W_in ( pResetWires[634] ) , + .pReset_W_out ( SYNOPSYS_UNCONNECTED_7706 ) , + .pReset_S_out ( pResetWires[636] ) , .pReset_E_out ( pResetWires[635] ) , + .prog_clk_0_S_in ( prog_clk_0_wires[479] ) , + .prog_clk_0_W_out ( SYNOPSYS_UNCONNECTED_7707 ) ) ; +cby_0__1_ cby_0__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7708 } ) , + .chany_bottom_in ( sb_0__0__0_chany_top_out ) , + .chany_top_in ( sb_0__1__0_chany_bottom_out ) , + .ccff_head ( sb_0__1__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__0_chany_bottom_out ) , + .chany_top_out ( cby_0__1__0_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[64] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[3] ) ) ; +cby_0__1_ cby_0__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7709 } ) , + .chany_bottom_in ( sb_0__1__0_chany_top_out ) , + .chany_top_in ( sb_0__1__1_chany_bottom_out ) , + .ccff_head ( sb_0__1__1_ccff_tail ) , + .chany_bottom_out ( cby_0__1__1_chany_bottom_out ) , + .chany_top_out ( cby_0__1__1_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[113] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[9] ) ) ; +cby_0__1_ cby_0__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7710 } ) , + .chany_bottom_in ( sb_0__1__1_chany_top_out ) , + .chany_top_in ( sb_0__1__2_chany_bottom_out ) , + .ccff_head ( sb_0__1__2_ccff_tail ) , + .chany_bottom_out ( cby_0__1__2_chany_bottom_out ) , + .chany_top_out ( cby_0__1__2_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__2_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_2_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_2_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[162] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[14] ) ) ; +cby_0__1_ cby_0__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7711 } ) , + .chany_bottom_in ( sb_0__1__2_chany_top_out ) , + .chany_top_in ( sb_0__1__3_chany_bottom_out ) , + .ccff_head ( sb_0__1__3_ccff_tail ) , + .chany_bottom_out ( cby_0__1__3_chany_bottom_out ) , + .chany_top_out ( cby_0__1__3_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__3_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_3_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_3_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[211] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[19] ) ) ; +cby_0__1_ cby_0__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7712 } ) , + .chany_bottom_in ( sb_0__1__3_chany_top_out ) , + .chany_top_in ( sb_0__1__4_chany_bottom_out ) , + .ccff_head ( sb_0__1__4_ccff_tail ) , + .chany_bottom_out ( cby_0__1__4_chany_bottom_out ) , + .chany_top_out ( cby_0__1__4_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__4_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_4_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_4_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[260] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[24] ) ) ; +cby_0__1_ cby_0__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7713 } ) , + .chany_bottom_in ( sb_0__1__4_chany_top_out ) , + .chany_top_in ( sb_0__1__5_chany_bottom_out ) , + .ccff_head ( sb_0__1__5_ccff_tail ) , + .chany_bottom_out ( cby_0__1__5_chany_bottom_out ) , + .chany_top_out ( cby_0__1__5_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__5_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_5_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_5_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[309] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[29] ) ) ; +cby_0__1_ cby_0__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7714 } ) , + .chany_bottom_in ( sb_0__1__5_chany_top_out ) , + .chany_top_in ( sb_0__1__6_chany_bottom_out ) , + .ccff_head ( sb_0__1__6_ccff_tail ) , + .chany_bottom_out ( cby_0__1__6_chany_bottom_out ) , + .chany_top_out ( cby_0__1__6_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__6_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_6_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_6_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[358] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[34] ) ) ; +cby_0__1_ cby_0__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7715 } ) , + .chany_bottom_in ( sb_0__1__6_chany_top_out ) , + .chany_top_in ( sb_0__1__7_chany_bottom_out ) , + .ccff_head ( sb_0__1__7_ccff_tail ) , + .chany_bottom_out ( cby_0__1__7_chany_bottom_out ) , + .chany_top_out ( cby_0__1__7_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__7_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_7_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_7_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[407] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[39] ) ) ; +cby_0__1_ cby_0__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7716 } ) , + .chany_bottom_in ( sb_0__1__7_chany_top_out ) , + .chany_top_in ( sb_0__1__8_chany_bottom_out ) , + .ccff_head ( sb_0__1__8_ccff_tail ) , + .chany_bottom_out ( cby_0__1__8_chany_bottom_out ) , + .chany_top_out ( cby_0__1__8_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__8_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_8_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_8_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[456] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[44] ) ) ; +cby_0__1_ cby_0__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7717 } ) , + .chany_bottom_in ( sb_0__1__8_chany_top_out ) , + .chany_top_in ( sb_0__1__9_chany_bottom_out ) , + .ccff_head ( sb_0__1__9_ccff_tail ) , + .chany_bottom_out ( cby_0__1__9_chany_bottom_out ) , + .chany_top_out ( cby_0__1__9_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__9_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_9_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_9_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[505] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[49] ) ) ; +cby_0__1_ cby_0__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7718 } ) , + .chany_bottom_in ( sb_0__1__9_chany_top_out ) , + .chany_top_in ( sb_0__1__10_chany_bottom_out ) , + .ccff_head ( sb_0__1__10_ccff_tail ) , + .chany_bottom_out ( cby_0__1__10_chany_bottom_out ) , + .chany_top_out ( cby_0__1__10_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__10_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_10_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_10_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[554] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[54] ) ) ; +cby_0__1_ cby_0__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7719 } ) , + .chany_bottom_in ( sb_0__1__10_chany_top_out ) , + .chany_top_in ( sb_0__12__0_chany_bottom_out ) , + .ccff_head ( sb_0__12__0_ccff_tail ) , + .chany_bottom_out ( cby_0__1__11_chany_bottom_out ) , + .chany_top_out ( cby_0__1__11_chany_top_out ) , + .left_grid_pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , + .ccff_tail ( grid_io_left_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] ) , + .right_width_0_height_0__pin_0_ ( cby_0__1__11_left_grid_pin_0_ ) , + .right_width_0_height_0__pin_1_upper ( grid_io_left_11_right_width_0_height_0__pin_1_upper ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_11_right_width_0_height_0__pin_1_lower ) , + .pReset_N_in ( pResetWires[603] ) , + .prog_clk_0_E_in ( prog_clk_0_wires[61] ) ) ; +cby_1__1_ cby_1__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7720 } ) , + .chany_bottom_in ( sb_1__0__0_chany_top_out ) , + .chany_top_in ( sb_1__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_0_ccff_tail ) , + .chany_bottom_out ( cby_1__1__0_chany_bottom_out ) , + .chany_top_out ( cby_1__1__0_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7721 ) , + .Test_en_E_in ( Test_enWires[26] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7722 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7723 ) , + .Test_en_W_out ( Test_enWires[24] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7724 ) , + .pReset_S_in ( pResetWires[27] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7725 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7726 ) , + .Reset_E_in ( ResetWires[26] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7727 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7728 ) , + .Reset_W_out ( ResetWires[24] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7729 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[1] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[2] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7730 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7731 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7732 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7733 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7734 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7735 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7736 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7737 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7738 ) ) ; +cby_1__1_ cby_1__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7739 } ) , + .chany_bottom_in ( sb_1__1__0_chany_top_out ) , + .chany_top_in ( sb_1__1__1_chany_bottom_out ) , + .ccff_head ( grid_clb_1_ccff_tail ) , + .chany_bottom_out ( cby_1__1__1_chany_bottom_out ) , + .chany_top_out ( cby_1__1__1_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7740 ) , + .Test_en_E_in ( Test_enWires[48] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7741 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7742 ) , + .Test_en_W_out ( Test_enWires[46] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7743 ) , + .pReset_S_in ( pResetWires[65] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7744 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7745 ) , + .Reset_E_in ( ResetWires[48] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7746 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7747 ) , + .Reset_W_out ( ResetWires[46] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7748 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[7] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[8] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7749 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[3] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7750 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[4] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7751 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7752 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7753 ) , + .clk_2_N_in ( clk_2_wires[3] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7754 ) , + .clk_2_S_out ( clk_2_wires[4] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7755 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7756 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7757 ) ) ; +cby_1__1_ cby_1__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7758 } ) , + .chany_bottom_in ( sb_1__1__1_chany_top_out ) , + .chany_top_in ( sb_1__1__2_chany_bottom_out ) , + .ccff_head ( grid_clb_2_ccff_tail ) , + .chany_bottom_out ( cby_1__1__2_chany_bottom_out ) , + .chany_top_out ( cby_1__1__2_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__2_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__2_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__2_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__2_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__2_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__2_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__2_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__2_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__2_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__2_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__2_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__2_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__2_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__2_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__2_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__2_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__2_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7759 ) , + .Test_en_E_in ( Test_enWires[70] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7760 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7761 ) , + .Test_en_W_out ( Test_enWires[68] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7762 ) , + .pReset_S_in ( pResetWires[114] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7763 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7764 ) , + .Reset_E_in ( ResetWires[70] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7765 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7766 ) , + .Reset_W_out ( ResetWires[68] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7767 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[12] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[13] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7768 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7769 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7770 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7771 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7772 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7773 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7774 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7775 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7776 ) ) ; +cby_1__1_ cby_1__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7777 } ) , + .chany_bottom_in ( sb_1__1__2_chany_top_out ) , + .chany_top_in ( sb_1__1__3_chany_bottom_out ) , + .ccff_head ( grid_clb_3_ccff_tail ) , + .chany_bottom_out ( cby_1__1__3_chany_bottom_out ) , + .chany_top_out ( cby_1__1__3_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__3_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__3_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__3_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__3_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__3_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__3_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__3_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__3_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__3_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__3_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__3_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__3_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__3_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__3_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__3_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__3_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__3_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7778 ) , + .Test_en_E_in ( Test_enWires[92] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7779 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7780 ) , + .Test_en_W_out ( Test_enWires[90] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7781 ) , + .pReset_S_in ( pResetWires[163] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7782 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7783 ) , + .Reset_E_in ( ResetWires[92] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7784 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7785 ) , + .Reset_W_out ( ResetWires[90] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7786 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[17] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[18] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7787 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[10] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7788 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[11] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7789 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7790 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7791 ) , + .clk_2_N_in ( clk_2_wires[10] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7792 ) , + .clk_2_S_out ( clk_2_wires[11] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7793 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7794 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7795 ) ) ; +cby_1__1_ cby_1__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7796 } ) , + .chany_bottom_in ( sb_1__1__3_chany_top_out ) , + .chany_top_in ( sb_1__1__4_chany_bottom_out ) , + .ccff_head ( grid_clb_4_ccff_tail ) , + .chany_bottom_out ( cby_1__1__4_chany_bottom_out ) , + .chany_top_out ( cby_1__1__4_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__4_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__4_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__4_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__4_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__4_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__4_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__4_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__4_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__4_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__4_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__4_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__4_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__4_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__4_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__4_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__4_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__4_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7797 ) , + .Test_en_E_in ( Test_enWires[114] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7798 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7799 ) , + .Test_en_W_out ( Test_enWires[112] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7800 ) , + .pReset_S_in ( pResetWires[212] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7801 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7802 ) , + .Reset_E_in ( ResetWires[114] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7803 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7804 ) , + .Reset_W_out ( ResetWires[112] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7805 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[22] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[23] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7806 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7807 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[8] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7808 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[9] ) , .prog_clk_3_S_in ( h_incr0 ) , + .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7809 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7810 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7811 ) , + .clk_2_S_in ( clk_2_wires[8] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7812 ) , + .clk_2_N_out ( clk_2_wires[9] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7813 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7814 ) ) ; +cby_1__1_ cby_1__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7815 } ) , + .chany_bottom_in ( sb_1__1__4_chany_top_out ) , + .chany_top_in ( sb_1__1__5_chany_bottom_out ) , + .ccff_head ( grid_clb_5_ccff_tail ) , + .chany_bottom_out ( cby_1__1__5_chany_bottom_out ) , + .chany_top_out ( cby_1__1__5_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__5_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__5_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__5_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__5_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__5_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__5_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__5_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__5_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__5_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__5_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__5_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__5_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__5_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__5_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__5_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__5_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__5_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7816 ) , + .Test_en_E_in ( Test_enWires[136] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7817 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7818 ) , + .Test_en_W_out ( Test_enWires[134] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7819 ) , + .pReset_S_in ( pResetWires[261] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7820 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7821 ) , + .Reset_E_in ( ResetWires[136] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7822 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7823 ) , + .Reset_W_out ( ResetWires[134] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7824 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[27] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[28] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7825 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7826 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7827 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7828 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7829 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7830 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7831 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7832 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7833 ) ) ; +cby_1__1_ cby_1__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7834 } ) , + .chany_bottom_in ( sb_1__1__5_chany_top_out ) , + .chany_top_in ( sb_1__1__6_chany_bottom_out ) , + .ccff_head ( grid_clb_6_ccff_tail ) , + .chany_bottom_out ( cby_1__1__6_chany_bottom_out ) , + .chany_top_out ( cby_1__1__6_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__6_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__6_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__6_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__6_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__6_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__6_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__6_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__6_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__6_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__6_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__6_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__6_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__6_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__6_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__6_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__6_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__6_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7835 ) , + .Test_en_E_in ( Test_enWires[158] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7836 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7837 ) , + .Test_en_W_out ( Test_enWires[156] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7838 ) , + .pReset_S_in ( pResetWires[310] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7839 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7840 ) , + .Reset_E_in ( ResetWires[158] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7841 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7842 ) , + .Reset_W_out ( ResetWires[156] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7843 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[32] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[33] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7844 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7845 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7846 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7847 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7848 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7849 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7850 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7851 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7852 ) ) ; +cby_1__1_ cby_1__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7853 } ) , + .chany_bottom_in ( sb_1__1__6_chany_top_out ) , + .chany_top_in ( sb_1__1__7_chany_bottom_out ) , + .ccff_head ( grid_clb_7_ccff_tail ) , + .chany_bottom_out ( cby_1__1__7_chany_bottom_out ) , + .chany_top_out ( cby_1__1__7_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__7_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__7_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__7_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__7_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__7_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__7_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__7_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__7_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__7_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__7_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__7_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__7_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__7_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__7_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__7_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__7_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__7_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7854 ) , + .Test_en_E_in ( Test_enWires[180] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7855 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7856 ) , + .Test_en_W_out ( Test_enWires[178] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7857 ) , + .pReset_S_in ( pResetWires[359] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7858 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7859 ) , + .Reset_E_in ( ResetWires[180] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7860 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7861 ) , + .Reset_W_out ( ResetWires[178] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7862 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[37] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[38] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7863 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[17] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_7864 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[18] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7865 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7866 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7867 ) , + .clk_2_N_in ( clk_2_wires[17] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_7868 ) , + .clk_2_S_out ( clk_2_wires[18] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7869 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7870 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7871 ) ) ; +cby_1__1_ cby_1__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7872 } ) , + .chany_bottom_in ( sb_1__1__7_chany_top_out ) , + .chany_top_in ( sb_1__1__8_chany_bottom_out ) , + .ccff_head ( grid_clb_8_ccff_tail ) , + .chany_bottom_out ( cby_1__1__8_chany_bottom_out ) , + .chany_top_out ( cby_1__1__8_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__8_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__8_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__8_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__8_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__8_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__8_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__8_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__8_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__8_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__8_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__8_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__8_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__8_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__8_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__8_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__8_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__8_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7873 ) , + .Test_en_E_in ( Test_enWires[202] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7874 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7875 ) , + .Test_en_W_out ( Test_enWires[200] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7876 ) , + .pReset_S_in ( pResetWires[408] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7877 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7878 ) , + .Reset_E_in ( ResetWires[202] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7879 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7880 ) , + .Reset_W_out ( ResetWires[200] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7881 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[42] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[43] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7882 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7883 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[15] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7884 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[16] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7885 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7886 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7887 ) , + .clk_2_S_in ( clk_2_wires[15] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7888 ) , + .clk_2_N_out ( clk_2_wires[16] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7889 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7890 ) ) ; +cby_1__1_ cby_1__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7891 } ) , + .chany_bottom_in ( sb_1__1__8_chany_top_out ) , + .chany_top_in ( sb_1__1__9_chany_bottom_out ) , + .ccff_head ( grid_clb_9_ccff_tail ) , + .chany_bottom_out ( cby_1__1__9_chany_bottom_out ) , + .chany_top_out ( cby_1__1__9_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__9_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__9_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__9_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__9_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__9_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__9_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__9_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__9_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__9_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__9_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__9_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__9_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__9_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__9_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__9_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__9_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__9_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7892 ) , + .Test_en_E_in ( Test_enWires[224] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7893 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7894 ) , + .Test_en_W_out ( Test_enWires[222] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7895 ) , + .pReset_S_in ( pResetWires[457] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7896 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7897 ) , + .Reset_E_in ( ResetWires[224] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7898 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7899 ) , + .Reset_W_out ( ResetWires[222] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7900 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[47] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[48] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7901 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7902 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7903 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7904 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7905 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7906 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7907 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7908 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7909 ) ) ; +cby_1__1_ cby_1__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7910 } ) , + .chany_bottom_in ( sb_1__1__9_chany_top_out ) , + .chany_top_in ( sb_1__1__10_chany_bottom_out ) , + .ccff_head ( grid_clb_10_ccff_tail ) , + .chany_bottom_out ( cby_1__1__10_chany_bottom_out ) , + .chany_top_out ( cby_1__1__10_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__10_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__10_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__10_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__10_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__10_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__10_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__10_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__10_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__10_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__10_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__10_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__10_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__10_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__10_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__10_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__10_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__10_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7911 ) , + .Test_en_E_in ( Test_enWires[246] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7912 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7913 ) , + .Test_en_W_out ( Test_enWires[244] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7914 ) , + .pReset_S_in ( pResetWires[506] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7915 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7916 ) , + .Reset_E_in ( ResetWires[246] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7917 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7918 ) , + .Reset_W_out ( ResetWires[244] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7919 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[52] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[53] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7920 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_7921 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[22] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7922 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[23] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7923 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7924 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_7925 ) , + .clk_2_S_in ( clk_2_wires[22] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7926 ) , + .clk_2_N_out ( clk_2_wires[23] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7927 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7928 ) ) ; +cby_1__1_ cby_1__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7929 } ) , + .chany_bottom_in ( sb_1__1__10_chany_top_out ) , + .chany_top_in ( sb_1__12__0_chany_bottom_out ) , + .ccff_head ( grid_clb_11_ccff_tail ) , + .chany_bottom_out ( cby_1__1__11_chany_bottom_out ) , + .chany_top_out ( cby_1__1__11_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__11_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__11_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__11_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__11_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__11_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__11_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__11_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__11_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__11_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__11_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__11_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__11_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__11_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__11_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__11_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__11_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__11_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7930 ) , + .Test_en_E_in ( Test_enWires[268] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7931 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7932 ) , + .Test_en_W_out ( Test_enWires[266] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7933 ) , + .pReset_S_in ( pResetWires[555] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7934 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7935 ) , + .Reset_E_in ( ResetWires[268] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7936 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7937 ) , + .Reset_W_out ( ResetWires[266] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7938 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[57] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[58] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[60] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7939 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7940 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7941 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7942 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7943 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7944 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7945 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7946 ) ) ; +cby_1__1_ cby_2__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7947 } ) , + .chany_bottom_in ( sb_1__0__1_chany_top_out ) , + .chany_top_in ( sb_1__1__11_chany_bottom_out ) , + .ccff_head ( grid_clb_12_ccff_tail ) , + .chany_bottom_out ( cby_1__1__12_chany_bottom_out ) , + .chany_top_out ( cby_1__1__12_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__12_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__12_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__12_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__12_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__12_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__12_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__12_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__12_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__12_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__12_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__12_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__12_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__12_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__12_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__12_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__12_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__12_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7948 ) , + .Test_en_E_in ( Test_enWires[28] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7949 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7950 ) , + .Test_en_W_out ( Test_enWires[25] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7951 ) , + .pReset_S_in ( pResetWires[30] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7952 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7953 ) , + .Reset_E_in ( ResetWires[28] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7954 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7955 ) , + .Reset_W_out ( ResetWires[25] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7956 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[64] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[65] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7957 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7958 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7959 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7960 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7961 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7962 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7963 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7964 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7965 ) ) ; +cby_1__1_ cby_2__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7966 } ) , + .chany_bottom_in ( sb_1__1__11_chany_top_out ) , + .chany_top_in ( sb_1__1__12_chany_bottom_out ) , + .ccff_head ( grid_clb_13_ccff_tail ) , + .chany_bottom_out ( cby_1__1__13_chany_bottom_out ) , + .chany_top_out ( cby_1__1__13_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__13_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__13_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__13_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__13_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__13_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__13_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__13_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__13_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__13_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__13_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__13_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__13_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__13_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__13_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__13_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__13_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__13_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7967 ) , + .Test_en_E_in ( Test_enWires[50] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7968 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7969 ) , + .Test_en_W_out ( Test_enWires[47] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7970 ) , + .pReset_S_in ( pResetWires[69] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7971 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7972 ) , + .Reset_E_in ( ResetWires[50] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7973 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7974 ) , + .Reset_W_out ( ResetWires[47] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7975 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[67] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[68] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7976 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7977 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7978 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7979 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_7980 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_7981 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_7982 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_7983 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_7984 ) ) ; +cby_1__1_ cby_2__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_7985 } ) , + .chany_bottom_in ( sb_1__1__12_chany_top_out ) , + .chany_top_in ( sb_1__1__13_chany_bottom_out ) , + .ccff_head ( grid_clb_14_ccff_tail ) , + .chany_bottom_out ( cby_1__1__14_chany_bottom_out ) , + .chany_top_out ( cby_1__1__14_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__14_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__14_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__14_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__14_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__14_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__14_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__14_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__14_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__14_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__14_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__14_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__14_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__14_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__14_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__14_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__14_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__14_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_7986 ) , + .Test_en_E_in ( Test_enWires[72] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_7987 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_7988 ) , + .Test_en_W_out ( Test_enWires[69] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_7989 ) , + .pReset_S_in ( pResetWires[118] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_7990 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_7991 ) , + .Reset_E_in ( ResetWires[72] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_7992 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_7993 ) , + .Reset_W_out ( ResetWires[69] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_7994 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[70] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[71] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_7995 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_7996 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_7997 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_7998 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[68] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_7999 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[69] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8000 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8001 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8002 ) , + .clk_3_N_in ( clk_3_wires[68] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8003 ) , + .clk_3_S_out ( clk_3_wires[69] ) ) ; +cby_1__1_ cby_2__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8004 } ) , + .chany_bottom_in ( sb_1__1__13_chany_top_out ) , + .chany_top_in ( sb_1__1__14_chany_bottom_out ) , + .ccff_head ( grid_clb_15_ccff_tail ) , + .chany_bottom_out ( cby_1__1__15_chany_bottom_out ) , + .chany_top_out ( cby_1__1__15_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__15_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__15_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__15_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__15_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__15_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__15_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__15_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__15_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__15_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__15_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__15_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__15_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__15_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__15_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__15_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__15_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__15_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8005 ) , + .Test_en_E_in ( Test_enWires[94] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8006 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8007 ) , + .Test_en_W_out ( Test_enWires[91] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8008 ) , + .pReset_S_in ( pResetWires[167] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8009 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8010 ) , + .Reset_E_in ( ResetWires[94] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8011 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8012 ) , + .Reset_W_out ( ResetWires[91] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8013 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[73] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[74] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8014 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8015 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8016 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8017 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[64] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8018 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[65] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8019 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8020 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8021 ) , + .clk_3_N_in ( clk_3_wires[64] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8022 ) , + .clk_3_S_out ( clk_3_wires[65] ) ) ; +cby_1__1_ cby_2__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8023 } ) , + .chany_bottom_in ( sb_1__1__14_chany_top_out ) , + .chany_top_in ( sb_1__1__15_chany_bottom_out ) , + .ccff_head ( grid_clb_16_ccff_tail ) , + .chany_bottom_out ( cby_1__1__16_chany_bottom_out ) , + .chany_top_out ( cby_1__1__16_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__16_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__16_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__16_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__16_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__16_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__16_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__16_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__16_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__16_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__16_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__16_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__16_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__16_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__16_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__16_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__16_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__16_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8024 ) , + .Test_en_E_in ( Test_enWires[116] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8025 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8026 ) , + .Test_en_W_out ( Test_enWires[113] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8027 ) , + .pReset_S_in ( pResetWires[216] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8028 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8029 ) , + .Reset_E_in ( ResetWires[116] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8030 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8031 ) , + .Reset_W_out ( ResetWires[113] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8032 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[76] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[77] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8033 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8034 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8035 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8036 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[58] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8037 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[59] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8038 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8039 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8040 ) , + .clk_3_N_in ( clk_3_wires[58] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8041 ) , + .clk_3_S_out ( clk_3_wires[59] ) ) ; +cby_1__1_ cby_2__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8042 } ) , + .chany_bottom_in ( sb_1__1__15_chany_top_out ) , + .chany_top_in ( sb_1__1__16_chany_bottom_out ) , + .ccff_head ( grid_clb_17_ccff_tail ) , + .chany_bottom_out ( cby_1__1__17_chany_bottom_out ) , + .chany_top_out ( cby_1__1__17_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__17_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__17_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__17_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__17_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__17_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__17_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__17_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__17_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__17_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__17_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__17_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__17_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__17_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__17_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__17_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__17_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__17_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8043 ) , + .Test_en_E_in ( Test_enWires[138] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8044 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8045 ) , + .Test_en_W_out ( Test_enWires[135] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8046 ) , + .pReset_S_in ( pResetWires[265] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8047 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8048 ) , + .Reset_E_in ( ResetWires[138] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8049 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8050 ) , + .Reset_W_out ( ResetWires[135] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8051 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[79] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[80] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8052 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8053 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8054 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8055 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[54] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8056 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[55] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8057 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8058 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8059 ) , + .clk_3_N_in ( clk_3_wires[54] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8060 ) , + .clk_3_S_out ( clk_3_wires[55] ) ) ; +cby_1__1_ cby_2__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8061 } ) , + .chany_bottom_in ( sb_1__1__16_chany_top_out ) , + .chany_top_in ( sb_1__1__17_chany_bottom_out ) , + .ccff_head ( grid_clb_18_ccff_tail ) , + .chany_bottom_out ( cby_1__1__18_chany_bottom_out ) , + .chany_top_out ( cby_1__1__18_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__18_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__18_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__18_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__18_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__18_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__18_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__18_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__18_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__18_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__18_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__18_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__18_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__18_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__18_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__18_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__18_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__18_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8062 ) , + .Test_en_E_in ( Test_enWires[160] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8063 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8064 ) , + .Test_en_W_out ( Test_enWires[157] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8065 ) , + .pReset_S_in ( pResetWires[314] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8066 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8067 ) , + .Reset_E_in ( ResetWires[160] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8068 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8069 ) , + .Reset_W_out ( ResetWires[157] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8070 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[82] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[83] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8071 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8072 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8073 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[52] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8074 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[53] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8075 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8076 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8077 ) , + .clk_3_S_in ( clk_3_wires[52] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8078 ) , + .clk_3_N_out ( clk_3_wires[53] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8079 ) ) ; +cby_1__1_ cby_2__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8080 } ) , + .chany_bottom_in ( sb_1__1__17_chany_top_out ) , + .chany_top_in ( sb_1__1__18_chany_bottom_out ) , + .ccff_head ( grid_clb_19_ccff_tail ) , + .chany_bottom_out ( cby_1__1__19_chany_bottom_out ) , + .chany_top_out ( cby_1__1__19_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__19_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__19_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__19_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__19_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__19_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__19_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__19_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__19_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__19_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__19_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__19_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__19_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__19_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__19_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__19_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__19_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__19_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8081 ) , + .Test_en_E_in ( Test_enWires[182] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8082 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8083 ) , + .Test_en_W_out ( Test_enWires[179] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8084 ) , + .pReset_S_in ( pResetWires[363] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8085 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8086 ) , + .Reset_E_in ( ResetWires[182] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8087 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8088 ) , + .Reset_W_out ( ResetWires[179] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8089 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[85] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[86] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8090 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8091 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8092 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[56] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8093 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[57] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8094 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8095 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8096 ) , + .clk_3_S_in ( clk_3_wires[56] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8097 ) , + .clk_3_N_out ( clk_3_wires[57] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8098 ) ) ; +cby_1__1_ cby_2__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8099 } ) , + .chany_bottom_in ( sb_1__1__18_chany_top_out ) , + .chany_top_in ( sb_1__1__19_chany_bottom_out ) , + .ccff_head ( grid_clb_20_ccff_tail ) , + .chany_bottom_out ( cby_1__1__20_chany_bottom_out ) , + .chany_top_out ( cby_1__1__20_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__20_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__20_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__20_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__20_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__20_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__20_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__20_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__20_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__20_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__20_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__20_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__20_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__20_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__20_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__20_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__20_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__20_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8100 ) , + .Test_en_E_in ( Test_enWires[204] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8101 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8102 ) , + .Test_en_W_out ( Test_enWires[201] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8103 ) , + .pReset_S_in ( pResetWires[412] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8104 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8105 ) , + .Reset_E_in ( ResetWires[204] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8106 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8107 ) , + .Reset_W_out ( ResetWires[201] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8108 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[88] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[89] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8109 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8110 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8111 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[62] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8112 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[63] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8113 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8114 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8115 ) , + .clk_3_S_in ( clk_3_wires[62] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8116 ) , + .clk_3_N_out ( clk_3_wires[63] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8117 ) ) ; +cby_1__1_ cby_2__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8118 } ) , + .chany_bottom_in ( sb_1__1__19_chany_top_out ) , + .chany_top_in ( sb_1__1__20_chany_bottom_out ) , + .ccff_head ( grid_clb_21_ccff_tail ) , + .chany_bottom_out ( cby_1__1__21_chany_bottom_out ) , + .chany_top_out ( cby_1__1__21_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__21_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__21_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__21_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__21_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__21_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__21_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__21_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__21_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__21_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__21_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__21_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__21_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__21_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__21_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__21_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__21_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__21_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8119 ) , + .Test_en_E_in ( Test_enWires[226] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8120 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8121 ) , + .Test_en_W_out ( Test_enWires[223] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8122 ) , + .pReset_S_in ( pResetWires[461] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8123 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8124 ) , + .Reset_E_in ( ResetWires[226] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8125 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8126 ) , + .Reset_W_out ( ResetWires[223] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8127 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[91] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[92] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8128 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8129 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8130 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[66] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8131 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[67] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8132 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8133 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8134 ) , + .clk_3_S_in ( clk_3_wires[66] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8135 ) , + .clk_3_N_out ( clk_3_wires[67] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8136 ) ) ; +cby_1__1_ cby_2__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8137 } ) , + .chany_bottom_in ( sb_1__1__20_chany_top_out ) , + .chany_top_in ( sb_1__1__21_chany_bottom_out ) , + .ccff_head ( grid_clb_22_ccff_tail ) , + .chany_bottom_out ( cby_1__1__22_chany_bottom_out ) , + .chany_top_out ( cby_1__1__22_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__22_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__22_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__22_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__22_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__22_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__22_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__22_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__22_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__22_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__22_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__22_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__22_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__22_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__22_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__22_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__22_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__22_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8138 ) , + .Test_en_E_in ( Test_enWires[248] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8139 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8140 ) , + .Test_en_W_out ( Test_enWires[245] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8141 ) , + .pReset_S_in ( pResetWires[510] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8142 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8143 ) , + .Reset_E_in ( ResetWires[248] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8144 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8145 ) , + .Reset_W_out ( ResetWires[245] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8146 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[94] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[95] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8147 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8148 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8149 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8150 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8151 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8152 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8153 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8154 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8155 ) ) ; +cby_1__1_ cby_2__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8156 } ) , + .chany_bottom_in ( sb_1__1__21_chany_top_out ) , + .chany_top_in ( sb_1__12__1_chany_bottom_out ) , + .ccff_head ( grid_clb_23_ccff_tail ) , + .chany_bottom_out ( cby_1__1__23_chany_bottom_out ) , + .chany_top_out ( cby_1__1__23_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__23_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__23_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__23_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__23_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__23_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__23_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__23_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__23_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__23_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__23_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__23_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__23_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__23_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__23_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__23_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__23_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__23_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8157 ) , + .Test_en_E_in ( Test_enWires[270] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8158 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8159 ) , + .Test_en_W_out ( Test_enWires[267] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8160 ) , + .pReset_S_in ( pResetWires[559] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8161 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8162 ) , + .Reset_E_in ( ResetWires[270] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8163 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8164 ) , + .Reset_W_out ( ResetWires[267] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8165 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[97] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[98] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[100] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8166 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8167 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8168 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8169 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8170 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8171 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8172 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8173 ) ) ; +cby_1__1_ cby_3__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8174 } ) , + .chany_bottom_in ( sb_1__0__2_chany_top_out ) , + .chany_top_in ( sb_1__1__22_chany_bottom_out ) , + .ccff_head ( grid_clb_24_ccff_tail ) , + .chany_bottom_out ( cby_1__1__24_chany_bottom_out ) , + .chany_top_out ( cby_1__1__24_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__24_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__24_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__24_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__24_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__24_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__24_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__24_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__24_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__24_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__24_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__24_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__24_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__24_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__24_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__24_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__24_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__24_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8175 ) , + .Test_en_E_in ( Test_enWires[30] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8176 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8177 ) , + .Test_en_W_out ( Test_enWires[27] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8178 ) , + .pReset_S_in ( pResetWires[33] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8179 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8180 ) , + .Reset_E_in ( ResetWires[30] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8181 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8182 ) , + .Reset_W_out ( ResetWires[27] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8183 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[102] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[103] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8184 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8185 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8186 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8187 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8188 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8189 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8190 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8191 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8192 ) ) ; +cby_1__1_ cby_3__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8193 } ) , + .chany_bottom_in ( sb_1__1__22_chany_top_out ) , + .chany_top_in ( sb_1__1__23_chany_bottom_out ) , + .ccff_head ( grid_clb_25_ccff_tail ) , + .chany_bottom_out ( cby_1__1__25_chany_bottom_out ) , + .chany_top_out ( cby_1__1__25_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__25_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__25_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__25_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__25_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__25_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__25_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__25_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__25_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__25_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__25_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__25_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__25_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__25_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__25_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__25_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__25_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__25_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8194 ) , + .Test_en_E_in ( Test_enWires[52] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8195 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8196 ) , + .Test_en_W_out ( Test_enWires[49] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8197 ) , + .pReset_S_in ( pResetWires[73] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8198 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8199 ) , + .Reset_E_in ( ResetWires[52] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8200 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8201 ) , + .Reset_W_out ( ResetWires[49] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8202 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[105] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[106] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8203 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[29] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8204 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[30] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8205 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8206 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8207 ) , + .clk_2_N_in ( clk_2_wires[29] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8208 ) , + .clk_2_S_out ( clk_2_wires[30] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8209 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8210 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8211 ) ) ; +cby_1__1_ cby_3__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8212 } ) , + .chany_bottom_in ( sb_1__1__23_chany_top_out ) , + .chany_top_in ( sb_1__1__24_chany_bottom_out ) , + .ccff_head ( grid_clb_26_ccff_tail ) , + .chany_bottom_out ( cby_1__1__26_chany_bottom_out ) , + .chany_top_out ( cby_1__1__26_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__26_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__26_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__26_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__26_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__26_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__26_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__26_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__26_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__26_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__26_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__26_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__26_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__26_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__26_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__26_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__26_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__26_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8213 ) , + .Test_en_E_in ( Test_enWires[74] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8214 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8215 ) , + .Test_en_W_out ( Test_enWires[71] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8216 ) , + .pReset_S_in ( pResetWires[122] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8217 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8218 ) , + .Reset_E_in ( ResetWires[74] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8219 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8220 ) , + .Reset_W_out ( ResetWires[71] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8221 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[108] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[109] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8222 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8223 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8224 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8225 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8226 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8227 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8228 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8229 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8230 ) ) ; +cby_1__1_ cby_3__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8231 } ) , + .chany_bottom_in ( sb_1__1__24_chany_top_out ) , + .chany_top_in ( sb_1__1__25_chany_bottom_out ) , + .ccff_head ( grid_clb_27_ccff_tail ) , + .chany_bottom_out ( cby_1__1__27_chany_bottom_out ) , + .chany_top_out ( cby_1__1__27_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__27_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__27_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__27_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__27_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__27_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__27_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__27_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__27_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__27_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__27_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__27_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__27_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__27_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__27_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__27_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__27_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__27_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8232 ) , + .Test_en_E_in ( Test_enWires[96] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8233 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8234 ) , + .Test_en_W_out ( Test_enWires[93] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8235 ) , + .pReset_S_in ( pResetWires[171] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8236 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8237 ) , + .Reset_E_in ( ResetWires[96] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8238 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8239 ) , + .Reset_W_out ( ResetWires[93] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8240 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[111] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[112] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8241 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[40] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8242 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[41] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8243 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8244 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8245 ) , + .clk_2_N_in ( clk_2_wires[40] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8246 ) , + .clk_2_S_out ( clk_2_wires[41] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8247 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8248 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8249 ) ) ; +cby_1__1_ cby_3__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8250 } ) , + .chany_bottom_in ( sb_1__1__25_chany_top_out ) , + .chany_top_in ( sb_1__1__26_chany_bottom_out ) , + .ccff_head ( grid_clb_28_ccff_tail ) , + .chany_bottom_out ( cby_1__1__28_chany_bottom_out ) , + .chany_top_out ( cby_1__1__28_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__28_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__28_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__28_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__28_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__28_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__28_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__28_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__28_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__28_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__28_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__28_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__28_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__28_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__28_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__28_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__28_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__28_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8251 ) , + .Test_en_E_in ( Test_enWires[118] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8252 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8253 ) , + .Test_en_W_out ( Test_enWires[115] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8254 ) , + .pReset_S_in ( pResetWires[220] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8255 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8256 ) , + .Reset_E_in ( ResetWires[118] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8257 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8258 ) , + .Reset_W_out ( ResetWires[115] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8259 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[114] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[115] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8260 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8261 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[38] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8262 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[39] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8263 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8264 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8265 ) , + .clk_2_S_in ( clk_2_wires[38] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8266 ) , + .clk_2_N_out ( clk_2_wires[39] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8267 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8268 ) ) ; +cby_1__1_ cby_3__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8269 } ) , + .chany_bottom_in ( sb_1__1__26_chany_top_out ) , + .chany_top_in ( sb_1__1__27_chany_bottom_out ) , + .ccff_head ( grid_clb_29_ccff_tail ) , + .chany_bottom_out ( cby_1__1__29_chany_bottom_out ) , + .chany_top_out ( cby_1__1__29_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__29_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__29_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__29_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__29_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__29_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__29_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__29_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__29_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__29_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__29_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__29_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__29_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__29_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__29_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__29_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__29_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__29_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8270 ) , + .Test_en_E_in ( Test_enWires[140] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8271 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8272 ) , + .Test_en_W_out ( Test_enWires[137] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8273 ) , + .pReset_S_in ( pResetWires[269] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8274 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8275 ) , + .Reset_E_in ( ResetWires[140] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8276 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8277 ) , + .Reset_W_out ( ResetWires[137] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8278 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[117] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[118] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8279 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8280 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8281 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8282 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8283 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8284 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8285 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8286 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8287 ) ) ; +cby_1__1_ cby_3__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8288 } ) , + .chany_bottom_in ( sb_1__1__27_chany_top_out ) , + .chany_top_in ( sb_1__1__28_chany_bottom_out ) , + .ccff_head ( grid_clb_30_ccff_tail ) , + .chany_bottom_out ( cby_1__1__30_chany_bottom_out ) , + .chany_top_out ( cby_1__1__30_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__30_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__30_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__30_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__30_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__30_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__30_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__30_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__30_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__30_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__30_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__30_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__30_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__30_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__30_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__30_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__30_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__30_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8289 ) , + .Test_en_E_in ( Test_enWires[162] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8290 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8291 ) , + .Test_en_W_out ( Test_enWires[159] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8292 ) , + .pReset_S_in ( pResetWires[318] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8293 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8294 ) , + .Reset_E_in ( ResetWires[162] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8295 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8296 ) , + .Reset_W_out ( ResetWires[159] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8297 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[120] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[121] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8298 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8299 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8300 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8301 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8302 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8303 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8304 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8305 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8306 ) ) ; +cby_1__1_ cby_3__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8307 } ) , + .chany_bottom_in ( sb_1__1__28_chany_top_out ) , + .chany_top_in ( sb_1__1__29_chany_bottom_out ) , + .ccff_head ( grid_clb_31_ccff_tail ) , + .chany_bottom_out ( cby_1__1__31_chany_bottom_out ) , + .chany_top_out ( cby_1__1__31_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__31_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__31_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__31_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__31_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__31_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__31_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__31_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__31_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__31_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__31_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__31_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__31_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__31_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__31_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__31_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__31_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__31_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8308 ) , + .Test_en_E_in ( Test_enWires[184] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8309 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8310 ) , + .Test_en_W_out ( Test_enWires[181] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8311 ) , + .pReset_S_in ( pResetWires[367] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8312 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8313 ) , + .Reset_E_in ( ResetWires[184] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8314 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8315 ) , + .Reset_W_out ( ResetWires[181] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8316 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[123] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[124] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8317 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[53] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8318 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[54] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8319 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8320 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8321 ) , + .clk_2_N_in ( clk_2_wires[53] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8322 ) , + .clk_2_S_out ( clk_2_wires[54] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8323 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8324 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8325 ) ) ; +cby_1__1_ cby_3__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8326 } ) , + .chany_bottom_in ( sb_1__1__29_chany_top_out ) , + .chany_top_in ( sb_1__1__30_chany_bottom_out ) , + .ccff_head ( grid_clb_32_ccff_tail ) , + .chany_bottom_out ( cby_1__1__32_chany_bottom_out ) , + .chany_top_out ( cby_1__1__32_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__32_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__32_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__32_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__32_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__32_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__32_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__32_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__32_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__32_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__32_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__32_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__32_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__32_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__32_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__32_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__32_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__32_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8327 ) , + .Test_en_E_in ( Test_enWires[206] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8328 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8329 ) , + .Test_en_W_out ( Test_enWires[203] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8330 ) , + .pReset_S_in ( pResetWires[416] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8331 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8332 ) , + .Reset_E_in ( ResetWires[206] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8333 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8334 ) , + .Reset_W_out ( ResetWires[203] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8335 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[126] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[127] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8336 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8337 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[51] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8338 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[52] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8339 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8340 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8341 ) , + .clk_2_S_in ( clk_2_wires[51] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8342 ) , + .clk_2_N_out ( clk_2_wires[52] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8343 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8344 ) ) ; +cby_1__1_ cby_3__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8345 } ) , + .chany_bottom_in ( sb_1__1__30_chany_top_out ) , + .chany_top_in ( sb_1__1__31_chany_bottom_out ) , + .ccff_head ( grid_clb_33_ccff_tail ) , + .chany_bottom_out ( cby_1__1__33_chany_bottom_out ) , + .chany_top_out ( cby_1__1__33_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__33_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__33_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__33_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__33_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__33_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__33_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__33_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__33_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__33_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__33_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__33_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__33_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__33_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__33_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__33_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__33_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__33_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8346 ) , + .Test_en_E_in ( Test_enWires[228] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8347 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8348 ) , + .Test_en_W_out ( Test_enWires[225] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8349 ) , + .pReset_S_in ( pResetWires[465] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8350 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8351 ) , + .Reset_E_in ( ResetWires[228] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8352 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8353 ) , + .Reset_W_out ( ResetWires[225] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8354 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[129] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[130] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8355 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8356 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8357 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8358 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8359 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8360 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8361 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8362 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8363 ) ) ; +cby_1__1_ cby_3__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8364 } ) , + .chany_bottom_in ( sb_1__1__31_chany_top_out ) , + .chany_top_in ( sb_1__1__32_chany_bottom_out ) , + .ccff_head ( grid_clb_34_ccff_tail ) , + .chany_bottom_out ( cby_1__1__34_chany_bottom_out ) , + .chany_top_out ( cby_1__1__34_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__34_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__34_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__34_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__34_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__34_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__34_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__34_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__34_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__34_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__34_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__34_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__34_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__34_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__34_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__34_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__34_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__34_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8365 ) , + .Test_en_E_in ( Test_enWires[250] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8366 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8367 ) , + .Test_en_W_out ( Test_enWires[247] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8368 ) , + .pReset_S_in ( pResetWires[514] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8369 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8370 ) , + .Reset_E_in ( ResetWires[250] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8371 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8372 ) , + .Reset_W_out ( ResetWires[247] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8373 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[132] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[133] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8374 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8375 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[64] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8376 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[65] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8377 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8378 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8379 ) , + .clk_2_S_in ( clk_2_wires[64] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8380 ) , + .clk_2_N_out ( clk_2_wires[65] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8381 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8382 ) ) ; +cby_1__1_ cby_3__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8383 } ) , + .chany_bottom_in ( sb_1__1__32_chany_top_out ) , + .chany_top_in ( sb_1__12__2_chany_bottom_out ) , + .ccff_head ( grid_clb_35_ccff_tail ) , + .chany_bottom_out ( cby_1__1__35_chany_bottom_out ) , + .chany_top_out ( cby_1__1__35_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__35_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__35_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__35_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__35_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__35_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__35_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__35_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__35_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__35_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__35_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__35_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__35_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__35_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__35_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__35_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__35_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__35_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8384 ) , + .Test_en_E_in ( Test_enWires[272] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8385 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8386 ) , + .Test_en_W_out ( Test_enWires[269] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8387 ) , + .pReset_S_in ( pResetWires[563] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8388 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8389 ) , + .Reset_E_in ( ResetWires[272] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8390 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8391 ) , + .Reset_W_out ( ResetWires[269] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8392 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[135] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[136] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[138] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8393 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8394 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8395 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8396 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8397 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8398 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8399 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8400 ) ) ; +cby_1__1_ cby_4__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8401 } ) , + .chany_bottom_in ( sb_1__0__3_chany_top_out ) , + .chany_top_in ( sb_1__1__33_chany_bottom_out ) , + .ccff_head ( grid_clb_36_ccff_tail ) , + .chany_bottom_out ( cby_1__1__36_chany_bottom_out ) , + .chany_top_out ( cby_1__1__36_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__36_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__36_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__36_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__36_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__36_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__36_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__36_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__36_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__36_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__36_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__36_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__36_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__36_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__36_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__36_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__36_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__36_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8402 ) , + .Test_en_E_in ( Test_enWires[32] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8403 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8404 ) , + .Test_en_W_out ( Test_enWires[29] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8405 ) , + .pReset_S_in ( pResetWires[36] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8406 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8407 ) , + .Reset_E_in ( ResetWires[32] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8408 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8409 ) , + .Reset_W_out ( ResetWires[29] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8410 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[140] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[141] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8411 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8412 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8413 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8414 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8415 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8416 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8417 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8418 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8419 ) ) ; +cby_1__1_ cby_4__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8420 } ) , + .chany_bottom_in ( sb_1__1__33_chany_top_out ) , + .chany_top_in ( sb_1__1__34_chany_bottom_out ) , + .ccff_head ( grid_clb_37_ccff_tail ) , + .chany_bottom_out ( cby_1__1__37_chany_bottom_out ) , + .chany_top_out ( cby_1__1__37_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__37_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__37_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__37_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__37_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__37_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__37_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__37_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__37_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__37_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__37_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__37_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__37_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__37_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__37_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__37_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__37_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__37_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8421 ) , + .Test_en_E_in ( Test_enWires[54] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8422 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8423 ) , + .Test_en_W_out ( Test_enWires[51] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8424 ) , + .pReset_S_in ( pResetWires[77] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8425 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8426 ) , + .Reset_E_in ( ResetWires[54] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8427 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8428 ) , + .Reset_W_out ( ResetWires[51] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8429 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[143] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[144] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8430 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8431 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8432 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8433 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8434 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8435 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8436 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8437 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8438 ) ) ; +cby_1__1_ cby_4__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8439 } ) , + .chany_bottom_in ( sb_1__1__34_chany_top_out ) , + .chany_top_in ( sb_1__1__35_chany_bottom_out ) , + .ccff_head ( grid_clb_38_ccff_tail ) , + .chany_bottom_out ( cby_1__1__38_chany_bottom_out ) , + .chany_top_out ( cby_1__1__38_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__38_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__38_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__38_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__38_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__38_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__38_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__38_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__38_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__38_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__38_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__38_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__38_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__38_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__38_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__38_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__38_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__38_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8440 ) , + .Test_en_E_in ( Test_enWires[76] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8441 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8442 ) , + .Test_en_W_out ( Test_enWires[73] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8443 ) , + .pReset_S_in ( pResetWires[126] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8444 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8445 ) , + .Reset_E_in ( ResetWires[76] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8446 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8447 ) , + .Reset_W_out ( ResetWires[73] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8448 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[146] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[147] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8449 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8450 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8451 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8452 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[24] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8453 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[25] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8454 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8455 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8456 ) , + .clk_3_N_in ( clk_3_wires[24] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8457 ) , + .clk_3_S_out ( clk_3_wires[25] ) ) ; +cby_1__1_ cby_4__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8458 } ) , + .chany_bottom_in ( sb_1__1__35_chany_top_out ) , + .chany_top_in ( sb_1__1__36_chany_bottom_out ) , + .ccff_head ( grid_clb_39_ccff_tail ) , + .chany_bottom_out ( cby_1__1__39_chany_bottom_out ) , + .chany_top_out ( cby_1__1__39_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__39_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__39_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__39_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__39_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__39_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__39_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__39_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__39_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__39_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__39_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__39_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__39_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__39_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__39_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__39_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__39_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__39_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8459 ) , + .Test_en_E_in ( Test_enWires[98] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8460 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8461 ) , + .Test_en_W_out ( Test_enWires[95] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8462 ) , + .pReset_S_in ( pResetWires[175] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8463 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8464 ) , + .Reset_E_in ( ResetWires[98] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8465 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8466 ) , + .Reset_W_out ( ResetWires[95] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8467 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[149] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[150] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8468 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8469 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8470 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8471 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[20] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8472 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[21] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8473 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8474 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8475 ) , + .clk_3_N_in ( clk_3_wires[20] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8476 ) , + .clk_3_S_out ( clk_3_wires[21] ) ) ; +cby_1__1_ cby_4__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8477 } ) , + .chany_bottom_in ( sb_1__1__36_chany_top_out ) , + .chany_top_in ( sb_1__1__37_chany_bottom_out ) , + .ccff_head ( grid_clb_40_ccff_tail ) , + .chany_bottom_out ( cby_1__1__40_chany_bottom_out ) , + .chany_top_out ( cby_1__1__40_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__40_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__40_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__40_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__40_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__40_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__40_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__40_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__40_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__40_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__40_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__40_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__40_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__40_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__40_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__40_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__40_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__40_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8478 ) , + .Test_en_E_in ( Test_enWires[120] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8479 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8480 ) , + .Test_en_W_out ( Test_enWires[117] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8481 ) , + .pReset_S_in ( pResetWires[224] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8482 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8483 ) , + .Reset_E_in ( ResetWires[120] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8484 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8485 ) , + .Reset_W_out ( ResetWires[117] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8486 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[152] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[153] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8487 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8488 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8489 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8490 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[14] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8491 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[15] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8492 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8493 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8494 ) , + .clk_3_N_in ( clk_3_wires[14] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8495 ) , + .clk_3_S_out ( clk_3_wires[15] ) ) ; +cby_1__1_ cby_4__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8496 } ) , + .chany_bottom_in ( sb_1__1__37_chany_top_out ) , + .chany_top_in ( sb_1__1__38_chany_bottom_out ) , + .ccff_head ( grid_clb_41_ccff_tail ) , + .chany_bottom_out ( cby_1__1__41_chany_bottom_out ) , + .chany_top_out ( cby_1__1__41_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__41_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__41_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__41_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__41_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__41_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__41_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__41_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__41_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__41_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__41_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__41_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__41_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__41_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__41_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__41_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__41_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__41_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8497 ) , + .Test_en_E_in ( Test_enWires[142] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8498 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8499 ) , + .Test_en_W_out ( Test_enWires[139] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8500 ) , + .pReset_S_in ( pResetWires[273] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8501 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8502 ) , + .Reset_E_in ( ResetWires[142] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8503 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8504 ) , + .Reset_W_out ( ResetWires[139] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8505 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[155] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[156] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8506 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8507 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8508 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_8509 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[10] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8510 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[11] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8511 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8512 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_8513 ) , + .clk_3_N_in ( clk_3_wires[10] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8514 ) , + .clk_3_S_out ( clk_3_wires[11] ) ) ; +cby_1__1_ cby_4__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8515 } ) , + .chany_bottom_in ( sb_1__1__38_chany_top_out ) , + .chany_top_in ( sb_1__1__39_chany_bottom_out ) , + .ccff_head ( grid_clb_42_ccff_tail ) , + .chany_bottom_out ( cby_1__1__42_chany_bottom_out ) , + .chany_top_out ( cby_1__1__42_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__42_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__42_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__42_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__42_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__42_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__42_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__42_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__42_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__42_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__42_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__42_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__42_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__42_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__42_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__42_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__42_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__42_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8516 ) , + .Test_en_E_in ( Test_enWires[164] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8517 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8518 ) , + .Test_en_W_out ( Test_enWires[161] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8519 ) , + .pReset_S_in ( pResetWires[322] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8520 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8521 ) , + .Reset_E_in ( ResetWires[164] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8522 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8523 ) , + .Reset_W_out ( ResetWires[161] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8524 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[158] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[159] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8525 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8526 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8527 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[8] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8528 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[9] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8529 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8530 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8531 ) , + .clk_3_S_in ( clk_3_wires[8] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8532 ) , + .clk_3_N_out ( clk_3_wires[9] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8533 ) ) ; +cby_1__1_ cby_4__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8534 } ) , + .chany_bottom_in ( sb_1__1__39_chany_top_out ) , + .chany_top_in ( sb_1__1__40_chany_bottom_out ) , + .ccff_head ( grid_clb_43_ccff_tail ) , + .chany_bottom_out ( cby_1__1__43_chany_bottom_out ) , + .chany_top_out ( cby_1__1__43_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__43_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__43_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__43_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__43_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__43_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__43_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__43_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__43_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__43_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__43_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__43_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__43_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__43_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__43_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__43_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__43_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__43_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8535 ) , + .Test_en_E_in ( Test_enWires[186] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8536 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8537 ) , + .Test_en_W_out ( Test_enWires[183] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8538 ) , + .pReset_S_in ( pResetWires[371] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8539 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8540 ) , + .Reset_E_in ( ResetWires[186] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8541 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8542 ) , + .Reset_W_out ( ResetWires[183] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8543 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[161] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[162] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8544 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8545 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8546 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[12] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8547 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[13] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8548 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8549 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8550 ) , + .clk_3_S_in ( clk_3_wires[12] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8551 ) , + .clk_3_N_out ( clk_3_wires[13] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8552 ) ) ; +cby_1__1_ cby_4__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8553 } ) , + .chany_bottom_in ( sb_1__1__40_chany_top_out ) , + .chany_top_in ( sb_1__1__41_chany_bottom_out ) , + .ccff_head ( grid_clb_44_ccff_tail ) , + .chany_bottom_out ( cby_1__1__44_chany_bottom_out ) , + .chany_top_out ( cby_1__1__44_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__44_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__44_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__44_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__44_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__44_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__44_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__44_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__44_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__44_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__44_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__44_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__44_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__44_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__44_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__44_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__44_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__44_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8554 ) , + .Test_en_E_in ( Test_enWires[208] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8555 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8556 ) , + .Test_en_W_out ( Test_enWires[205] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8557 ) , + .pReset_S_in ( pResetWires[420] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8558 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8559 ) , + .Reset_E_in ( ResetWires[208] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8560 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8561 ) , + .Reset_W_out ( ResetWires[205] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8562 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[164] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[165] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8563 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8564 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8565 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[18] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8566 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[19] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8567 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8568 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8569 ) , + .clk_3_S_in ( clk_3_wires[18] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8570 ) , + .clk_3_N_out ( clk_3_wires[19] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8571 ) ) ; +cby_1__1_ cby_4__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8572 } ) , + .chany_bottom_in ( sb_1__1__41_chany_top_out ) , + .chany_top_in ( sb_1__1__42_chany_bottom_out ) , + .ccff_head ( grid_clb_45_ccff_tail ) , + .chany_bottom_out ( cby_1__1__45_chany_bottom_out ) , + .chany_top_out ( cby_1__1__45_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__45_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__45_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__45_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__45_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__45_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__45_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__45_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__45_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__45_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__45_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__45_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__45_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__45_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__45_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__45_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__45_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__45_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8573 ) , + .Test_en_E_in ( Test_enWires[230] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8574 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8575 ) , + .Test_en_W_out ( Test_enWires[227] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8576 ) , + .pReset_S_in ( pResetWires[469] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8577 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8578 ) , + .Reset_E_in ( ResetWires[230] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8579 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8580 ) , + .Reset_W_out ( ResetWires[227] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8581 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[167] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[168] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8582 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8583 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8584 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[22] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8585 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[23] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8586 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8587 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8588 ) , + .clk_3_S_in ( clk_3_wires[22] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8589 ) , + .clk_3_N_out ( clk_3_wires[23] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8590 ) ) ; +cby_1__1_ cby_4__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8591 } ) , + .chany_bottom_in ( sb_1__1__42_chany_top_out ) , + .chany_top_in ( sb_1__1__43_chany_bottom_out ) , + .ccff_head ( grid_clb_46_ccff_tail ) , + .chany_bottom_out ( cby_1__1__46_chany_bottom_out ) , + .chany_top_out ( cby_1__1__46_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__46_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__46_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__46_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__46_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__46_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__46_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__46_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__46_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__46_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__46_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__46_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__46_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__46_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__46_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__46_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__46_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__46_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8592 ) , + .Test_en_E_in ( Test_enWires[252] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8593 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8594 ) , + .Test_en_W_out ( Test_enWires[249] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8595 ) , + .pReset_S_in ( pResetWires[518] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8596 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8597 ) , + .Reset_E_in ( ResetWires[252] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8598 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8599 ) , + .Reset_W_out ( ResetWires[249] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8600 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[170] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[171] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8601 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8602 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8603 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8604 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8605 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8606 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8607 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8608 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8609 ) ) ; +cby_1__1_ cby_4__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8610 } ) , + .chany_bottom_in ( sb_1__1__43_chany_top_out ) , + .chany_top_in ( sb_1__12__3_chany_bottom_out ) , + .ccff_head ( grid_clb_47_ccff_tail ) , + .chany_bottom_out ( cby_1__1__47_chany_bottom_out ) , + .chany_top_out ( cby_1__1__47_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__47_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__47_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__47_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__47_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__47_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__47_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__47_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__47_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__47_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__47_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__47_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__47_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__47_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__47_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__47_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__47_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__47_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8611 ) , + .Test_en_E_in ( Test_enWires[274] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8612 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8613 ) , + .Test_en_W_out ( Test_enWires[271] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8614 ) , + .pReset_S_in ( pResetWires[567] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8615 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8616 ) , + .Reset_E_in ( ResetWires[274] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8617 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8618 ) , + .Reset_W_out ( ResetWires[271] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8619 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[173] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[174] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[176] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8620 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8621 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8622 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8623 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8624 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8625 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8626 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8627 ) ) ; +cby_1__1_ cby_5__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8628 } ) , + .chany_bottom_in ( sb_1__0__4_chany_top_out ) , + .chany_top_in ( sb_1__1__44_chany_bottom_out ) , + .ccff_head ( grid_clb_48_ccff_tail ) , + .chany_bottom_out ( cby_1__1__48_chany_bottom_out ) , + .chany_top_out ( cby_1__1__48_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__48_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__48_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__48_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__48_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__48_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__48_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__48_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__48_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__48_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__48_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__48_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__48_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__48_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__48_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__48_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__48_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__48_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8629 ) , + .Test_en_E_in ( Test_enWires[34] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8630 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8631 ) , + .Test_en_W_out ( Test_enWires[31] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8632 ) , + .pReset_S_in ( pResetWires[39] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8633 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8634 ) , + .Reset_E_in ( ResetWires[34] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8635 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8636 ) , + .Reset_W_out ( ResetWires[31] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8637 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[178] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[179] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8638 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8639 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8640 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8641 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8642 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8643 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8644 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8645 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8646 ) ) ; +cby_1__1_ cby_5__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8647 } ) , + .chany_bottom_in ( sb_1__1__44_chany_top_out ) , + .chany_top_in ( sb_1__1__45_chany_bottom_out ) , + .ccff_head ( grid_clb_49_ccff_tail ) , + .chany_bottom_out ( cby_1__1__49_chany_bottom_out ) , + .chany_top_out ( cby_1__1__49_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__49_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__49_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__49_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__49_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__49_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__49_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__49_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__49_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__49_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__49_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__49_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__49_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__49_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__49_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__49_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__49_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__49_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8648 ) , + .Test_en_E_in ( Test_enWires[56] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8649 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8650 ) , + .Test_en_W_out ( Test_enWires[53] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8651 ) , + .pReset_S_in ( pResetWires[81] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8652 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8653 ) , + .Reset_E_in ( ResetWires[56] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8654 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8655 ) , + .Reset_W_out ( ResetWires[53] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8656 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[181] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[182] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8657 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[31] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8658 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[32] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8659 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8660 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8661 ) , + .clk_2_N_in ( clk_2_wires[31] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8662 ) , + .clk_2_S_out ( clk_2_wires[32] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8663 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8664 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8665 ) ) ; +cby_1__1_ cby_5__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8666 } ) , + .chany_bottom_in ( sb_1__1__45_chany_top_out ) , + .chany_top_in ( sb_1__1__46_chany_bottom_out ) , + .ccff_head ( grid_clb_50_ccff_tail ) , + .chany_bottom_out ( cby_1__1__50_chany_bottom_out ) , + .chany_top_out ( cby_1__1__50_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__50_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__50_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__50_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__50_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__50_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__50_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__50_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__50_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__50_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__50_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__50_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__50_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__50_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__50_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__50_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__50_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__50_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8667 ) , + .Test_en_E_in ( Test_enWires[78] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8668 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8669 ) , + .Test_en_W_out ( Test_enWires[75] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8670 ) , + .pReset_S_in ( pResetWires[130] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8671 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8672 ) , + .Reset_E_in ( ResetWires[78] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8673 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8674 ) , + .Reset_W_out ( ResetWires[75] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8675 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[184] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[185] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8676 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8677 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8678 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8679 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8680 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8681 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8682 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8683 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8684 ) ) ; +cby_1__1_ cby_5__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8685 } ) , + .chany_bottom_in ( sb_1__1__46_chany_top_out ) , + .chany_top_in ( sb_1__1__47_chany_bottom_out ) , + .ccff_head ( grid_clb_51_ccff_tail ) , + .chany_bottom_out ( cby_1__1__51_chany_bottom_out ) , + .chany_top_out ( cby_1__1__51_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__51_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__51_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__51_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__51_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__51_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__51_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__51_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__51_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__51_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__51_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__51_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__51_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__51_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__51_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__51_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__51_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__51_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8686 ) , + .Test_en_E_in ( Test_enWires[100] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8687 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8688 ) , + .Test_en_W_out ( Test_enWires[97] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8689 ) , + .pReset_S_in ( pResetWires[179] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8690 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8691 ) , + .Reset_E_in ( ResetWires[100] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8692 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8693 ) , + .Reset_W_out ( ResetWires[97] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8694 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[187] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[188] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8695 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[44] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8696 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[45] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8697 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8698 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8699 ) , + .clk_2_N_in ( clk_2_wires[44] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8700 ) , + .clk_2_S_out ( clk_2_wires[45] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8701 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8702 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8703 ) ) ; +cby_1__1_ cby_5__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8704 } ) , + .chany_bottom_in ( sb_1__1__47_chany_top_out ) , + .chany_top_in ( sb_1__1__48_chany_bottom_out ) , + .ccff_head ( grid_clb_52_ccff_tail ) , + .chany_bottom_out ( cby_1__1__52_chany_bottom_out ) , + .chany_top_out ( cby_1__1__52_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__52_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__52_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__52_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__52_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__52_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__52_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__52_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__52_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__52_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__52_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__52_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__52_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__52_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__52_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__52_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__52_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__52_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8705 ) , + .Test_en_E_in ( Test_enWires[122] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8706 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8707 ) , + .Test_en_W_out ( Test_enWires[119] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8708 ) , + .pReset_S_in ( pResetWires[228] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8709 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8710 ) , + .Reset_E_in ( ResetWires[122] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8711 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8712 ) , + .Reset_W_out ( ResetWires[119] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8713 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[190] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[191] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8714 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8715 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[42] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8716 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[43] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8717 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8718 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8719 ) , + .clk_2_S_in ( clk_2_wires[42] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8720 ) , + .clk_2_N_out ( clk_2_wires[43] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8721 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8722 ) ) ; +cby_1__1_ cby_5__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8723 } ) , + .chany_bottom_in ( sb_1__1__48_chany_top_out ) , + .chany_top_in ( sb_1__1__49_chany_bottom_out ) , + .ccff_head ( grid_clb_53_ccff_tail ) , + .chany_bottom_out ( cby_1__1__53_chany_bottom_out ) , + .chany_top_out ( cby_1__1__53_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__53_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__53_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__53_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__53_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__53_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__53_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__53_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__53_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__53_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__53_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__53_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__53_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__53_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__53_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__53_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__53_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__53_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8724 ) , + .Test_en_E_in ( Test_enWires[144] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8725 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8726 ) , + .Test_en_W_out ( Test_enWires[141] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8727 ) , + .pReset_S_in ( pResetWires[277] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8728 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8729 ) , + .Reset_E_in ( ResetWires[144] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8730 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8731 ) , + .Reset_W_out ( ResetWires[141] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8732 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[193] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[194] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8733 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8734 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8735 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8736 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8737 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8738 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8739 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8740 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8741 ) ) ; +cby_1__1_ cby_5__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8742 } ) , + .chany_bottom_in ( sb_1__1__49_chany_top_out ) , + .chany_top_in ( sb_1__1__50_chany_bottom_out ) , + .ccff_head ( grid_clb_54_ccff_tail ) , + .chany_bottom_out ( cby_1__1__54_chany_bottom_out ) , + .chany_top_out ( cby_1__1__54_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__54_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__54_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__54_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__54_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__54_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__54_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__54_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__54_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__54_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__54_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__54_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__54_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__54_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__54_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__54_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__54_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__54_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8743 ) , + .Test_en_E_in ( Test_enWires[166] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8744 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8745 ) , + .Test_en_W_out ( Test_enWires[163] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8746 ) , + .pReset_S_in ( pResetWires[326] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8747 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8748 ) , + .Reset_E_in ( ResetWires[166] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8749 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8750 ) , + .Reset_W_out ( ResetWires[163] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8751 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[196] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[197] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8752 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8753 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8754 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8755 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8756 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8757 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8758 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8759 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8760 ) ) ; +cby_1__1_ cby_5__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8761 } ) , + .chany_bottom_in ( sb_1__1__50_chany_top_out ) , + .chany_top_in ( sb_1__1__51_chany_bottom_out ) , + .ccff_head ( grid_clb_55_ccff_tail ) , + .chany_bottom_out ( cby_1__1__55_chany_bottom_out ) , + .chany_top_out ( cby_1__1__55_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__55_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__55_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__55_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__55_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__55_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__55_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__55_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__55_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__55_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__55_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__55_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__55_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__55_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__55_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__55_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__55_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__55_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8762 ) , + .Test_en_E_in ( Test_enWires[188] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8763 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8764 ) , + .Test_en_W_out ( Test_enWires[185] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8765 ) , + .pReset_S_in ( pResetWires[375] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8766 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8767 ) , + .Reset_E_in ( ResetWires[188] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8768 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8769 ) , + .Reset_W_out ( ResetWires[185] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8770 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[199] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[200] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8771 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[57] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_8772 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[58] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8773 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8774 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8775 ) , + .clk_2_N_in ( clk_2_wires[57] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_8776 ) , + .clk_2_S_out ( clk_2_wires[58] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8777 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8778 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8779 ) ) ; +cby_1__1_ cby_5__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8780 } ) , + .chany_bottom_in ( sb_1__1__51_chany_top_out ) , + .chany_top_in ( sb_1__1__52_chany_bottom_out ) , + .ccff_head ( grid_clb_56_ccff_tail ) , + .chany_bottom_out ( cby_1__1__56_chany_bottom_out ) , + .chany_top_out ( cby_1__1__56_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__56_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__56_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__56_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__56_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__56_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__56_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__56_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__56_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__56_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__56_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__56_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__56_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__56_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__56_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__56_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__56_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__56_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8781 ) , + .Test_en_E_in ( Test_enWires[210] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8782 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8783 ) , + .Test_en_W_out ( Test_enWires[207] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8784 ) , + .pReset_S_in ( pResetWires[424] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8785 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8786 ) , + .Reset_E_in ( ResetWires[210] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8787 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8788 ) , + .Reset_W_out ( ResetWires[207] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8789 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[202] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[203] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8790 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8791 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[55] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8792 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[56] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8793 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8794 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8795 ) , + .clk_2_S_in ( clk_2_wires[55] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8796 ) , + .clk_2_N_out ( clk_2_wires[56] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8797 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8798 ) ) ; +cby_1__1_ cby_5__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8799 } ) , + .chany_bottom_in ( sb_1__1__52_chany_top_out ) , + .chany_top_in ( sb_1__1__53_chany_bottom_out ) , + .ccff_head ( grid_clb_57_ccff_tail ) , + .chany_bottom_out ( cby_1__1__57_chany_bottom_out ) , + .chany_top_out ( cby_1__1__57_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__57_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__57_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__57_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__57_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__57_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__57_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__57_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__57_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__57_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__57_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__57_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__57_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__57_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__57_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__57_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__57_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__57_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8800 ) , + .Test_en_E_in ( Test_enWires[232] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8801 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8802 ) , + .Test_en_W_out ( Test_enWires[229] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8803 ) , + .pReset_S_in ( pResetWires[473] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8804 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8805 ) , + .Reset_E_in ( ResetWires[232] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8806 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8807 ) , + .Reset_W_out ( ResetWires[229] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8808 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[205] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[206] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8809 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8810 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8811 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8812 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8813 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8814 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8815 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8816 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8817 ) ) ; +cby_1__1_ cby_5__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8818 } ) , + .chany_bottom_in ( sb_1__1__53_chany_top_out ) , + .chany_top_in ( sb_1__1__54_chany_bottom_out ) , + .ccff_head ( grid_clb_58_ccff_tail ) , + .chany_bottom_out ( cby_1__1__58_chany_bottom_out ) , + .chany_top_out ( cby_1__1__58_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__58_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__58_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__58_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__58_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__58_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__58_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__58_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__58_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__58_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__58_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__58_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__58_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__58_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__58_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__58_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__58_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__58_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8819 ) , + .Test_en_E_in ( Test_enWires[254] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8820 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8821 ) , + .Test_en_W_out ( Test_enWires[251] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8822 ) , + .pReset_S_in ( pResetWires[522] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8823 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8824 ) , + .Reset_E_in ( ResetWires[254] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8825 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8826 ) , + .Reset_W_out ( ResetWires[251] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8827 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[208] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[209] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8828 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_8829 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[66] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8830 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[67] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8831 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8832 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_8833 ) , + .clk_2_S_in ( clk_2_wires[66] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8834 ) , + .clk_2_N_out ( clk_2_wires[67] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8835 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8836 ) ) ; +cby_1__1_ cby_5__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8837 } ) , + .chany_bottom_in ( sb_1__1__54_chany_top_out ) , + .chany_top_in ( sb_1__12__4_chany_bottom_out ) , + .ccff_head ( grid_clb_59_ccff_tail ) , + .chany_bottom_out ( cby_1__1__59_chany_bottom_out ) , + .chany_top_out ( cby_1__1__59_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__59_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__59_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__59_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__59_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__59_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__59_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__59_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__59_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__59_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__59_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__59_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__59_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__59_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__59_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__59_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__59_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__59_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_8838 ) , + .Test_en_E_in ( Test_enWires[276] ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8839 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_8840 ) , + .Test_en_W_out ( Test_enWires[273] ) , + .Test_en_E_out ( SYNOPSYS_UNCONNECTED_8841 ) , + .pReset_S_in ( pResetWires[571] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_8842 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_8843 ) , + .Reset_E_in ( ResetWires[276] ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8844 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_8845 ) , + .Reset_W_out ( ResetWires[273] ) , + .Reset_E_out ( SYNOPSYS_UNCONNECTED_8846 ) , + .prog_clk_0_W_in ( prog_clk_0_wires[211] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[212] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[214] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8847 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8848 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8849 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8850 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8851 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8852 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8853 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8854 ) ) ; +cby_1__1_ cby_6__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8855 } ) , + .chany_bottom_in ( sb_1__0__5_chany_top_out ) , + .chany_top_in ( sb_1__1__55_chany_bottom_out ) , + .ccff_head ( grid_clb_60_ccff_tail ) , + .chany_bottom_out ( cby_1__1__60_chany_bottom_out ) , + .chany_top_out ( cby_1__1__60_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__60_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__60_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__60_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__60_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__60_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__60_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__60_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__60_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__60_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__60_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__60_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__60_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__60_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__60_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__60_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__60_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__60_ccff_tail ) , + .Test_en_S_in ( Test_enWires[1] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8856 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8857 ) , + .Test_en_N_out ( Test_enWires[2] ) , .Test_en_W_out ( Test_enWires[33] ) , + .Test_en_E_out ( Test_enWires[35] ) , .pReset_S_in ( pResetWires[42] ) , + .pReset_N_out ( pResetWires[2] ) , .Reset_S_in ( ResetWires[1] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8858 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8859 ) , + .Reset_N_out ( ResetWires[2] ) , .Reset_W_out ( ResetWires[33] ) , + .Reset_E_out ( ResetWires[35] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[216] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[217] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8860 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8861 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8862 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[90] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8863 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[89] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8864 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8865 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8866 ) , + .clk_3_S_in ( clk_3_wires[90] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8867 ) , + .clk_3_N_out ( clk_3_wires[89] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8868 ) ) ; +cby_1__1_ cby_6__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8869 } ) , + .chany_bottom_in ( sb_1__1__55_chany_top_out ) , + .chany_top_in ( sb_1__1__56_chany_bottom_out ) , + .ccff_head ( grid_clb_61_ccff_tail ) , + .chany_bottom_out ( cby_1__1__61_chany_bottom_out ) , + .chany_top_out ( cby_1__1__61_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__61_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__61_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__61_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__61_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__61_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__61_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__61_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__61_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__61_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__61_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__61_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__61_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__61_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__61_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__61_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__61_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__61_ccff_tail ) , + .Test_en_S_in ( Test_enWires[3] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8870 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8871 ) , + .Test_en_N_out ( Test_enWires[4] ) , .Test_en_W_out ( Test_enWires[55] ) , + .Test_en_E_out ( Test_enWires[57] ) , .pReset_S_in ( pResetWires[85] ) , + .pReset_N_out ( pResetWires[4] ) , .Reset_S_in ( ResetWires[3] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8872 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8873 ) , + .Reset_N_out ( ResetWires[4] ) , .Reset_W_out ( ResetWires[55] ) , + .Reset_E_out ( ResetWires[57] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[219] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[220] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8874 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8875 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8876 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[92] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8877 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[91] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8878 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8879 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8880 ) , + .clk_3_S_in ( clk_3_wires[92] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8881 ) , + .clk_3_N_out ( clk_3_wires[91] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8882 ) ) ; +cby_1__1_ cby_6__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8883 } ) , + .chany_bottom_in ( sb_1__1__56_chany_top_out ) , + .chany_top_in ( sb_1__1__57_chany_bottom_out ) , + .ccff_head ( grid_clb_62_ccff_tail ) , + .chany_bottom_out ( cby_1__1__62_chany_bottom_out ) , + .chany_top_out ( cby_1__1__62_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__62_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__62_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__62_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__62_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__62_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__62_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__62_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__62_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__62_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__62_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__62_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__62_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__62_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__62_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__62_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__62_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__62_ccff_tail ) , + .Test_en_S_in ( Test_enWires[5] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8884 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8885 ) , + .Test_en_N_out ( Test_enWires[6] ) , .Test_en_W_out ( Test_enWires[77] ) , + .Test_en_E_out ( Test_enWires[79] ) , .pReset_S_in ( pResetWires[134] ) , + .pReset_N_out ( pResetWires[6] ) , .Reset_S_in ( ResetWires[5] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8886 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8887 ) , + .Reset_N_out ( ResetWires[6] ) , .Reset_W_out ( ResetWires[77] ) , + .Reset_E_out ( ResetWires[79] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[222] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[223] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8888 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8889 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8890 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[94] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8891 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[93] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8892 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8893 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8894 ) , + .clk_3_S_in ( clk_3_wires[94] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8895 ) , + .clk_3_N_out ( clk_3_wires[93] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8896 ) ) ; +cby_1__1_ cby_6__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8897 } ) , + .chany_bottom_in ( sb_1__1__57_chany_top_out ) , + .chany_top_in ( sb_1__1__58_chany_bottom_out ) , + .ccff_head ( grid_clb_63_ccff_tail ) , + .chany_bottom_out ( cby_1__1__63_chany_bottom_out ) , + .chany_top_out ( cby_1__1__63_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__63_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__63_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__63_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__63_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__63_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__63_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__63_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__63_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__63_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__63_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__63_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__63_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__63_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__63_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__63_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__63_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__63_ccff_tail ) , + .Test_en_S_in ( Test_enWires[7] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8898 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8899 ) , + .Test_en_N_out ( Test_enWires[8] ) , .Test_en_W_out ( Test_enWires[99] ) , + .Test_en_E_out ( Test_enWires[101] ) , .pReset_S_in ( pResetWires[183] ) , + .pReset_N_out ( pResetWires[8] ) , .Reset_S_in ( ResetWires[7] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8900 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8901 ) , + .Reset_N_out ( ResetWires[8] ) , .Reset_W_out ( ResetWires[99] ) , + .Reset_E_out ( ResetWires[101] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[225] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[226] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8902 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8903 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8904 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[96] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8905 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[95] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8906 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8907 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8908 ) , + .clk_3_S_in ( clk_3_wires[96] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8909 ) , + .clk_3_N_out ( clk_3_wires[95] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8910 ) ) ; +cby_1__1_ cby_6__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8911 } ) , + .chany_bottom_in ( sb_1__1__58_chany_top_out ) , + .chany_top_in ( sb_1__1__59_chany_bottom_out ) , + .ccff_head ( grid_clb_64_ccff_tail ) , + .chany_bottom_out ( cby_1__1__64_chany_bottom_out ) , + .chany_top_out ( cby_1__1__64_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__64_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__64_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__64_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__64_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__64_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__64_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__64_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__64_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__64_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__64_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__64_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__64_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__64_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__64_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__64_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__64_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__64_ccff_tail ) , + .Test_en_S_in ( Test_enWires[9] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8912 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8913 ) , + .Test_en_N_out ( Test_enWires[10] ) , + .Test_en_W_out ( Test_enWires[121] ) , + .Test_en_E_out ( Test_enWires[123] ) , .pReset_S_in ( pResetWires[232] ) , + .pReset_N_out ( pResetWires[10] ) , .Reset_S_in ( ResetWires[9] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8914 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8915 ) , + .Reset_N_out ( ResetWires[10] ) , .Reset_W_out ( ResetWires[121] ) , + .Reset_E_out ( ResetWires[123] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[228] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[229] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8916 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8917 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8918 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[98] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8919 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[97] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8920 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8921 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8922 ) , + .clk_3_S_in ( clk_3_wires[98] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8923 ) , + .clk_3_N_out ( clk_3_wires[97] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8924 ) ) ; +cby_1__1_ cby_6__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8925 } ) , + .chany_bottom_in ( sb_1__1__59_chany_top_out ) , + .chany_top_in ( sb_1__1__60_chany_bottom_out ) , + .ccff_head ( grid_clb_65_ccff_tail ) , + .chany_bottom_out ( cby_1__1__65_chany_bottom_out ) , + .chany_top_out ( cby_1__1__65_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__65_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__65_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__65_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__65_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__65_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__65_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__65_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__65_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__65_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__65_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__65_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__65_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__65_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__65_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__65_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__65_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__65_ccff_tail ) , + .Test_en_S_in ( Test_enWires[11] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8926 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8927 ) , + .Test_en_N_out ( Test_enWires[12] ) , + .Test_en_W_out ( Test_enWires[143] ) , + .Test_en_E_out ( Test_enWires[145] ) , .pReset_S_in ( pResetWires[281] ) , + .pReset_N_out ( pResetWires[12] ) , .Reset_S_in ( ResetWires[11] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8928 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8929 ) , + .Reset_N_out ( ResetWires[12] ) , .Reset_W_out ( ResetWires[143] ) , + .Reset_E_out ( ResetWires[145] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[231] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[232] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8930 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8931 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8932 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[100] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_8933 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[99] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8934 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8935 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8936 ) , + .clk_3_S_in ( clk_3_wires[100] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_8937 ) , + .clk_3_N_out ( clk_3_wires[99] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8938 ) ) ; +cby_1__1_ cby_6__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8939 } ) , + .chany_bottom_in ( sb_1__1__60_chany_top_out ) , + .chany_top_in ( sb_1__1__61_chany_bottom_out ) , + .ccff_head ( grid_clb_66_ccff_tail ) , + .chany_bottom_out ( cby_1__1__66_chany_bottom_out ) , + .chany_top_out ( cby_1__1__66_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__66_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__66_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__66_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__66_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__66_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__66_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__66_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__66_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__66_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__66_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__66_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__66_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__66_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__66_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__66_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__66_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__66_ccff_tail ) , + .Test_en_S_in ( Test_enWires[13] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8940 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8941 ) , + .Test_en_N_out ( Test_enWires[14] ) , + .Test_en_W_out ( Test_enWires[165] ) , + .Test_en_E_out ( Test_enWires[167] ) , .pReset_S_in ( pResetWires[330] ) , + .pReset_N_out ( pResetWires[14] ) , .Reset_S_in ( ResetWires[13] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8942 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8943 ) , + .Reset_N_out ( ResetWires[14] ) , .Reset_W_out ( ResetWires[165] ) , + .Reset_E_out ( ResetWires[167] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[234] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[235] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8944 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8945 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8946 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8947 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8948 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8949 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8950 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8951 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8952 ) ) ; +cby_1__1_ cby_6__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8953 } ) , + .chany_bottom_in ( sb_1__1__61_chany_top_out ) , + .chany_top_in ( sb_1__1__62_chany_bottom_out ) , + .ccff_head ( grid_clb_67_ccff_tail ) , + .chany_bottom_out ( cby_1__1__67_chany_bottom_out ) , + .chany_top_out ( cby_1__1__67_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__67_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__67_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__67_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__67_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__67_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__67_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__67_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__67_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__67_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__67_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__67_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__67_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__67_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__67_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__67_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__67_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__67_ccff_tail ) , + .Test_en_S_in ( Test_enWires[15] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8954 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8955 ) , + .Test_en_N_out ( Test_enWires[16] ) , + .Test_en_W_out ( Test_enWires[187] ) , + .Test_en_E_out ( Test_enWires[189] ) , .pReset_S_in ( pResetWires[379] ) , + .pReset_N_out ( pResetWires[16] ) , .Reset_S_in ( ResetWires[15] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8956 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8957 ) , + .Reset_N_out ( ResetWires[16] ) , .Reset_W_out ( ResetWires[187] ) , + .Reset_E_out ( ResetWires[189] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[237] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[238] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8958 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8959 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8960 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8961 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8962 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8963 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8964 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8965 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8966 ) ) ; +cby_1__1_ cby_6__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8967 } ) , + .chany_bottom_in ( sb_1__1__62_chany_top_out ) , + .chany_top_in ( sb_1__1__63_chany_bottom_out ) , + .ccff_head ( grid_clb_68_ccff_tail ) , + .chany_bottom_out ( cby_1__1__68_chany_bottom_out ) , + .chany_top_out ( cby_1__1__68_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__68_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__68_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__68_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__68_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__68_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__68_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__68_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__68_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__68_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__68_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__68_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__68_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__68_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__68_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__68_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__68_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__68_ccff_tail ) , + .Test_en_S_in ( Test_enWires[17] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8968 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8969 ) , + .Test_en_N_out ( Test_enWires[18] ) , + .Test_en_W_out ( Test_enWires[209] ) , + .Test_en_E_out ( Test_enWires[211] ) , .pReset_S_in ( pResetWires[428] ) , + .pReset_N_out ( pResetWires[18] ) , .Reset_S_in ( ResetWires[17] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8970 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8971 ) , + .Reset_N_out ( ResetWires[18] ) , .Reset_W_out ( ResetWires[209] ) , + .Reset_E_out ( ResetWires[211] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[240] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[241] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8972 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8973 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8974 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8975 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8976 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8977 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8978 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8979 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8980 ) ) ; +cby_1__1_ cby_6__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8981 } ) , + .chany_bottom_in ( sb_1__1__63_chany_top_out ) , + .chany_top_in ( sb_1__1__64_chany_bottom_out ) , + .ccff_head ( grid_clb_69_ccff_tail ) , + .chany_bottom_out ( cby_1__1__69_chany_bottom_out ) , + .chany_top_out ( cby_1__1__69_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__69_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__69_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__69_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__69_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__69_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__69_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__69_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__69_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__69_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__69_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__69_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__69_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__69_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__69_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__69_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__69_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__69_ccff_tail ) , + .Test_en_S_in ( Test_enWires[19] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8982 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8983 ) , + .Test_en_N_out ( Test_enWires[20] ) , + .Test_en_W_out ( Test_enWires[231] ) , + .Test_en_E_out ( Test_enWires[233] ) , .pReset_S_in ( pResetWires[477] ) , + .pReset_N_out ( pResetWires[20] ) , .Reset_S_in ( ResetWires[19] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8984 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8985 ) , + .Reset_N_out ( ResetWires[20] ) , .Reset_W_out ( ResetWires[231] ) , + .Reset_E_out ( ResetWires[233] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[243] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[244] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_8986 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_8987 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_8988 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_8989 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_8990 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_8991 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_8992 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_8993 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_8994 ) ) ; +cby_1__1_ cby_6__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_8995 } ) , + .chany_bottom_in ( sb_1__1__64_chany_top_out ) , + .chany_top_in ( sb_1__1__65_chany_bottom_out ) , + .ccff_head ( grid_clb_70_ccff_tail ) , + .chany_bottom_out ( cby_1__1__70_chany_bottom_out ) , + .chany_top_out ( cby_1__1__70_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__70_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__70_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__70_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__70_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__70_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__70_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__70_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__70_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__70_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__70_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__70_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__70_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__70_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__70_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__70_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__70_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__70_ccff_tail ) , + .Test_en_S_in ( Test_enWires[21] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_8996 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_8997 ) , + .Test_en_N_out ( Test_enWires[22] ) , + .Test_en_W_out ( Test_enWires[253] ) , + .Test_en_E_out ( Test_enWires[255] ) , .pReset_S_in ( pResetWires[526] ) , + .pReset_N_out ( pResetWires[22] ) , .Reset_S_in ( ResetWires[21] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_8998 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_8999 ) , + .Reset_N_out ( ResetWires[22] ) , .Reset_W_out ( ResetWires[253] ) , + .Reset_E_out ( ResetWires[255] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[246] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[247] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9000 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9001 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9002 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9003 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9004 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9005 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9006 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9007 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9008 ) ) ; +cby_1__1_ cby_6__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9009 } ) , + .chany_bottom_in ( sb_1__1__65_chany_top_out ) , + .chany_top_in ( sb_1__12__5_chany_bottom_out ) , + .ccff_head ( grid_clb_71_ccff_tail ) , + .chany_bottom_out ( cby_1__1__71_chany_bottom_out ) , + .chany_top_out ( cby_1__1__71_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__71_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__71_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__71_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__71_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__71_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__71_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__71_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__71_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__71_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__71_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__71_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__71_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__71_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__71_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__71_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__71_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__71_ccff_tail ) , + .Test_en_S_in ( Test_enWires[23] ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9010 ) , + .Test_en_W_in ( SYNOPSYS_UNCONNECTED_9011 ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9012 ) , + .Test_en_W_out ( Test_enWires[275] ) , + .Test_en_E_out ( Test_enWires[277] ) , .pReset_S_in ( pResetWires[575] ) , + .pReset_N_out ( pResetWires[24] ) , .Reset_S_in ( ResetWires[23] ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9013 ) , + .Reset_W_in ( SYNOPSYS_UNCONNECTED_9014 ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9015 ) , + .Reset_W_out ( ResetWires[275] ) , .Reset_E_out ( ResetWires[277] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[249] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[250] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[252] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9016 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9017 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9018 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9019 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9020 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9021 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9022 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9023 ) ) ; +cby_1__1_ cby_7__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9024 } ) , + .chany_bottom_in ( sb_1__0__6_chany_top_out ) , + .chany_top_in ( sb_1__1__66_chany_bottom_out ) , + .ccff_head ( grid_clb_72_ccff_tail ) , + .chany_bottom_out ( cby_1__1__72_chany_bottom_out ) , + .chany_top_out ( cby_1__1__72_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__72_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__72_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__72_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__72_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__72_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__72_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__72_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__72_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__72_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__72_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__72_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__72_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__72_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__72_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__72_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__72_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__72_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9025 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9026 ) , + .Test_en_W_in ( Test_enWires[36] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9027 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9028 ) , + .Test_en_E_out ( Test_enWires[37] ) , .pReset_S_in ( pResetWires[45] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9029 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9030 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9031 ) , + .Reset_W_in ( ResetWires[36] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9032 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9033 ) , + .Reset_E_out ( ResetWires[37] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[254] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[255] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9034 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9035 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9036 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9037 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9038 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9039 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9040 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9041 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9042 ) ) ; +cby_1__1_ cby_7__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9043 } ) , + .chany_bottom_in ( sb_1__1__66_chany_top_out ) , + .chany_top_in ( sb_1__1__67_chany_bottom_out ) , + .ccff_head ( grid_clb_73_ccff_tail ) , + .chany_bottom_out ( cby_1__1__73_chany_bottom_out ) , + .chany_top_out ( cby_1__1__73_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__73_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__73_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__73_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__73_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__73_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__73_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__73_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__73_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__73_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__73_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__73_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__73_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__73_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__73_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__73_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__73_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__73_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9044 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9045 ) , + .Test_en_W_in ( Test_enWires[58] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9046 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9047 ) , + .Test_en_E_out ( Test_enWires[59] ) , .pReset_S_in ( pResetWires[89] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9048 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9049 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9050 ) , + .Reset_W_in ( ResetWires[58] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9051 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9052 ) , + .Reset_E_out ( ResetWires[59] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[257] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[258] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9053 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[73] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9054 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[74] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9055 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9056 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9057 ) , + .clk_2_N_in ( clk_2_wires[73] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9058 ) , + .clk_2_S_out ( clk_2_wires[74] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9059 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9060 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9061 ) ) ; +cby_1__1_ cby_7__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9062 } ) , + .chany_bottom_in ( sb_1__1__67_chany_top_out ) , + .chany_top_in ( sb_1__1__68_chany_bottom_out ) , + .ccff_head ( grid_clb_74_ccff_tail ) , + .chany_bottom_out ( cby_1__1__74_chany_bottom_out ) , + .chany_top_out ( cby_1__1__74_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__74_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__74_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__74_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__74_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__74_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__74_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__74_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__74_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__74_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__74_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__74_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__74_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__74_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__74_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__74_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__74_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__74_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9063 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9064 ) , + .Test_en_W_in ( Test_enWires[80] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9065 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9066 ) , + .Test_en_E_out ( Test_enWires[81] ) , .pReset_S_in ( pResetWires[138] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9067 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9068 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9069 ) , + .Reset_W_in ( ResetWires[80] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9070 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9071 ) , + .Reset_E_out ( ResetWires[81] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[260] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[261] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9072 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9073 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9074 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9075 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9076 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9077 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9078 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9079 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9080 ) ) ; +cby_1__1_ cby_7__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9081 } ) , + .chany_bottom_in ( sb_1__1__68_chany_top_out ) , + .chany_top_in ( sb_1__1__69_chany_bottom_out ) , + .ccff_head ( grid_clb_75_ccff_tail ) , + .chany_bottom_out ( cby_1__1__75_chany_bottom_out ) , + .chany_top_out ( cby_1__1__75_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__75_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__75_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__75_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__75_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__75_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__75_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__75_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__75_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__75_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__75_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__75_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__75_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__75_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__75_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__75_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__75_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__75_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9082 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9083 ) , + .Test_en_W_in ( Test_enWires[102] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9084 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9085 ) , + .Test_en_E_out ( Test_enWires[103] ) , .pReset_S_in ( pResetWires[187] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9086 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9087 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9088 ) , + .Reset_W_in ( ResetWires[102] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9089 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9090 ) , + .Reset_E_out ( ResetWires[103] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[263] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[264] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9091 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[84] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9092 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[85] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9093 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9094 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9095 ) , + .clk_2_N_in ( clk_2_wires[84] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9096 ) , + .clk_2_S_out ( clk_2_wires[85] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9097 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9098 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9099 ) ) ; +cby_1__1_ cby_7__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9100 } ) , + .chany_bottom_in ( sb_1__1__69_chany_top_out ) , + .chany_top_in ( sb_1__1__70_chany_bottom_out ) , + .ccff_head ( grid_clb_76_ccff_tail ) , + .chany_bottom_out ( cby_1__1__76_chany_bottom_out ) , + .chany_top_out ( cby_1__1__76_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__76_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__76_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__76_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__76_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__76_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__76_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__76_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__76_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__76_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__76_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__76_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__76_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__76_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__76_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__76_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__76_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__76_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9101 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9102 ) , + .Test_en_W_in ( Test_enWires[124] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9103 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9104 ) , + .Test_en_E_out ( Test_enWires[125] ) , .pReset_S_in ( pResetWires[236] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9105 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9106 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9107 ) , + .Reset_W_in ( ResetWires[124] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9108 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9109 ) , + .Reset_E_out ( ResetWires[125] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[266] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[267] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9110 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9111 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[82] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9112 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[83] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9113 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9114 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9115 ) , + .clk_2_S_in ( clk_2_wires[82] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9116 ) , + .clk_2_N_out ( clk_2_wires[83] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9117 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9118 ) ) ; +cby_1__1_ cby_7__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9119 } ) , + .chany_bottom_in ( sb_1__1__70_chany_top_out ) , + .chany_top_in ( sb_1__1__71_chany_bottom_out ) , + .ccff_head ( grid_clb_77_ccff_tail ) , + .chany_bottom_out ( cby_1__1__77_chany_bottom_out ) , + .chany_top_out ( cby_1__1__77_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__77_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__77_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__77_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__77_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__77_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__77_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__77_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__77_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__77_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__77_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__77_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__77_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__77_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__77_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__77_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__77_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__77_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9120 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9121 ) , + .Test_en_W_in ( Test_enWires[146] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9122 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9123 ) , + .Test_en_E_out ( Test_enWires[147] ) , .pReset_S_in ( pResetWires[285] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9124 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9125 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9126 ) , + .Reset_W_in ( ResetWires[146] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9127 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9128 ) , + .Reset_E_out ( ResetWires[147] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[269] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[270] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9129 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9130 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9131 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9132 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9133 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9134 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9135 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9136 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9137 ) ) ; +cby_1__1_ cby_7__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9138 } ) , + .chany_bottom_in ( sb_1__1__71_chany_top_out ) , + .chany_top_in ( sb_1__1__72_chany_bottom_out ) , + .ccff_head ( grid_clb_78_ccff_tail ) , + .chany_bottom_out ( cby_1__1__78_chany_bottom_out ) , + .chany_top_out ( cby_1__1__78_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__78_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__78_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__78_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__78_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__78_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__78_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__78_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__78_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__78_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__78_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__78_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__78_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__78_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__78_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__78_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__78_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__78_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9139 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9140 ) , + .Test_en_W_in ( Test_enWires[168] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9141 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9142 ) , + .Test_en_E_out ( Test_enWires[169] ) , .pReset_S_in ( pResetWires[334] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9143 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9144 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9145 ) , + .Reset_W_in ( ResetWires[168] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9146 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9147 ) , + .Reset_E_out ( ResetWires[169] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[272] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[273] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9148 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9149 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9150 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9151 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9152 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9153 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9154 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9155 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9156 ) ) ; +cby_1__1_ cby_7__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9157 } ) , + .chany_bottom_in ( sb_1__1__72_chany_top_out ) , + .chany_top_in ( sb_1__1__73_chany_bottom_out ) , + .ccff_head ( grid_clb_79_ccff_tail ) , + .chany_bottom_out ( cby_1__1__79_chany_bottom_out ) , + .chany_top_out ( cby_1__1__79_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__79_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__79_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__79_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__79_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__79_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__79_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__79_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__79_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__79_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__79_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__79_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__79_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__79_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__79_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__79_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__79_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__79_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9158 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9159 ) , + .Test_en_W_in ( Test_enWires[190] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9160 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9161 ) , + .Test_en_E_out ( Test_enWires[191] ) , .pReset_S_in ( pResetWires[383] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9162 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9163 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9164 ) , + .Reset_W_in ( ResetWires[190] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9165 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9166 ) , + .Reset_E_out ( ResetWires[191] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[275] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[276] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9167 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[97] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9168 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[98] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9169 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9170 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9171 ) , + .clk_2_N_in ( clk_2_wires[97] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9172 ) , + .clk_2_S_out ( clk_2_wires[98] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9173 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9174 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9175 ) ) ; +cby_1__1_ cby_7__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9176 } ) , + .chany_bottom_in ( sb_1__1__73_chany_top_out ) , + .chany_top_in ( sb_1__1__74_chany_bottom_out ) , + .ccff_head ( grid_clb_80_ccff_tail ) , + .chany_bottom_out ( cby_1__1__80_chany_bottom_out ) , + .chany_top_out ( cby_1__1__80_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__80_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__80_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__80_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__80_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__80_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__80_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__80_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__80_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__80_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__80_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__80_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__80_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__80_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__80_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__80_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__80_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__80_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9177 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9178 ) , + .Test_en_W_in ( Test_enWires[212] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9179 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9180 ) , + .Test_en_E_out ( Test_enWires[213] ) , .pReset_S_in ( pResetWires[432] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9181 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9182 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9183 ) , + .Reset_W_in ( ResetWires[212] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9184 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9185 ) , + .Reset_E_out ( ResetWires[213] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[278] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[279] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9186 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9187 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[95] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9188 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[96] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9189 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9190 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9191 ) , + .clk_2_S_in ( clk_2_wires[95] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9192 ) , + .clk_2_N_out ( clk_2_wires[96] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9193 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9194 ) ) ; +cby_1__1_ cby_7__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9195 } ) , + .chany_bottom_in ( sb_1__1__74_chany_top_out ) , + .chany_top_in ( sb_1__1__75_chany_bottom_out ) , + .ccff_head ( grid_clb_81_ccff_tail ) , + .chany_bottom_out ( cby_1__1__81_chany_bottom_out ) , + .chany_top_out ( cby_1__1__81_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__81_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__81_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__81_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__81_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__81_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__81_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__81_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__81_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__81_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__81_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__81_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__81_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__81_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__81_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__81_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__81_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__81_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9196 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9197 ) , + .Test_en_W_in ( Test_enWires[234] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9198 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9199 ) , + .Test_en_E_out ( Test_enWires[235] ) , .pReset_S_in ( pResetWires[481] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9200 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9201 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9202 ) , + .Reset_W_in ( ResetWires[234] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9203 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9204 ) , + .Reset_E_out ( ResetWires[235] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[281] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[282] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9205 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9206 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9207 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9208 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9209 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9210 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9211 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9212 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9213 ) ) ; +cby_1__1_ cby_7__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9214 } ) , + .chany_bottom_in ( sb_1__1__75_chany_top_out ) , + .chany_top_in ( sb_1__1__76_chany_bottom_out ) , + .ccff_head ( grid_clb_82_ccff_tail ) , + .chany_bottom_out ( cby_1__1__82_chany_bottom_out ) , + .chany_top_out ( cby_1__1__82_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__82_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__82_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__82_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__82_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__82_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__82_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__82_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__82_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__82_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__82_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__82_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__82_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__82_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__82_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__82_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__82_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__82_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9215 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9216 ) , + .Test_en_W_in ( Test_enWires[256] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9217 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9218 ) , + .Test_en_E_out ( Test_enWires[257] ) , .pReset_S_in ( pResetWires[530] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9219 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9220 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9221 ) , + .Reset_W_in ( ResetWires[256] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9222 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9223 ) , + .Reset_E_out ( ResetWires[257] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[284] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[285] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9224 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9225 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[108] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9226 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[109] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9227 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9228 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9229 ) , + .clk_2_S_in ( clk_2_wires[108] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9230 ) , + .clk_2_N_out ( clk_2_wires[109] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9231 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9232 ) ) ; +cby_1__1_ cby_7__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9233 } ) , + .chany_bottom_in ( sb_1__1__76_chany_top_out ) , + .chany_top_in ( sb_1__12__6_chany_bottom_out ) , + .ccff_head ( grid_clb_83_ccff_tail ) , + .chany_bottom_out ( cby_1__1__83_chany_bottom_out ) , + .chany_top_out ( cby_1__1__83_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__83_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__83_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__83_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__83_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__83_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__83_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__83_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__83_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__83_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__83_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__83_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__83_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__83_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__83_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__83_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__83_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__83_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9234 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9235 ) , + .Test_en_W_in ( Test_enWires[278] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9236 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9237 ) , + .Test_en_E_out ( Test_enWires[279] ) , .pReset_S_in ( pResetWires[579] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9238 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9239 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9240 ) , + .Reset_W_in ( ResetWires[278] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9241 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9242 ) , + .Reset_E_out ( ResetWires[279] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[287] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[288] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[290] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9243 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9244 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9245 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9246 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9247 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9248 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9249 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9250 ) ) ; +cby_1__1_ cby_8__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9251 } ) , + .chany_bottom_in ( sb_1__0__7_chany_top_out ) , + .chany_top_in ( sb_1__1__77_chany_bottom_out ) , + .ccff_head ( grid_clb_84_ccff_tail ) , + .chany_bottom_out ( cby_1__1__84_chany_bottom_out ) , + .chany_top_out ( cby_1__1__84_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__84_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__84_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__84_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__84_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__84_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__84_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__84_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__84_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__84_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__84_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__84_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__84_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__84_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__84_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__84_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__84_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__84_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9252 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9253 ) , + .Test_en_W_in ( Test_enWires[38] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9254 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9255 ) , + .Test_en_E_out ( Test_enWires[39] ) , .pReset_S_in ( pResetWires[48] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9256 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9257 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9258 ) , + .Reset_W_in ( ResetWires[38] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9259 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9260 ) , + .Reset_E_out ( ResetWires[39] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[292] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[293] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9261 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9262 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9263 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9264 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9265 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9266 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9267 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9268 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9269 ) ) ; +cby_1__1_ cby_8__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9270 } ) , + .chany_bottom_in ( sb_1__1__77_chany_top_out ) , + .chany_top_in ( sb_1__1__78_chany_bottom_out ) , + .ccff_head ( grid_clb_85_ccff_tail ) , + .chany_bottom_out ( cby_1__1__85_chany_bottom_out ) , + .chany_top_out ( cby_1__1__85_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__85_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__85_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__85_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__85_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__85_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__85_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__85_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__85_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__85_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__85_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__85_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__85_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__85_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__85_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__85_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__85_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__85_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9271 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9272 ) , + .Test_en_W_in ( Test_enWires[60] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9273 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9274 ) , + .Test_en_E_out ( Test_enWires[61] ) , .pReset_S_in ( pResetWires[93] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9275 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9276 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9277 ) , + .Reset_W_in ( ResetWires[60] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9278 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9279 ) , + .Reset_E_out ( ResetWires[61] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[295] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[296] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9280 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9281 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9282 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9283 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9284 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9285 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9286 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9287 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9288 ) ) ; +cby_1__1_ cby_8__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9289 } ) , + .chany_bottom_in ( sb_1__1__78_chany_top_out ) , + .chany_top_in ( sb_1__1__79_chany_bottom_out ) , + .ccff_head ( grid_clb_86_ccff_tail ) , + .chany_bottom_out ( cby_1__1__86_chany_bottom_out ) , + .chany_top_out ( cby_1__1__86_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__86_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__86_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__86_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__86_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__86_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__86_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__86_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__86_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__86_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__86_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__86_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__86_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__86_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__86_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__86_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__86_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__86_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9290 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9291 ) , + .Test_en_W_in ( Test_enWires[82] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9292 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9293 ) , + .Test_en_E_out ( Test_enWires[83] ) , .pReset_S_in ( pResetWires[142] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9294 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9295 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9296 ) , + .Reset_W_in ( ResetWires[82] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9297 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9298 ) , + .Reset_E_out ( ResetWires[83] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[298] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[299] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9299 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9300 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9301 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9302 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[42] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9303 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[43] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9304 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9305 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9306 ) , + .clk_3_N_in ( clk_3_wires[42] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9307 ) , + .clk_3_S_out ( clk_3_wires[43] ) ) ; +cby_1__1_ cby_8__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9308 } ) , + .chany_bottom_in ( sb_1__1__79_chany_top_out ) , + .chany_top_in ( sb_1__1__80_chany_bottom_out ) , + .ccff_head ( grid_clb_87_ccff_tail ) , + .chany_bottom_out ( cby_1__1__87_chany_bottom_out ) , + .chany_top_out ( cby_1__1__87_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__87_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__87_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__87_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__87_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__87_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__87_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__87_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__87_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__87_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__87_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__87_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__87_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__87_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__87_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__87_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__87_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__87_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9309 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9310 ) , + .Test_en_W_in ( Test_enWires[104] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9311 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9312 ) , + .Test_en_E_out ( Test_enWires[105] ) , .pReset_S_in ( pResetWires[191] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9313 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9314 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9315 ) , + .Reset_W_in ( ResetWires[104] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9316 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9317 ) , + .Reset_E_out ( ResetWires[105] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[301] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[302] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9318 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9319 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9320 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9321 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[38] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9322 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[39] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9323 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9324 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9325 ) , + .clk_3_N_in ( clk_3_wires[38] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9326 ) , + .clk_3_S_out ( clk_3_wires[39] ) ) ; +cby_1__1_ cby_8__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9327 } ) , + .chany_bottom_in ( sb_1__1__80_chany_top_out ) , + .chany_top_in ( sb_1__1__81_chany_bottom_out ) , + .ccff_head ( grid_clb_88_ccff_tail ) , + .chany_bottom_out ( cby_1__1__88_chany_bottom_out ) , + .chany_top_out ( cby_1__1__88_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__88_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__88_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__88_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__88_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__88_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__88_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__88_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__88_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__88_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__88_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__88_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__88_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__88_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__88_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__88_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__88_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__88_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9328 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9329 ) , + .Test_en_W_in ( Test_enWires[126] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9330 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9331 ) , + .Test_en_E_out ( Test_enWires[127] ) , .pReset_S_in ( pResetWires[240] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9332 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9333 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9334 ) , + .Reset_W_in ( ResetWires[126] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9335 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9336 ) , + .Reset_E_out ( ResetWires[127] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[304] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[305] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9337 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9338 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9339 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9340 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[32] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9341 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[33] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9342 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9343 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9344 ) , + .clk_3_N_in ( clk_3_wires[32] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9345 ) , + .clk_3_S_out ( clk_3_wires[33] ) ) ; +cby_1__1_ cby_8__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9346 } ) , + .chany_bottom_in ( sb_1__1__81_chany_top_out ) , + .chany_top_in ( sb_1__1__82_chany_bottom_out ) , + .ccff_head ( grid_clb_89_ccff_tail ) , + .chany_bottom_out ( cby_1__1__89_chany_bottom_out ) , + .chany_top_out ( cby_1__1__89_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__89_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__89_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__89_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__89_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__89_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__89_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__89_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__89_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__89_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__89_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__89_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__89_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__89_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__89_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__89_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__89_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__89_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9347 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9348 ) , + .Test_en_W_in ( Test_enWires[148] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9349 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9350 ) , + .Test_en_E_out ( Test_enWires[149] ) , .pReset_S_in ( pResetWires[289] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9351 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9352 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9353 ) , + .Reset_W_in ( ResetWires[148] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9354 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9355 ) , + .Reset_E_out ( ResetWires[149] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[307] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[308] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9356 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9357 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9358 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9359 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[28] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9360 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[29] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9361 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9362 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9363 ) , + .clk_3_N_in ( clk_3_wires[28] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9364 ) , + .clk_3_S_out ( clk_3_wires[29] ) ) ; +cby_1__1_ cby_8__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9365 } ) , + .chany_bottom_in ( sb_1__1__82_chany_top_out ) , + .chany_top_in ( sb_1__1__83_chany_bottom_out ) , + .ccff_head ( grid_clb_90_ccff_tail ) , + .chany_bottom_out ( cby_1__1__90_chany_bottom_out ) , + .chany_top_out ( cby_1__1__90_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__90_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__90_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__90_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__90_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__90_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__90_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__90_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__90_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__90_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__90_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__90_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__90_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__90_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__90_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__90_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__90_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__90_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9366 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9367 ) , + .Test_en_W_in ( Test_enWires[170] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9368 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9369 ) , + .Test_en_E_out ( Test_enWires[171] ) , .pReset_S_in ( pResetWires[338] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9370 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9371 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9372 ) , + .Reset_W_in ( ResetWires[170] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9373 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9374 ) , + .Reset_E_out ( ResetWires[171] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[310] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[311] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9375 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9376 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9377 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[26] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9378 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[27] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9379 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9380 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9381 ) , + .clk_3_S_in ( clk_3_wires[26] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9382 ) , + .clk_3_N_out ( clk_3_wires[27] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9383 ) ) ; +cby_1__1_ cby_8__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9384 } ) , + .chany_bottom_in ( sb_1__1__83_chany_top_out ) , + .chany_top_in ( sb_1__1__84_chany_bottom_out ) , + .ccff_head ( grid_clb_91_ccff_tail ) , + .chany_bottom_out ( cby_1__1__91_chany_bottom_out ) , + .chany_top_out ( cby_1__1__91_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__91_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__91_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__91_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__91_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__91_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__91_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__91_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__91_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__91_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__91_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__91_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__91_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__91_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__91_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__91_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__91_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__91_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9385 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9386 ) , + .Test_en_W_in ( Test_enWires[192] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9387 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9388 ) , + .Test_en_E_out ( Test_enWires[193] ) , .pReset_S_in ( pResetWires[387] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9389 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9390 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9391 ) , + .Reset_W_in ( ResetWires[192] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9392 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9393 ) , + .Reset_E_out ( ResetWires[193] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[313] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[314] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9394 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9395 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9396 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[30] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9397 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[31] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9398 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9399 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9400 ) , + .clk_3_S_in ( clk_3_wires[30] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9401 ) , + .clk_3_N_out ( clk_3_wires[31] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9402 ) ) ; +cby_1__1_ cby_8__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9403 } ) , + .chany_bottom_in ( sb_1__1__84_chany_top_out ) , + .chany_top_in ( sb_1__1__85_chany_bottom_out ) , + .ccff_head ( grid_clb_92_ccff_tail ) , + .chany_bottom_out ( cby_1__1__92_chany_bottom_out ) , + .chany_top_out ( cby_1__1__92_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__92_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__92_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__92_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__92_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__92_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__92_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__92_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__92_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__92_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__92_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__92_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__92_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__92_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__92_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__92_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__92_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__92_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9404 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9405 ) , + .Test_en_W_in ( Test_enWires[214] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9406 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9407 ) , + .Test_en_E_out ( Test_enWires[215] ) , .pReset_S_in ( pResetWires[436] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9408 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9409 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9410 ) , + .Reset_W_in ( ResetWires[214] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9411 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9412 ) , + .Reset_E_out ( ResetWires[215] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[316] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[317] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9413 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9414 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9415 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[36] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9416 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[37] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9417 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9418 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9419 ) , + .clk_3_S_in ( clk_3_wires[36] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9420 ) , + .clk_3_N_out ( clk_3_wires[37] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9421 ) ) ; +cby_1__1_ cby_8__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9422 } ) , + .chany_bottom_in ( sb_1__1__85_chany_top_out ) , + .chany_top_in ( sb_1__1__86_chany_bottom_out ) , + .ccff_head ( grid_clb_93_ccff_tail ) , + .chany_bottom_out ( cby_1__1__93_chany_bottom_out ) , + .chany_top_out ( cby_1__1__93_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__93_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__93_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__93_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__93_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__93_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__93_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__93_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__93_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__93_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__93_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__93_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__93_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__93_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__93_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__93_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__93_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__93_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9423 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9424 ) , + .Test_en_W_in ( Test_enWires[236] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9425 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9426 ) , + .Test_en_E_out ( Test_enWires[237] ) , .pReset_S_in ( pResetWires[485] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9427 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9428 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9429 ) , + .Reset_W_in ( ResetWires[236] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9430 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9431 ) , + .Reset_E_out ( ResetWires[237] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[319] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[320] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9432 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9433 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9434 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[40] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9435 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[41] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9436 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9437 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9438 ) , + .clk_3_S_in ( clk_3_wires[40] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9439 ) , + .clk_3_N_out ( clk_3_wires[41] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9440 ) ) ; +cby_1__1_ cby_8__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9441 } ) , + .chany_bottom_in ( sb_1__1__86_chany_top_out ) , + .chany_top_in ( sb_1__1__87_chany_bottom_out ) , + .ccff_head ( grid_clb_94_ccff_tail ) , + .chany_bottom_out ( cby_1__1__94_chany_bottom_out ) , + .chany_top_out ( cby_1__1__94_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__94_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__94_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__94_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__94_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__94_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__94_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__94_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__94_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__94_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__94_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__94_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__94_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__94_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__94_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__94_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__94_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__94_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9442 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9443 ) , + .Test_en_W_in ( Test_enWires[258] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9444 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9445 ) , + .Test_en_E_out ( Test_enWires[259] ) , .pReset_S_in ( pResetWires[534] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9446 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9447 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9448 ) , + .Reset_W_in ( ResetWires[258] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9449 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9450 ) , + .Reset_E_out ( ResetWires[259] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[322] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[323] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9451 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9452 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9453 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9454 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9455 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9456 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9457 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9458 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9459 ) ) ; +cby_1__1_ cby_8__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9460 } ) , + .chany_bottom_in ( sb_1__1__87_chany_top_out ) , + .chany_top_in ( sb_1__12__7_chany_bottom_out ) , + .ccff_head ( grid_clb_95_ccff_tail ) , + .chany_bottom_out ( cby_1__1__95_chany_bottom_out ) , + .chany_top_out ( cby_1__1__95_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__95_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__95_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__95_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__95_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__95_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__95_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__95_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__95_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__95_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__95_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__95_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__95_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__95_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__95_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__95_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__95_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__95_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9461 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9462 ) , + .Test_en_W_in ( Test_enWires[280] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9463 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9464 ) , + .Test_en_E_out ( Test_enWires[281] ) , .pReset_S_in ( pResetWires[583] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9465 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9466 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9467 ) , + .Reset_W_in ( ResetWires[280] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9468 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9469 ) , + .Reset_E_out ( ResetWires[281] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[325] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[326] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[328] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9470 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9471 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9472 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9473 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9474 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9475 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9476 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9477 ) ) ; +cby_1__1_ cby_9__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9478 } ) , + .chany_bottom_in ( sb_1__0__8_chany_top_out ) , + .chany_top_in ( sb_1__1__88_chany_bottom_out ) , + .ccff_head ( grid_clb_96_ccff_tail ) , + .chany_bottom_out ( cby_1__1__96_chany_bottom_out ) , + .chany_top_out ( cby_1__1__96_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__96_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__96_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__96_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__96_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__96_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__96_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__96_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__96_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__96_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__96_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__96_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__96_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__96_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__96_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__96_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__96_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__96_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9479 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9480 ) , + .Test_en_W_in ( Test_enWires[40] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9481 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9482 ) , + .Test_en_E_out ( Test_enWires[41] ) , .pReset_S_in ( pResetWires[51] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9483 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9484 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9485 ) , + .Reset_W_in ( ResetWires[40] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9486 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9487 ) , + .Reset_E_out ( ResetWires[41] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[330] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[331] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9488 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9489 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9490 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9491 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9492 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9493 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9494 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9495 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9496 ) ) ; +cby_1__1_ cby_9__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9497 } ) , + .chany_bottom_in ( sb_1__1__88_chany_top_out ) , + .chany_top_in ( sb_1__1__89_chany_bottom_out ) , + .ccff_head ( grid_clb_97_ccff_tail ) , + .chany_bottom_out ( cby_1__1__97_chany_bottom_out ) , + .chany_top_out ( cby_1__1__97_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__97_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__97_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__97_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__97_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__97_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__97_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__97_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__97_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__97_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__97_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__97_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__97_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__97_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__97_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__97_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__97_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__97_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9498 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9499 ) , + .Test_en_W_in ( Test_enWires[62] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9500 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9501 ) , + .Test_en_E_out ( Test_enWires[63] ) , .pReset_S_in ( pResetWires[97] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9502 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9503 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9504 ) , + .Reset_W_in ( ResetWires[62] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9505 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9506 ) , + .Reset_E_out ( ResetWires[63] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[333] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[334] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9507 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[75] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9508 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[76] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9509 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9510 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9511 ) , + .clk_2_N_in ( clk_2_wires[75] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9512 ) , + .clk_2_S_out ( clk_2_wires[76] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9513 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9514 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9515 ) ) ; +cby_1__1_ cby_9__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9516 } ) , + .chany_bottom_in ( sb_1__1__89_chany_top_out ) , + .chany_top_in ( sb_1__1__90_chany_bottom_out ) , + .ccff_head ( grid_clb_98_ccff_tail ) , + .chany_bottom_out ( cby_1__1__98_chany_bottom_out ) , + .chany_top_out ( cby_1__1__98_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__98_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__98_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__98_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__98_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__98_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__98_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__98_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__98_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__98_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__98_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__98_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__98_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__98_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__98_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__98_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__98_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__98_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9517 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9518 ) , + .Test_en_W_in ( Test_enWires[84] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9519 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9520 ) , + .Test_en_E_out ( Test_enWires[85] ) , .pReset_S_in ( pResetWires[146] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9521 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9522 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9523 ) , + .Reset_W_in ( ResetWires[84] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9524 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9525 ) , + .Reset_E_out ( ResetWires[85] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[336] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[337] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9526 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9527 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9528 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9529 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9530 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9531 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9532 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9533 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9534 ) ) ; +cby_1__1_ cby_9__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9535 } ) , + .chany_bottom_in ( sb_1__1__90_chany_top_out ) , + .chany_top_in ( sb_1__1__91_chany_bottom_out ) , + .ccff_head ( grid_clb_99_ccff_tail ) , + .chany_bottom_out ( cby_1__1__99_chany_bottom_out ) , + .chany_top_out ( cby_1__1__99_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__99_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__99_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__99_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__99_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__99_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__99_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__99_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__99_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__99_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__99_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__99_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__99_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__99_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__99_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__99_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__99_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__99_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9536 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9537 ) , + .Test_en_W_in ( Test_enWires[106] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9538 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9539 ) , + .Test_en_E_out ( Test_enWires[107] ) , .pReset_S_in ( pResetWires[195] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9540 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9541 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9542 ) , + .Reset_W_in ( ResetWires[106] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9543 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9544 ) , + .Reset_E_out ( ResetWires[107] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[339] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[340] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9545 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[88] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9546 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[89] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9547 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9548 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9549 ) , + .clk_2_N_in ( clk_2_wires[88] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9550 ) , + .clk_2_S_out ( clk_2_wires[89] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9551 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9552 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9553 ) ) ; +cby_1__1_ cby_9__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9554 } ) , + .chany_bottom_in ( sb_1__1__91_chany_top_out ) , + .chany_top_in ( sb_1__1__92_chany_bottom_out ) , + .ccff_head ( grid_clb_100_ccff_tail ) , + .chany_bottom_out ( cby_1__1__100_chany_bottom_out ) , + .chany_top_out ( cby_1__1__100_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__100_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__100_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__100_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__100_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__100_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__100_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__100_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__100_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__100_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__100_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__100_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__100_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__100_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__100_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__100_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__100_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__100_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9555 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9556 ) , + .Test_en_W_in ( Test_enWires[128] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9557 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9558 ) , + .Test_en_E_out ( Test_enWires[129] ) , .pReset_S_in ( pResetWires[244] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9559 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9560 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9561 ) , + .Reset_W_in ( ResetWires[128] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9562 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9563 ) , + .Reset_E_out ( ResetWires[129] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[342] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[343] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9564 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9565 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[86] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9566 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[87] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9567 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9568 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9569 ) , + .clk_2_S_in ( clk_2_wires[86] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9570 ) , + .clk_2_N_out ( clk_2_wires[87] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9571 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9572 ) ) ; +cby_1__1_ cby_9__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9573 } ) , + .chany_bottom_in ( sb_1__1__92_chany_top_out ) , + .chany_top_in ( sb_1__1__93_chany_bottom_out ) , + .ccff_head ( grid_clb_101_ccff_tail ) , + .chany_bottom_out ( cby_1__1__101_chany_bottom_out ) , + .chany_top_out ( cby_1__1__101_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__101_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__101_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__101_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__101_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__101_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__101_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__101_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__101_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__101_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__101_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__101_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__101_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__101_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__101_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__101_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__101_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__101_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9574 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9575 ) , + .Test_en_W_in ( Test_enWires[150] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9576 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9577 ) , + .Test_en_E_out ( Test_enWires[151] ) , .pReset_S_in ( pResetWires[293] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9578 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9579 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9580 ) , + .Reset_W_in ( ResetWires[150] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9581 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9582 ) , + .Reset_E_out ( ResetWires[151] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[345] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[346] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9583 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9584 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9585 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9586 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9587 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9588 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9589 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9590 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9591 ) ) ; +cby_1__1_ cby_9__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9592 } ) , + .chany_bottom_in ( sb_1__1__93_chany_top_out ) , + .chany_top_in ( sb_1__1__94_chany_bottom_out ) , + .ccff_head ( grid_clb_102_ccff_tail ) , + .chany_bottom_out ( cby_1__1__102_chany_bottom_out ) , + .chany_top_out ( cby_1__1__102_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__102_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__102_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__102_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__102_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__102_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__102_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__102_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__102_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__102_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__102_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__102_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__102_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__102_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__102_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__102_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__102_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__102_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9593 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9594 ) , + .Test_en_W_in ( Test_enWires[172] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9595 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9596 ) , + .Test_en_E_out ( Test_enWires[173] ) , .pReset_S_in ( pResetWires[342] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9597 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9598 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9599 ) , + .Reset_W_in ( ResetWires[172] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9600 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9601 ) , + .Reset_E_out ( ResetWires[173] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[348] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[349] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9602 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9603 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9604 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9605 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9606 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9607 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9608 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9609 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9610 ) ) ; +cby_1__1_ cby_9__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9611 } ) , + .chany_bottom_in ( sb_1__1__94_chany_top_out ) , + .chany_top_in ( sb_1__1__95_chany_bottom_out ) , + .ccff_head ( grid_clb_103_ccff_tail ) , + .chany_bottom_out ( cby_1__1__103_chany_bottom_out ) , + .chany_top_out ( cby_1__1__103_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__103_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__103_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__103_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__103_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__103_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__103_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__103_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__103_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__103_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__103_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__103_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__103_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__103_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__103_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__103_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__103_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__103_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9612 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9613 ) , + .Test_en_W_in ( Test_enWires[194] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9614 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9615 ) , + .Test_en_E_out ( Test_enWires[195] ) , .pReset_S_in ( pResetWires[391] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9616 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9617 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9618 ) , + .Reset_W_in ( ResetWires[194] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9619 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9620 ) , + .Reset_E_out ( ResetWires[195] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[351] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[352] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9621 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[101] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9622 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[102] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9623 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9624 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9625 ) , + .clk_2_N_in ( clk_2_wires[101] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9626 ) , + .clk_2_S_out ( clk_2_wires[102] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9627 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9628 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9629 ) ) ; +cby_1__1_ cby_9__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9630 } ) , + .chany_bottom_in ( sb_1__1__95_chany_top_out ) , + .chany_top_in ( sb_1__1__96_chany_bottom_out ) , + .ccff_head ( grid_clb_104_ccff_tail ) , + .chany_bottom_out ( cby_1__1__104_chany_bottom_out ) , + .chany_top_out ( cby_1__1__104_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__104_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__104_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__104_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__104_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__104_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__104_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__104_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__104_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__104_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__104_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__104_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__104_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__104_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__104_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__104_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__104_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__104_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9631 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9632 ) , + .Test_en_W_in ( Test_enWires[216] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9633 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9634 ) , + .Test_en_E_out ( Test_enWires[217] ) , .pReset_S_in ( pResetWires[440] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9635 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9636 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9637 ) , + .Reset_W_in ( ResetWires[216] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9638 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9639 ) , + .Reset_E_out ( ResetWires[217] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[354] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[355] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9640 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9641 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[99] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9642 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[100] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9643 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9644 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9645 ) , + .clk_2_S_in ( clk_2_wires[99] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9646 ) , + .clk_2_N_out ( clk_2_wires[100] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9647 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9648 ) ) ; +cby_1__1_ cby_9__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9649 } ) , + .chany_bottom_in ( sb_1__1__96_chany_top_out ) , + .chany_top_in ( sb_1__1__97_chany_bottom_out ) , + .ccff_head ( grid_clb_105_ccff_tail ) , + .chany_bottom_out ( cby_1__1__105_chany_bottom_out ) , + .chany_top_out ( cby_1__1__105_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__105_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__105_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__105_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__105_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__105_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__105_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__105_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__105_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__105_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__105_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__105_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__105_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__105_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__105_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__105_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__105_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__105_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9650 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9651 ) , + .Test_en_W_in ( Test_enWires[238] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9652 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9653 ) , + .Test_en_E_out ( Test_enWires[239] ) , .pReset_S_in ( pResetWires[489] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9654 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9655 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9656 ) , + .Reset_W_in ( ResetWires[238] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9657 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9658 ) , + .Reset_E_out ( ResetWires[239] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[357] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[358] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9659 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9660 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9661 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9662 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9663 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9664 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9665 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9666 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9667 ) ) ; +cby_1__1_ cby_9__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9668 } ) , + .chany_bottom_in ( sb_1__1__97_chany_top_out ) , + .chany_top_in ( sb_1__1__98_chany_bottom_out ) , + .ccff_head ( grid_clb_106_ccff_tail ) , + .chany_bottom_out ( cby_1__1__106_chany_bottom_out ) , + .chany_top_out ( cby_1__1__106_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__106_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__106_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__106_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__106_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__106_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__106_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__106_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__106_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__106_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__106_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__106_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__106_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__106_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__106_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__106_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__106_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__106_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9669 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9670 ) , + .Test_en_W_in ( Test_enWires[260] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9671 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9672 ) , + .Test_en_E_out ( Test_enWires[261] ) , .pReset_S_in ( pResetWires[538] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9673 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9674 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9675 ) , + .Reset_W_in ( ResetWires[260] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9676 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9677 ) , + .Reset_E_out ( ResetWires[261] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[360] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[361] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9678 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_9679 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[110] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9680 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[111] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9681 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9682 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_9683 ) , + .clk_2_S_in ( clk_2_wires[110] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9684 ) , + .clk_2_N_out ( clk_2_wires[111] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9685 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9686 ) ) ; +cby_1__1_ cby_9__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9687 } ) , + .chany_bottom_in ( sb_1__1__98_chany_top_out ) , + .chany_top_in ( sb_1__12__8_chany_bottom_out ) , + .ccff_head ( grid_clb_107_ccff_tail ) , + .chany_bottom_out ( cby_1__1__107_chany_bottom_out ) , + .chany_top_out ( cby_1__1__107_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__107_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__107_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__107_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__107_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__107_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__107_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__107_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__107_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__107_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__107_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__107_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__107_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__107_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__107_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__107_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__107_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__107_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9688 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9689 ) , + .Test_en_W_in ( Test_enWires[282] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9690 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9691 ) , + .Test_en_E_out ( Test_enWires[283] ) , .pReset_S_in ( pResetWires[587] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9692 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9693 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9694 ) , + .Reset_W_in ( ResetWires[282] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9695 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9696 ) , + .Reset_E_out ( ResetWires[283] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[363] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[364] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[366] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9697 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9698 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9699 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9700 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9701 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9702 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9703 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9704 ) ) ; +cby_1__1_ cby_10__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9705 } ) , + .chany_bottom_in ( sb_1__0__9_chany_top_out ) , + .chany_top_in ( sb_1__1__99_chany_bottom_out ) , + .ccff_head ( grid_clb_108_ccff_tail ) , + .chany_bottom_out ( cby_1__1__108_chany_bottom_out ) , + .chany_top_out ( cby_1__1__108_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__108_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__108_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__108_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__108_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__108_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__108_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__108_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__108_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__108_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__108_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__108_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__108_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__108_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__108_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__108_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__108_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__108_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9706 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9707 ) , + .Test_en_W_in ( Test_enWires[42] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9708 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9709 ) , + .Test_en_E_out ( Test_enWires[43] ) , .pReset_S_in ( pResetWires[54] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9710 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9711 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9712 ) , + .Reset_W_in ( ResetWires[42] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9713 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9714 ) , + .Reset_E_out ( ResetWires[43] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[368] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[369] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9715 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9716 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9717 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9718 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9719 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9720 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9721 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9722 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9723 ) ) ; +cby_1__1_ cby_10__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9724 } ) , + .chany_bottom_in ( sb_1__1__99_chany_top_out ) , + .chany_top_in ( sb_1__1__100_chany_bottom_out ) , + .ccff_head ( grid_clb_109_ccff_tail ) , + .chany_bottom_out ( cby_1__1__109_chany_bottom_out ) , + .chany_top_out ( cby_1__1__109_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__109_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__109_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__109_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__109_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__109_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__109_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__109_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__109_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__109_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__109_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__109_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__109_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__109_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__109_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__109_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__109_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__109_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9725 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9726 ) , + .Test_en_W_in ( Test_enWires[64] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9727 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9728 ) , + .Test_en_E_out ( Test_enWires[65] ) , .pReset_S_in ( pResetWires[101] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9729 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9730 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9731 ) , + .Reset_W_in ( ResetWires[64] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9732 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9733 ) , + .Reset_E_out ( ResetWires[65] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[371] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[372] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9734 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9735 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9736 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9737 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9738 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9739 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9740 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9741 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9742 ) ) ; +cby_1__1_ cby_10__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9743 } ) , + .chany_bottom_in ( sb_1__1__100_chany_top_out ) , + .chany_top_in ( sb_1__1__101_chany_bottom_out ) , + .ccff_head ( grid_clb_110_ccff_tail ) , + .chany_bottom_out ( cby_1__1__110_chany_bottom_out ) , + .chany_top_out ( cby_1__1__110_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__110_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__110_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__110_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__110_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__110_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__110_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__110_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__110_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__110_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__110_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__110_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__110_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__110_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__110_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__110_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__110_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__110_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9744 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9745 ) , + .Test_en_W_in ( Test_enWires[86] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9746 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9747 ) , + .Test_en_E_out ( Test_enWires[87] ) , .pReset_S_in ( pResetWires[150] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9748 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9749 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9750 ) , + .Reset_W_in ( ResetWires[86] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9751 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9752 ) , + .Reset_E_out ( ResetWires[87] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[374] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[375] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9753 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9754 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9755 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9756 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[86] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9757 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[87] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9758 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9759 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9760 ) , + .clk_3_N_in ( clk_3_wires[86] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9761 ) , + .clk_3_S_out ( clk_3_wires[87] ) ) ; +cby_1__1_ cby_10__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9762 } ) , + .chany_bottom_in ( sb_1__1__101_chany_top_out ) , + .chany_top_in ( sb_1__1__102_chany_bottom_out ) , + .ccff_head ( grid_clb_111_ccff_tail ) , + .chany_bottom_out ( cby_1__1__111_chany_bottom_out ) , + .chany_top_out ( cby_1__1__111_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__111_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__111_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__111_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__111_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__111_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__111_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__111_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__111_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__111_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__111_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__111_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__111_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__111_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__111_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__111_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__111_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__111_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9763 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9764 ) , + .Test_en_W_in ( Test_enWires[108] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9765 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9766 ) , + .Test_en_E_out ( Test_enWires[109] ) , .pReset_S_in ( pResetWires[199] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9767 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9768 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9769 ) , + .Reset_W_in ( ResetWires[108] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9770 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9771 ) , + .Reset_E_out ( ResetWires[109] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[377] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[378] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9772 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9773 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9774 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9775 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[82] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9776 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[83] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9777 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9778 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9779 ) , + .clk_3_N_in ( clk_3_wires[82] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9780 ) , + .clk_3_S_out ( clk_3_wires[83] ) ) ; +cby_1__1_ cby_10__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9781 } ) , + .chany_bottom_in ( sb_1__1__102_chany_top_out ) , + .chany_top_in ( sb_1__1__103_chany_bottom_out ) , + .ccff_head ( grid_clb_112_ccff_tail ) , + .chany_bottom_out ( cby_1__1__112_chany_bottom_out ) , + .chany_top_out ( cby_1__1__112_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__112_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__112_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__112_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__112_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__112_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__112_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__112_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__112_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__112_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__112_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__112_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__112_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__112_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__112_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__112_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__112_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__112_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9782 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9783 ) , + .Test_en_W_in ( Test_enWires[130] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9784 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9785 ) , + .Test_en_E_out ( Test_enWires[131] ) , .pReset_S_in ( pResetWires[248] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9786 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9787 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9788 ) , + .Reset_W_in ( ResetWires[130] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9789 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9790 ) , + .Reset_E_out ( ResetWires[131] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[380] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[381] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9791 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9792 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9793 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9794 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[76] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9795 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[77] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9796 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9797 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9798 ) , + .clk_3_N_in ( clk_3_wires[76] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9799 ) , + .clk_3_S_out ( clk_3_wires[77] ) ) ; +cby_1__1_ cby_10__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9800 } ) , + .chany_bottom_in ( sb_1__1__103_chany_top_out ) , + .chany_top_in ( sb_1__1__104_chany_bottom_out ) , + .ccff_head ( grid_clb_113_ccff_tail ) , + .chany_bottom_out ( cby_1__1__113_chany_bottom_out ) , + .chany_top_out ( cby_1__1__113_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__113_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__113_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__113_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__113_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__113_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__113_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__113_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__113_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__113_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__113_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__113_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__113_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__113_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__113_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__113_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__113_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__113_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9801 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9802 ) , + .Test_en_W_in ( Test_enWires[152] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9803 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9804 ) , + .Test_en_E_out ( Test_enWires[153] ) , .pReset_S_in ( pResetWires[297] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9805 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9806 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9807 ) , + .Reset_W_in ( ResetWires[152] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9808 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9809 ) , + .Reset_E_out ( ResetWires[153] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[383] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[384] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9810 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9811 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9812 ) , + .prog_clk_3_S_in ( SYNOPSYS_UNCONNECTED_9813 ) , + .prog_clk_3_N_in ( prog_clk_3_wires[72] ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9814 ) , + .prog_clk_3_S_out ( prog_clk_3_wires[73] ) , .clk_2_N_in ( h_incr0 ) , + .clk_2_S_in ( h_incr0 ) , .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9815 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9816 ) , + .clk_3_S_in ( SYNOPSYS_UNCONNECTED_9817 ) , + .clk_3_N_in ( clk_3_wires[72] ) , + .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9818 ) , + .clk_3_S_out ( clk_3_wires[73] ) ) ; +cby_1__1_ cby_10__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9819 } ) , + .chany_bottom_in ( sb_1__1__104_chany_top_out ) , + .chany_top_in ( sb_1__1__105_chany_bottom_out ) , + .ccff_head ( grid_clb_114_ccff_tail ) , + .chany_bottom_out ( cby_1__1__114_chany_bottom_out ) , + .chany_top_out ( cby_1__1__114_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__114_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__114_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__114_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__114_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__114_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__114_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__114_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__114_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__114_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__114_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__114_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__114_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__114_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__114_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__114_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__114_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__114_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9820 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9821 ) , + .Test_en_W_in ( Test_enWires[174] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9822 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9823 ) , + .Test_en_E_out ( Test_enWires[175] ) , .pReset_S_in ( pResetWires[346] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9824 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9825 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9826 ) , + .Reset_W_in ( ResetWires[174] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9827 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9828 ) , + .Reset_E_out ( ResetWires[175] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[386] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[387] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9829 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9830 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9831 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[70] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9832 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[71] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9833 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9834 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9835 ) , + .clk_3_S_in ( clk_3_wires[70] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9836 ) , + .clk_3_N_out ( clk_3_wires[71] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9837 ) ) ; +cby_1__1_ cby_10__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9838 } ) , + .chany_bottom_in ( sb_1__1__105_chany_top_out ) , + .chany_top_in ( sb_1__1__106_chany_bottom_out ) , + .ccff_head ( grid_clb_115_ccff_tail ) , + .chany_bottom_out ( cby_1__1__115_chany_bottom_out ) , + .chany_top_out ( cby_1__1__115_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__115_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__115_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__115_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__115_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__115_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__115_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__115_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__115_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__115_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__115_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__115_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__115_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__115_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__115_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__115_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__115_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__115_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9839 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9840 ) , + .Test_en_W_in ( Test_enWires[196] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9841 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9842 ) , + .Test_en_E_out ( Test_enWires[197] ) , .pReset_S_in ( pResetWires[395] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9843 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9844 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9845 ) , + .Reset_W_in ( ResetWires[196] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9846 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9847 ) , + .Reset_E_out ( ResetWires[197] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[389] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[390] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9848 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9849 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9850 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[74] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9851 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[75] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9852 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9853 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9854 ) , + .clk_3_S_in ( clk_3_wires[74] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9855 ) , + .clk_3_N_out ( clk_3_wires[75] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9856 ) ) ; +cby_1__1_ cby_10__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9857 } ) , + .chany_bottom_in ( sb_1__1__106_chany_top_out ) , + .chany_top_in ( sb_1__1__107_chany_bottom_out ) , + .ccff_head ( grid_clb_116_ccff_tail ) , + .chany_bottom_out ( cby_1__1__116_chany_bottom_out ) , + .chany_top_out ( cby_1__1__116_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__116_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__116_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__116_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__116_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__116_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__116_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__116_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__116_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__116_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__116_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__116_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__116_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__116_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__116_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__116_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__116_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__116_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9858 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9859 ) , + .Test_en_W_in ( Test_enWires[218] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9860 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9861 ) , + .Test_en_E_out ( Test_enWires[219] ) , .pReset_S_in ( pResetWires[444] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9862 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9863 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9864 ) , + .Reset_W_in ( ResetWires[218] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9865 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9866 ) , + .Reset_E_out ( ResetWires[219] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[392] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[393] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9867 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9868 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9869 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[80] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9870 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[81] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9871 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9872 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9873 ) , + .clk_3_S_in ( clk_3_wires[80] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9874 ) , + .clk_3_N_out ( clk_3_wires[81] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9875 ) ) ; +cby_1__1_ cby_10__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9876 } ) , + .chany_bottom_in ( sb_1__1__107_chany_top_out ) , + .chany_top_in ( sb_1__1__108_chany_bottom_out ) , + .ccff_head ( grid_clb_117_ccff_tail ) , + .chany_bottom_out ( cby_1__1__117_chany_bottom_out ) , + .chany_top_out ( cby_1__1__117_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__117_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__117_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__117_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__117_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__117_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__117_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__117_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__117_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__117_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__117_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__117_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__117_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__117_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__117_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__117_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__117_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__117_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9877 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9878 ) , + .Test_en_W_in ( Test_enWires[240] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9879 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9880 ) , + .Test_en_E_out ( Test_enWires[241] ) , .pReset_S_in ( pResetWires[493] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9881 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9882 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9883 ) , + .Reset_W_in ( ResetWires[240] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9884 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9885 ) , + .Reset_E_out ( ResetWires[241] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[395] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[396] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9886 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9887 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9888 ) , + .prog_clk_3_S_in ( prog_clk_3_wires[84] ) , + .prog_clk_3_N_in ( SYNOPSYS_UNCONNECTED_9889 ) , + .prog_clk_3_N_out ( prog_clk_3_wires[85] ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9890 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9891 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9892 ) , + .clk_3_S_in ( clk_3_wires[84] ) , + .clk_3_N_in ( SYNOPSYS_UNCONNECTED_9893 ) , + .clk_3_N_out ( clk_3_wires[85] ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9894 ) ) ; +cby_1__1_ cby_10__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9895 } ) , + .chany_bottom_in ( sb_1__1__108_chany_top_out ) , + .chany_top_in ( sb_1__1__109_chany_bottom_out ) , + .ccff_head ( grid_clb_118_ccff_tail ) , + .chany_bottom_out ( cby_1__1__118_chany_bottom_out ) , + .chany_top_out ( cby_1__1__118_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__118_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__118_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__118_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__118_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__118_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__118_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__118_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__118_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__118_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__118_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__118_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__118_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__118_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__118_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__118_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__118_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__118_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9896 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9897 ) , + .Test_en_W_in ( Test_enWires[262] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9898 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9899 ) , + .Test_en_E_out ( Test_enWires[263] ) , .pReset_S_in ( pResetWires[542] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9900 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9901 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9902 ) , + .Reset_W_in ( ResetWires[262] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9903 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9904 ) , + .Reset_E_out ( ResetWires[263] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[398] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[399] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9905 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9906 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9907 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9908 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9909 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9910 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9911 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9912 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9913 ) ) ; +cby_1__1_ cby_10__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9914 } ) , + .chany_bottom_in ( sb_1__1__109_chany_top_out ) , + .chany_top_in ( sb_1__12__9_chany_bottom_out ) , + .ccff_head ( grid_clb_119_ccff_tail ) , + .chany_bottom_out ( cby_1__1__119_chany_bottom_out ) , + .chany_top_out ( cby_1__1__119_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__119_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__119_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__119_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__119_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__119_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__119_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__119_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__119_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__119_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__119_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__119_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__119_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__119_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__119_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__119_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__119_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__119_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9915 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9916 ) , + .Test_en_W_in ( Test_enWires[284] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9917 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9918 ) , + .Test_en_E_out ( Test_enWires[285] ) , .pReset_S_in ( pResetWires[591] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9919 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9920 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9921 ) , + .Reset_W_in ( ResetWires[284] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9922 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9923 ) , + .Reset_E_out ( ResetWires[285] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[401] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[402] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[404] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9924 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9925 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9926 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9927 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9928 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9929 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9930 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9931 ) ) ; +cby_1__1_ cby_11__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9932 } ) , + .chany_bottom_in ( sb_1__0__10_chany_top_out ) , + .chany_top_in ( sb_1__1__110_chany_bottom_out ) , + .ccff_head ( grid_clb_120_ccff_tail ) , + .chany_bottom_out ( cby_1__1__120_chany_bottom_out ) , + .chany_top_out ( cby_1__1__120_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__120_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__120_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__120_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__120_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__120_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__120_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__120_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__120_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__120_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__120_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__120_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__120_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__120_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__120_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__120_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__120_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__120_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9933 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9934 ) , + .Test_en_W_in ( Test_enWires[44] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9935 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9936 ) , + .Test_en_E_out ( Test_enWires[45] ) , .pReset_S_in ( pResetWires[57] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9937 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9938 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9939 ) , + .Reset_W_in ( ResetWires[44] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9940 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9941 ) , + .Reset_E_out ( ResetWires[45] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[406] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[407] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9942 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9943 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9944 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9945 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9946 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9947 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9948 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9949 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9950 ) ) ; +cby_1__1_ cby_11__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9951 } ) , + .chany_bottom_in ( sb_1__1__110_chany_top_out ) , + .chany_top_in ( sb_1__1__111_chany_bottom_out ) , + .ccff_head ( grid_clb_121_ccff_tail ) , + .chany_bottom_out ( cby_1__1__121_chany_bottom_out ) , + .chany_top_out ( cby_1__1__121_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__121_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__121_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__121_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__121_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__121_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__121_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__121_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__121_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__121_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__121_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__121_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__121_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__121_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__121_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__121_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__121_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__121_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9952 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9953 ) , + .Test_en_W_in ( Test_enWires[66] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9954 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9955 ) , + .Test_en_E_out ( Test_enWires[67] ) , .pReset_S_in ( pResetWires[105] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9956 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9957 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9958 ) , + .Reset_W_in ( ResetWires[66] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9959 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9960 ) , + .Reset_E_out ( ResetWires[67] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[409] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[410] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9961 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[115] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_9962 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[116] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9963 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9964 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9965 ) , + .clk_2_N_in ( clk_2_wires[115] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_9966 ) , + .clk_2_S_out ( clk_2_wires[116] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9967 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9968 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9969 ) ) ; +cby_1__1_ cby_11__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9970 } ) , + .chany_bottom_in ( sb_1__1__111_chany_top_out ) , + .chany_top_in ( sb_1__1__112_chany_bottom_out ) , + .ccff_head ( grid_clb_122_ccff_tail ) , + .chany_bottom_out ( cby_1__1__122_chany_bottom_out ) , + .chany_top_out ( cby_1__1__122_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__122_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__122_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__122_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__122_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__122_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__122_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__122_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__122_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__122_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__122_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__122_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__122_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__122_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__122_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__122_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__122_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__122_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9971 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9972 ) , + .Test_en_W_in ( Test_enWires[88] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9973 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9974 ) , + .Test_en_E_out ( Test_enWires[89] ) , .pReset_S_in ( pResetWires[154] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9975 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9976 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9977 ) , + .Reset_W_in ( ResetWires[88] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9978 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9979 ) , + .Reset_E_out ( ResetWires[89] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[412] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[413] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9980 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_9981 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_9982 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_9983 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_9984 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_9985 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_9986 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_9987 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_9988 ) ) ; +cby_1__1_ cby_11__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_9989 } ) , + .chany_bottom_in ( sb_1__1__112_chany_top_out ) , + .chany_top_in ( sb_1__1__113_chany_bottom_out ) , + .ccff_head ( grid_clb_123_ccff_tail ) , + .chany_bottom_out ( cby_1__1__123_chany_bottom_out ) , + .chany_top_out ( cby_1__1__123_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__123_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__123_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__123_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__123_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__123_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__123_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__123_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__123_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__123_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__123_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__123_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__123_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__123_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__123_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__123_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__123_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__123_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_9990 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_9991 ) , + .Test_en_W_in ( Test_enWires[110] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_9992 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_9993 ) , + .Test_en_E_out ( Test_enWires[111] ) , .pReset_S_in ( pResetWires[203] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_9994 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_9995 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_9996 ) , + .Reset_W_in ( ResetWires[110] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_9997 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_9998 ) , + .Reset_E_out ( ResetWires[111] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[415] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[416] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_9999 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[122] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10000 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[123] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10001 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10002 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10003 ) , + .clk_2_N_in ( clk_2_wires[122] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10004 ) , + .clk_2_S_out ( clk_2_wires[123] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10005 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10006 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10007 ) ) ; +cby_1__1_ cby_11__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10008 } ) , + .chany_bottom_in ( sb_1__1__113_chany_top_out ) , + .chany_top_in ( sb_1__1__114_chany_bottom_out ) , + .ccff_head ( grid_clb_124_ccff_tail ) , + .chany_bottom_out ( cby_1__1__124_chany_bottom_out ) , + .chany_top_out ( cby_1__1__124_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__124_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__124_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__124_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__124_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__124_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__124_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__124_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__124_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__124_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__124_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__124_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__124_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__124_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__124_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__124_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__124_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__124_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10009 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10010 ) , + .Test_en_W_in ( Test_enWires[132] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10011 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10012 ) , + .Test_en_E_out ( Test_enWires[133] ) , .pReset_S_in ( pResetWires[252] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10013 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10014 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10015 ) , + .Reset_W_in ( ResetWires[132] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10016 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10017 ) , + .Reset_E_out ( ResetWires[133] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[418] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[419] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10018 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10019 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[120] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10020 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[121] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10021 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10022 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10023 ) , + .clk_2_S_in ( clk_2_wires[120] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10024 ) , + .clk_2_N_out ( clk_2_wires[121] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10025 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10026 ) ) ; +cby_1__1_ cby_11__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10027 } ) , + .chany_bottom_in ( sb_1__1__114_chany_top_out ) , + .chany_top_in ( sb_1__1__115_chany_bottom_out ) , + .ccff_head ( grid_clb_125_ccff_tail ) , + .chany_bottom_out ( cby_1__1__125_chany_bottom_out ) , + .chany_top_out ( cby_1__1__125_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__125_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__125_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__125_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__125_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__125_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__125_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__125_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__125_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__125_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__125_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__125_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__125_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__125_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__125_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__125_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__125_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__125_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10028 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10029 ) , + .Test_en_W_in ( Test_enWires[154] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10030 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10031 ) , + .Test_en_E_out ( Test_enWires[155] ) , .pReset_S_in ( pResetWires[301] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10032 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10033 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10034 ) , + .Reset_W_in ( ResetWires[154] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10035 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10036 ) , + .Reset_E_out ( ResetWires[155] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[421] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[422] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10037 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10038 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10039 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10040 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10041 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10042 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10043 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10044 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10045 ) ) ; +cby_1__1_ cby_11__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10046 } ) , + .chany_bottom_in ( sb_1__1__115_chany_top_out ) , + .chany_top_in ( sb_1__1__116_chany_bottom_out ) , + .ccff_head ( grid_clb_126_ccff_tail ) , + .chany_bottom_out ( cby_1__1__126_chany_bottom_out ) , + .chany_top_out ( cby_1__1__126_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__126_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__126_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__126_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__126_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__126_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__126_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__126_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__126_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__126_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__126_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__126_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__126_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__126_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__126_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__126_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__126_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__126_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10047 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10048 ) , + .Test_en_W_in ( Test_enWires[176] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10049 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10050 ) , + .Test_en_E_out ( Test_enWires[177] ) , .pReset_S_in ( pResetWires[350] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10051 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10052 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10053 ) , + .Reset_W_in ( ResetWires[176] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10054 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10055 ) , + .Reset_E_out ( ResetWires[177] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[424] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[425] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10056 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10057 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10058 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10059 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10060 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10061 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10062 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10063 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10064 ) ) ; +cby_1__1_ cby_11__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10065 } ) , + .chany_bottom_in ( sb_1__1__116_chany_top_out ) , + .chany_top_in ( sb_1__1__117_chany_bottom_out ) , + .ccff_head ( grid_clb_127_ccff_tail ) , + .chany_bottom_out ( cby_1__1__127_chany_bottom_out ) , + .chany_top_out ( cby_1__1__127_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__127_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__127_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__127_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__127_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__127_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__127_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__127_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__127_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__127_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__127_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__127_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__127_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__127_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__127_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__127_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__127_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__127_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10066 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10067 ) , + .Test_en_W_in ( Test_enWires[198] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10068 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10069 ) , + .Test_en_E_out ( Test_enWires[199] ) , .pReset_S_in ( pResetWires[399] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10070 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10071 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10072 ) , + .Reset_W_in ( ResetWires[198] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10073 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10074 ) , + .Reset_E_out ( ResetWires[199] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[427] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[428] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10075 ) , + .prog_clk_2_N_in ( prog_clk_2_wires[129] ) , + .prog_clk_2_S_in ( SYNOPSYS_UNCONNECTED_10076 ) , + .prog_clk_2_S_out ( prog_clk_2_wires[130] ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10077 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10078 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10079 ) , + .clk_2_N_in ( clk_2_wires[129] ) , + .clk_2_S_in ( SYNOPSYS_UNCONNECTED_10080 ) , + .clk_2_S_out ( clk_2_wires[130] ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10081 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10082 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10083 ) ) ; +cby_1__1_ cby_11__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10084 } ) , + .chany_bottom_in ( sb_1__1__117_chany_top_out ) , + .chany_top_in ( sb_1__1__118_chany_bottom_out ) , + .ccff_head ( grid_clb_128_ccff_tail ) , + .chany_bottom_out ( cby_1__1__128_chany_bottom_out ) , + .chany_top_out ( cby_1__1__128_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__128_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__128_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__128_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__128_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__128_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__128_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__128_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__128_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__128_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__128_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__128_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__128_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__128_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__128_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__128_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__128_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__128_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10085 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10086 ) , + .Test_en_W_in ( Test_enWires[220] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10087 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10088 ) , + .Test_en_E_out ( Test_enWires[221] ) , .pReset_S_in ( pResetWires[448] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10089 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10090 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10091 ) , + .Reset_W_in ( ResetWires[220] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10092 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10093 ) , + .Reset_E_out ( ResetWires[221] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[430] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[431] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10094 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10095 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[127] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10096 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[128] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10097 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10098 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10099 ) , + .clk_2_S_in ( clk_2_wires[127] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10100 ) , + .clk_2_N_out ( clk_2_wires[128] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10101 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10102 ) ) ; +cby_1__1_ cby_11__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10103 } ) , + .chany_bottom_in ( sb_1__1__118_chany_top_out ) , + .chany_top_in ( sb_1__1__119_chany_bottom_out ) , + .ccff_head ( grid_clb_129_ccff_tail ) , + .chany_bottom_out ( cby_1__1__129_chany_bottom_out ) , + .chany_top_out ( cby_1__1__129_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__129_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__129_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__129_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__129_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__129_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__129_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__129_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__129_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__129_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__129_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__129_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__129_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__129_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__129_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__129_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__129_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__129_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10104 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10105 ) , + .Test_en_W_in ( Test_enWires[242] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10106 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10107 ) , + .Test_en_E_out ( Test_enWires[243] ) , .pReset_S_in ( pResetWires[497] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10108 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10109 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10110 ) , + .Reset_W_in ( ResetWires[242] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10111 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10112 ) , + .Reset_E_out ( ResetWires[243] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[433] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[434] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10113 ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10114 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10115 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10116 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10117 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10118 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10119 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10120 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10121 ) ) ; +cby_1__1_ cby_11__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10122 } ) , + .chany_bottom_in ( sb_1__1__119_chany_top_out ) , + .chany_top_in ( sb_1__1__120_chany_bottom_out ) , + .ccff_head ( grid_clb_130_ccff_tail ) , + .chany_bottom_out ( cby_1__1__130_chany_bottom_out ) , + .chany_top_out ( cby_1__1__130_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__130_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__130_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__130_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__130_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__130_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__130_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__130_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__130_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__130_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__130_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__130_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__130_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__130_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__130_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__130_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__130_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__130_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10123 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10124 ) , + .Test_en_W_in ( Test_enWires[264] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10125 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10126 ) , + .Test_en_E_out ( Test_enWires[265] ) , .pReset_S_in ( pResetWires[546] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10127 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10128 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10129 ) , + .Reset_W_in ( ResetWires[264] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10130 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10131 ) , + .Reset_E_out ( ResetWires[265] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[436] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[437] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10132 ) , + .prog_clk_2_N_in ( SYNOPSYS_UNCONNECTED_10133 ) , + .prog_clk_2_S_in ( prog_clk_2_wires[134] ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10134 ) , + .prog_clk_2_N_out ( prog_clk_2_wires[135] ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10135 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10136 ) , + .clk_2_N_in ( SYNOPSYS_UNCONNECTED_10137 ) , + .clk_2_S_in ( clk_2_wires[134] ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10138 ) , + .clk_2_N_out ( clk_2_wires[135] ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10139 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10140 ) ) ; +cby_1__1_ cby_11__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10141 } ) , + .chany_bottom_in ( sb_1__1__120_chany_top_out ) , + .chany_top_in ( sb_1__12__10_chany_bottom_out ) , + .ccff_head ( grid_clb_131_ccff_tail ) , + .chany_bottom_out ( cby_1__1__131_chany_bottom_out ) , + .chany_top_out ( cby_1__1__131_chany_top_out ) , + .left_grid_pin_16_ ( cby_1__1__131_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_1__1__131_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_1__1__131_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_1__1__131_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_1__1__131_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_1__1__131_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_1__1__131_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_1__1__131_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_1__1__131_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_1__1__131_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_1__1__131_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_1__1__131_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_1__1__131_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_1__1__131_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_1__1__131_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_1__1__131_left_grid_pin_31_ ) , + .ccff_tail ( cby_1__1__131_ccff_tail ) , + .Test_en_S_in ( SYNOPSYS_UNCONNECTED_10142 ) , + .Test_en_E_in ( SYNOPSYS_UNCONNECTED_10143 ) , + .Test_en_W_in ( Test_enWires[286] ) , + .Test_en_N_out ( SYNOPSYS_UNCONNECTED_10144 ) , + .Test_en_W_out ( SYNOPSYS_UNCONNECTED_10145 ) , + .Test_en_E_out ( Test_enWires[287] ) , .pReset_S_in ( pResetWires[595] ) , + .pReset_N_out ( SYNOPSYS_UNCONNECTED_10146 ) , + .Reset_S_in ( SYNOPSYS_UNCONNECTED_10147 ) , + .Reset_E_in ( SYNOPSYS_UNCONNECTED_10148 ) , + .Reset_W_in ( ResetWires[286] ) , + .Reset_N_out ( SYNOPSYS_UNCONNECTED_10149 ) , + .Reset_W_out ( SYNOPSYS_UNCONNECTED_10150 ) , + .Reset_E_out ( ResetWires[287] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[439] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[440] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[442] ) , + .prog_clk_2_N_in ( h_incr0 ) , .prog_clk_2_S_in ( h_incr0 ) , + .prog_clk_2_S_out ( SYNOPSYS_UNCONNECTED_10151 ) , + .prog_clk_2_N_out ( SYNOPSYS_UNCONNECTED_10152 ) , + .prog_clk_3_S_in ( h_incr0 ) , .prog_clk_3_N_in ( h_incr0 ) , + .prog_clk_3_N_out ( SYNOPSYS_UNCONNECTED_10153 ) , + .prog_clk_3_S_out ( SYNOPSYS_UNCONNECTED_10154 ) , + .clk_2_N_in ( h_incr0 ) , .clk_2_S_in ( h_incr0 ) , + .clk_2_S_out ( SYNOPSYS_UNCONNECTED_10155 ) , + .clk_2_N_out ( SYNOPSYS_UNCONNECTED_10156 ) , .clk_3_S_in ( h_incr0 ) , + .clk_3_N_in ( h_incr0 ) , .clk_3_N_out ( SYNOPSYS_UNCONNECTED_10157 ) , + .clk_3_S_out ( SYNOPSYS_UNCONNECTED_10158 ) ) ; +cby_2__1_ cby_12__1_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10159 } ) , + .chany_bottom_in ( sb_12__0__0_chany_top_out ) , + .chany_top_in ( sb_12__1__0_chany_bottom_out ) , + .ccff_head ( grid_clb_132_ccff_tail ) , + .chany_bottom_out ( cby_12__1__0_chany_bottom_out ) , + .chany_top_out ( cby_12__1__0_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__0_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__0_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__0_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__0_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__0_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__0_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__0_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__0_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__0_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__0_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__0_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__0_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__0_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__0_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__0_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__0_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_11_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__0_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_11_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_11_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[60] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[444] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[445] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10160 ) ) ; +cby_2__1_ cby_12__2_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10161 } ) , + .chany_bottom_in ( sb_12__1__0_chany_top_out ) , + .chany_top_in ( sb_12__1__1_chany_bottom_out ) , + .ccff_head ( grid_clb_133_ccff_tail ) , + .chany_bottom_out ( cby_12__1__1_chany_bottom_out ) , + .chany_top_out ( cby_12__1__1_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__1_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__1_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__1_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__1_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__1_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__1_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__1_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__1_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__1_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__1_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__1_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__1_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__1_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__1_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__1_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__1_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_10_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__1_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_10_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_10_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[109] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[447] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[448] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10162 ) ) ; +cby_2__1_ cby_12__3_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10163 } ) , + .chany_bottom_in ( sb_12__1__1_chany_top_out ) , + .chany_top_in ( sb_12__1__2_chany_bottom_out ) , + .ccff_head ( grid_clb_134_ccff_tail ) , + .chany_bottom_out ( cby_12__1__2_chany_bottom_out ) , + .chany_top_out ( cby_12__1__2_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__2_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__2_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__2_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__2_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__2_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__2_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__2_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__2_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__2_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__2_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__2_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__2_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__2_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__2_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__2_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__2_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_9_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__2_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_9_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_9_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[158] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[450] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[451] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10164 ) ) ; +cby_2__1_ cby_12__4_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10165 } ) , + .chany_bottom_in ( sb_12__1__2_chany_top_out ) , + .chany_top_in ( sb_12__1__3_chany_bottom_out ) , + .ccff_head ( grid_clb_135_ccff_tail ) , + .chany_bottom_out ( cby_12__1__3_chany_bottom_out ) , + .chany_top_out ( cby_12__1__3_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__3_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__3_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__3_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__3_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__3_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__3_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__3_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__3_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__3_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__3_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__3_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__3_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__3_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__3_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__3_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__3_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_8_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__3_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_8_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_8_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[207] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[453] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[454] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10166 ) ) ; +cby_2__1_ cby_12__5_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10167 } ) , + .chany_bottom_in ( sb_12__1__3_chany_top_out ) , + .chany_top_in ( sb_12__1__4_chany_bottom_out ) , + .ccff_head ( grid_clb_136_ccff_tail ) , + .chany_bottom_out ( cby_12__1__4_chany_bottom_out ) , + .chany_top_out ( cby_12__1__4_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__4_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__4_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__4_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__4_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__4_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__4_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__4_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__4_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__4_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__4_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__4_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__4_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__4_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__4_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__4_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__4_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_7_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__4_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_7_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_7_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[256] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[456] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[457] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10168 ) ) ; +cby_2__1_ cby_12__6_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10169 } ) , + .chany_bottom_in ( sb_12__1__4_chany_top_out ) , + .chany_top_in ( sb_12__1__5_chany_bottom_out ) , + .ccff_head ( grid_clb_137_ccff_tail ) , + .chany_bottom_out ( cby_12__1__5_chany_bottom_out ) , + .chany_top_out ( cby_12__1__5_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__5_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__5_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__5_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__5_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__5_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__5_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__5_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__5_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__5_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__5_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__5_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__5_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__5_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__5_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__5_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__5_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_6_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__5_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_6_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_6_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[305] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[459] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[460] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10170 ) ) ; +cby_2__1_ cby_12__7_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10171 } ) , + .chany_bottom_in ( sb_12__1__5_chany_top_out ) , + .chany_top_in ( sb_12__1__6_chany_bottom_out ) , + .ccff_head ( grid_clb_138_ccff_tail ) , + .chany_bottom_out ( cby_12__1__6_chany_bottom_out ) , + .chany_top_out ( cby_12__1__6_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__6_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__6_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__6_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__6_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__6_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__6_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__6_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__6_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__6_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__6_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__6_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__6_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__6_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__6_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__6_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__6_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_5_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__6_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_5_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_5_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[354] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[462] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[463] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10172 ) ) ; +cby_2__1_ cby_12__8_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10173 } ) , + .chany_bottom_in ( sb_12__1__6_chany_top_out ) , + .chany_top_in ( sb_12__1__7_chany_bottom_out ) , + .ccff_head ( grid_clb_139_ccff_tail ) , + .chany_bottom_out ( cby_12__1__7_chany_bottom_out ) , + .chany_top_out ( cby_12__1__7_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__7_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__7_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__7_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__7_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__7_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__7_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__7_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__7_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__7_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__7_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__7_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__7_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__7_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__7_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__7_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__7_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_4_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__7_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_4_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_4_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[403] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[465] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[466] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10174 ) ) ; +cby_2__1_ cby_12__9_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10175 } ) , + .chany_bottom_in ( sb_12__1__7_chany_top_out ) , + .chany_top_in ( sb_12__1__8_chany_bottom_out ) , + .ccff_head ( grid_clb_140_ccff_tail ) , + .chany_bottom_out ( cby_12__1__8_chany_bottom_out ) , + .chany_top_out ( cby_12__1__8_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__8_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__8_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__8_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__8_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__8_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__8_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__8_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__8_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__8_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__8_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__8_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__8_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__8_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__8_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__8_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__8_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_3_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__8_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_3_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_3_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[452] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[468] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[469] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10176 ) ) ; +cby_2__1_ cby_12__10_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10177 } ) , + .chany_bottom_in ( sb_12__1__8_chany_top_out ) , + .chany_top_in ( sb_12__1__9_chany_bottom_out ) , + .ccff_head ( grid_clb_141_ccff_tail ) , + .chany_bottom_out ( cby_12__1__9_chany_bottom_out ) , + .chany_top_out ( cby_12__1__9_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__9_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__9_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__9_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__9_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__9_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__9_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__9_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__9_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__9_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__9_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__9_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__9_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__9_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__9_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__9_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__9_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_2_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__9_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_2_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_2_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[501] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[471] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[472] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10178 ) ) ; +cby_2__1_ cby_12__11_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10179 } ) , + .chany_bottom_in ( sb_12__1__9_chany_top_out ) , + .chany_top_in ( sb_12__1__10_chany_bottom_out ) , + .ccff_head ( grid_clb_142_ccff_tail ) , + .chany_bottom_out ( cby_12__1__10_chany_bottom_out ) , + .chany_top_out ( cby_12__1__10_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__10_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__10_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__10_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__10_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__10_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__10_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__10_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__10_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__10_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__10_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__10_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__10_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__10_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__10_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__10_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__10_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_1_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__10_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[550] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[474] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[475] ) , + .prog_clk_0_N_out ( SYNOPSYS_UNCONNECTED_10180 ) ) ; +cby_2__1_ cby_12__12_ ( + .pReset ( { SYNOPSYS_UNCONNECTED_10181 } ) , + .chany_bottom_in ( sb_12__1__10_chany_top_out ) , + .chany_top_in ( sb_12__12__0_chany_bottom_out ) , + .ccff_head ( grid_clb_143_ccff_tail ) , + .chany_bottom_out ( cby_12__1__11_chany_bottom_out ) , + .chany_top_out ( cby_12__1__11_chany_top_out ) , + .right_grid_pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , + .left_grid_pin_16_ ( cby_12__1__11_left_grid_pin_16_ ) , + .left_grid_pin_17_ ( cby_12__1__11_left_grid_pin_17_ ) , + .left_grid_pin_18_ ( cby_12__1__11_left_grid_pin_18_ ) , + .left_grid_pin_19_ ( cby_12__1__11_left_grid_pin_19_ ) , + .left_grid_pin_20_ ( cby_12__1__11_left_grid_pin_20_ ) , + .left_grid_pin_21_ ( cby_12__1__11_left_grid_pin_21_ ) , + .left_grid_pin_22_ ( cby_12__1__11_left_grid_pin_22_ ) , + .left_grid_pin_23_ ( cby_12__1__11_left_grid_pin_23_ ) , + .left_grid_pin_24_ ( cby_12__1__11_left_grid_pin_24_ ) , + .left_grid_pin_25_ ( cby_12__1__11_left_grid_pin_25_ ) , + .left_grid_pin_26_ ( cby_12__1__11_left_grid_pin_26_ ) , + .left_grid_pin_27_ ( cby_12__1__11_left_grid_pin_27_ ) , + .left_grid_pin_28_ ( cby_12__1__11_left_grid_pin_28_ ) , + .left_grid_pin_29_ ( cby_12__1__11_left_grid_pin_29_ ) , + .left_grid_pin_30_ ( cby_12__1__11_left_grid_pin_30_ ) , + .left_grid_pin_31_ ( cby_12__1__11_left_grid_pin_31_ ) , + .ccff_tail ( grid_io_right_0_ccff_tail ) , .IO_ISOL_N ( IO_ISOL_N ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] ) , + .left_width_0_height_0__pin_0_ ( cby_12__1__11_right_grid_pin_0_ ) , + .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .pReset_S_in ( pResetWires[599] ) , + .prog_clk_0_W_in ( prog_clk_0_wires[477] ) , + .prog_clk_0_S_out ( prog_clk_0_wires[478] ) , + .prog_clk_0_N_out ( prog_clk_0_wires[480] ) ) ; +endmodule + + +module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , + vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , + wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , + la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ , + analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ , + analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ , + analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ , + analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ , + analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , + analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , + analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , + analog_io_9_ , user_clock2 ) ; +inout vdda1 ; +inout vdda2 ; +inout vssa1 ; +inout vssa2 ; +inout vccd1 ; +inout vccd2 ; +inout vssd1 ; +inout vssd2 ; +input wb_clk_i ; +input wb_rst_i ; +input wbs_stb_i ; +input wbs_cyc_i ; +input wbs_we_i ; +input [3:0] wbs_sel_i ; +input [31:0] wbs_dat_i ; +input [31:0] wbs_adr_i ; +output wbs_ack_o ; +output [31:0] wbs_dat_o ; +input [127:0] la_data_in ; +output [127:0] la_data_out ; +input [127:0] la_oen ; +input [37:0] io_in ; +output [37:0] io_out ; +output [37:0] io_oeb ; +inout analog_io_0_ ; +inout analog_io_10_ ; +inout analog_io_11_ ; +inout analog_io_12_ ; +inout analog_io_13_ ; +inout analog_io_14_ ; +inout analog_io_15_ ; +inout analog_io_16_ ; +inout analog_io_17_ ; +inout analog_io_18_ ; +inout analog_io_19_ ; +inout analog_io_1_ ; +inout analog_io_20_ ; +inout analog_io_21_ ; +inout analog_io_22_ ; +inout analog_io_23_ ; +inout analog_io_24_ ; +inout analog_io_25_ ; +inout analog_io_26_ ; +inout analog_io_27_ ; +inout analog_io_28_ ; +inout analog_io_29_ ; +inout analog_io_2_ ; +inout analog_io_30_ ; +inout analog_io_3_ ; +inout analog_io_4_ ; +inout analog_io_5_ ; +inout analog_io_6_ ; +inout analog_io_7_ ; +inout analog_io_8_ ; +inout analog_io_9_ ; +input user_clock2 ; + +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +wire ccff_head ; +wire sc_tail ; +wire pReset ; +wire Reset ; +wire IO_ISOL_N ; +wire Test_en ; +wire prog_clk ; +wire clk ; +wire ccff_tail ; +wire sc_head ; +wire wb_la_switch ; + +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ; +assign ccff_head = io_in[12] ; +assign sc_tail = io_out[11] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ; +assign pReset = io_in[3] ; +assign Reset = io_in[2] ; +assign IO_ISOL_N = io_in[1] ; +assign Test_en = io_in[0] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ; +assign prog_clk = io_in[37] ; +assign clk = io_in[36] ; +assign ccff_tail = io_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ; +assign sc_head = io_in[26] ; +assign wb_la_switch = io_in[25] ; + +sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) , + .Y ( wb_la_switch_b ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[0] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[116] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[1] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[115] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[2] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[114] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[3] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[113] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[4] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[112] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[5] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[111] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[6] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[110] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[7] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[109] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[8] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[108] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[9] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[107] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[10] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[106] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[11] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[105] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[12] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[104] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[13] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[103] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[14] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[102] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[15] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[101] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[16] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[100] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[17] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[99] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[18] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[98] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[19] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[97] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[20] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[96] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[21] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[95] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[22] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[94] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[23] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[93] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[24] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[92] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[25] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[91] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[26] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[90] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[27] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[89] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[28] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[88] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[29] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[87] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[30] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[86] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[31] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[85] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) , + .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) , + .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) , + .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) , + .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) , + .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) , + .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) , + .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) , + .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) , + .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) , + .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) , + .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) , + .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) , + .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) , + .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) , + .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) , + .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) , + .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) , + .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) , + .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) , + .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) , + .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) , + .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) , + .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) , + .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) , + .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) , + .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) , + .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) , + .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) , + .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) , + .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) , + .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) , + .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) , + .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) , + .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) , + .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) , + .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) , + .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) , + .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) , + .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) , + .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) , + .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) , + .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) , + .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) , + .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) , + .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) , + .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) , + .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) , + .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) , + .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) , + .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) , + .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) , + .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) , + .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) , + .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) , + .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) , + .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) , + .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) , + .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) , + .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) , + .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) , + .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) , + .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) , + .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) , + .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) , + .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) , + .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) , + .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) , + .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) , + .A1 ( wbs_we_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) , + .A1 ( wbs_stb_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) , + .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_ack_o ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[13] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) , + .A1 ( wb_rst_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) , + .A1 ( wb_clk_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ; +fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , + .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) , + .Reset ( io_in[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] , + io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] , + io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] , + io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] , + la_data_in[127] , la_data_in[126] , la_data_in[125] , + la_data_in[124] , la_data_in[123] , la_data_in[122] , + la_data_in[121] , la_data_in[120] , la_data_in[119] , + la_data_in[118] , la_data_in[117] , la_data_in[116] , + la_data_in[115] , la_data_in[114] , la_data_in[113] , + la_data_in[112] , la_data_in[111] , la_data_in[110] , + la_data_in[109] , la_data_in[108] , la_data_in[107] , + la_data_in[106] , la_data_in[105] , la_data_in[104] , + la_data_in[103] , la_data_in[102] , la_data_in[101] , + la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] , + la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] , + la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] , + la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] , + io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] , + io_in[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] , + io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] , + io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] , + io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] , + io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] , + la_data_out[125] , la_data_out[124] , la_data_out[123] , + la_data_out[122] , la_data_out[121] , la_data_out[120] , + la_data_out[119] , la_data_out[118] , la_data_out[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] , + la_data_out[83] , la_data_out[82] , la_data_out[81] , + la_data_out[80] , la_data_out[79] , la_data_out[78] , + la_data_out[77] , la_data_out[76] , la_data_out[75] , + la_data_out[74] , la_data_out[73] , la_data_out[72] , + la_data_out[71] , la_data_out[70] , la_data_out[69] , + la_data_out[68] , la_data_out[67] , la_data_out[66] , + la_data_out[65] , la_data_out[64] , la_data_out[63] , + la_data_out[62] , la_data_out[61] , la_data_out[60] , + la_data_out[59] , la_data_out[58] , la_data_out[57] , + la_data_out[56] , la_data_out[55] , la_data_out[54] , + la_data_out[53] , la_data_out[52] , la_data_out[51] , + la_data_out[50] , la_data_out[49] , la_data_out[48] , + la_data_out[47] , la_data_out[46] , la_data_out[45] , + la_data_out[44] , la_data_out[43] , la_data_out[42] , + la_data_out[41] , la_data_out[40] , la_data_out[39] , + la_data_out[38] , la_data_out[37] , la_data_out[36] , + la_data_out[35] , la_data_out[34] , la_data_out[33] , + la_data_out[32] , la_data_out[31] , la_data_out[30] , + la_data_out[29] , la_data_out[28] , la_data_out[27] , + la_data_out[26] , la_data_out[25] , la_data_out[24] , + la_data_out[23] , la_data_out[22] , la_data_out[21] , + la_data_out[20] , la_data_out[19] , la_data_out[18] , + la_data_out[17] , la_data_out[16] , la_data_out[15] , + la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] , + la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] , + io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] , + io_out[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] , + io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] , + io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] , + io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] , + io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] , + io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] , + io_oeb[27] } ) , + .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) , + .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , .h_incr0 ( 1'b0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( io_oeb[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( io_oeb[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( io_oeb[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( io_oeb[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( io_oeb[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( io_oeb[25] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( io_oeb[26] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( io_oeb[36] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , + .HI ( io_oeb[37] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) , + .HI ( SYNOPSYS_UNCONNECTED_10 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) , + .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) , + .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) , + .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) , + .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) , + .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) , + .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) , + .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) , + .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) , + .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , + .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ; +endmodule + + diff --git a/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v new file mode 100644 index 0000000..319af31 --- /dev/null +++ b/FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v @@ -0,0 +1,1060 @@ +// +// +// +// +// +// +module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , + vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , + wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , + la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ , + analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ , + analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ , + analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ , + analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ , + analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , + analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , + analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , + analog_io_9_ , user_clock2 ) ; +inout vdda1 ; +inout vdda2 ; +inout vssa1 ; +inout vssa2 ; +inout vccd1 ; +inout vccd2 ; +inout vssd1 ; +inout vssd2 ; +input wb_clk_i ; +input wb_rst_i ; +input wbs_stb_i ; +input wbs_cyc_i ; +input wbs_we_i ; +input [3:0] wbs_sel_i ; +input [31:0] wbs_dat_i ; +input [31:0] wbs_adr_i ; +output wbs_ack_o ; +output [31:0] wbs_dat_o ; +input [127:0] la_data_in ; +output [127:0] la_data_out ; +input [127:0] la_oen ; +input [37:0] io_in ; +output [37:0] io_out ; +output [37:0] io_oeb ; +inout analog_io_0_ ; +inout analog_io_10_ ; +inout analog_io_11_ ; +inout analog_io_12_ ; +inout analog_io_13_ ; +inout analog_io_14_ ; +inout analog_io_15_ ; +inout analog_io_16_ ; +inout analog_io_17_ ; +inout analog_io_18_ ; +inout analog_io_19_ ; +inout analog_io_1_ ; +inout analog_io_20_ ; +inout analog_io_21_ ; +inout analog_io_22_ ; +inout analog_io_23_ ; +inout analog_io_24_ ; +inout analog_io_25_ ; +inout analog_io_26_ ; +inout analog_io_27_ ; +inout analog_io_28_ ; +inout analog_io_29_ ; +inout analog_io_2_ ; +inout analog_io_30_ ; +inout analog_io_3_ ; +inout analog_io_4_ ; +inout analog_io_5_ ; +inout analog_io_6_ ; +inout analog_io_7_ ; +inout analog_io_8_ ; +inout analog_io_9_ ; +input user_clock2 ; + +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; +wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ; +wire ccff_head ; +wire sc_tail ; +wire pReset ; +wire Reset ; +wire IO_ISOL_N ; +wire Test_en ; +wire prog_clk ; +wire clk ; +wire ccff_tail ; +wire sc_head ; +wire wb_la_switch ; + +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] = io_in[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] = io_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] = io_oeb[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] = io_in[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] = io_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] = io_oeb[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] = io_in[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] = io_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] = io_oeb[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] = io_in[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] = io_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] = io_oeb[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] = io_in[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] = io_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] = io_oeb[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] = io_in[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] = io_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] = io_oeb[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] = io_in[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] = io_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] = io_oeb[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] = io_in[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] = io_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] = io_oeb[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] = io_in[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] = io_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] = io_oeb[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[9] = io_in[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[9] = io_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[9] = io_oeb[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[10] = io_in[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[10] = io_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[10] = io_oeb[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[11] = io_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[11] = io_out[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[11] = io_oeb[13] ; +assign ccff_head = io_in[12] ; +assign sc_tail = io_out[11] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[12] = io_in[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[12] = io_out[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[12] = io_oeb[10] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[13] = io_in[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[13] = io_out[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[13] = io_oeb[9] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[14] = io_in[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[14] = io_out[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[14] = io_oeb[8] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[15] = io_in[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[15] = io_out[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[15] = io_oeb[7] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[16] = io_in[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[16] = io_out[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[16] = io_oeb[6] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[17] = io_in[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[17] = io_out[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[17] = io_oeb[5] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[18] = io_in[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[18] = io_out[4] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[18] = io_oeb[4] ; +assign pReset = io_in[3] ; +assign Reset = io_in[2] ; +assign IO_ISOL_N = io_in[1] ; +assign Test_en = io_in[0] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[19] = la_data_in[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[19] = la_data_out[127] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[20] = la_data_in[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[20] = la_data_out[126] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[21] = la_data_in[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[21] = la_data_out[125] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[22] = la_data_in[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[22] = la_data_out[124] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[23] = la_data_in[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[23] = la_data_out[123] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[24] = la_data_in[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[24] = la_data_out[122] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[25] = la_data_in[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[25] = la_data_out[121] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[26] = la_data_in[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[26] = la_data_out[120] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[27] = la_data_in[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[27] = la_data_out[119] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[28] = la_data_in[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[28] = la_data_out[118] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[29] = la_data_in[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[29] = la_data_out[117] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[30] = la_data_in[116] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[31] = la_data_in[115] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[32] = la_data_in[114] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[33] = la_data_in[113] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[34] = la_data_in[112] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[35] = la_data_in[111] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[36] = la_data_in[110] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[37] = la_data_in[109] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[38] = la_data_in[108] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[39] = la_data_in[107] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[40] = la_data_in[106] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[41] = la_data_in[105] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[42] = la_data_in[104] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[43] = la_data_in[103] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[44] = la_data_in[102] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[45] = la_data_in[101] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[46] = la_data_in[100] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[47] = la_data_in[99] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[48] = la_data_in[98] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[49] = la_data_in[97] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[50] = la_data_in[96] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[51] = la_data_in[95] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[52] = la_data_in[94] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[53] = la_data_in[93] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[54] = la_data_in[92] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[55] = la_data_in[91] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[56] = la_data_in[90] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[57] = la_data_in[89] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[58] = la_data_in[88] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[59] = la_data_in[87] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[60] = la_data_in[86] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[61] = la_data_in[85] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[62] = la_data_out[84] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[63] = la_data_out[83] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[64] = la_data_out[82] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[65] = la_data_out[81] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[66] = la_data_out[80] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[67] = la_data_out[79] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[68] = la_data_out[78] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[69] = la_data_out[77] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[70] = la_data_out[76] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[71] = la_data_out[75] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[72] = la_data_out[74] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[73] = la_data_out[73] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[74] = la_data_out[72] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[75] = la_data_out[71] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[76] = la_data_out[70] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[77] = la_data_out[69] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[78] = la_data_out[68] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[79] = la_data_out[67] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[80] = la_data_out[66] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[81] = la_data_out[65] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[82] = la_data_out[64] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[83] = la_data_out[63] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[84] = la_data_out[62] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[85] = la_data_out[61] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[86] = la_data_out[60] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[87] = la_data_out[59] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[88] = la_data_out[58] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[89] = la_data_out[57] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[90] = la_data_out[56] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[91] = la_data_out[55] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[92] = la_data_out[54] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[93] = la_data_out[53] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[94] = la_data_out[52] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[95] = la_data_out[51] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[96] = la_data_out[50] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[97] = la_data_out[49] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[98] = la_data_out[48] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[99] = la_data_out[47] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[100] = la_data_out[46] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[101] = la_data_out[45] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[102] = la_data_out[44] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[103] = la_data_out[43] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[104] = la_data_out[42] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[105] = la_data_out[41] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[106] = la_data_out[40] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[107] = la_data_out[39] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[108] = la_data_out[38] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[109] = la_data_out[37] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[110] = la_data_out[36] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[111] = la_data_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[112] = la_data_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[113] = la_data_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[114] = la_data_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[115] = la_data_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[116] = la_data_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[117] = la_data_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[118] = la_data_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[119] = la_data_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[120] = la_data_out[26] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[121] = la_data_out[25] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[122] = la_data_out[24] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[123] = la_data_out[23] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[124] = la_data_out[22] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[125] = la_data_out[21] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[126] = la_data_out[20] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[127] = la_data_out[19] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[128] = la_data_out[18] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[129] = la_data_out[17] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[130] = la_data_out[16] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[131] = la_data_out[15] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[132] = la_data_out[14] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[133] = la_data_in[13] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[134] = la_data_out[12] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[135] = la_data_out[11] ; +assign prog_clk = io_in[37] ; +assign clk = io_in[36] ; +assign ccff_tail = io_out[35] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[136] = io_in[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[136] = io_out[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[136] = io_oeb[34] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[137] = io_in[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[137] = io_out[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[137] = io_oeb[33] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[138] = io_in[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[138] = io_out[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[138] = io_oeb[32] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[139] = io_in[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[139] = io_out[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[139] = io_oeb[31] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[140] = io_in[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[140] = io_out[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[140] = io_oeb[30] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[141] = io_in[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[141] = io_out[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[141] = io_oeb[29] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[142] = io_in[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[142] = io_out[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[142] = io_oeb[28] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[143] = io_in[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[143] = io_out[27] ; +assign gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[143] = io_oeb[27] ; +assign sc_head = io_in[26] ; +assign wb_la_switch = io_in[25] ; + +sky130_fd_sc_hd__inv_8 WB_LA_SWITCH_INV ( .A ( io_in[25] ) , + .Y ( wb_la_switch_b ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[0] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_30_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[116] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[1] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_31_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[115] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[2] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_32_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[114] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[3] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_33_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[113] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[4] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_34_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[112] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[5] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_35_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[111] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[6] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_36_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[110] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[7] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_37_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[109] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[8] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_38_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[108] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[9] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_39_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[107] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[10] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_40_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[106] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[11] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_41_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[105] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[12] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_42_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[104] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[13] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_43_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[103] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[14] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_44_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[102] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[15] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_45_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[101] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[16] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_46_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[100] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[17] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_47_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[99] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[18] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_48_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[98] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[19] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_49_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[97] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[20] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_50_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[96] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[21] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_51_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[95] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[22] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_52_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[94] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[23] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_53_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[93] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[24] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_54_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[92] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[25] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_55_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[91] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[26] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_56_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[90] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[27] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_57_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[89] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[28] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_58_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[88] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[29] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_59_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[87] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[30] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_60_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[86] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_dat_o[31] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_61_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[85] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_62_MUX ( .A0 ( la_data_in[84] ) , + .A1 ( wbs_dat_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_63_MUX ( .A0 ( la_data_in[83] ) , + .A1 ( wbs_dat_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_64_MUX ( .A0 ( la_data_in[82] ) , + .A1 ( wbs_dat_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_65_MUX ( .A0 ( la_data_in[81] ) , + .A1 ( wbs_dat_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_66_MUX ( .A0 ( la_data_in[80] ) , + .A1 ( wbs_dat_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_67_MUX ( .A0 ( la_data_in[79] ) , + .A1 ( wbs_dat_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_68_MUX ( .A0 ( la_data_in[78] ) , + .A1 ( wbs_dat_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_69_MUX ( .A0 ( la_data_in[77] ) , + .A1 ( wbs_dat_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_70_MUX ( .A0 ( la_data_in[76] ) , + .A1 ( wbs_dat_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_71_MUX ( .A0 ( la_data_in[75] ) , + .A1 ( wbs_dat_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_72_MUX ( .A0 ( la_data_in[74] ) , + .A1 ( wbs_dat_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_73_MUX ( .A0 ( la_data_in[73] ) , + .A1 ( wbs_dat_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_74_MUX ( .A0 ( la_data_in[72] ) , + .A1 ( wbs_dat_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_75_MUX ( .A0 ( la_data_in[71] ) , + .A1 ( wbs_dat_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_76_MUX ( .A0 ( la_data_in[70] ) , + .A1 ( wbs_dat_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_77_MUX ( .A0 ( la_data_in[69] ) , + .A1 ( wbs_dat_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_78_MUX ( .A0 ( la_data_in[68] ) , + .A1 ( wbs_dat_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_79_MUX ( .A0 ( la_data_in[67] ) , + .A1 ( wbs_dat_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_80_MUX ( .A0 ( la_data_in[66] ) , + .A1 ( wbs_dat_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_81_MUX ( .A0 ( la_data_in[65] ) , + .A1 ( wbs_dat_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_82_MUX ( .A0 ( la_data_in[64] ) , + .A1 ( wbs_dat_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_83_MUX ( .A0 ( la_data_in[63] ) , + .A1 ( wbs_dat_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_84_MUX ( .A0 ( la_data_in[62] ) , + .A1 ( wbs_dat_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_85_MUX ( .A0 ( la_data_in[61] ) , + .A1 ( wbs_dat_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_86_MUX ( .A0 ( la_data_in[60] ) , + .A1 ( wbs_dat_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_87_MUX ( .A0 ( la_data_in[59] ) , + .A1 ( wbs_dat_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_88_MUX ( .A0 ( la_data_in[58] ) , + .A1 ( wbs_dat_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_89_MUX ( .A0 ( la_data_in[57] ) , + .A1 ( wbs_dat_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_90_MUX ( .A0 ( la_data_in[56] ) , + .A1 ( wbs_dat_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_91_MUX ( .A0 ( la_data_in[55] ) , + .A1 ( wbs_dat_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_92_MUX ( .A0 ( la_data_in[54] ) , + .A1 ( wbs_dat_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_93_MUX ( .A0 ( la_data_in[53] ) , + .A1 ( wbs_dat_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_94_MUX ( .A0 ( la_data_in[52] ) , + .A1 ( wbs_adr_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_95_MUX ( .A0 ( la_data_in[51] ) , + .A1 ( wbs_adr_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_96_MUX ( .A0 ( la_data_in[50] ) , + .A1 ( wbs_adr_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_97_MUX ( .A0 ( la_data_in[49] ) , + .A1 ( wbs_adr_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_98_MUX ( .A0 ( la_data_in[48] ) , + .A1 ( wbs_adr_i[4] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_99_MUX ( .A0 ( la_data_in[47] ) , + .A1 ( wbs_adr_i[5] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_100_MUX ( .A0 ( la_data_in[46] ) , + .A1 ( wbs_adr_i[6] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_101_MUX ( .A0 ( la_data_in[45] ) , + .A1 ( wbs_adr_i[7] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_102_MUX ( .A0 ( la_data_in[44] ) , + .A1 ( wbs_adr_i[8] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_103_MUX ( .A0 ( la_data_in[43] ) , + .A1 ( wbs_adr_i[9] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_104_MUX ( .A0 ( la_data_in[42] ) , + .A1 ( wbs_adr_i[10] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_105_MUX ( .A0 ( la_data_in[41] ) , + .A1 ( wbs_adr_i[11] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_106_MUX ( .A0 ( la_data_in[40] ) , + .A1 ( wbs_adr_i[12] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_107_MUX ( .A0 ( la_data_in[39] ) , + .A1 ( wbs_adr_i[13] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_108_MUX ( .A0 ( la_data_in[38] ) , + .A1 ( wbs_adr_i[14] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_109_MUX ( .A0 ( la_data_in[37] ) , + .A1 ( wbs_adr_i[15] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_110_MUX ( .A0 ( la_data_in[36] ) , + .A1 ( wbs_adr_i[16] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_111_MUX ( .A0 ( la_data_in[35] ) , + .A1 ( wbs_adr_i[17] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_112_MUX ( .A0 ( la_data_in[34] ) , + .A1 ( wbs_adr_i[18] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_113_MUX ( .A0 ( la_data_in[33] ) , + .A1 ( wbs_adr_i[19] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_114_MUX ( .A0 ( la_data_in[32] ) , + .A1 ( wbs_adr_i[20] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_115_MUX ( .A0 ( la_data_in[31] ) , + .A1 ( wbs_adr_i[21] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_116_MUX ( .A0 ( la_data_in[30] ) , + .A1 ( wbs_adr_i[22] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_117_MUX ( .A0 ( la_data_in[29] ) , + .A1 ( wbs_adr_i[23] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_118_MUX ( .A0 ( la_data_in[28] ) , + .A1 ( wbs_adr_i[24] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_119_MUX ( .A0 ( la_data_in[27] ) , + .A1 ( wbs_adr_i[25] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_120_MUX ( .A0 ( la_data_in[26] ) , + .A1 ( wbs_adr_i[26] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_121_MUX ( .A0 ( la_data_in[25] ) , + .A1 ( wbs_adr_i[27] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_122_MUX ( .A0 ( la_data_in[24] ) , + .A1 ( wbs_adr_i[28] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_123_MUX ( .A0 ( la_data_in[23] ) , + .A1 ( wbs_adr_i[29] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_124_MUX ( .A0 ( la_data_in[22] ) , + .A1 ( wbs_adr_i[30] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_125_MUX ( .A0 ( la_data_in[21] ) , + .A1 ( wbs_adr_i[31] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_126_MUX ( .A0 ( la_data_in[20] ) , + .A1 ( wbs_sel_i[0] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_127_MUX ( .A0 ( la_data_in[19] ) , + .A1 ( wbs_sel_i[1] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_128_MUX ( .A0 ( la_data_in[18] ) , + .A1 ( wbs_sel_i[2] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_129_MUX ( .A0 ( la_data_in[17] ) , + .A1 ( wbs_sel_i[3] ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_130_MUX ( .A0 ( la_data_in[16] ) , + .A1 ( wbs_we_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_131_MUX ( .A0 ( la_data_in[15] ) , + .A1 ( wbs_stb_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_132_MUX ( .A0 ( la_data_in[14] ) , + .A1 ( wbs_cyc_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_WB ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( wb_la_switch_b ) , + .Z ( wbs_ack_o ) ) ; +sky130_fd_sc_hd__ebufn_4 FPGA2SOC_OUT_133_DEMUX_LA ( + .A ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] ) , .TE_B ( io_in[25] ) , + .Z ( la_data_out[13] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_134_MUX ( .A0 ( la_data_in[12] ) , + .A1 ( wb_rst_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] ) ) ; +sky130_fd_sc_hd__mux2_1 FPGA2SOC_IN_135_MUX ( .A0 ( la_data_in[11] ) , + .A1 ( wb_clk_i ) , .S ( io_in[25] ) , + .X ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] ) ) ; +fpga_core fpga_core_uut ( .pReset ( io_in[3] ) , .prog_clk ( io_in[37] ) , + .Test_en ( io_in[0] ) , .IO_ISOL_N ( io_in[1] ) , .clk ( io_in[36] ) , + .Reset ( io_in[2] ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( { io_in[24] , io_in[23] , io_in[22] , + io_in[21] , io_in[20] , io_in[19] , io_in[18] , io_in[17] , + io_in[16] , io_in[15] , io_in[14] , io_in[13] , io_in[10] , io_in[9] , + io_in[8] , io_in[7] , io_in[6] , io_in[5] , io_in[4] , + la_data_in[127] , la_data_in[126] , la_data_in[125] , + la_data_in[124] , la_data_in[123] , la_data_in[122] , + la_data_in[121] , la_data_in[120] , la_data_in[119] , + la_data_in[118] , la_data_in[117] , la_data_in[116] , + la_data_in[115] , la_data_in[114] , la_data_in[113] , + la_data_in[112] , la_data_in[111] , la_data_in[110] , + la_data_in[109] , la_data_in[108] , la_data_in[107] , + la_data_in[106] , la_data_in[105] , la_data_in[104] , + la_data_in[103] , la_data_in[102] , la_data_in[101] , + la_data_in[100] , la_data_in[99] , la_data_in[98] , la_data_in[97] , + la_data_in[96] , la_data_in[95] , la_data_in[94] , la_data_in[93] , + la_data_in[92] , la_data_in[91] , la_data_in[90] , la_data_in[89] , + la_data_in[88] , la_data_in[87] , la_data_in[86] , la_data_in[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[132] , la_data_in[13] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_IN[135] , io_in[34] , io_in[33] , + io_in[32] , io_in[31] , io_in[30] , io_in[29] , io_in[28] , + io_in[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( { io_out[24] , io_out[23] , + io_out[22] , io_out[21] , io_out[20] , io_out[19] , io_out[18] , + io_out[17] , io_out[16] , io_out[15] , io_out[14] , io_out[13] , + io_out[10] , io_out[9] , io_out[8] , io_out[7] , io_out[6] , + io_out[5] , io_out[4] , la_data_out[127] , la_data_out[126] , + la_data_out[125] , la_data_out[124] , la_data_out[123] , + la_data_out[122] , la_data_out[121] , la_data_out[120] , + la_data_out[119] , la_data_out[118] , la_data_out[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[61] , la_data_out[84] , + la_data_out[83] , la_data_out[82] , la_data_out[81] , + la_data_out[80] , la_data_out[79] , la_data_out[78] , + la_data_out[77] , la_data_out[76] , la_data_out[75] , + la_data_out[74] , la_data_out[73] , la_data_out[72] , + la_data_out[71] , la_data_out[70] , la_data_out[69] , + la_data_out[68] , la_data_out[67] , la_data_out[66] , + la_data_out[65] , la_data_out[64] , la_data_out[63] , + la_data_out[62] , la_data_out[61] , la_data_out[60] , + la_data_out[59] , la_data_out[58] , la_data_out[57] , + la_data_out[56] , la_data_out[55] , la_data_out[54] , + la_data_out[53] , la_data_out[52] , la_data_out[51] , + la_data_out[50] , la_data_out[49] , la_data_out[48] , + la_data_out[47] , la_data_out[46] , la_data_out[45] , + la_data_out[44] , la_data_out[43] , la_data_out[42] , + la_data_out[41] , la_data_out[40] , la_data_out[39] , + la_data_out[38] , la_data_out[37] , la_data_out[36] , + la_data_out[35] , la_data_out[34] , la_data_out[33] , + la_data_out[32] , la_data_out[31] , la_data_out[30] , + la_data_out[29] , la_data_out[28] , la_data_out[27] , + la_data_out[26] , la_data_out[25] , la_data_out[24] , + la_data_out[23] , la_data_out[22] , la_data_out[21] , + la_data_out[20] , la_data_out[19] , la_data_out[18] , + la_data_out[17] , la_data_out[16] , la_data_out[15] , + la_data_out[14] , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[133] , + la_data_out[12] , la_data_out[11] , io_out[34] , io_out[33] , + io_out[32] , io_out[31] , io_out[30] , io_out[29] , io_out[28] , + io_out[27] } ) , + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { io_oeb[24] , io_oeb[23] , + io_oeb[22] , io_oeb[21] , io_oeb[20] , io_oeb[19] , io_oeb[18] , + io_oeb[17] , io_oeb[16] , io_oeb[15] , io_oeb[14] , io_oeb[13] , + io_oeb[10] , io_oeb[9] , io_oeb[8] , io_oeb[7] , io_oeb[6] , + io_oeb[5] , io_oeb[4] , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[19] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[20] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[21] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[22] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[23] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[24] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[25] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[26] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[27] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[28] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[29] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[30] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[31] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[32] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[33] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[34] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[35] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[36] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[37] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[38] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[39] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[40] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[41] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[42] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[43] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[44] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[45] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[46] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[47] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[48] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[49] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[50] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[51] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[52] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[53] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[54] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[55] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[56] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[57] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[58] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[59] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[60] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[61] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[62] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[63] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[64] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[65] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[66] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[67] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[68] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[69] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[70] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[71] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[72] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[73] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[74] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[75] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[76] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[77] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[78] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[79] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[80] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[81] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[82] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[83] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[84] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[85] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[86] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[87] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[88] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[89] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[90] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[91] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[92] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[93] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[94] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[95] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[96] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[97] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[98] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[99] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[100] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[101] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[102] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[103] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[104] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[105] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[106] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[107] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[108] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[109] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[110] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[111] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[112] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[113] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[114] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[115] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[116] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[117] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[118] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[119] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[120] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[121] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[122] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[123] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[124] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[125] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[126] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[127] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[128] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[129] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[130] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[131] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[132] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[133] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[134] , + gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[135] , io_oeb[34] , io_oeb[33] , + io_oeb[32] , io_oeb[31] , io_oeb[30] , io_oeb[29] , io_oeb[28] , + io_oeb[27] } ) , + .ccff_head ( io_in[12] ) , .ccff_tail ( io_out[35] ) , + .sc_head ( io_in[26] ) , .sc_tail ( io_out[11] ) , .h_incr0 ( 1'b0 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_0 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( io_oeb[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_1 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( io_oeb[1] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_2 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( io_oeb[2] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_3 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( io_oeb[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_4 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( io_oeb[12] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_5 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( io_oeb[25] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_6 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( io_oeb[26] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_7 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( io_oeb[36] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_8 ( .LO ( SYNOPSYS_UNCONNECTED_9 ) , + .HI ( io_oeb[37] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_9 ( .LO ( io_oeb[11] ) , + .HI ( SYNOPSYS_UNCONNECTED_10 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_10 ( .LO ( io_oeb[35] ) , + .HI ( SYNOPSYS_UNCONNECTED_11 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_11 ( .LO ( io_out[0] ) , + .HI ( SYNOPSYS_UNCONNECTED_12 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_12 ( .LO ( io_out[1] ) , + .HI ( SYNOPSYS_UNCONNECTED_13 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_13 ( .LO ( io_out[2] ) , + .HI ( SYNOPSYS_UNCONNECTED_14 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_14 ( .LO ( io_out[3] ) , + .HI ( SYNOPSYS_UNCONNECTED_15 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_15 ( .LO ( io_out[12] ) , + .HI ( SYNOPSYS_UNCONNECTED_16 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_16 ( .LO ( io_out[25] ) , + .HI ( SYNOPSYS_UNCONNECTED_17 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_17 ( .LO ( io_out[26] ) , + .HI ( SYNOPSYS_UNCONNECTED_18 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_18 ( .LO ( io_out[36] ) , + .HI ( SYNOPSYS_UNCONNECTED_19 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_19 ( .LO ( io_out[37] ) , + .HI ( SYNOPSYS_UNCONNECTED_20 ) ) ; +endmodule + +